Merge branch 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...

[pandora-kernel.git] / arch / arm / mach-omap2 / clock44xx_data.c

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 96bc668..25473a1 100644 (file)
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
        .set_rate       = &omap2_clksel_set_rate,
 };
 
-/* DPLL_UNIPRO */
-static struct dpll_data dpll_unipro_dd = {
-       .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-       .clk_bypass     = &sys_clkin_ck,
-       .clk_ref        = &sys_clkin_ck,
-       .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
-       .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
-       .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
-       .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-       .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-       .enable_mask    = OMAP4430_DPLL_EN_MASK,
-       .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-       .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-       .max_multiplier = 2047,
-       .max_divider    = 128,
-       .min_divider    = 1,
-};
-
-
-static struct clk dpll_unipro_ck = {
-       .name           = "dpll_unipro_ck",
-       .parent         = &sys_clkin_ck,
-       .dpll_data      = &dpll_unipro_dd,
-       .init           = &omap2_init_dpll_parent,
-       .ops            = &clkops_omap3_noncore_dpll_ops,
-       .recalc         = &omap3_dpll_recalc,
-       .round_rate     = &omap2_dpll_round_rate,
-       .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
-       .name           = "dpll_unipro_x2_ck",
-       .parent         = &dpll_unipro_ck,
-       .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-       .flags          = CLOCK_CLKOUTX2,
-       .ops            = &clkops_omap4_dpllmx_ops,
-       .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel dpll_unipro_m2x2_div[] = {
-       { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
-       { .parent = NULL },
-};
-
-static struct clk dpll_unipro_m2x2_ck = {
-       .name           = "dpll_unipro_m2x2_ck",
-       .parent         = &dpll_unipro_x2_ck,
-       .clksel         = dpll_unipro_m2x2_div,
-       .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-       .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-       .ops            = &clkops_omap4_dpllmx_ops,
-       .recalc         = &omap2_clksel_recalc,
-       .round_rate     = &omap2_clksel_round_rate,
-       .set_rate       = &omap2_clksel_set_rate,
-};
-
 static struct clk usb_hs_clk_div_ck = {
        .name           = "usb_hs_clk_div_ck",
        .parent         = &dpll_abe_m3x2_ck,
@@ -1454,6 +1397,40 @@ static struct clk dss_dss_clk = {
        .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate div3_8to32_rates[] = {
+       { .div = 8, .val = 0, .flags = RATE_IN_44XX },
+       { .div = 16, .val = 1, .flags = RATE_IN_44XX },
+       { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+       { .div = 0 },
+};
+
+static const struct clksel div_ts_div[] = {
+       { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+       { .parent = NULL },
+};
+
+static struct clk div_ts_ck = {
+       .name           = "div_ts_ck",
+       .parent         = &l4_wkup_clk_mux_ck,
+       .clksel         = div_ts_div,
+       .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+       .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+       .ops            = &clkops_null,
+       .recalc         = &omap2_clksel_recalc,
+       .round_rate     = &omap2_clksel_round_rate,
+       .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk bandgap_ts_fclk = {
+       .name           = "bandgap_ts_fclk",
+       .ops            = &clkops_omap2_dflt,
+       .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+       .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+       .clkdm_name     = "l4_wkup_clkdm",
+       .parent         = &div_ts_ck,
+       .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_48mhz_clk = {
        .name           = "dss_48mhz_clk",
        .ops            = &clkops_omap2_dflt,
@@ -1662,6 +1639,7 @@ static struct clk gpmc_ick = {
        .ops            = &clkops_omap2_dflt,
        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "l3_2_clkdm",
        .parent         = &l3_div_ck,
        .recalc         = &followparent_recalc,
@@ -3058,9 +3036,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-       CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
-       CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
-       CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3088,14 +3063,16 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
+       CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
+       CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-       CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
-       CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-       CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-       CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+       CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+       CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+       CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+       CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3268,6 +3245,9 @@ int __init omap4xxx_clk_init(void)
        if (cpu_is_omap44xx()) {
                cpu_mask = RATE_IN_4430;
                cpu_clkflg = CK_443X;
+       } else if (cpu_is_omap446x()) {
+               cpu_mask = RATE_IN_4460;
+               cpu_clkflg = CK_446X;
        }
 
        clk_init(&omap2_clk_functions);