"pal" and "ntsc"
panel_name
tear_elim Tearing elimination 0=off, 1=on
+venc_type Output type (video encoder only): "composite" or "svideo"
There are also some debugfs files at <debugfs>/omapdss/ which show information
about clocks and registers.
Misc notes
----------
-OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
+OMAP FB allocates the framebuffer memory using the standard dma allocator. You
+can enable Contiguous Memory Allocator (CONFIG_CMA) to improve the dma
+allocator, and if CMA is enabled, you use "cma=" kernel parameter to increase
+the global memory area for CMA.
Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
Kernel boot arguments
---------------------
-vram=<size>[,<physaddr>]
- - Amount of total VRAM to preallocate and optionally a physical start
- memory address. For example, "10M". omapfb allocates memory for
- framebuffers from VRAM.
-
omapfb.mode=<display>:<mode>[,...]
- Default video mode for specified displays. For example,
"dvi:800x400MR-24@60". See drivers/video/modedb.c.
omapfb.mirror=<y|n>
- Default mirror for all framebuffers. Only works with DMA rotation.
+omapfb.vram_cache=<y|n>
+ - Sets the framebuffer memory to be write-through cached. This may be
+ useful in the configurations where only CPU is allowed to write to
+ the framebuffer and eliminate the need for enabling shadow
+ framebuffer in Xorg DDX drivers such as xf86-video-fbdev and
+ xf86-video-omapfb. Enabling write-through cache is only useful
+ for ARM11 and Cortex-A8 processors. Cortex-A9 does not support
+ write-through cache well, see "Cortex-A9 behavior for Normal Memory
+ Cacheable memory regions" section in Cortex-A9 TRM for more details.
+
omapdss.def_disp=<display>
- Name of default display, to which all overlays will be connected.
Common examples are "lcd" or "tv".