sound/soc/s3c24xx/s3c2443-ac97.c

   1 /*
   2  * s3c2443-ac97.c  --  ALSA Soc Audio Layer
   3  *
   4  * (c) 2007 Wolfson Microelectronics PLC.
   5  * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
   6  *
   7  *  Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
   8  *  All rights reserved.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/wait.h>
  21 #include <linux/delay.h>
  22 #include <linux/gpio.h>
  23 #include <linux/clk.h>
  24
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/ac97_codec.h>
  28 #include <sound/initval.h>
  29 #include <sound/soc.h>
  30
  31 #include <mach/hardware.h>
  32 #include <plat/regs-ac97.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/regs-clock.h>
  35 #include <plat/audio.h>
  36 #include <asm/dma.h>
  37 #include <mach/dma.h>
  38
  39 #include "s3c24xx-pcm.h"
  40 #include "s3c24xx-ac97.h"
  41
  42 struct s3c24xx_ac97_info {
  43         void __iomem    *regs;
  44         struct clk      *ac97_clk;
  45 };
  46 static struct s3c24xx_ac97_info s3c24xx_ac97;
  47
  48 static DECLARE_COMPLETION(ac97_completion);
  49 static u32 codec_ready;
  50 static DEFINE_MUTEX(ac97_mutex);
  51
  52 static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
  53         unsigned short reg)
  54 {
  55         u32 ac_glbctrl;
  56         u32 ac_codec_cmd;
  57         u32 stat, addr, data;
  58
  59         mutex_lock(&ac97_mutex);
  60
  61         codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  62         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  63         ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  64         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  65
  66         udelay(50);
  67
  68         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  69         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  70         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  71
  72         wait_for_completion(&ac97_completion);
  73
  74         stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
  75         addr = (stat >> 16) & 0x7f;
  76         data = (stat & 0xffff);
  77
  78         if (addr != reg)
  79                 printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
  80                                 " rep addr = %02x\n", reg, addr);
  81
  82         mutex_unlock(&ac97_mutex);
  83
  84         return (unsigned short)data;
  85 }
  86
  87 static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  88         unsigned short val)
  89 {
  90         u32 ac_glbctrl;
  91         u32 ac_codec_cmd;
  92
  93         mutex_lock(&ac97_mutex);
  94
  95         codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  96         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  97         ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  98         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  99
 100         udelay(50);
 101
 102         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 103         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
 104         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 105
 106         wait_for_completion(&ac97_completion);
 107
 108         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
 109         ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
 110         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
 111
 112         mutex_unlock(&ac97_mutex);
 113
 114 }
 115
 116 static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
 117 {
 118         u32 ac_glbctrl;
 119
 120         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 121         ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
 122         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 123         msleep(1);
 124
 125         ac_glbctrl = 0;
 126         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 127         msleep(1);
 128 }
 129
 130 static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
 131 {
 132         u32 ac_glbctrl;
 133
 134         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 135         ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
 136         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 137         msleep(1);
 138
 139         ac_glbctrl = 0;
 140         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 141         msleep(1);
 142
 143         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 144         ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
 145         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 146         msleep(1);
 147
 148         ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
 149         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 150         msleep(1);
 151
 152         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
 153                 S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
 154         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 155 }
 156
 157 static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
 158 {
 159         int status;
 160         u32 ac_glbctrl;
 161
 162         status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
 163
 164         if (status) {
 165                 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 166                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
 167                 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 168                 complete(&ac97_completion);
 169         }
 170         return IRQ_HANDLED;
 171 }
 172
 173 struct snd_ac97_bus_ops soc_ac97_ops = {
 174         .read   = s3c2443_ac97_read,
 175         .write  = s3c2443_ac97_write,
 176         .warm_reset     = s3c2443_ac97_warm_reset,
 177         .reset  = s3c2443_ac97_cold_reset,
 178 };
 179
 180 static struct s3c2410_dma_client s3c2443_dma_client_out = {
 181         .name = "AC97 PCM Stereo out"
 182 };
 183
 184 static struct s3c2410_dma_client s3c2443_dma_client_in = {
 185         .name = "AC97 PCM Stereo in"
 186 };
 187
 188 static struct s3c2410_dma_client s3c2443_dma_client_micin = {
 189         .name = "AC97 Mic Mono in"
 190 };
 191
 192 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
 193         .client         = &s3c2443_dma_client_out,
 194         .channel        = DMACH_PCM_OUT,
 195         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
 196         .dma_size       = 4,
 197 };
 198
 199 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
 200         .client         = &s3c2443_dma_client_in,
 201         .channel        = DMACH_PCM_IN,
 202         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
 203         .dma_size       = 4,
 204 };
 205
 206 static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
 207         .client         = &s3c2443_dma_client_micin,
 208         .channel        = DMACH_MIC_IN,
 209         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
 210         .dma_size       = 4,
 211 };
 212
 213 static int s3c2443_ac97_probe(struct platform_device *pdev,
 214                               struct snd_soc_dai *dai)
 215 {
 216         int ret;
 217         u32 ac_glbctrl;
 218
 219         s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
 220         if (s3c24xx_ac97.regs == NULL)
 221                 return -ENXIO;
 222
 223         s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
 224         if (s3c24xx_ac97.ac97_clk == NULL) {
 225                 printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
 226                 iounmap(s3c24xx_ac97.regs);
 227                 return -ENODEV;
 228         }
 229         clk_enable(s3c24xx_ac97.ac97_clk);
 230
 231         s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
 232         s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
 233         s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
 234         s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
 235         s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
 236
 237         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 238         ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
 239         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 240         msleep(1);
 241
 242         ac_glbctrl = 0;
 243         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 244         msleep(1);
 245
 246         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 247         ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
 248         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 249         msleep(1);
 250
 251         ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
 252         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 253
 254         ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
 255                 IRQF_DISABLED, "AC97", NULL);
 256         if (ret < 0) {
 257                 printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
 258                 clk_disable(s3c24xx_ac97.ac97_clk);
 259                 clk_put(s3c24xx_ac97.ac97_clk);
 260                 iounmap(s3c24xx_ac97.regs);
 261         }
 262         return ret;
 263 }
 264
 265 static void s3c2443_ac97_remove(struct platform_device *pdev,
 266                                 struct snd_soc_dai *dai)
 267 {
 268         free_irq(IRQ_S3C244x_AC97, NULL);
 269         clk_disable(s3c24xx_ac97.ac97_clk);
 270         clk_put(s3c24xx_ac97.ac97_clk);
 271         iounmap(s3c24xx_ac97.regs);
 272 }
 273
 274 static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
 275                                   struct snd_pcm_hw_params *params,
 276                                   struct snd_soc_dai *dai)
 277 {
 278         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 279         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 280
 281         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 282                 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
 283         else
 284                 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
 285
 286         return 0;
 287 }
 288
 289 static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
 290                                 struct snd_soc_dai *dai)
 291 {
 292         u32 ac_glbctrl;
 293         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 294         int channel = ((struct s3c24xx_pcm_dma_params *)
 295                   rtd->dai->cpu_dai->dma_data)->channel;
 296
 297         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 298         switch (cmd) {
 299         case SNDRV_PCM_TRIGGER_START:
 300         case SNDRV_PCM_TRIGGER_RESUME:
 301         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 302                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 303                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
 304                 else
 305                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
 306                 break;
 307         case SNDRV_PCM_TRIGGER_STOP:
 308         case SNDRV_PCM_TRIGGER_SUSPEND:
 309         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 310                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 311                         ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
 312                 else
 313                         ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
 314                 break;
 315         }
 316         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 317
 318         s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
 319
 320         return 0;
 321 }
 322
 323 static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
 324                                       struct snd_pcm_hw_params *params,
 325                                       struct snd_soc_dai *dai)
 326 {
 327         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 328         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 329
 330         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 331                 return -ENODEV;
 332         else
 333                 cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
 334
 335         return 0;
 336 }
 337
 338 static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
 339                                     int cmd, struct snd_soc_dai *dai)
 340 {
 341         u32 ac_glbctrl;
 342         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 343         int channel = ((struct s3c24xx_pcm_dma_params *)
 344                   rtd->dai->cpu_dai->dma_data)->channel;
 345
 346         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 347         switch (cmd) {
 348         case SNDRV_PCM_TRIGGER_START:
 349         case SNDRV_PCM_TRIGGER_RESUME:
 350         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 351                 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
 352                 break;
 353         case SNDRV_PCM_TRIGGER_STOP:
 354         case SNDRV_PCM_TRIGGER_SUSPEND:
 355         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 356                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
 357         }
 358         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 359
 360         s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
 361
 362         return 0;
 363 }
 364
 365 #define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 366                 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
 367                 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 368
 369 static struct snd_soc_dai_ops s3c2443_ac97_dai_ops = {
 370         .hw_params      = s3c2443_ac97_hw_params,
 371         .trigger        = s3c2443_ac97_trigger,
 372 };
 373
 374 static struct snd_soc_dai_ops s3c2443_ac97_mic_dai_ops = {
 375         .hw_params      = s3c2443_ac97_hw_mic_params,
 376         .trigger        = s3c2443_ac97_mic_trigger,
 377 };
 378
 379 struct snd_soc_dai s3c2443_ac97_dai[] = {
 380 {
 381         .name = "s3c2443-ac97",
 382         .id = 0,
 383         .ac97_control = 1,
 384         .probe = s3c2443_ac97_probe,
 385         .remove = s3c2443_ac97_remove,
 386         .playback = {
 387                 .stream_name = "AC97 Playback",
 388                 .channels_min = 2,
 389                 .channels_max = 2,
 390                 .rates = s3c2443_AC97_RATES,
 391                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 392         .capture = {
 393                 .stream_name = "AC97 Capture",
 394                 .channels_min = 2,
 395                 .channels_max = 2,
 396                 .rates = s3c2443_AC97_RATES,
 397                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 398         .ops = &s3c2443_ac97_dai_ops,
 399 },
 400 {
 401         .name = "pxa2xx-ac97-mic",
 402         .id = 1,
 403         .ac97_control = 1,
 404         .capture = {
 405                 .stream_name = "AC97 Mic Capture",
 406                 .channels_min = 1,
 407                 .channels_max = 1,
 408                 .rates = s3c2443_AC97_RATES,
 409                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 410         .ops = &s3c2443_ac97_mic_dai_ops,
 411 },
 412 };
 413 EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
 414 EXPORT_SYMBOL_GPL(soc_ac97_ops);
 415
 416 static int __init s3c2443_ac97_init(void)
 417 {
 418         return snd_soc_register_dais(s3c2443_ac97_dai,
 419                                      ARRAY_SIZE(s3c2443_ac97_dai));
 420 }
 421 module_init(s3c2443_ac97_init);
 422
 423 static void __exit s3c2443_ac97_exit(void)
 424 {
 425         snd_soc_unregister_dais(s3c2443_ac97_dai,
 426                                 ARRAY_SIZE(s3c2443_ac97_dai));
 427 }
 428 module_exit(s3c2443_ac97_exit);
 429
 430
 431 MODULE_AUTHOR("Graeme Gregory");
 432 MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
 433 MODULE_LICENSE("GPL");