2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
31 #include "davinci-pcm.h"
32 #include "davinci-mcasp.h"
35 * McASP register definitions
37 #define DAVINCI_MCASP_PID_REG 0x00
38 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
40 #define DAVINCI_MCASP_PFUNC_REG 0x10
41 #define DAVINCI_MCASP_PDIR_REG 0x14
42 #define DAVINCI_MCASP_PDOUT_REG 0x18
43 #define DAVINCI_MCASP_PDSET_REG 0x1c
45 #define DAVINCI_MCASP_PDCLR_REG 0x20
47 #define DAVINCI_MCASP_TLGC_REG 0x30
48 #define DAVINCI_MCASP_TLMR_REG 0x34
50 #define DAVINCI_MCASP_GBLCTL_REG 0x44
51 #define DAVINCI_MCASP_AMUTE_REG 0x48
52 #define DAVINCI_MCASP_LBCTL_REG 0x4c
54 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
56 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
57 #define DAVINCI_MCASP_RXMASK_REG 0x64
58 #define DAVINCI_MCASP_RXFMT_REG 0x68
59 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
61 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
62 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
63 #define DAVINCI_MCASP_RXTDM_REG 0x78
64 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
66 #define DAVINCI_MCASP_RXSTAT_REG 0x80
67 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
68 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
69 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
71 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
72 #define DAVINCI_MCASP_TXMASK_REG 0xa4
73 #define DAVINCI_MCASP_TXFMT_REG 0xa8
74 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
76 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
77 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
78 #define DAVINCI_MCASP_TXTDM_REG 0xb8
79 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
81 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
82 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
83 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
84 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
86 /* Left(even TDM Slot) Channel Status Register File */
87 #define DAVINCI_MCASP_DITCSRA_REG 0x100
88 /* Right(odd TDM slot) Channel Status Register File */
89 #define DAVINCI_MCASP_DITCSRB_REG 0x118
90 /* Left(even TDM slot) User Data Register File */
91 #define DAVINCI_MCASP_DITUDRA_REG 0x130
92 /* Right(odd TDM Slot) User Data Register File */
93 #define DAVINCI_MCASP_DITUDRB_REG 0x148
95 /* Serializer n Control Register */
96 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
97 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
100 /* Transmit Buffer for Serializer n */
101 #define DAVINCI_MCASP_TXBUF_REG 0x200
102 /* Receive Buffer for Serializer n */
103 #define DAVINCI_MCASP_RXBUF_REG 0x280
107 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
110 #define MCASP_FREE BIT(0)
111 #define MCASP_SOFT BIT(1)
114 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
116 #define AXR(n) (1<<n)
117 #define PFUNC_AMUTE BIT(25)
118 #define ACLKX BIT(26)
119 #define AHCLKX BIT(27)
121 #define ACLKR BIT(29)
122 #define AHCLKR BIT(30)
126 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
128 #define AXR(n) (1<<n)
129 #define PDIR_AMUTE BIT(25)
130 #define ACLKX BIT(26)
131 #define AHCLKX BIT(27)
133 #define ACLKR BIT(29)
134 #define AHCLKR BIT(30)
138 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
140 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
145 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
147 #define TXROT(val) (val)
149 #define TXSSZ(val) (val<<4)
150 #define TXPBIT(val) (val<<8)
151 #define TXPAD(val) (val<<13)
152 #define TXORD BIT(15)
153 #define FSXDLY(val) (val<<16)
156 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
158 #define RXROT(val) (val)
160 #define RXSSZ(val) (val<<4)
161 #define RXPBIT(val) (val<<8)
162 #define RXPAD(val) (val<<13)
163 #define RXORD BIT(15)
164 #define FSRDLY(val) (val<<16)
167 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
169 #define FSXPOL BIT(0)
171 #define FSXDUR BIT(4)
172 #define FSXMOD(val) (val<<7)
175 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
177 #define FSRPOL BIT(0)
179 #define FSRDUR BIT(4)
180 #define FSRMOD(val) (val<<7)
183 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
185 #define ACLKXDIV(val) (val)
186 #define ACLKXE BIT(5)
187 #define TX_ASYNC BIT(6)
188 #define ACLKXPOL BIT(7)
191 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
193 #define ACLKRDIV(val) (val)
194 #define ACLKRE BIT(5)
195 #define RX_ASYNC BIT(6)
196 #define ACLKRPOL BIT(7)
199 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
202 #define AHCLKXDIV(val) (val)
203 #define AHCLKXPOL BIT(14)
204 #define AHCLKXE BIT(15)
207 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
210 #define AHCLKRDIV(val) (val)
211 #define AHCLKRPOL BIT(14)
212 #define AHCLKRE BIT(15)
215 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
217 #define MODE(val) (val)
218 #define DISMOD (val)(val<<2)
219 #define TXSTATE BIT(4)
220 #define RXSTATE BIT(5)
223 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
227 #define LBGENMODE(val) (val<<2)
230 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
232 #define TXTDMS(n) (1<<n)
235 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
237 #define RXTDMS(n) (1<<n)
240 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
242 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
243 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
244 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
245 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
246 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
247 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
248 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
249 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
250 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
251 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
254 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
256 #define MUTENA(val) (val)
257 #define MUTEINPOL BIT(2)
258 #define MUTEINENA BIT(3)
259 #define MUTEIN BIT(4)
262 #define MUTEFSR BIT(7)
263 #define MUTEFSX BIT(8)
264 #define MUTEBADCLKR BIT(9)
265 #define MUTEBADCLKX BIT(10)
266 #define MUTERXDMAERR BIT(11)
267 #define MUTETXDMAERR BIT(12)
270 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
272 #define RXDATADMADIS BIT(0)
275 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
277 #define TXDATADMADIS BIT(0)
279 #define DAVINCI_MCASP_NUM_SERIALIZER 16
281 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
283 __raw_writel(__raw_readl(reg) | val, reg);
286 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
288 __raw_writel((__raw_readl(reg) & ~(val)), reg);
291 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
293 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
296 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
298 __raw_writel(val, reg);
301 static inline u32 mcasp_get_reg(void __iomem *reg)
303 return (unsigned int)__raw_readl(reg);
306 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
310 mcasp_set_bits(regs, val);
312 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
313 /* loop count is to avoid the lock-up */
314 for (i = 0; i < 1000; i++) {
315 if ((mcasp_get_reg(regs) & val) == val)
319 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
320 printk(KERN_ERR "GBLCTL write error\n");
323 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
324 struct snd_soc_dai *cpu_dai)
326 struct davinci_audio_dev *dev = cpu_dai->private_data;
327 cpu_dai->dma_data = dev->dma_params[substream->stream];
331 static void mcasp_start_rx(struct davinci_audio_dev *dev)
333 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
334 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
335 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
336 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
340 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
342 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
346 static void mcasp_start_tx(struct davinci_audio_dev *dev)
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
349 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
351 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
353 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
355 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
356 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
359 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
361 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
367 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
369 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
373 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
375 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
379 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
381 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
387 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
390 struct davinci_audio_dev *dev = cpu_dai->private_data;
391 void __iomem *base = dev->base;
393 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
394 case SND_SOC_DAIFMT_CBS_CFS:
395 /* codec is clock and frame slave */
396 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
397 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
399 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
400 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
402 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
405 case SND_SOC_DAIFMT_CBM_CFM:
406 /* codec is clock and frame master */
407 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
408 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
410 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
411 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
413 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
420 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
421 case SND_SOC_DAIFMT_IB_NF:
422 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
423 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
425 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
426 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
429 case SND_SOC_DAIFMT_NB_IF:
430 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
431 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
433 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
434 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
437 case SND_SOC_DAIFMT_IB_IF:
438 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
439 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
442 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
445 case SND_SOC_DAIFMT_NB_NF:
446 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
447 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
449 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
450 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
460 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
465 switch (channel_size) {
466 case DAVINCI_AUDIO_WORD_8:
470 case DAVINCI_AUDIO_WORD_12:
474 case DAVINCI_AUDIO_WORD_16:
478 case DAVINCI_AUDIO_WORD_20:
482 case DAVINCI_AUDIO_WORD_24:
486 case DAVINCI_AUDIO_WORD_28:
490 case DAVINCI_AUDIO_WORD_32:
498 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
499 RXSSZ(fmt), RXSSZ(0x0F));
500 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
501 TXSSZ(fmt), TXSSZ(0x0F));
505 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
509 /* Default configuration */
510 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
512 /* All PINS as McASP */
513 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
515 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
516 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
517 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
520 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
521 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
525 for (i = 0; i < dev->num_serializer; i++) {
526 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
528 if (dev->serial_dir[i] == TX_MODE)
529 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
531 else if (dev->serial_dir[i] == RX_MODE)
532 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
537 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
542 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
543 for (i = 0; i < active_slots; i++)
546 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
547 /* bit stream is MSB first with no delay */
549 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
551 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
552 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
554 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
555 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
556 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
558 printk(KERN_ERR "playback tdm slot %d not supported\n",
561 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF);
562 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
564 /* bit stream is MSB first with no delay */
566 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
567 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
569 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
571 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
572 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
573 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
575 printk(KERN_ERR "capture tdm slot %d not supported\n",
578 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF);
579 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
584 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
586 /* Set the PDIR for Serialiser as output */
587 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
589 /* TXMASK for 24 bits */
590 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
592 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
594 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
595 TXROT(6) | TXSSZ(15));
597 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
598 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
599 AFSXE | FSXMOD(0x180));
601 /* Set the TX tdm : for all the slots */
602 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
604 /* Set the TX clock controls : div = 1 and internal */
605 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
608 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
610 /* Only 44100 and 48000 are valid, both have the same setting */
611 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
614 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
617 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
618 struct snd_pcm_hw_params *params,
619 struct snd_soc_dai *cpu_dai)
621 struct davinci_audio_dev *dev = cpu_dai->private_data;
622 struct davinci_pcm_dma_params *dma_params =
623 dev->dma_params[substream->stream];
626 davinci_hw_common_param(dev, substream->stream);
628 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
629 davinci_hw_dit_param(dev);
631 davinci_hw_param(dev, substream->stream);
633 switch (params_format(params)) {
634 case SNDRV_PCM_FORMAT_S8:
635 dma_params->data_type = 1;
636 word_length = DAVINCI_AUDIO_WORD_8;
639 case SNDRV_PCM_FORMAT_S16_LE:
640 dma_params->data_type = 2;
641 word_length = DAVINCI_AUDIO_WORD_16;
644 case SNDRV_PCM_FORMAT_S32_LE:
645 dma_params->data_type = 4;
646 word_length = DAVINCI_AUDIO_WORD_32;
650 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
653 davinci_config_channel_size(dev, word_length);
658 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
659 int cmd, struct snd_soc_dai *cpu_dai)
661 struct snd_soc_pcm_runtime *rtd = substream->private_data;
662 struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
666 case SNDRV_PCM_TRIGGER_START:
667 case SNDRV_PCM_TRIGGER_RESUME:
668 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
669 davinci_mcasp_start(dev, substream->stream);
672 case SNDRV_PCM_TRIGGER_STOP:
673 case SNDRV_PCM_TRIGGER_SUSPEND:
674 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
675 davinci_mcasp_stop(dev, substream->stream);
685 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
686 .startup = davinci_mcasp_startup,
687 .trigger = davinci_mcasp_trigger,
688 .hw_params = davinci_mcasp_hw_params,
689 .set_fmt = davinci_mcasp_set_dai_fmt,
693 struct snd_soc_dai davinci_mcasp_dai[] = {
695 .name = "davinci-i2s",
700 .rates = DAVINCI_MCASP_RATES,
701 .formats = SNDRV_PCM_FMTBIT_S8 |
702 SNDRV_PCM_FMTBIT_S16_LE |
703 SNDRV_PCM_FMTBIT_S32_LE,
708 .rates = DAVINCI_MCASP_RATES,
709 .formats = SNDRV_PCM_FMTBIT_S8 |
710 SNDRV_PCM_FMTBIT_S16_LE |
711 SNDRV_PCM_FMTBIT_S32_LE,
713 .ops = &davinci_mcasp_dai_ops,
717 .name = "davinci-dit",
722 .rates = DAVINCI_MCASP_RATES,
723 .formats = SNDRV_PCM_FMTBIT_S16_LE,
725 .ops = &davinci_mcasp_dai_ops,
729 EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
731 static int davinci_mcasp_probe(struct platform_device *pdev)
733 struct davinci_pcm_dma_params *dma_data;
734 struct resource *mem, *ioarea, *res;
735 struct snd_platform_data *pdata;
736 struct davinci_audio_dev *dev;
740 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
744 dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * 2,
748 goto err_release_dev;
751 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753 dev_err(&pdev->dev, "no mem resource?\n");
755 goto err_release_data;
758 ioarea = request_mem_region(mem->start,
759 (mem->end - mem->start) + 1, pdev->name);
761 dev_err(&pdev->dev, "Audio region already claimed\n");
763 goto err_release_data;
766 pdata = pdev->dev.platform_data;
767 dev->clk = clk_get(&pdev->dev, NULL);
768 if (IS_ERR(dev->clk)) {
770 goto err_release_region;
773 clk_enable(dev->clk);
775 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
776 dev->op_mode = pdata->op_mode;
777 dev->tdm_slots = pdata->tdm_slots;
778 dev->num_serializer = pdata->num_serializer;
779 dev->serial_dir = pdata->serial_dir;
780 dev->codec_fmt = pdata->codec_fmt;
782 dma_data[count].name = "I2S PCM Stereo out";
783 dma_data[count].eventq_no = pdata->eventq_no;
784 dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
786 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &dma_data[count];
788 /* first TX, then RX */
789 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
791 dev_err(&pdev->dev, "no DMA resource\n");
792 goto err_release_region;
795 dma_data[count].channel = res->start;
797 dma_data[count].name = "I2S PCM Stereo in";
798 dma_data[count].eventq_no = pdata->eventq_no;
799 dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
801 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &dma_data[count];
803 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
805 dev_err(&pdev->dev, "no DMA resource\n");
806 goto err_release_region;
809 dma_data[count].channel = res->start;
810 davinci_mcasp_dai[pdev->id].private_data = dev;
811 davinci_mcasp_dai[pdev->id].dev = &pdev->dev;
812 ret = snd_soc_register_dai(&davinci_mcasp_dai[pdev->id]);
815 goto err_release_region;
819 release_mem_region(mem->start, (mem->end - mem->start) + 1);
828 static int davinci_mcasp_remove(struct platform_device *pdev)
830 struct davinci_pcm_dma_params *dma_data;
831 struct davinci_audio_dev *dev;
832 struct resource *mem;
834 snd_soc_unregister_dai(&davinci_mcasp_dai[pdev->id]);
835 dev = davinci_mcasp_dai[pdev->id].private_data;
836 clk_disable(dev->clk);
840 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841 release_mem_region(mem->start, (mem->end - mem->start) + 1);
843 dma_data = dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
850 static struct platform_driver davinci_mcasp_driver = {
851 .probe = davinci_mcasp_probe,
852 .remove = davinci_mcasp_remove,
854 .name = "davinci-mcasp",
855 .owner = THIS_MODULE,
859 static int __init davinci_mcasp_init(void)
861 return platform_driver_register(&davinci_mcasp_driver);
863 module_init(davinci_mcasp_init);
865 static void __exit davinci_mcasp_exit(void)
867 platform_driver_unregister(&davinci_mcasp_driver);
869 module_exit(davinci_mcasp_exit);
871 MODULE_AUTHOR("Steve Chen");
872 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
873 MODULE_LICENSE("GPL");