2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
25 #include "davinci-pcm.h"
29 * NOTE: terminology here is confusing.
31 * - This driver supports the "Audio Serial Port" (ASP),
32 * found on dm6446, dm355, and other DaVinci chips.
34 * - But it labels it a "Multi-channel Buffered Serial Port"
35 * (McBSP) as on older chips like the dm642 ... which was
36 * backward-compatible, possibly explaining that confusion.
38 * - OMAP chips have a controller called McBSP, which is
39 * incompatible with the DaVinci flavor of McBSP.
41 * - Newer DaVinci chips have a controller called McASP,
42 * incompatible with ASP and with either McBSP.
44 * In short: this uses ASP to implement I2S, not McBSP.
45 * And it won't be the only DaVinci implemention of I2S.
47 #define DAVINCI_MCBSP_DRR_REG 0x00
48 #define DAVINCI_MCBSP_DXR_REG 0x04
49 #define DAVINCI_MCBSP_SPCR_REG 0x08
50 #define DAVINCI_MCBSP_RCR_REG 0x0c
51 #define DAVINCI_MCBSP_XCR_REG 0x10
52 #define DAVINCI_MCBSP_SRGR_REG 0x14
53 #define DAVINCI_MCBSP_PCR_REG 0x24
55 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
56 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
57 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
58 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
59 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
60 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
61 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
65 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
66 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
68 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
69 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
70 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
71 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
72 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
74 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
75 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
76 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
78 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
79 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
80 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
81 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
82 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
83 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
84 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
85 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
86 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
89 DAVINCI_MCBSP_WORD_8 = 0,
90 DAVINCI_MCBSP_WORD_12,
91 DAVINCI_MCBSP_WORD_16,
92 DAVINCI_MCBSP_WORD_20,
93 DAVINCI_MCBSP_WORD_24,
94 DAVINCI_MCBSP_WORD_32,
97 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
98 .name = "I2S PCM Stereo out",
101 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
102 .name = "I2S PCM Stereo in",
105 struct davinci_mcbsp_dev {
108 struct davinci_pcm_dma_params *dma_params[2];
111 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
114 __raw_writel(val, dev->base + reg);
117 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
119 return __raw_readl(dev->base + reg);
122 static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
124 struct snd_soc_pcm_runtime *rtd = substream->private_data;
125 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
126 struct snd_soc_device *socdev = rtd->socdev;
127 struct snd_soc_platform *platform = socdev->card->platform;
131 /* Start the sample generator and enable transmitter/receiver */
132 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
133 spcr |= DAVINCI_MCBSP_SPCR_GRST;
134 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
136 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
137 /* Stop the DMA to avoid data loss */
138 /* while the transmitter is out of reset to handle XSYNCERR */
139 if (platform->pcm_ops->trigger) {
140 ret = platform->pcm_ops->trigger(substream,
141 SNDRV_PCM_TRIGGER_STOP);
143 printk(KERN_DEBUG "Playback DMA stop failed\n");
146 /* Enable the transmitter */
147 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
148 spcr |= DAVINCI_MCBSP_SPCR_XRST;
149 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
151 /* wait for any unexpected frame sync error to occur */
154 /* Disable the transmitter to clear any outstanding XSYNCERR */
155 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
156 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
157 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
159 /* Restart the DMA */
160 if (platform->pcm_ops->trigger) {
161 ret = platform->pcm_ops->trigger(substream,
162 SNDRV_PCM_TRIGGER_START);
164 printk(KERN_DEBUG "Playback DMA start failed\n");
166 /* Enable the transmitter */
167 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
168 spcr |= DAVINCI_MCBSP_SPCR_XRST;
169 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
173 /* Enable the reciever */
174 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
175 spcr |= DAVINCI_MCBSP_SPCR_RRST;
176 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
180 /* Start frame sync */
181 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
182 spcr |= DAVINCI_MCBSP_SPCR_FRST;
183 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
186 static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
188 struct snd_soc_pcm_runtime *rtd = substream->private_data;
189 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
192 /* Reset transmitter/receiver and sample rate/frame sync generators */
193 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
194 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
196 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
198 spcr &= ~DAVINCI_MCBSP_SPCR_RRST;
199 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
202 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
203 struct snd_soc_dai *dai)
205 struct snd_soc_pcm_runtime *rtd = substream->private_data;
206 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
207 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
209 cpu_dai->dma_data = dev->dma_params[substream->stream];
214 #define DEFAULT_BITPERSAMPLE 16
216 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
219 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
224 srgr = DAVINCI_MCBSP_SRGR_FSGM |
225 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
226 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
228 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
229 case SND_SOC_DAIFMT_CBS_CFS:
231 pcr = DAVINCI_MCBSP_PCR_FSXM |
232 DAVINCI_MCBSP_PCR_FSRM |
233 DAVINCI_MCBSP_PCR_CLKXM |
234 DAVINCI_MCBSP_PCR_CLKRM;
236 case SND_SOC_DAIFMT_CBM_CFS:
237 /* McBSP CLKR pin is the input for the Sample Rate Generator.
238 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
239 pcr = DAVINCI_MCBSP_PCR_SCLKME |
240 DAVINCI_MCBSP_PCR_FSXM |
241 DAVINCI_MCBSP_PCR_FSRM;
243 case SND_SOC_DAIFMT_CBM_CFM:
244 /* codec is master */
248 printk(KERN_ERR "%s:bad master\n", __func__);
252 rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
253 xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
254 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
255 case SND_SOC_DAIFMT_DSP_B:
257 case SND_SOC_DAIFMT_I2S:
258 /* Davinci doesn't support TRUE I2S, but some codecs will have
259 * the left and right channels contiguous. This allows
260 * dsp_a mode to be used with an inverted normal frame clk.
261 * If your codec is master and does not have contiguous
262 * channels, then you will have sound on only one channel.
263 * Try using a different mode, or codec as slave.
265 * The TLV320AIC33 is an example of a codec where this works.
266 * It has a variable bit clock frequency allowing it to have
267 * valid data on every bit clock.
269 * The TLV320AIC23 is an example of a codec where this does not
270 * work. It has a fixed bit clock frequency with progressively
271 * more empty bit clock slots between channels as the sample
274 fmt ^= SND_SOC_DAIFMT_NB_IF;
275 case SND_SOC_DAIFMT_DSP_A:
276 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
277 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
280 printk(KERN_ERR "%s:bad format\n", __func__);
284 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
285 case SND_SOC_DAIFMT_NB_NF:
286 /* CLKRP Receive clock polarity,
287 * 1 - sampled on rising edge of CLKR
288 * valid on rising edge
289 * CLKXP Transmit clock polarity,
290 * 1 - clocked on falling edge of CLKX
291 * valid on rising edge
292 * FSRP Receive frame sync pol, 0 - active high
293 * FSXP Transmit frame sync pol, 0 - active high
295 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
297 case SND_SOC_DAIFMT_IB_IF:
298 /* CLKRP Receive clock polarity,
299 * 0 - sampled on falling edge of CLKR
300 * valid on falling edge
301 * CLKXP Transmit clock polarity,
302 * 0 - clocked on rising edge of CLKX
303 * valid on falling edge
304 * FSRP Receive frame sync pol, 1 - active low
305 * FSXP Transmit frame sync pol, 1 - active low
307 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
309 case SND_SOC_DAIFMT_NB_IF:
310 /* CLKRP Receive clock polarity,
311 * 1 - sampled on rising edge of CLKR
312 * valid on rising edge
313 * CLKXP Transmit clock polarity,
314 * 1 - clocked on falling edge of CLKX
315 * valid on rising edge
316 * FSRP Receive frame sync pol, 1 - active low
317 * FSXP Transmit frame sync pol, 1 - active low
319 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
320 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
322 case SND_SOC_DAIFMT_IB_NF:
323 /* CLKRP Receive clock polarity,
324 * 0 - sampled on falling edge of CLKR
325 * valid on falling edge
326 * CLKXP Transmit clock polarity,
327 * 0 - clocked on rising edge of CLKX
328 * valid on falling edge
329 * FSRP Receive frame sync pol, 0 - active high
330 * FSXP Transmit frame sync pol, 0 - active high
336 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
337 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
338 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
339 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
343 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
344 struct snd_pcm_hw_params *params,
345 struct snd_soc_dai *dai)
347 struct snd_soc_pcm_runtime *rtd = substream->private_data;
348 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
349 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
350 struct snd_interval *i = NULL;
351 int mcbsp_word_length;
352 unsigned int rcr, xcr, srgr;
355 /* general line settings */
356 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
357 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
358 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
359 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
361 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
362 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
365 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
366 srgr = DAVINCI_MCBSP_SRGR_FSGM;
367 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
369 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
370 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
371 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
373 /* Determine xfer data type */
374 switch (params_format(params)) {
375 case SNDRV_PCM_FORMAT_S8:
376 dma_params->data_type = 1;
377 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
379 case SNDRV_PCM_FORMAT_S16_LE:
380 dma_params->data_type = 2;
381 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
383 case SNDRV_PCM_FORMAT_S32_LE:
384 dma_params->data_type = 4;
385 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
388 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
392 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
393 rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
394 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
395 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
396 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
399 xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
400 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
401 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
402 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
408 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
409 struct snd_soc_dai *dai)
414 case SNDRV_PCM_TRIGGER_START:
415 case SNDRV_PCM_TRIGGER_RESUME:
416 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
417 davinci_mcbsp_start(substream);
419 case SNDRV_PCM_TRIGGER_STOP:
420 case SNDRV_PCM_TRIGGER_SUSPEND:
421 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
422 davinci_mcbsp_stop(substream);
431 static int davinci_i2s_probe(struct platform_device *pdev,
432 struct snd_soc_dai *dai)
434 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
435 struct snd_soc_card *card = socdev->card;
436 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
437 struct davinci_mcbsp_dev *dev;
438 struct resource *mem, *ioarea;
439 struct evm_snd_platform_data *pdata;
442 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 dev_err(&pdev->dev, "no mem resource?\n");
448 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
451 dev_err(&pdev->dev, "McBSP region already claimed\n");
455 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
458 goto err_release_region;
461 cpu_dai->private_data = dev;
463 dev->clk = clk_get(&pdev->dev, NULL);
464 if (IS_ERR(dev->clk)) {
468 clk_enable(dev->clk);
470 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
471 pdata = pdev->dev.platform_data;
473 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
474 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
475 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
476 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
478 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
479 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
480 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
481 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
488 release_mem_region(mem->start, (mem->end - mem->start) + 1);
493 static void davinci_i2s_remove(struct platform_device *pdev,
494 struct snd_soc_dai *dai)
496 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
497 struct snd_soc_card *card = socdev->card;
498 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
499 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
500 struct resource *mem;
502 clk_disable(dev->clk);
508 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
509 release_mem_region(mem->start, (mem->end - mem->start) + 1);
512 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
514 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
515 .startup = davinci_i2s_startup,
516 .trigger = davinci_i2s_trigger,
517 .hw_params = davinci_i2s_hw_params,
518 .set_fmt = davinci_i2s_set_dai_fmt,
521 struct snd_soc_dai davinci_i2s_dai = {
522 .name = "davinci-i2s",
524 .probe = davinci_i2s_probe,
525 .remove = davinci_i2s_remove,
529 .rates = DAVINCI_I2S_RATES,
530 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
534 .rates = DAVINCI_I2S_RATES,
535 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
536 .ops = &davinci_i2s_dai_ops,
538 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
540 static int __init davinci_i2s_init(void)
542 return snd_soc_register_dai(&davinci_i2s_dai);
544 module_init(davinci_i2s_init);
546 static void __exit davinci_i2s_exit(void)
548 snd_soc_unregister_dai(&davinci_i2s_dai);
550 module_exit(davinci_i2s_exit);
552 MODULE_AUTHOR("Vladimir Barinov");
553 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
554 MODULE_LICENSE("GPL");