sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static struct {
  45         unsigned int reg;
  46         unsigned int mask;
  47 } wm8994_vu_bits[] = {
  48         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  49         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  50         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  51         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  52         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  53         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  54         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  55         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  56         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  57         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  58
  59         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  60         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  61         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  62         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  63         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  64         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  65         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  66         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  67         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  68         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  69         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  70         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  71         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  72         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  73         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  74         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  75 };
  76
  77 static int wm8994_drc_base[] = {
  78         WM8994_AIF1_DRC1_1,
  79         WM8994_AIF1_DRC2_1,
  80         WM8994_AIF2_DRC_1,
  81 };
  82
  83 static int wm8994_retune_mobile_base[] = {
  84         WM8994_AIF1_DAC1_EQ_GAINS_1,
  85         WM8994_AIF1_DAC2_EQ_GAINS_1,
  86         WM8994_AIF2_EQ_GAINS_1,
  87 };
  88
  89 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  90 {
  91         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  92         struct wm8994 *control = codec->control_data;
  93
  94         switch (reg) {
  95         case WM8994_GPIO_1:
  96         case WM8994_GPIO_2:
  97         case WM8994_GPIO_3:
  98         case WM8994_GPIO_4:
  99         case WM8994_GPIO_5:
 100         case WM8994_GPIO_6:
 101         case WM8994_GPIO_7:
 102         case WM8994_GPIO_8:
 103         case WM8994_GPIO_9:
 104         case WM8994_GPIO_10:
 105         case WM8994_GPIO_11:
 106         case WM8994_INTERRUPT_STATUS_1:
 107         case WM8994_INTERRUPT_STATUS_2:
 108         case WM8994_INTERRUPT_RAW_STATUS_2:
 109                 return 1;
 110
 111         case WM8958_DSP2_PROGRAM:
 112         case WM8958_DSP2_CONFIG:
 113         case WM8958_DSP2_EXECCONTROL:
 114                 if (control->type == WM8958)
 115                         return 1;
 116                 else
 117                         return 0;
 118
 119         default:
 120                 break;
 121         }
 122
 123         if (reg >= WM8994_CACHE_SIZE)
 124                 return 0;
 125         return wm8994_access_masks[reg].readable != 0;
 126 }
 127
 128 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
 129 {
 130         if (reg >= WM8994_CACHE_SIZE)
 131                 return 1;
 132
 133         switch (reg) {
 134         case WM8994_SOFTWARE_RESET:
 135         case WM8994_CHIP_REVISION:
 136         case WM8994_DC_SERVO_1:
 137         case WM8994_DC_SERVO_READBACK:
 138         case WM8994_RATE_STATUS:
 139         case WM8994_LDO_1:
 140         case WM8994_LDO_2:
 141         case WM8958_DSP2_EXECCONTROL:
 142         case WM8958_MIC_DETECT_3:
 143         case WM8994_DC_SERVO_4E:
 144                 return 1;
 145         default:
 146                 return 0;
 147         }
 148 }
 149
 150 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 151         unsigned int value)
 152 {
 153         int ret;
 154
 155         BUG_ON(reg > WM8994_MAX_REGISTER);
 156
 157         if (!wm8994_volatile(codec, reg)) {
 158                 ret = snd_soc_cache_write(codec, reg, value);
 159                 if (ret != 0)
 160                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 161                                 reg, ret);
 162         }
 163
 164         return wm8994_reg_write(codec->control_data, reg, value);
 165 }
 166
 167 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 168                                 unsigned int reg)
 169 {
 170         unsigned int val;
 171         int ret;
 172
 173         BUG_ON(reg > WM8994_MAX_REGISTER);
 174
 175         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 176             reg < codec->driver->reg_cache_size) {
 177                 ret = snd_soc_cache_read(codec, reg, &val);
 178                 if (ret >= 0)
 179                         return val;
 180                 else
 181                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 182                                 reg, ret);
 183         }
 184
 185         return wm8994_reg_read(codec->control_data, reg);
 186 }
 187
 188 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 189 {
 190         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 191         int rate;
 192         int reg1 = 0;
 193         int offset;
 194
 195         if (aif)
 196                 offset = 4;
 197         else
 198                 offset = 0;
 199
 200         switch (wm8994->sysclk[aif]) {
 201         case WM8994_SYSCLK_MCLK1:
 202                 rate = wm8994->mclk[0];
 203                 break;
 204
 205         case WM8994_SYSCLK_MCLK2:
 206                 reg1 |= 0x8;
 207                 rate = wm8994->mclk[1];
 208                 break;
 209
 210         case WM8994_SYSCLK_FLL1:
 211                 reg1 |= 0x10;
 212                 rate = wm8994->fll[0].out;
 213                 break;
 214
 215         case WM8994_SYSCLK_FLL2:
 216                 reg1 |= 0x18;
 217                 rate = wm8994->fll[1].out;
 218                 break;
 219
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         if (rate >= 13500000) {
 225                 rate /= 2;
 226                 reg1 |= WM8994_AIF1CLK_DIV;
 227
 228                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 229                         aif + 1, rate);
 230         }
 231
 232         wm8994->aifclk[aif] = rate;
 233
 234         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 235                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 236                             reg1);
 237
 238         return 0;
 239 }
 240
 241 static int configure_clock(struct snd_soc_codec *codec)
 242 {
 243         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 244         int change, new;
 245
 246         /* Bring up the AIF clocks first */
 247         configure_aif_clock(codec, 0);
 248         configure_aif_clock(codec, 1);
 249
 250         /* Then switch CLK_SYS over to the higher of them; a change
 251          * can only happen as a result of a clocking change which can
 252          * only be made outside of DAPM so we can safely redo the
 253          * clocking.
 254          */
 255
 256         /* If they're equal it doesn't matter which is used */
 257         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 258                 return 0;
 259
 260         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 261                 new = WM8994_SYSCLK_SRC;
 262         else
 263                 new = 0;
 264
 265         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 266                                      WM8994_SYSCLK_SRC, new);
 267         if (!change)
 268                 return 0;
 269
 270         snd_soc_dapm_sync(&codec->dapm);
 271
 272         return 0;
 273 }
 274
 275 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 276                          struct snd_soc_dapm_widget *sink)
 277 {
 278         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 279         const char *clk;
 280
 281         /* Check what we're currently using for CLK_SYS */
 282         if (reg & WM8994_SYSCLK_SRC)
 283                 clk = "AIF2CLK";
 284         else
 285                 clk = "AIF1CLK";
 286
 287         return strcmp(source->name, clk) == 0;
 288 }
 289
 290 static const char *sidetone_hpf_text[] = {
 291         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 292 };
 293
 294 static const struct soc_enum sidetone_hpf =
 295         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 296
 297 static const char *adc_hpf_text[] = {
 298         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 299 };
 300
 301 static const struct soc_enum aif1adc1_hpf =
 302         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 303
 304 static const struct soc_enum aif1adc2_hpf =
 305         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 306
 307 static const struct soc_enum aif2adc_hpf =
 308         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 309
 310 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 311 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 312 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 313 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 314 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 315 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 316 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 317
 318 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 319 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 320         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 321         .put = wm8994_put_drc_sw, \
 322         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 323
 324 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 325                              struct snd_ctl_elem_value *ucontrol)
 326 {
 327         struct soc_mixer_control *mc =
 328                 (struct soc_mixer_control *)kcontrol->private_value;
 329         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 330         int mask, ret;
 331
 332         /* Can't enable both ADC and DAC paths simultaneously */
 333         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 334                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 335                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 336         else
 337                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 338
 339         ret = snd_soc_read(codec, mc->reg);
 340         if (ret < 0)
 341                 return ret;
 342         if (ret & mask)
 343                 return -EINVAL;
 344
 345         return snd_soc_put_volsw(kcontrol, ucontrol);
 346 }
 347
 348 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 349 {
 350         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 351         struct wm8994_pdata *pdata = wm8994->pdata;
 352         int base = wm8994_drc_base[drc];
 353         int cfg = wm8994->drc_cfg[drc];
 354         int save, i;
 355
 356         /* Save any enables; the configuration should clear them. */
 357         save = snd_soc_read(codec, base);
 358         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 359                 WM8994_AIF1ADC1R_DRC_ENA;
 360
 361         for (i = 0; i < WM8994_DRC_REGS; i++)
 362                 snd_soc_update_bits(codec, base + i, 0xffff,
 363                                     pdata->drc_cfgs[cfg].regs[i]);
 364
 365         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 366                              WM8994_AIF1ADC1L_DRC_ENA |
 367                              WM8994_AIF1ADC1R_DRC_ENA, save);
 368 }
 369
 370 /* Icky as hell but saves code duplication */
 371 static int wm8994_get_drc(const char *name)
 372 {
 373         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 374                 return 0;
 375         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 376                 return 1;
 377         if (strcmp(name, "AIF2DRC Mode") == 0)
 378                 return 2;
 379         return -EINVAL;
 380 }
 381
 382 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 383                                struct snd_ctl_elem_value *ucontrol)
 384 {
 385         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 387         struct wm8994_pdata *pdata = wm8994->pdata;
 388         int drc = wm8994_get_drc(kcontrol->id.name);
 389         int value = ucontrol->value.integer.value[0];
 390
 391         if (drc < 0)
 392                 return drc;
 393
 394         if (value >= pdata->num_drc_cfgs)
 395                 return -EINVAL;
 396
 397         wm8994->drc_cfg[drc] = value;
 398
 399         wm8994_set_drc(codec, drc);
 400
 401         return 0;
 402 }
 403
 404 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 405                                struct snd_ctl_elem_value *ucontrol)
 406 {
 407         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 408         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 409         int drc = wm8994_get_drc(kcontrol->id.name);
 410
 411         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 412
 413         return 0;
 414 }
 415
 416 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 417 {
 418         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 419         struct wm8994_pdata *pdata = wm8994->pdata;
 420         int base = wm8994_retune_mobile_base[block];
 421         int iface, best, best_val, save, i, cfg;
 422
 423         if (!pdata || !wm8994->num_retune_mobile_texts)
 424                 return;
 425
 426         switch (block) {
 427         case 0:
 428         case 1:
 429                 iface = 0;
 430                 break;
 431         case 2:
 432                 iface = 1;
 433                 break;
 434         default:
 435                 return;
 436         }
 437
 438         /* Find the version of the currently selected configuration
 439          * with the nearest sample rate. */
 440         cfg = wm8994->retune_mobile_cfg[block];
 441         best = 0;
 442         best_val = INT_MAX;
 443         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 444                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 445                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 446                     abs(pdata->retune_mobile_cfgs[i].rate
 447                         - wm8994->dac_rates[iface]) < best_val) {
 448                         best = i;
 449                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 450                                        - wm8994->dac_rates[iface]);
 451                 }
 452         }
 453
 454         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 455                 block,
 456                 pdata->retune_mobile_cfgs[best].name,
 457                 pdata->retune_mobile_cfgs[best].rate,
 458                 wm8994->dac_rates[iface]);
 459
 460         /* The EQ will be disabled while reconfiguring it, remember the
 461          * current configuration.
 462          */
 463         save = snd_soc_read(codec, base);
 464         save &= WM8994_AIF1DAC1_EQ_ENA;
 465
 466         for (i = 0; i < WM8994_EQ_REGS; i++)
 467                 snd_soc_update_bits(codec, base + i, 0xffff,
 468                                 pdata->retune_mobile_cfgs[best].regs[i]);
 469
 470         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 471 }
 472
 473 /* Icky as hell but saves code duplication */
 474 static int wm8994_get_retune_mobile_block(const char *name)
 475 {
 476         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 477                 return 0;
 478         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 479                 return 1;
 480         if (strcmp(name, "AIF2 EQ Mode") == 0)
 481                 return 2;
 482         return -EINVAL;
 483 }
 484
 485 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 486                                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 490         struct wm8994_pdata *pdata = wm8994->pdata;
 491         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 492         int value = ucontrol->value.integer.value[0];
 493
 494         if (block < 0)
 495                 return block;
 496
 497         if (value >= pdata->num_retune_mobile_cfgs)
 498                 return -EINVAL;
 499
 500         wm8994->retune_mobile_cfg[block] = value;
 501
 502         wm8994_set_retune_mobile(codec, block);
 503
 504         return 0;
 505 }
 506
 507 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 508                                          struct snd_ctl_elem_value *ucontrol)
 509 {
 510         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 511         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 512         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 513
 514         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 515
 516         return 0;
 517 }
 518
 519 static const char *aif_chan_src_text[] = {
 520         "Left", "Right"
 521 };
 522
 523 static const struct soc_enum aif1adcl_src =
 524         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 525
 526 static const struct soc_enum aif1adcr_src =
 527         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 528
 529 static const struct soc_enum aif2adcl_src =
 530         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 531
 532 static const struct soc_enum aif2adcr_src =
 533         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 534
 535 static const struct soc_enum aif1dacl_src =
 536         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 537
 538 static const struct soc_enum aif1dacr_src =
 539         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 540
 541 static const struct soc_enum aif2dacl_src =
 542         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 543
 544 static const struct soc_enum aif2dacr_src =
 545         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 546
 547 static const char *osr_text[] = {
 548         "Low Power", "High Performance",
 549 };
 550
 551 static const struct soc_enum dac_osr =
 552         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 553
 554 static const struct soc_enum adc_osr =
 555         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 556
 557 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 558 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 559                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 560                  1, 119, 0, digital_tlv),
 561 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 562                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 563                  1, 119, 0, digital_tlv),
 564 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 565                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 566                  1, 119, 0, digital_tlv),
 567
 568 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 569 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 570 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 571 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 572
 573 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 574 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 575 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 576 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 577
 578 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 579                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 580 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 581                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 582 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 583                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 584
 585 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 586 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 587
 588 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 589 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 590 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 591
 592 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 593 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 594 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 595
 596 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 597 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 598 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 599
 600 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 601 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 602 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 603
 604 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 605                5, 12, 0, st_tlv),
 606 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 607                0, 12, 0, st_tlv),
 608 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 609                5, 12, 0, st_tlv),
 610 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 611                0, 12, 0, st_tlv),
 612 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 613 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 614
 615 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 616 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 617
 618 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 619 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 620
 621 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 622 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 623
 624 SOC_ENUM("ADC OSR", adc_osr),
 625 SOC_ENUM("DAC OSR", dac_osr),
 626
 627 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 628                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 629 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 630              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 631
 632 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 633                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 634 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 635              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 636
 637 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 638                6, 1, 1, wm_hubs_spkmix_tlv),
 639 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 640                2, 1, 1, wm_hubs_spkmix_tlv),
 641
 642 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 643                6, 1, 1, wm_hubs_spkmix_tlv),
 644 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 645                2, 1, 1, wm_hubs_spkmix_tlv),
 646
 647 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 648                10, 15, 0, wm8994_3d_tlv),
 649 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 650            8, 1, 0),
 651 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 652                10, 15, 0, wm8994_3d_tlv),
 653 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 654            8, 1, 0),
 655 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 656                10, 15, 0, wm8994_3d_tlv),
 657 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 658            8, 1, 0),
 659 };
 660
 661 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 662 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 667                eq_tlv),
 668 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 669                eq_tlv),
 670 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 671                eq_tlv),
 672
 673 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 674                eq_tlv),
 675 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 676                eq_tlv),
 677 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 678                eq_tlv),
 679 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 680                eq_tlv),
 681 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 682                eq_tlv),
 683
 684 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 685                eq_tlv),
 686 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 687                eq_tlv),
 688 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 689                eq_tlv),
 690 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 691                eq_tlv),
 692 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 693                eq_tlv),
 694 };
 695
 696 static const char *wm8958_ng_text[] = {
 697         "30ms", "125ms", "250ms", "500ms",
 698 };
 699
 700 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 701         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 702                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 703
 704 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 705         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 706                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 707
 708 static const struct soc_enum wm8958_aif2dac_ng_hold =
 709         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 710                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 711
 712 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 713 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 714
 715 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 716            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 717 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 718 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 719                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 720                7, 1, ng_tlv),
 721
 722 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 723            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 724 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 725 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 726                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 727                7, 1, ng_tlv),
 728
 729 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 730            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 731 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 732 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 733                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 734                7, 1, ng_tlv),
 735 };
 736
 737 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 738 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 739                mixin_boost_tlv),
 740 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 741                mixin_boost_tlv),
 742 };
 743
 744 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 745                          struct snd_kcontrol *kcontrol, int event)
 746 {
 747         struct snd_soc_codec *codec = w->codec;
 748
 749         switch (event) {
 750         case SND_SOC_DAPM_PRE_PMU:
 751                 return configure_clock(codec);
 752
 753         case SND_SOC_DAPM_POST_PMD:
 754                 configure_clock(codec);
 755                 break;
 756         }
 757
 758         return 0;
 759 }
 760
 761 static void vmid_reference(struct snd_soc_codec *codec)
 762 {
 763         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 764
 765         pm_runtime_get_sync(codec->dev);
 766
 767         wm8994->vmid_refcount++;
 768
 769         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 770                 wm8994->vmid_refcount);
 771
 772         if (wm8994->vmid_refcount == 1) {
 773                 /* Startup bias, VMID ramp & buffer */
 774                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 775                                     WM8994_STARTUP_BIAS_ENA |
 776                                     WM8994_VMID_BUF_ENA |
 777                                     WM8994_VMID_RAMP_MASK,
 778                                     WM8994_STARTUP_BIAS_ENA |
 779                                     WM8994_VMID_BUF_ENA |
 780                                     (0x3 << WM8994_VMID_RAMP_SHIFT));
 781
 782                 /* Main bias enable, VMID=2x40k */
 783                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 784                                     WM8994_BIAS_ENA |
 785                                     WM8994_VMID_SEL_MASK,
 786                                     WM8994_BIAS_ENA | 0x2);
 787
 788                 msleep(20);
 789         }
 790 }
 791
 792 static void vmid_dereference(struct snd_soc_codec *codec)
 793 {
 794         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 795
 796         wm8994->vmid_refcount--;
 797
 798         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 799                 wm8994->vmid_refcount);
 800
 801         if (wm8994->vmid_refcount == 0) {
 802                 /* Switch over to startup biases */
 803                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 804                                     WM8994_BIAS_SRC |
 805                                     WM8994_STARTUP_BIAS_ENA |
 806                                     WM8994_VMID_BUF_ENA |
 807                                     WM8994_VMID_RAMP_MASK,
 808                                     WM8994_BIAS_SRC |
 809                                     WM8994_STARTUP_BIAS_ENA |
 810                                     WM8994_VMID_BUF_ENA |
 811                                     (1 << WM8994_VMID_RAMP_SHIFT));
 812
 813                 /* Disable main biases */
 814                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 815                                     WM8994_BIAS_ENA |
 816                                     WM8994_VMID_SEL_MASK, 0);
 817
 818                 /* Discharge line */
 819                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 820                                     WM8994_LINEOUT1_DISCH |
 821                                     WM8994_LINEOUT2_DISCH,
 822                                     WM8994_LINEOUT1_DISCH |
 823                                     WM8994_LINEOUT2_DISCH);
 824
 825                 msleep(5);
 826
 827                 /* Switch off startup biases */
 828                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 829                                     WM8994_BIAS_SRC |
 830                                     WM8994_STARTUP_BIAS_ENA |
 831                                     WM8994_VMID_BUF_ENA |
 832                                     WM8994_VMID_RAMP_MASK, 0);
 833         }
 834
 835         pm_runtime_put(codec->dev);
 836 }
 837
 838 static int vmid_event(struct snd_soc_dapm_widget *w,
 839                       struct snd_kcontrol *kcontrol, int event)
 840 {
 841         struct snd_soc_codec *codec = w->codec;
 842
 843         switch (event) {
 844         case SND_SOC_DAPM_PRE_PMU:
 845                 vmid_reference(codec);
 846                 break;
 847
 848         case SND_SOC_DAPM_POST_PMD:
 849                 vmid_dereference(codec);
 850                 break;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 857 {
 858         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 859         int enable = 1;
 860         int source = 0;  /* GCC flow analysis can't track enable */
 861         int reg, reg_r;
 862
 863         /* Only support direct DAC->headphone paths */
 864         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 865         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 866                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 867                 enable = 0;
 868         }
 869
 870         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 871         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 872                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 873                 enable = 0;
 874         }
 875
 876         /* We also need the same setting for L/R and only one path */
 877         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 878         switch (reg) {
 879         case WM8994_AIF2DACL_TO_DAC1L:
 880                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 881                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 882                 break;
 883         case WM8994_AIF1DAC2L_TO_DAC1L:
 884                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 885                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 886                 break;
 887         case WM8994_AIF1DAC1L_TO_DAC1L:
 888                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 889                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 890                 break;
 891         default:
 892                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 893                 enable = 0;
 894                 break;
 895         }
 896
 897         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 898         if (reg_r != reg) {
 899                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 900                 enable = 0;
 901         }
 902
 903         if (enable) {
 904                 dev_dbg(codec->dev, "Class W enabled\n");
 905                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 906                                     WM8994_CP_DYN_PWR |
 907                                     WM8994_CP_DYN_SRC_SEL_MASK,
 908                                     source | WM8994_CP_DYN_PWR);
 909                 wm8994->hubs.class_w = true;
 910
 911         } else {
 912                 dev_dbg(codec->dev, "Class W disabled\n");
 913                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 914                                     WM8994_CP_DYN_PWR, 0);
 915                 wm8994->hubs.class_w = false;
 916         }
 917 }
 918
 919 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 920                       struct snd_kcontrol *kcontrol, int event)
 921 {
 922         struct snd_soc_codec *codec = w->codec;
 923         struct wm8994 *control = codec->control_data;
 924         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
 925         int i;
 926         int dac;
 927         int adc;
 928         int val;
 929
 930         switch (control->type) {
 931         case WM8994:
 932         case WM8958:
 933                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         switch (event) {
 940         case SND_SOC_DAPM_PRE_PMU:
 941                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
 942                 if ((val & WM8994_AIF1ADCL_SRC) &&
 943                     (val & WM8994_AIF1ADCR_SRC))
 944                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
 945                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
 946                          !(val & WM8994_AIF1ADCR_SRC))
 947                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
 948                 else
 949                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
 950                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
 951
 952                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
 953                 if ((val & WM8994_AIF1DACL_SRC) &&
 954                     (val & WM8994_AIF1DACR_SRC))
 955                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
 956                 else if (!(val & WM8994_AIF1DACL_SRC) &&
 957                          !(val & WM8994_AIF1DACR_SRC))
 958                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
 959                 else
 960                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
 961                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
 962
 963                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
 964                                     mask, adc);
 965                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 966                                     mask, dac);
 967                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 968                                     WM8994_AIF1DSPCLK_ENA |
 969                                     WM8994_SYSDSPCLK_ENA,
 970                                     WM8994_AIF1DSPCLK_ENA |
 971                                     WM8994_SYSDSPCLK_ENA);
 972                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
 973                                     WM8994_AIF1ADC1R_ENA |
 974                                     WM8994_AIF1ADC1L_ENA |
 975                                     WM8994_AIF1ADC2R_ENA |
 976                                     WM8994_AIF1ADC2L_ENA);
 977                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
 978                                     WM8994_AIF1DAC1R_ENA |
 979                                     WM8994_AIF1DAC1L_ENA |
 980                                     WM8994_AIF1DAC2R_ENA |
 981                                     WM8994_AIF1DAC2L_ENA);
 982                 break;
 983
 984         case SND_SOC_DAPM_POST_PMU:
 985                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
 986                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
 987                                       snd_soc_read(codec,
 988                                                    wm8994_vu_bits[i].reg));
 989                 break;
 990
 991         case SND_SOC_DAPM_PRE_PMD:
 992         case SND_SOC_DAPM_POST_PMD:
 993                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 994                                     mask, 0);
 995                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
 996                                     mask, 0);
 997
 998                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
 999                 if (val & WM8994_AIF2DSPCLK_ENA)
1000                         val = WM8994_SYSDSPCLK_ENA;
1001                 else
1002                         val = 0;
1003                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1004                                     WM8994_SYSDSPCLK_ENA |
1005                                     WM8994_AIF1DSPCLK_ENA, val);
1006                 break;
1007         }
1008
1009         return 0;
1010 }
1011
1012 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1013                       struct snd_kcontrol *kcontrol, int event)
1014 {
1015         struct snd_soc_codec *codec = w->codec;
1016         int i;
1017         int dac;
1018         int adc;
1019         int val;
1020
1021         switch (event) {
1022         case SND_SOC_DAPM_PRE_PMU:
1023                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1024                 if ((val & WM8994_AIF2ADCL_SRC) &&
1025                     (val & WM8994_AIF2ADCR_SRC))
1026                         adc = WM8994_AIF2ADCR_ENA;
1027                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1028                          !(val & WM8994_AIF2ADCR_SRC))
1029                         adc = WM8994_AIF2ADCL_ENA;
1030                 else
1031                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1032
1033
1034                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1035                 if ((val & WM8994_AIF2DACL_SRC) &&
1036                     (val & WM8994_AIF2DACR_SRC))
1037                         dac = WM8994_AIF2DACR_ENA;
1038                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1039                          !(val & WM8994_AIF2DACR_SRC))
1040                         dac = WM8994_AIF2DACL_ENA;
1041                 else
1042                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1043
1044                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1045                                     WM8994_AIF2ADCL_ENA |
1046                                     WM8994_AIF2ADCR_ENA, adc);
1047                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1048                                     WM8994_AIF2DACL_ENA |
1049                                     WM8994_AIF2DACR_ENA, dac);
1050                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1051                                     WM8994_AIF2DSPCLK_ENA |
1052                                     WM8994_SYSDSPCLK_ENA,
1053                                     WM8994_AIF2DSPCLK_ENA |
1054                                     WM8994_SYSDSPCLK_ENA);
1055                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1056                                     WM8994_AIF2ADCL_ENA |
1057                                     WM8994_AIF2ADCR_ENA,
1058                                     WM8994_AIF2ADCL_ENA |
1059                                     WM8994_AIF2ADCR_ENA);
1060                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1061                                     WM8994_AIF2DACL_ENA |
1062                                     WM8994_AIF2DACR_ENA,
1063                                     WM8994_AIF2DACL_ENA |
1064                                     WM8994_AIF2DACR_ENA);
1065                 break;
1066
1067         case SND_SOC_DAPM_POST_PMU:
1068                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1069                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1070                                       snd_soc_read(codec,
1071                                                    wm8994_vu_bits[i].reg));
1072                 break;
1073
1074         case SND_SOC_DAPM_PRE_PMD:
1075         case SND_SOC_DAPM_POST_PMD:
1076                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1077                                     WM8994_AIF2DACL_ENA |
1078                                     WM8994_AIF2DACR_ENA, 0);
1079                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080                                     WM8994_AIF2ADCL_ENA |
1081                                     WM8994_AIF2ADCR_ENA, 0);
1082
1083                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1084                 if (val & WM8994_AIF1DSPCLK_ENA)
1085                         val = WM8994_SYSDSPCLK_ENA;
1086                 else
1087                         val = 0;
1088                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1089                                     WM8994_SYSDSPCLK_ENA |
1090                                     WM8994_AIF2DSPCLK_ENA, val);
1091                 break;
1092         }
1093
1094         return 0;
1095 }
1096
1097 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1098                            struct snd_kcontrol *kcontrol, int event)
1099 {
1100         struct snd_soc_codec *codec = w->codec;
1101         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1102
1103         switch (event) {
1104         case SND_SOC_DAPM_PRE_PMU:
1105                 wm8994->aif1clk_enable = 1;
1106                 break;
1107         case SND_SOC_DAPM_POST_PMD:
1108                 wm8994->aif1clk_disable = 1;
1109                 break;
1110         }
1111
1112         return 0;
1113 }
1114
1115 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1116                            struct snd_kcontrol *kcontrol, int event)
1117 {
1118         struct snd_soc_codec *codec = w->codec;
1119         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1120
1121         switch (event) {
1122         case SND_SOC_DAPM_PRE_PMU:
1123                 wm8994->aif2clk_enable = 1;
1124                 break;
1125         case SND_SOC_DAPM_POST_PMD:
1126                 wm8994->aif2clk_disable = 1;
1127                 break;
1128         }
1129
1130         return 0;
1131 }
1132
1133 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1134                           struct snd_kcontrol *kcontrol, int event)
1135 {
1136         struct snd_soc_codec *codec = w->codec;
1137         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1138
1139         switch (event) {
1140         case SND_SOC_DAPM_PRE_PMU:
1141                 if (wm8994->aif1clk_enable) {
1142                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1143                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1144                                             WM8994_AIF1CLK_ENA_MASK,
1145                                             WM8994_AIF1CLK_ENA);
1146                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1147                         wm8994->aif1clk_enable = 0;
1148                 }
1149                 if (wm8994->aif2clk_enable) {
1150                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1151                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1152                                             WM8994_AIF2CLK_ENA_MASK,
1153                                             WM8994_AIF2CLK_ENA);
1154                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1155                         wm8994->aif2clk_enable = 0;
1156                 }
1157                 break;
1158         }
1159
1160         /* We may also have postponed startup of DSP, handle that. */
1161         wm8958_aif_ev(w, kcontrol, event);
1162
1163         return 0;
1164 }
1165
1166 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1167                            struct snd_kcontrol *kcontrol, int event)
1168 {
1169         struct snd_soc_codec *codec = w->codec;
1170         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1171
1172         switch (event) {
1173         case SND_SOC_DAPM_POST_PMD:
1174                 if (wm8994->aif1clk_disable) {
1175                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1176                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1177                                             WM8994_AIF1CLK_ENA_MASK, 0);
1178                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1179                         wm8994->aif1clk_disable = 0;
1180                 }
1181                 if (wm8994->aif2clk_disable) {
1182                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1183                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1184                                             WM8994_AIF2CLK_ENA_MASK, 0);
1185                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1186                         wm8994->aif2clk_disable = 0;
1187                 }
1188                 break;
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1195                       struct snd_kcontrol *kcontrol, int event)
1196 {
1197         late_enable_ev(w, kcontrol, event);
1198         return 0;
1199 }
1200
1201 static int micbias_ev(struct snd_soc_dapm_widget *w,
1202                       struct snd_kcontrol *kcontrol, int event)
1203 {
1204         late_enable_ev(w, kcontrol, event);
1205         return 0;
1206 }
1207
1208 static int dac_ev(struct snd_soc_dapm_widget *w,
1209                   struct snd_kcontrol *kcontrol, int event)
1210 {
1211         struct snd_soc_codec *codec = w->codec;
1212         unsigned int mask = 1 << w->shift;
1213
1214         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1215                             mask, mask);
1216         return 0;
1217 }
1218
1219 static const char *hp_mux_text[] = {
1220         "Mixer",
1221         "DAC",
1222 };
1223
1224 #define WM8994_HP_ENUM(xname, xenum) \
1225 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1226         .info = snd_soc_info_enum_double, \
1227         .get = snd_soc_dapm_get_enum_double, \
1228         .put = wm8994_put_hp_enum, \
1229         .private_value = (unsigned long)&xenum }
1230
1231 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1232                               struct snd_ctl_elem_value *ucontrol)
1233 {
1234         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1235         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1236         struct snd_soc_codec *codec = w->codec;
1237         int ret;
1238
1239         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1240
1241         wm8994_update_class_w(codec);
1242
1243         return ret;
1244 }
1245
1246 static const struct soc_enum hpl_enum =
1247         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1248
1249 static const struct snd_kcontrol_new hpl_mux =
1250         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1251
1252 static const struct soc_enum hpr_enum =
1253         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1254
1255 static const struct snd_kcontrol_new hpr_mux =
1256         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1257
1258 static const char *adc_mux_text[] = {
1259         "ADC",
1260         "DMIC",
1261 };
1262
1263 static const struct soc_enum adc_enum =
1264         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1265
1266 static const struct snd_kcontrol_new adcl_mux =
1267         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1268
1269 static const struct snd_kcontrol_new adcr_mux =
1270         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1271
1272 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1273 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1274 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1275 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1276 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1277 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1278 };
1279
1280 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1281 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1282 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1283 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1284 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1285 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1286 };
1287
1288 /* Debugging; dump chip status after DAPM transitions */
1289 static int post_ev(struct snd_soc_dapm_widget *w,
1290             struct snd_kcontrol *kcontrol, int event)
1291 {
1292         struct snd_soc_codec *codec = w->codec;
1293         dev_dbg(codec->dev, "SRC status: %x\n",
1294                 snd_soc_read(codec,
1295                              WM8994_RATE_STATUS));
1296         return 0;
1297 }
1298
1299 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1300 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1301                 1, 1, 0),
1302 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1303                 0, 1, 0),
1304 };
1305
1306 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1307 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1308                 1, 1, 0),
1309 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1310                 0, 1, 0),
1311 };
1312
1313 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1314 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1315                 1, 1, 0),
1316 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1317                 0, 1, 0),
1318 };
1319
1320 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1321 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1322                 1, 1, 0),
1323 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1324                 0, 1, 0),
1325 };
1326
1327 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1328 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1329                 5, 1, 0),
1330 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1331                 4, 1, 0),
1332 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1333                 2, 1, 0),
1334 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1335                 1, 1, 0),
1336 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1337                 0, 1, 0),
1338 };
1339
1340 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1341 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1342                 5, 1, 0),
1343 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1344                 4, 1, 0),
1345 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1346                 2, 1, 0),
1347 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1348                 1, 1, 0),
1349 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1350                 0, 1, 0),
1351 };
1352
1353 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1354 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1355         .info = snd_soc_info_volsw, \
1356         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1357         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1358
1359 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1360                               struct snd_ctl_elem_value *ucontrol)
1361 {
1362         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1363         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1364         struct snd_soc_codec *codec = w->codec;
1365         int ret;
1366
1367         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1368
1369         wm8994_update_class_w(codec);
1370
1371         return ret;
1372 }
1373
1374 static const struct snd_kcontrol_new dac1l_mix[] = {
1375 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1376                       5, 1, 0),
1377 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1378                       4, 1, 0),
1379 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1380                       2, 1, 0),
1381 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1382                       1, 1, 0),
1383 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1384                       0, 1, 0),
1385 };
1386
1387 static const struct snd_kcontrol_new dac1r_mix[] = {
1388 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1389                       5, 1, 0),
1390 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1391                       4, 1, 0),
1392 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1393                       2, 1, 0),
1394 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1395                       1, 1, 0),
1396 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1397                       0, 1, 0),
1398 };
1399
1400 static const char *sidetone_text[] = {
1401         "ADC/DMIC1", "DMIC2",
1402 };
1403
1404 static const struct soc_enum sidetone1_enum =
1405         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1406
1407 static const struct snd_kcontrol_new sidetone1_mux =
1408         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1409
1410 static const struct soc_enum sidetone2_enum =
1411         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1412
1413 static const struct snd_kcontrol_new sidetone2_mux =
1414         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1415
1416 static const char *aif1dac_text[] = {
1417         "AIF1DACDAT", "AIF3DACDAT",
1418 };
1419
1420 static const struct soc_enum aif1dac_enum =
1421         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1422
1423 static const struct snd_kcontrol_new aif1dac_mux =
1424         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1425
1426 static const char *aif2dac_text[] = {
1427         "AIF2DACDAT", "AIF3DACDAT",
1428 };
1429
1430 static const struct soc_enum aif2dac_enum =
1431         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1432
1433 static const struct snd_kcontrol_new aif2dac_mux =
1434         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1435
1436 static const char *aif2adc_text[] = {
1437         "AIF2ADCDAT", "AIF3DACDAT",
1438 };
1439
1440 static const struct soc_enum aif2adc_enum =
1441         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1442
1443 static const struct snd_kcontrol_new aif2adc_mux =
1444         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1445
1446 static const char *aif3adc_text[] = {
1447         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1448 };
1449
1450 static const struct soc_enum wm8994_aif3adc_enum =
1451         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1452
1453 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1454         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1455
1456 static const struct soc_enum wm8958_aif3adc_enum =
1457         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1458
1459 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1460         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1461
1462 static const char *mono_pcm_out_text[] = {
1463         "None", "AIF2ADCL", "AIF2ADCR",
1464 };
1465
1466 static const struct soc_enum mono_pcm_out_enum =
1467         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1468
1469 static const struct snd_kcontrol_new mono_pcm_out_mux =
1470         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1471
1472 static const char *aif2dac_src_text[] = {
1473         "AIF2", "AIF3",
1474 };
1475
1476 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1477 static const struct soc_enum aif2dacl_src_enum =
1478         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1479
1480 static const struct snd_kcontrol_new aif2dacl_src_mux =
1481         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1482
1483 static const struct soc_enum aif2dacr_src_enum =
1484         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1485
1486 static const struct snd_kcontrol_new aif2dacr_src_mux =
1487         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1488
1489 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1490 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1491         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1492 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1493         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1494
1495 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1496         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1497 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1498         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1499 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1500         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1501 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1502         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1503 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1504         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1505
1506 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1507                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1508                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1509 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1510                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1511                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1512 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1513                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1514 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1515                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1516
1517 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1518 };
1519
1520 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1521 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1522                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1523                     SND_SOC_DAPM_PRE_PMD),
1524 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1525                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1526                     SND_SOC_DAPM_PRE_PMD),
1527 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1528 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1529                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1530 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1531                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1532 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1533 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1534 };
1535
1536 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1537 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1538         dac_ev, SND_SOC_DAPM_PRE_PMU),
1539 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1540         dac_ev, SND_SOC_DAPM_PRE_PMU),
1541 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1542         dac_ev, SND_SOC_DAPM_PRE_PMU),
1543 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1544         dac_ev, SND_SOC_DAPM_PRE_PMU),
1545 };
1546
1547 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1548 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1549 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1550 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1551 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1552 };
1553
1554 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1555 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1556                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1557 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1558                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1559 };
1560
1561 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1562 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1563 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1564 };
1565
1566 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1567 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1568 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1569 SND_SOC_DAPM_INPUT("Clock"),
1570
1571 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1572                       SND_SOC_DAPM_PRE_PMU),
1573 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1574                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1575
1576 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1577                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1578
1579 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1580 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1581 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1582
1583 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1584                      0, SND_SOC_NOPM, 9, 0),
1585 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1586                      0, SND_SOC_NOPM, 8, 0),
1587 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1588                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1589                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1590 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1591                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1592                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1593
1594 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1595                      0, SND_SOC_NOPM, 11, 0),
1596 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1597                      0, SND_SOC_NOPM, 10, 0),
1598 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1599                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1600                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1601 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1602                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1603                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1604
1605 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1606                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1607 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1608                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1609
1610 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1611                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1612 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1613                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1614
1615 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1616                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1617 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1618                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1619
1620 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1621 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1622
1623 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1624                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1625 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1626                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1627
1628 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1629                      SND_SOC_NOPM, 13, 0),
1630 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1631                      SND_SOC_NOPM, 12, 0),
1632 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1633                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1634                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1635 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1636                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1637                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1638
1639 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1640 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1641 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1642 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1643
1644 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1645 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1646 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1647
1648 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1649 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1650
1651 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1652
1653 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1654 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1655 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1656 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1657
1658 /* Power is done with the muxes since the ADC power also controls the
1659  * downsampling chain, the chip will automatically manage the analogue
1660  * specific portions.
1661  */
1662 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1663 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1664
1665 SND_SOC_DAPM_POST("Debug log", post_ev),
1666 };
1667
1668 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1669 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1670 };
1671
1672 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1673 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1674 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1675 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1676 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1677 };
1678
1679 static const struct snd_soc_dapm_route intercon[] = {
1680         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1681         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1682
1683         { "DSP1CLK", NULL, "CLK_SYS" },
1684         { "DSP2CLK", NULL, "CLK_SYS" },
1685         { "DSPINTCLK", NULL, "CLK_SYS" },
1686
1687         { "AIF1ADC1L", NULL, "AIF1CLK" },
1688         { "AIF1ADC1L", NULL, "DSP1CLK" },
1689         { "AIF1ADC1R", NULL, "AIF1CLK" },
1690         { "AIF1ADC1R", NULL, "DSP1CLK" },
1691         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1692
1693         { "AIF1DAC1L", NULL, "AIF1CLK" },
1694         { "AIF1DAC1L", NULL, "DSP1CLK" },
1695         { "AIF1DAC1R", NULL, "AIF1CLK" },
1696         { "AIF1DAC1R", NULL, "DSP1CLK" },
1697         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1698
1699         { "AIF1ADC2L", NULL, "AIF1CLK" },
1700         { "AIF1ADC2L", NULL, "DSP1CLK" },
1701         { "AIF1ADC2R", NULL, "AIF1CLK" },
1702         { "AIF1ADC2R", NULL, "DSP1CLK" },
1703         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1704
1705         { "AIF1DAC2L", NULL, "AIF1CLK" },
1706         { "AIF1DAC2L", NULL, "DSP1CLK" },
1707         { "AIF1DAC2R", NULL, "AIF1CLK" },
1708         { "AIF1DAC2R", NULL, "DSP1CLK" },
1709         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1710
1711         { "AIF2ADCL", NULL, "AIF2CLK" },
1712         { "AIF2ADCL", NULL, "DSP2CLK" },
1713         { "AIF2ADCR", NULL, "AIF2CLK" },
1714         { "AIF2ADCR", NULL, "DSP2CLK" },
1715         { "AIF2ADCR", NULL, "DSPINTCLK" },
1716
1717         { "AIF2DACL", NULL, "AIF2CLK" },
1718         { "AIF2DACL", NULL, "DSP2CLK" },
1719         { "AIF2DACR", NULL, "AIF2CLK" },
1720         { "AIF2DACR", NULL, "DSP2CLK" },
1721         { "AIF2DACR", NULL, "DSPINTCLK" },
1722
1723         { "DMIC1L", NULL, "DMIC1DAT" },
1724         { "DMIC1L", NULL, "CLK_SYS" },
1725         { "DMIC1R", NULL, "DMIC1DAT" },
1726         { "DMIC1R", NULL, "CLK_SYS" },
1727         { "DMIC2L", NULL, "DMIC2DAT" },
1728         { "DMIC2L", NULL, "CLK_SYS" },
1729         { "DMIC2R", NULL, "DMIC2DAT" },
1730         { "DMIC2R", NULL, "CLK_SYS" },
1731
1732         { "ADCL", NULL, "AIF1CLK" },
1733         { "ADCL", NULL, "DSP1CLK" },
1734         { "ADCL", NULL, "DSPINTCLK" },
1735
1736         { "ADCR", NULL, "AIF1CLK" },
1737         { "ADCR", NULL, "DSP1CLK" },
1738         { "ADCR", NULL, "DSPINTCLK" },
1739
1740         { "ADCL Mux", "ADC", "ADCL" },
1741         { "ADCL Mux", "DMIC", "DMIC1L" },
1742         { "ADCR Mux", "ADC", "ADCR" },
1743         { "ADCR Mux", "DMIC", "DMIC1R" },
1744
1745         { "DAC1L", NULL, "AIF1CLK" },
1746         { "DAC1L", NULL, "DSP1CLK" },
1747         { "DAC1L", NULL, "DSPINTCLK" },
1748
1749         { "DAC1R", NULL, "AIF1CLK" },
1750         { "DAC1R", NULL, "DSP1CLK" },
1751         { "DAC1R", NULL, "DSPINTCLK" },
1752
1753         { "DAC2L", NULL, "AIF2CLK" },
1754         { "DAC2L", NULL, "DSP2CLK" },
1755         { "DAC2L", NULL, "DSPINTCLK" },
1756
1757         { "DAC2R", NULL, "AIF2DACR" },
1758         { "DAC2R", NULL, "AIF2CLK" },
1759         { "DAC2R", NULL, "DSP2CLK" },
1760         { "DAC2R", NULL, "DSPINTCLK" },
1761
1762         { "TOCLK", NULL, "CLK_SYS" },
1763
1764         /* AIF1 outputs */
1765         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1766         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1767         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1768
1769         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1770         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1771         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1772
1773         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1774         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1775         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1776
1777         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1778         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1779         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1780
1781         /* Pin level routing for AIF3 */
1782         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1783         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1784         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1785         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1786
1787         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1788         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1789         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1790         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1791         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1792         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1793         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1794
1795         /* DAC1 inputs */
1796         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1797         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1798         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1799         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1800         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1801
1802         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1803         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1804         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1805         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1806         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1807
1808         /* DAC2/AIF2 outputs  */
1809         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1810         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1811         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1812         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1813         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1814         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1815
1816         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1817         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1818         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1819         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1820         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1821         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1822
1823         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1824         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1825         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1826         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1827
1828         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1829
1830         /* AIF3 output */
1831         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1832         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1833         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1834         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1835         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1836         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1837         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1838         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1839
1840         /* Sidetone */
1841         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1842         { "Left Sidetone", "DMIC2", "DMIC2L" },
1843         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1844         { "Right Sidetone", "DMIC2", "DMIC2R" },
1845
1846         /* Output stages */
1847         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1848         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1849
1850         { "SPKL", "DAC1 Switch", "DAC1L" },
1851         { "SPKL", "DAC2 Switch", "DAC2L" },
1852
1853         { "SPKR", "DAC1 Switch", "DAC1R" },
1854         { "SPKR", "DAC2 Switch", "DAC2R" },
1855
1856         { "Left Headphone Mux", "DAC", "DAC1L" },
1857         { "Right Headphone Mux", "DAC", "DAC1R" },
1858 };
1859
1860 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1861         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1862         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1863         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1864         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1865         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1866         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1867         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1868         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1869 };
1870
1871 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1872         { "DAC1L", NULL, "DAC1L Mixer" },
1873         { "DAC1R", NULL, "DAC1R Mixer" },
1874         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1875         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1876 };
1877
1878 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1879         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1880         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1881         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1882         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1883         { "MICBIAS1", NULL, "CLK_SYS" },
1884         { "MICBIAS1", NULL, "MICBIAS Supply" },
1885         { "MICBIAS2", NULL, "CLK_SYS" },
1886         { "MICBIAS2", NULL, "MICBIAS Supply" },
1887 };
1888
1889 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1890         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1891         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1892         { "MICBIAS1", NULL, "VMID" },
1893         { "MICBIAS2", NULL, "VMID" },
1894 };
1895
1896 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1897         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1898         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1899
1900         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1901         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1902         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1903         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1904
1905         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1906         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1907
1908         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1909 };
1910
1911 /* The size in bits of the FLL divide multiplied by 10
1912  * to allow rounding later */
1913 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1914
1915 struct fll_div {
1916         u16 outdiv;
1917         u16 n;
1918         u16 k;
1919         u16 clk_ref_div;
1920         u16 fll_fratio;
1921 };
1922
1923 static int wm8994_get_fll_config(struct fll_div *fll,
1924                                  int freq_in, int freq_out)
1925 {
1926         u64 Kpart;
1927         unsigned int K, Ndiv, Nmod;
1928
1929         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1930
1931         /* Scale the input frequency down to <= 13.5MHz */
1932         fll->clk_ref_div = 0;
1933         while (freq_in > 13500000) {
1934                 fll->clk_ref_div++;
1935                 freq_in /= 2;
1936
1937                 if (fll->clk_ref_div > 3)
1938                         return -EINVAL;
1939         }
1940         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1941
1942         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1943         fll->outdiv = 3;
1944         while (freq_out * (fll->outdiv + 1) < 90000000) {
1945                 fll->outdiv++;
1946                 if (fll->outdiv > 63)
1947                         return -EINVAL;
1948         }
1949         freq_out *= fll->outdiv + 1;
1950         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1951
1952         if (freq_in > 1000000) {
1953                 fll->fll_fratio = 0;
1954         } else if (freq_in > 256000) {
1955                 fll->fll_fratio = 1;
1956                 freq_in *= 2;
1957         } else if (freq_in > 128000) {
1958                 fll->fll_fratio = 2;
1959                 freq_in *= 4;
1960         } else if (freq_in > 64000) {
1961                 fll->fll_fratio = 3;
1962                 freq_in *= 8;
1963         } else {
1964                 fll->fll_fratio = 4;
1965                 freq_in *= 16;
1966         }
1967         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1968
1969         /* Now, calculate N.K */
1970         Ndiv = freq_out / freq_in;
1971
1972         fll->n = Ndiv;
1973         Nmod = freq_out % freq_in;
1974         pr_debug("Nmod=%d\n", Nmod);
1975
1976         /* Calculate fractional part - scale up so we can round. */
1977         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1978
1979         do_div(Kpart, freq_in);
1980
1981         K = Kpart & 0xFFFFFFFF;
1982
1983         if ((K % 10) >= 5)
1984                 K += 5;
1985
1986         /* Move down to proper range now rounding is done */
1987         fll->k = K / 10;
1988
1989         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1990
1991         return 0;
1992 }
1993
1994 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1995                           unsigned int freq_in, unsigned int freq_out)
1996 {
1997         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1998         struct wm8994 *control = codec->control_data;
1999         int reg_offset, ret;
2000         struct fll_div fll;
2001         u16 reg, aif1, aif2;
2002         unsigned long timeout;
2003         bool was_enabled;
2004
2005         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2006                 & WM8994_AIF1CLK_ENA;
2007
2008         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2009                 & WM8994_AIF2CLK_ENA;
2010
2011         switch (id) {
2012         case WM8994_FLL1:
2013                 reg_offset = 0;
2014                 id = 0;
2015                 break;
2016         case WM8994_FLL2:
2017                 reg_offset = 0x20;
2018                 id = 1;
2019                 break;
2020         default:
2021                 return -EINVAL;
2022         }
2023
2024         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2025         was_enabled = reg & WM8994_FLL1_ENA;
2026
2027         switch (src) {
2028         case 0:
2029                 /* Allow no source specification when stopping */
2030                 if (freq_out)
2031                         return -EINVAL;
2032                 src = wm8994->fll[id].src;
2033                 break;
2034         case WM8994_FLL_SRC_MCLK1:
2035         case WM8994_FLL_SRC_MCLK2:
2036         case WM8994_FLL_SRC_LRCLK:
2037         case WM8994_FLL_SRC_BCLK:
2038                 break;
2039         default:
2040                 return -EINVAL;
2041         }
2042
2043         /* Are we changing anything? */
2044         if (wm8994->fll[id].src == src &&
2045             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2046                 return 0;
2047
2048         /* If we're stopping the FLL redo the old config - no
2049          * registers will actually be written but we avoid GCC flow
2050          * analysis bugs spewing warnings.
2051          */
2052         if (freq_out)
2053                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2054         else
2055                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2056                                             wm8994->fll[id].out);
2057         if (ret < 0)
2058                 return ret;
2059
2060         /* Gate the AIF clocks while we reclock */
2061         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2062                             WM8994_AIF1CLK_ENA, 0);
2063         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2064                             WM8994_AIF2CLK_ENA, 0);
2065
2066         /* We always need to disable the FLL while reconfiguring */
2067         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2068                             WM8994_FLL1_ENA, 0);
2069
2070         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2071                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2072         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2073                             WM8994_FLL1_OUTDIV_MASK |
2074                             WM8994_FLL1_FRATIO_MASK, reg);
2075
2076         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
2077
2078         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2079                             WM8994_FLL1_N_MASK,
2080                                     fll.n << WM8994_FLL1_N_SHIFT);
2081
2082         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2083                             WM8994_FLL1_REFCLK_DIV_MASK |
2084                             WM8994_FLL1_REFCLK_SRC_MASK,
2085                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2086                             (src - 1));
2087
2088         /* Clear any pending completion from a previous failure */
2089         try_wait_for_completion(&wm8994->fll_locked[id]);
2090
2091         /* Enable (with fractional mode if required) */
2092         if (freq_out) {
2093                 /* Enable VMID if we need it */
2094                 if (!was_enabled) {
2095                         switch (control->type) {
2096                         case WM8994:
2097                                 vmid_reference(codec);
2098                                 break;
2099                         case WM8958:
2100                                 if (wm8994->revision < 1)
2101                                         vmid_reference(codec);
2102                                 break;
2103                         default:
2104                                 break;
2105                         }
2106                 }
2107
2108                 if (fll.k)
2109                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2110                 else
2111                         reg = WM8994_FLL1_ENA;
2112                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2113                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2114                                     reg);
2115
2116                 if (wm8994->fll_locked_irq) {
2117                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2118                                                               msecs_to_jiffies(10));
2119                         if (timeout == 0)
2120                                 dev_warn(codec->dev,
2121                                          "Timed out waiting for FLL lock\n");
2122                 } else {
2123                         msleep(5);
2124                 }
2125         } else {
2126                 if (was_enabled) {
2127                         switch (control->type) {
2128                         case WM8994:
2129                                 vmid_dereference(codec);
2130                                 break;
2131                         case WM8958:
2132                                 if (wm8994->revision < 1)
2133                                         vmid_dereference(codec);
2134                                 break;
2135                         default:
2136                                 break;
2137                         }
2138                 }
2139         }
2140
2141         wm8994->fll[id].in = freq_in;
2142         wm8994->fll[id].out = freq_out;
2143         wm8994->fll[id].src = src;
2144
2145         /* Enable any gated AIF clocks */
2146         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2147                             WM8994_AIF1CLK_ENA, aif1);
2148         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2149                             WM8994_AIF2CLK_ENA, aif2);
2150
2151         configure_clock(codec);
2152
2153         return 0;
2154 }
2155
2156 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2157 {
2158         struct completion *completion = data;
2159
2160         complete(completion);
2161
2162         return IRQ_HANDLED;
2163 }
2164
2165 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2166
2167 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2168                           unsigned int freq_in, unsigned int freq_out)
2169 {
2170         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2171 }
2172
2173 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2174                 int clk_id, unsigned int freq, int dir)
2175 {
2176         struct snd_soc_codec *codec = dai->codec;
2177         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2178         int i;
2179
2180         switch (dai->id) {
2181         case 1:
2182         case 2:
2183                 break;
2184
2185         default:
2186                 /* AIF3 shares clocking with AIF1/2 */
2187                 return -EINVAL;
2188         }
2189
2190         switch (clk_id) {
2191         case WM8994_SYSCLK_MCLK1:
2192                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2193                 wm8994->mclk[0] = freq;
2194                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2195                         dai->id, freq);
2196                 break;
2197
2198         case WM8994_SYSCLK_MCLK2:
2199                 /* TODO: Set GPIO AF */
2200                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2201                 wm8994->mclk[1] = freq;
2202                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2203                         dai->id, freq);
2204                 break;
2205
2206         case WM8994_SYSCLK_FLL1:
2207                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2208                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2209                 break;
2210
2211         case WM8994_SYSCLK_FLL2:
2212                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2213                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2214                 break;
2215
2216         case WM8994_SYSCLK_OPCLK:
2217                 /* Special case - a division (times 10) is given and
2218                  * no effect on main clocking.
2219                  */
2220                 if (freq) {
2221                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2222                                 if (opclk_divs[i] == freq)
2223                                         break;
2224                         if (i == ARRAY_SIZE(opclk_divs))
2225                                 return -EINVAL;
2226                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2227                                             WM8994_OPCLK_DIV_MASK, i);
2228                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2229                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2230                 } else {
2231                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2232                                             WM8994_OPCLK_ENA, 0);
2233                 }
2234
2235         default:
2236                 return -EINVAL;
2237         }
2238
2239         configure_clock(codec);
2240
2241         return 0;
2242 }
2243
2244 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2245                                  enum snd_soc_bias_level level)
2246 {
2247         struct wm8994 *control = codec->control_data;
2248         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2249
2250         switch (level) {
2251         case SND_SOC_BIAS_ON:
2252                 break;
2253
2254         case SND_SOC_BIAS_PREPARE:
2255                 break;
2256
2257         case SND_SOC_BIAS_STANDBY:
2258                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2259                         pm_runtime_get_sync(codec->dev);
2260
2261                         switch (control->type) {
2262                         case WM8994:
2263                                 if (wm8994->revision < 4) {
2264                                         /* Tweak DC servo and DSP
2265                                          * configuration for improved
2266                                          * performance. */
2267                                         snd_soc_write(codec, 0x102, 0x3);
2268                                         snd_soc_write(codec, 0x56, 0x3);
2269                                         snd_soc_write(codec, 0x817, 0);
2270                                         snd_soc_write(codec, 0x102, 0);
2271                                 }
2272                                 break;
2273
2274                         case WM8958:
2275                                 if (wm8994->revision == 0) {
2276                                         /* Optimise performance for rev A */
2277                                         snd_soc_write(codec, 0x102, 0x3);
2278                                         snd_soc_write(codec, 0xcb, 0x81);
2279                                         snd_soc_write(codec, 0x817, 0);
2280                                         snd_soc_write(codec, 0x102, 0);
2281
2282                                         snd_soc_update_bits(codec,
2283                                                             WM8958_CHARGE_PUMP_2,
2284                                                             WM8958_CP_DISCH,
2285                                                             WM8958_CP_DISCH);
2286                                 }
2287                                 break;
2288
2289                         case WM1811:
2290                                 if (wm8994->revision < 2) {
2291                                         snd_soc_write(codec, 0x102, 0x3);
2292                                         snd_soc_write(codec, 0x5d, 0x7e);
2293                                         snd_soc_write(codec, 0x5e, 0x0);
2294                                         snd_soc_write(codec, 0x102, 0x0);
2295                                 }
2296                                 break;
2297                         }
2298
2299                         /* Discharge LINEOUT1 & 2 */
2300                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2301                                             WM8994_LINEOUT1_DISCH |
2302                                             WM8994_LINEOUT2_DISCH,
2303                                             WM8994_LINEOUT1_DISCH |
2304                                             WM8994_LINEOUT2_DISCH);
2305                 }
2306
2307
2308                 break;
2309
2310         case SND_SOC_BIAS_OFF:
2311                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2312                         wm8994->cur_fw = NULL;
2313
2314                         pm_runtime_put(codec->dev);
2315                 }
2316                 break;
2317         }
2318         codec->dapm.bias_level = level;
2319         return 0;
2320 }
2321
2322 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2323 {
2324         struct snd_soc_codec *codec = dai->codec;
2325         struct wm8994 *control = codec->control_data;
2326         int ms_reg;
2327         int aif1_reg;
2328         int ms = 0;
2329         int aif1 = 0;
2330
2331         switch (dai->id) {
2332         case 1:
2333                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2334                 aif1_reg = WM8994_AIF1_CONTROL_1;
2335                 break;
2336         case 2:
2337                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2338                 aif1_reg = WM8994_AIF2_CONTROL_1;
2339                 break;
2340         default:
2341                 return -EINVAL;
2342         }
2343
2344         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2345         case SND_SOC_DAIFMT_CBS_CFS:
2346                 break;
2347         case SND_SOC_DAIFMT_CBM_CFM:
2348                 ms = WM8994_AIF1_MSTR;
2349                 break;
2350         default:
2351                 return -EINVAL;
2352         }
2353
2354         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2355         case SND_SOC_DAIFMT_DSP_B:
2356                 aif1 |= WM8994_AIF1_LRCLK_INV;
2357         case SND_SOC_DAIFMT_DSP_A:
2358                 aif1 |= 0x18;
2359                 break;
2360         case SND_SOC_DAIFMT_I2S:
2361                 aif1 |= 0x10;
2362                 break;
2363         case SND_SOC_DAIFMT_RIGHT_J:
2364                 break;
2365         case SND_SOC_DAIFMT_LEFT_J:
2366                 aif1 |= 0x8;
2367                 break;
2368         default:
2369                 return -EINVAL;
2370         }
2371
2372         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2373         case SND_SOC_DAIFMT_DSP_A:
2374         case SND_SOC_DAIFMT_DSP_B:
2375                 /* frame inversion not valid for DSP modes */
2376                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2377                 case SND_SOC_DAIFMT_NB_NF:
2378                         break;
2379                 case SND_SOC_DAIFMT_IB_NF:
2380                         aif1 |= WM8994_AIF1_BCLK_INV;
2381                         break;
2382                 default:
2383                         return -EINVAL;
2384                 }
2385                 break;
2386
2387         case SND_SOC_DAIFMT_I2S:
2388         case SND_SOC_DAIFMT_RIGHT_J:
2389         case SND_SOC_DAIFMT_LEFT_J:
2390                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2391                 case SND_SOC_DAIFMT_NB_NF:
2392                         break;
2393                 case SND_SOC_DAIFMT_IB_IF:
2394                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2395                         break;
2396                 case SND_SOC_DAIFMT_IB_NF:
2397                         aif1 |= WM8994_AIF1_BCLK_INV;
2398                         break;
2399                 case SND_SOC_DAIFMT_NB_IF:
2400                         aif1 |= WM8994_AIF1_LRCLK_INV;
2401                         break;
2402                 default:
2403                         return -EINVAL;
2404                 }
2405                 break;
2406         default:
2407                 return -EINVAL;
2408         }
2409
2410         /* The AIF2 format configuration needs to be mirrored to AIF3
2411          * on WM8958 if it's in use so just do it all the time. */
2412         switch (control->type) {
2413         case WM1811:
2414         case WM8958:
2415                 if (dai->id == 2)
2416                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2417                                             WM8994_AIF1_LRCLK_INV |
2418                                             WM8958_AIF3_FMT_MASK, aif1);
2419                 break;
2420
2421         default:
2422                 break;
2423         }
2424
2425         snd_soc_update_bits(codec, aif1_reg,
2426                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2427                             WM8994_AIF1_FMT_MASK,
2428                             aif1);
2429         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2430                             ms);
2431
2432         return 0;
2433 }
2434
2435 static struct {
2436         int val, rate;
2437 } srs[] = {
2438         { 0,   8000 },
2439         { 1,  11025 },
2440         { 2,  12000 },
2441         { 3,  16000 },
2442         { 4,  22050 },
2443         { 5,  24000 },
2444         { 6,  32000 },
2445         { 7,  44100 },
2446         { 8,  48000 },
2447         { 9,  88200 },
2448         { 10, 96000 },
2449 };
2450
2451 static int fs_ratios[] = {
2452         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2453 };
2454
2455 static int bclk_divs[] = {
2456         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2457         640, 880, 960, 1280, 1760, 1920
2458 };
2459
2460 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2461                             struct snd_pcm_hw_params *params,
2462                             struct snd_soc_dai *dai)
2463 {
2464         struct snd_soc_codec *codec = dai->codec;
2465         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2466         int aif1_reg;
2467         int aif2_reg;
2468         int bclk_reg;
2469         int lrclk_reg;
2470         int rate_reg;
2471         int aif1 = 0;
2472         int aif2 = 0;
2473         int bclk = 0;
2474         int lrclk = 0;
2475         int rate_val = 0;
2476         int id = dai->id - 1;
2477
2478         int i, cur_val, best_val, bclk_rate, best;
2479
2480         switch (dai->id) {
2481         case 1:
2482                 aif1_reg = WM8994_AIF1_CONTROL_1;
2483                 aif2_reg = WM8994_AIF1_CONTROL_2;
2484                 bclk_reg = WM8994_AIF1_BCLK;
2485                 rate_reg = WM8994_AIF1_RATE;
2486                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2487                     wm8994->lrclk_shared[0]) {
2488                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2489                 } else {
2490                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2491                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2492                 }
2493                 break;
2494         case 2:
2495                 aif1_reg = WM8994_AIF2_CONTROL_1;
2496                 aif2_reg = WM8994_AIF2_CONTROL_2;
2497                 bclk_reg = WM8994_AIF2_BCLK;
2498                 rate_reg = WM8994_AIF2_RATE;
2499                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2500                     wm8994->lrclk_shared[1]) {
2501                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2502                 } else {
2503                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2504                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2505                 }
2506                 break;
2507         default:
2508                 return -EINVAL;
2509         }
2510
2511         bclk_rate = params_rate(params) * 4;
2512         switch (params_format(params)) {
2513         case SNDRV_PCM_FORMAT_S16_LE:
2514                 bclk_rate *= 16;
2515                 break;
2516         case SNDRV_PCM_FORMAT_S20_3LE:
2517                 bclk_rate *= 20;
2518                 aif1 |= 0x20;
2519                 break;
2520         case SNDRV_PCM_FORMAT_S24_LE:
2521                 bclk_rate *= 24;
2522                 aif1 |= 0x40;
2523                 break;
2524         case SNDRV_PCM_FORMAT_S32_LE:
2525                 bclk_rate *= 32;
2526                 aif1 |= 0x60;
2527                 break;
2528         default:
2529                 return -EINVAL;
2530         }
2531
2532         /* Try to find an appropriate sample rate; look for an exact match. */
2533         for (i = 0; i < ARRAY_SIZE(srs); i++)
2534                 if (srs[i].rate == params_rate(params))
2535                         break;
2536         if (i == ARRAY_SIZE(srs))
2537                 return -EINVAL;
2538         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2539
2540         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2541         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2542                 dai->id, wm8994->aifclk[id], bclk_rate);
2543
2544         if (params_channels(params) == 1 &&
2545             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2546                 aif2 |= WM8994_AIF1_MONO;
2547
2548         if (wm8994->aifclk[id] == 0) {
2549                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2550                 return -EINVAL;
2551         }
2552
2553         /* AIFCLK/fs ratio; look for a close match in either direction */
2554         best = 0;
2555         best_val = abs((fs_ratios[0] * params_rate(params))
2556                        - wm8994->aifclk[id]);
2557         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2558                 cur_val = abs((fs_ratios[i] * params_rate(params))
2559                               - wm8994->aifclk[id]);
2560                 if (cur_val >= best_val)
2561                         continue;
2562                 best = i;
2563                 best_val = cur_val;
2564         }
2565         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2566                 dai->id, fs_ratios[best]);
2567         rate_val |= best;
2568
2569         /* We may not get quite the right frequency if using
2570          * approximate clocks so look for the closest match that is
2571          * higher than the target (we need to ensure that there enough
2572          * BCLKs to clock out the samples).
2573          */
2574         best = 0;
2575         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2576                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2577                 if (cur_val < 0) /* BCLK table is sorted */
2578                         break;
2579                 best = i;
2580         }
2581         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2582         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2583                 bclk_divs[best], bclk_rate);
2584         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2585
2586         lrclk = bclk_rate / params_rate(params);
2587         if (!lrclk) {
2588                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2589                         bclk_rate);
2590                 return -EINVAL;
2591         }
2592         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2593                 lrclk, bclk_rate / lrclk);
2594
2595         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2596         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2597         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2598         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2599                             lrclk);
2600         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2601                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2602
2603         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2604                 switch (dai->id) {
2605                 case 1:
2606                         wm8994->dac_rates[0] = params_rate(params);
2607                         wm8994_set_retune_mobile(codec, 0);
2608                         wm8994_set_retune_mobile(codec, 1);
2609                         break;
2610                 case 2:
2611                         wm8994->dac_rates[1] = params_rate(params);
2612                         wm8994_set_retune_mobile(codec, 2);
2613                         break;
2614                 }
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2621                                  struct snd_pcm_hw_params *params,
2622                                  struct snd_soc_dai *dai)
2623 {
2624         struct snd_soc_codec *codec = dai->codec;
2625         struct wm8994 *control = codec->control_data;
2626         int aif1_reg;
2627         int aif1 = 0;
2628
2629         switch (dai->id) {
2630         case 3:
2631                 switch (control->type) {
2632                 case WM1811:
2633                 case WM8958:
2634                         aif1_reg = WM8958_AIF3_CONTROL_1;
2635                         break;
2636                 default:
2637                         return 0;
2638                 }
2639                 break;
2640         default:
2641                 return 0;
2642         }
2643
2644         switch (params_format(params)) {
2645         case SNDRV_PCM_FORMAT_S16_LE:
2646                 break;
2647         case SNDRV_PCM_FORMAT_S20_3LE:
2648                 aif1 |= 0x20;
2649                 break;
2650         case SNDRV_PCM_FORMAT_S24_LE:
2651                 aif1 |= 0x40;
2652                 break;
2653         case SNDRV_PCM_FORMAT_S32_LE:
2654                 aif1 |= 0x60;
2655                 break;
2656         default:
2657                 return -EINVAL;
2658         }
2659
2660         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2661 }
2662
2663 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2664                                 struct snd_soc_dai *dai)
2665 {
2666         struct snd_soc_codec *codec = dai->codec;
2667         int rate_reg = 0;
2668
2669         switch (dai->id) {
2670         case 1:
2671                 rate_reg = WM8994_AIF1_RATE;
2672                 break;
2673         case 2:
2674                 rate_reg = WM8994_AIF2_RATE;
2675                 break;
2676         default:
2677                 break;
2678         }
2679
2680         /* If the DAI is idle then configure the divider tree for the
2681          * lowest output rate to save a little power if the clock is
2682          * still active (eg, because it is system clock).
2683          */
2684         if (rate_reg && !dai->playback_active && !dai->capture_active)
2685                 snd_soc_update_bits(codec, rate_reg,
2686                                     WM8994_AIF1_SR_MASK |
2687                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2688 }
2689
2690 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2691 {
2692         struct snd_soc_codec *codec = codec_dai->codec;
2693         int mute_reg;
2694         int reg;
2695
2696         switch (codec_dai->id) {
2697         case 1:
2698                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2699                 break;
2700         case 2:
2701                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2702                 break;
2703         default:
2704                 return -EINVAL;
2705         }
2706
2707         if (mute)
2708                 reg = WM8994_AIF1DAC1_MUTE;
2709         else
2710                 reg = 0;
2711
2712         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2713
2714         return 0;
2715 }
2716
2717 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2718 {
2719         struct snd_soc_codec *codec = codec_dai->codec;
2720         int reg, val, mask;
2721
2722         switch (codec_dai->id) {
2723         case 1:
2724                 reg = WM8994_AIF1_MASTER_SLAVE;
2725                 mask = WM8994_AIF1_TRI;
2726                 break;
2727         case 2:
2728                 reg = WM8994_AIF2_MASTER_SLAVE;
2729                 mask = WM8994_AIF2_TRI;
2730                 break;
2731         case 3:
2732                 reg = WM8994_POWER_MANAGEMENT_6;
2733                 mask = WM8994_AIF3_TRI;
2734                 break;
2735         default:
2736                 return -EINVAL;
2737         }
2738
2739         if (tristate)
2740                 val = mask;
2741         else
2742                 val = 0;
2743
2744         return snd_soc_update_bits(codec, reg, mask, val);
2745 }
2746
2747 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2748 {
2749         struct snd_soc_codec *codec = dai->codec;
2750
2751         /* Disable the pulls on the AIF if we're using it to save power. */
2752         snd_soc_update_bits(codec, WM8994_GPIO_3,
2753                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2754         snd_soc_update_bits(codec, WM8994_GPIO_4,
2755                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2756         snd_soc_update_bits(codec, WM8994_GPIO_5,
2757                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2758
2759         return 0;
2760 }
2761
2762 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2763
2764 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2765                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2766
2767 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2768         .set_sysclk     = wm8994_set_dai_sysclk,
2769         .set_fmt        = wm8994_set_dai_fmt,
2770         .hw_params      = wm8994_hw_params,
2771         .shutdown       = wm8994_aif_shutdown,
2772         .digital_mute   = wm8994_aif_mute,
2773         .set_pll        = wm8994_set_fll,
2774         .set_tristate   = wm8994_set_tristate,
2775 };
2776
2777 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2778         .set_sysclk     = wm8994_set_dai_sysclk,
2779         .set_fmt        = wm8994_set_dai_fmt,
2780         .hw_params      = wm8994_hw_params,
2781         .shutdown       = wm8994_aif_shutdown,
2782         .digital_mute   = wm8994_aif_mute,
2783         .set_pll        = wm8994_set_fll,
2784         .set_tristate   = wm8994_set_tristate,
2785 };
2786
2787 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2788         .hw_params      = wm8994_aif3_hw_params,
2789         .set_tristate   = wm8994_set_tristate,
2790 };
2791
2792 static struct snd_soc_dai_driver wm8994_dai[] = {
2793         {
2794                 .name = "wm8994-aif1",
2795                 .id = 1,
2796                 .playback = {
2797                         .stream_name = "AIF1 Playback",
2798                         .channels_min = 1,
2799                         .channels_max = 2,
2800                         .rates = WM8994_RATES,
2801                         .formats = WM8994_FORMATS,
2802                 },
2803                 .capture = {
2804                         .stream_name = "AIF1 Capture",
2805                         .channels_min = 1,
2806                         .channels_max = 2,
2807                         .rates = WM8994_RATES,
2808                         .formats = WM8994_FORMATS,
2809                  },
2810                 .ops = &wm8994_aif1_dai_ops,
2811         },
2812         {
2813                 .name = "wm8994-aif2",
2814                 .id = 2,
2815                 .playback = {
2816                         .stream_name = "AIF2 Playback",
2817                         .channels_min = 1,
2818                         .channels_max = 2,
2819                         .rates = WM8994_RATES,
2820                         .formats = WM8994_FORMATS,
2821                 },
2822                 .capture = {
2823                         .stream_name = "AIF2 Capture",
2824                         .channels_min = 1,
2825                         .channels_max = 2,
2826                         .rates = WM8994_RATES,
2827                         .formats = WM8994_FORMATS,
2828                 },
2829                 .probe = wm8994_aif2_probe,
2830                 .ops = &wm8994_aif2_dai_ops,
2831         },
2832         {
2833                 .name = "wm8994-aif3",
2834                 .id = 3,
2835                 .playback = {
2836                         .stream_name = "AIF3 Playback",
2837                         .channels_min = 1,
2838                         .channels_max = 2,
2839                         .rates = WM8994_RATES,
2840                         .formats = WM8994_FORMATS,
2841                 },
2842                 .capture = {
2843                         .stream_name = "AIF3 Capture",
2844                         .channels_min = 1,
2845                         .channels_max = 2,
2846                         .rates = WM8994_RATES,
2847                         .formats = WM8994_FORMATS,
2848                 },
2849                 .ops = &wm8994_aif3_dai_ops,
2850         }
2851 };
2852
2853 #ifdef CONFIG_PM
2854 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2855 {
2856         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2857         struct wm8994 *control = codec->control_data;
2858         int i, ret;
2859
2860         switch (control->type) {
2861         case WM8994:
2862                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2863                 break;
2864         case WM1811:
2865         case WM8958:
2866                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2867                                     WM8958_MICD_ENA, 0);
2868                 break;
2869         }
2870
2871         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2872                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2873                        sizeof(struct wm8994_fll_config));
2874                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2875                 if (ret < 0)
2876                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2877                                  i + 1, ret);
2878         }
2879
2880         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2881
2882         return 0;
2883 }
2884
2885 static int wm8994_resume(struct snd_soc_codec *codec)
2886 {
2887         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2888         struct wm8994 *control = codec->control_data;
2889         int i, ret;
2890         unsigned int val, mask;
2891
2892         if (wm8994->revision < 4) {
2893                 /* force a HW read */
2894                 val = wm8994_reg_read(codec->control_data,
2895                                       WM8994_POWER_MANAGEMENT_5);
2896
2897                 /* modify the cache only */
2898                 codec->cache_only = 1;
2899                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2900                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2901                 val &= mask;
2902                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2903                                     mask, val);
2904                 codec->cache_only = 0;
2905         }
2906
2907         /* Restore the registers */
2908         ret = snd_soc_cache_sync(codec);
2909         if (ret != 0)
2910                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2911
2912         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2913
2914         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2915                 if (!wm8994->fll_suspend[i].out)
2916                         continue;
2917
2918                 ret = _wm8994_set_fll(codec, i + 1,
2919                                      wm8994->fll_suspend[i].src,
2920                                      wm8994->fll_suspend[i].in,
2921                                      wm8994->fll_suspend[i].out);
2922                 if (ret < 0)
2923                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2924                                  i + 1, ret);
2925         }
2926
2927         switch (control->type) {
2928         case WM8994:
2929                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2930                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2931                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2932                 break;
2933         case WM1811:
2934         case WM8958:
2935                 if (wm8994->jack_cb)
2936                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2937                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2938                 break;
2939         }
2940
2941         return 0;
2942 }
2943 #else
2944 #define wm8994_suspend NULL
2945 #define wm8994_resume NULL
2946 #endif
2947
2948 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2949 {
2950         struct snd_soc_codec *codec = wm8994->codec;
2951         struct wm8994_pdata *pdata = wm8994->pdata;
2952         struct snd_kcontrol_new controls[] = {
2953                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2954                              wm8994->retune_mobile_enum,
2955                              wm8994_get_retune_mobile_enum,
2956                              wm8994_put_retune_mobile_enum),
2957                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2958                              wm8994->retune_mobile_enum,
2959                              wm8994_get_retune_mobile_enum,
2960                              wm8994_put_retune_mobile_enum),
2961                 SOC_ENUM_EXT("AIF2 EQ Mode",
2962                              wm8994->retune_mobile_enum,
2963                              wm8994_get_retune_mobile_enum,
2964                              wm8994_put_retune_mobile_enum),
2965         };
2966         int ret, i, j;
2967         const char **t;
2968
2969         /* We need an array of texts for the enum API but the number
2970          * of texts is likely to be less than the number of
2971          * configurations due to the sample rate dependency of the
2972          * configurations. */
2973         wm8994->num_retune_mobile_texts = 0;
2974         wm8994->retune_mobile_texts = NULL;
2975         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2976                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2977                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2978                                    wm8994->retune_mobile_texts[j]) == 0)
2979                                 break;
2980                 }
2981
2982                 if (j != wm8994->num_retune_mobile_texts)
2983                         continue;
2984
2985                 /* Expand the array... */
2986                 t = krealloc(wm8994->retune_mobile_texts,
2987                              sizeof(char *) *
2988                              (wm8994->num_retune_mobile_texts + 1),
2989                              GFP_KERNEL);
2990                 if (t == NULL)
2991                         continue;
2992
2993                 /* ...store the new entry... */
2994                 t[wm8994->num_retune_mobile_texts] =
2995                         pdata->retune_mobile_cfgs[i].name;
2996
2997                 /* ...and remember the new version. */
2998                 wm8994->num_retune_mobile_texts++;
2999                 wm8994->retune_mobile_texts = t;
3000         }
3001
3002         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3003                 wm8994->num_retune_mobile_texts);
3004
3005         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3006         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3007
3008         ret = snd_soc_add_controls(wm8994->codec, controls,
3009                                    ARRAY_SIZE(controls));
3010         if (ret != 0)
3011                 dev_err(wm8994->codec->dev,
3012                         "Failed to add ReTune Mobile controls: %d\n", ret);
3013 }
3014
3015 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3016 {
3017         struct snd_soc_codec *codec = wm8994->codec;
3018         struct wm8994_pdata *pdata = wm8994->pdata;
3019         int ret, i;
3020
3021         if (!pdata)
3022                 return;
3023
3024         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3025                                       pdata->lineout2_diff,
3026                                       pdata->lineout1fb,
3027                                       pdata->lineout2fb,
3028                                       pdata->jd_scthr,
3029                                       pdata->jd_thr,
3030                                       pdata->micbias1_lvl,
3031                                       pdata->micbias2_lvl);
3032
3033         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3034
3035         if (pdata->num_drc_cfgs) {
3036                 struct snd_kcontrol_new controls[] = {
3037                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3038                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3039                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3040                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3041                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3042                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3043                 };
3044
3045                 /* We need an array of texts for the enum API */
3046                 wm8994->drc_texts = kmalloc(sizeof(char *)
3047                                             * pdata->num_drc_cfgs, GFP_KERNEL);
3048                 if (!wm8994->drc_texts) {
3049                         dev_err(wm8994->codec->dev,
3050                                 "Failed to allocate %d DRC config texts\n",
3051                                 pdata->num_drc_cfgs);
3052                         return;
3053                 }
3054
3055                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3056                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3057
3058                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3059                 wm8994->drc_enum.texts = wm8994->drc_texts;
3060
3061                 ret = snd_soc_add_controls(wm8994->codec, controls,
3062                                            ARRAY_SIZE(controls));
3063                 if (ret != 0)
3064                         dev_err(wm8994->codec->dev,
3065                                 "Failed to add DRC mode controls: %d\n", ret);
3066
3067                 for (i = 0; i < WM8994_NUM_DRC; i++)
3068                         wm8994_set_drc(codec, i);
3069         }
3070
3071         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3072                 pdata->num_retune_mobile_cfgs);
3073
3074         if (pdata->num_retune_mobile_cfgs)
3075                 wm8994_handle_retune_mobile_pdata(wm8994);
3076         else
3077                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
3078                                      ARRAY_SIZE(wm8994_eq_controls));
3079
3080         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3081                 if (pdata->micbias[i]) {
3082                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3083                                 pdata->micbias[i] & 0xffff);
3084                 }
3085         }
3086 }
3087
3088 /**
3089  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3090  *
3091  * @codec:   WM8994 codec
3092  * @jack:    jack to report detection events on
3093  * @micbias: microphone bias to detect on
3094  * @det:     value to report for presence detection
3095  * @shrt:    value to report for short detection
3096  *
3097  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3098  * being used to bring out signals to the processor then only platform
3099  * data configuration is needed for WM8994 and processor GPIOs should
3100  * be configured using snd_soc_jack_add_gpios() instead.
3101  *
3102  * Configuration of detection levels is available via the micbias1_lvl
3103  * and micbias2_lvl platform data members.
3104  */
3105 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3106                       int micbias, int det, int shrt)
3107 {
3108         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3109         struct wm8994_micdet *micdet;
3110         struct wm8994 *control = codec->control_data;
3111         int reg;
3112
3113         if (control->type != WM8994)
3114                 return -EINVAL;
3115
3116         switch (micbias) {
3117         case 1:
3118                 micdet = &wm8994->micdet[0];
3119                 break;
3120         case 2:
3121                 micdet = &wm8994->micdet[1];
3122                 break;
3123         default:
3124                 return -EINVAL;
3125         }
3126
3127         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3128                 micbias, det, shrt);
3129
3130         /* Store the configuration */
3131         micdet->jack = jack;
3132         micdet->det = det;
3133         micdet->shrt = shrt;
3134
3135         /* If either of the jacks is set up then enable detection */
3136         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3137                 reg = WM8994_MICD_ENA;
3138         else
3139                 reg = 0;
3140
3141         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3142
3143         return 0;
3144 }
3145 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3146
3147 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3148 {
3149         struct wm8994_priv *priv = data;
3150         struct snd_soc_codec *codec = priv->codec;
3151         int reg;
3152         int report;
3153
3154 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3155         trace_snd_soc_jack_irq(dev_name(codec->dev));
3156 #endif
3157
3158         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3159         if (reg < 0) {
3160                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3161                         reg);
3162                 return IRQ_HANDLED;
3163         }
3164
3165         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3166
3167         report = 0;
3168         if (reg & WM8994_MIC1_DET_STS)
3169                 report |= priv->micdet[0].det;
3170         if (reg & WM8994_MIC1_SHRT_STS)
3171                 report |= priv->micdet[0].shrt;
3172         snd_soc_jack_report(priv->micdet[0].jack, report,
3173                             priv->micdet[0].det | priv->micdet[0].shrt);
3174
3175         report = 0;
3176         if (reg & WM8994_MIC2_DET_STS)
3177                 report |= priv->micdet[1].det;
3178         if (reg & WM8994_MIC2_SHRT_STS)
3179                 report |= priv->micdet[1].shrt;
3180         snd_soc_jack_report(priv->micdet[1].jack, report,
3181                             priv->micdet[1].det | priv->micdet[1].shrt);
3182
3183         return IRQ_HANDLED;
3184 }
3185
3186 /* Default microphone detection handler for WM8958 - the user can
3187  * override this if they wish.
3188  */
3189 static void wm8958_default_micdet(u16 status, void *data)
3190 {
3191         struct snd_soc_codec *codec = data;
3192         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3193         int report = 0;
3194
3195         /* If nothing present then clear our statuses */
3196         if (!(status & WM8958_MICD_STS))
3197                 goto done;
3198
3199         report = SND_JACK_MICROPHONE;
3200
3201         /* Everything else is buttons; just assign slots */
3202         if (status & 0x1c)
3203                 report |= SND_JACK_BTN_0;
3204
3205 done:
3206         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3207                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
3208 }
3209
3210 /**
3211  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3212  *
3213  * @codec:   WM8958 codec
3214  * @jack:    jack to report detection events on
3215  *
3216  * Enable microphone detection functionality for the WM8958.  By
3217  * default simple detection which supports the detection of up to 6
3218  * buttons plus video and microphone functionality is supported.
3219  *
3220  * The WM8958 has an advanced jack detection facility which is able to
3221  * support complex accessory detection, especially when used in
3222  * conjunction with external circuitry.  In order to provide maximum
3223  * flexiblity a callback is provided which allows a completely custom
3224  * detection algorithm.
3225  */
3226 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3227                       wm8958_micdet_cb cb, void *cb_data)
3228 {
3229         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3230         struct wm8994 *control = codec->control_data;
3231
3232         switch (control->type) {
3233         case WM1811:
3234         case WM8958:
3235                 break;
3236         default:
3237                 return -EINVAL;
3238         }
3239
3240         if (jack) {
3241                 if (!cb) {
3242                         dev_dbg(codec->dev, "Using default micdet callback\n");
3243                         cb = wm8958_default_micdet;
3244                         cb_data = codec;
3245                 }
3246
3247                 wm8994->micdet[0].jack = jack;
3248                 wm8994->jack_cb = cb;
3249                 wm8994->jack_cb_data = cb_data;
3250
3251                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3252                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3253         } else {
3254                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3255                                     WM8958_MICD_ENA, 0);
3256         }
3257
3258         return 0;
3259 }
3260 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3261
3262 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3263 {
3264         struct wm8994_priv *wm8994 = data;
3265         struct snd_soc_codec *codec = wm8994->codec;
3266         int reg, count;
3267
3268         /* We may occasionally read a detection without an impedence
3269          * range being provided - if that happens loop again.
3270          */
3271         count = 10;
3272         do {
3273                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3274                 if (reg < 0) {
3275                         dev_err(codec->dev,
3276                                 "Failed to read mic detect status: %d\n",
3277                                 reg);
3278                         return IRQ_NONE;
3279                 }
3280
3281                 if (!(reg & WM8958_MICD_VALID)) {
3282                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3283                         goto out;
3284                 }
3285
3286                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3287                         break;
3288
3289                 msleep(1);
3290         } while (count--);
3291
3292         if (count == 0)
3293                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3294
3295 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3296         trace_snd_soc_jack_irq(dev_name(codec->dev));
3297 #endif
3298
3299         if (wm8994->jack_cb)
3300                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3301         else
3302                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3303
3304 out:
3305         return IRQ_HANDLED;
3306 }
3307
3308 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3309 {
3310         struct snd_soc_codec *codec = data;
3311
3312         dev_err(codec->dev, "FIFO error\n");
3313
3314         return IRQ_HANDLED;
3315 }
3316
3317 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3318 {
3319         struct snd_soc_codec *codec = data;
3320
3321         dev_err(codec->dev, "Thermal warning\n");
3322
3323         return IRQ_HANDLED;
3324 }
3325
3326 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3327 {
3328         struct snd_soc_codec *codec = data;
3329
3330         dev_crit(codec->dev, "Thermal shutdown\n");
3331
3332         return IRQ_HANDLED;
3333 }
3334
3335 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3336 {
3337         struct wm8994 *control;
3338         struct wm8994_priv *wm8994;
3339         struct snd_soc_dapm_context *dapm = &codec->dapm;
3340         int ret, i;
3341
3342         codec->control_data = dev_get_drvdata(codec->dev->parent);
3343         control = codec->control_data;
3344
3345         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3346         if (wm8994 == NULL)
3347                 return -ENOMEM;
3348         snd_soc_codec_set_drvdata(codec, wm8994);
3349
3350         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3351         wm8994->codec = codec;
3352
3353         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3354                 init_completion(&wm8994->fll_locked[i]);
3355
3356         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3357                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3358         else if (wm8994->pdata && wm8994->pdata->irq_base)
3359                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3360                                      WM8994_IRQ_MIC1_DET;
3361
3362         pm_runtime_enable(codec->dev);
3363         pm_runtime_resume(codec->dev);
3364
3365         /* Read our current status back from the chip - we don't want to
3366          * reset as this may interfere with the GPIO or LDO operation. */
3367         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3368                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3369                         continue;
3370
3371                 ret = wm8994_reg_read(codec->control_data, i);
3372                 if (ret <= 0)
3373                         continue;
3374
3375                 ret = snd_soc_cache_write(codec, i, ret);
3376                 if (ret != 0) {
3377                         dev_err(codec->dev,
3378                                 "Failed to initialise cache for 0x%x: %d\n",
3379                                 i, ret);
3380                         goto err;
3381                 }
3382         }
3383
3384         /* Set revision-specific configuration */
3385         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3386         switch (control->type) {
3387         case WM8994:
3388                 switch (wm8994->revision) {
3389                 case 2:
3390                 case 3:
3391                         wm8994->hubs.dcs_codes_l = -5;
3392                         wm8994->hubs.dcs_codes_r = -5;
3393                         wm8994->hubs.hp_startup_mode = 1;
3394                         wm8994->hubs.dcs_readback_mode = 1;
3395                         wm8994->hubs.series_startup = 1;
3396                         break;
3397                 default:
3398                         wm8994->hubs.dcs_readback_mode = 2;
3399                         break;
3400                 }
3401                 break;
3402
3403         case WM8958:
3404                 wm8994->hubs.dcs_readback_mode = 1;
3405                 break;
3406
3407         case WM1811:
3408                 wm8994->hubs.dcs_readback_mode = 2;
3409                 wm8994->hubs.no_series_update = 1;
3410
3411                 switch (wm8994->revision) {
3412                 case 0:
3413                 case 1:
3414                 case 2:
3415                 case 3:
3416                         wm8994->hubs.dcs_codes_l = -9;
3417                         wm8994->hubs.dcs_codes_r = -7;
3418                         break;
3419                 default:
3420                         break;
3421                 }
3422
3423                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3424                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3425                 break;
3426
3427         default:
3428                 break;
3429         }
3430
3431         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3432                            wm8994_fifo_error, "FIFO error", codec);
3433         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_WARN,
3434                            wm8994_temp_warn, "Thermal warning", codec);
3435         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT,
3436                            wm8994_temp_shut, "Thermal shutdown", codec);
3437
3438         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3439                                  wm_hubs_dcs_done, "DC servo done",
3440                                  &wm8994->hubs);
3441         if (ret == 0)
3442                 wm8994->hubs.dcs_done_irq = true;
3443
3444         switch (control->type) {
3445         case WM8994:
3446                 if (wm8994->micdet_irq) {
3447                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3448                                                    wm8994_mic_irq,
3449                                                    IRQF_TRIGGER_RISING,
3450                                                    "Mic1 detect",
3451                                                    wm8994);
3452                         if (ret != 0)
3453                                 dev_warn(codec->dev,
3454                                          "Failed to request Mic1 detect IRQ: %d\n",
3455                                          ret);
3456                 }
3457
3458                 ret = wm8994_request_irq(codec->control_data,
3459                                          WM8994_IRQ_MIC1_SHRT,
3460                                          wm8994_mic_irq, "Mic 1 short",
3461                                          wm8994);
3462                 if (ret != 0)
3463                         dev_warn(codec->dev,
3464                                  "Failed to request Mic1 short IRQ: %d\n",
3465                                  ret);
3466
3467                 ret = wm8994_request_irq(codec->control_data,
3468                                          WM8994_IRQ_MIC2_DET,
3469                                          wm8994_mic_irq, "Mic 2 detect",
3470                                          wm8994);
3471                 if (ret != 0)
3472                         dev_warn(codec->dev,
3473                                  "Failed to request Mic2 detect IRQ: %d\n",
3474                                  ret);
3475
3476                 ret = wm8994_request_irq(codec->control_data,
3477                                          WM8994_IRQ_MIC2_SHRT,
3478                                          wm8994_mic_irq, "Mic 2 short",
3479                                          wm8994);
3480                 if (ret != 0)
3481                         dev_warn(codec->dev,
3482                                  "Failed to request Mic2 short IRQ: %d\n",
3483                                  ret);
3484                 break;
3485
3486         case WM8958:
3487         case WM1811:
3488                 if (wm8994->micdet_irq) {
3489                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3490                                                    wm8958_mic_irq,
3491                                                    IRQF_TRIGGER_RISING,
3492                                                    "Mic detect",
3493                                                    wm8994);
3494                         if (ret != 0)
3495                                 dev_warn(codec->dev,
3496                                          "Failed to request Mic detect IRQ: %d\n",
3497                                          ret);
3498                 }
3499         }
3500
3501         wm8994->fll_locked_irq = true;
3502         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3503                 ret = wm8994_request_irq(codec->control_data,
3504                                          WM8994_IRQ_FLL1_LOCK + i,
3505                                          wm8994_fll_locked_irq, "FLL lock",
3506                                          &wm8994->fll_locked[i]);
3507                 if (ret != 0)
3508                         wm8994->fll_locked_irq = false;
3509         }
3510
3511         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3512          * configured on init - if a system wants to do this dynamically
3513          * at runtime we can deal with that then.
3514          */
3515         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3516         if (ret < 0) {
3517                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3518                 goto err_irq;
3519         }
3520         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3521                 wm8994->lrclk_shared[0] = 1;
3522                 wm8994_dai[0].symmetric_rates = 1;
3523         } else {
3524                 wm8994->lrclk_shared[0] = 0;
3525         }
3526
3527         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3528         if (ret < 0) {
3529                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3530                 goto err_irq;
3531         }
3532         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3533                 wm8994->lrclk_shared[1] = 1;
3534                 wm8994_dai[1].symmetric_rates = 1;
3535         } else {
3536                 wm8994->lrclk_shared[1] = 0;
3537         }
3538
3539         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3540
3541         /* Latch volume update bits */
3542         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3543                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3544                                     wm8994_vu_bits[i].mask,
3545                                     wm8994_vu_bits[i].mask);
3546
3547         /* Set the low bit of the 3D stereo depth so TLV matches */
3548         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3549                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3550                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3551         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3552                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3553                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3554         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3555                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3556                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3557
3558         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3559          * use this; it only affects behaviour on idle TDM clock
3560          * cycles. */
3561         switch (control->type) {
3562         case WM8994:
3563         case WM8958:
3564                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3565                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3566                 break;
3567         default:
3568                 break;
3569         }
3570
3571         wm8994_update_class_w(codec);
3572
3573         wm8994_handle_pdata(wm8994);
3574
3575         wm_hubs_add_analogue_controls(codec);
3576         snd_soc_add_controls(codec, wm8994_snd_controls,
3577                              ARRAY_SIZE(wm8994_snd_controls));
3578         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3579                                   ARRAY_SIZE(wm8994_dapm_widgets));
3580
3581         switch (control->type) {
3582         case WM8994:
3583                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3584                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3585                 if (wm8994->revision < 4) {
3586                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3587                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3588                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3589                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3590                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3591                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3592                 } else {
3593                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3594                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3595                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3596                                                   ARRAY_SIZE(wm8994_adc_widgets));
3597                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3598                                                   ARRAY_SIZE(wm8994_dac_widgets));
3599                 }
3600                 break;
3601         case WM8958:
3602                 snd_soc_add_controls(codec, wm8958_snd_controls,
3603                                      ARRAY_SIZE(wm8958_snd_controls));
3604                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3605                                           ARRAY_SIZE(wm8958_dapm_widgets));
3606                 if (wm8994->revision < 1) {
3607                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3608                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3609                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3610                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3611                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3612                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3613                 } else {
3614                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3615                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3616                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3617                                                   ARRAY_SIZE(wm8994_adc_widgets));
3618                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3619                                                   ARRAY_SIZE(wm8994_dac_widgets));
3620                 }
3621                 break;
3622
3623         case WM1811:
3624                 snd_soc_add_controls(codec, wm8958_snd_controls,
3625                                      ARRAY_SIZE(wm8958_snd_controls));
3626                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3627                                           ARRAY_SIZE(wm8958_dapm_widgets));
3628                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3629                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3630                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3631                                           ARRAY_SIZE(wm8994_adc_widgets));
3632                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3633                                           ARRAY_SIZE(wm8994_dac_widgets));
3634                 break;
3635         }
3636
3637
3638         wm_hubs_add_analogue_routes(codec, 0, 0);
3639         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3640
3641         switch (control->type) {
3642         case WM8994:
3643                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3644                                         ARRAY_SIZE(wm8994_intercon));
3645
3646                 if (wm8994->revision < 4) {
3647                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3648                                                 ARRAY_SIZE(wm8994_revd_intercon));
3649                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3650                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3651                 } else {
3652                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3653                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3654                 }
3655                 break;
3656         case WM8958:
3657                 if (wm8994->revision < 1) {
3658                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3659                                                 ARRAY_SIZE(wm8994_revd_intercon));
3660                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3661                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3662                 } else {
3663                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3664                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3665                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3666                                                 ARRAY_SIZE(wm8958_intercon));
3667                 }
3668
3669                 wm8958_dsp2_init(codec);
3670                 break;
3671         case WM1811:
3672                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3673                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3674                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3675                                         ARRAY_SIZE(wm8958_intercon));
3676                 break;
3677         }
3678
3679         return 0;
3680
3681 err_irq:
3682         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3683         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3684         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3685         if (wm8994->micdet_irq)
3686                 free_irq(wm8994->micdet_irq, wm8994);
3687         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3688                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3689                                 &wm8994->fll_locked[i]);
3690         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3691                         &wm8994->hubs);
3692         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3693         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3694         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3695 err:
3696         kfree(wm8994);
3697         return ret;
3698 }
3699
3700 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3701 {
3702         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3703         struct wm8994 *control = codec->control_data;
3704         int i;
3705
3706         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3707
3708         pm_runtime_disable(codec->dev);
3709
3710         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3711                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3712                                 &wm8994->fll_locked[i]);
3713
3714         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3715                         &wm8994->hubs);
3716         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3717         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3718         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3719
3720         switch (control->type) {
3721         case WM8994:
3722                 if (wm8994->micdet_irq)
3723                         free_irq(wm8994->micdet_irq, wm8994);
3724                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3725                                 wm8994);
3726                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3727                                 wm8994);
3728                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3729                                 wm8994);
3730                 break;
3731
3732         case WM1811:
3733         case WM8958:
3734                 if (wm8994->micdet_irq)
3735                         free_irq(wm8994->micdet_irq, wm8994);
3736                 break;
3737         }
3738         if (wm8994->mbc)
3739                 release_firmware(wm8994->mbc);
3740         if (wm8994->mbc_vss)
3741                 release_firmware(wm8994->mbc_vss);
3742         if (wm8994->enh_eq)
3743                 release_firmware(wm8994->enh_eq);
3744         kfree(wm8994->retune_mobile_texts);
3745         kfree(wm8994->drc_texts);
3746         kfree(wm8994);
3747
3748         return 0;
3749 }
3750
3751 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3752         .probe =        wm8994_codec_probe,
3753         .remove =       wm8994_codec_remove,
3754         .suspend =      wm8994_suspend,
3755         .resume =       wm8994_resume,
3756         .read =         wm8994_read,
3757         .write =        wm8994_write,
3758         .readable_register = wm8994_readable,
3759         .volatile_register = wm8994_volatile,
3760         .set_bias_level = wm8994_set_bias_level,
3761
3762         .reg_cache_size = WM8994_CACHE_SIZE,
3763         .reg_cache_default = wm8994_reg_defaults,
3764         .reg_word_size = 2,
3765         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3766 };
3767
3768 static int __devinit wm8994_probe(struct platform_device *pdev)
3769 {
3770         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3771                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3772 }
3773
3774 static int __devexit wm8994_remove(struct platform_device *pdev)
3775 {
3776         snd_soc_unregister_codec(&pdev->dev);
3777         return 0;
3778 }
3779
3780 static struct platform_driver wm8994_codec_driver = {
3781         .driver = {
3782                    .name = "wm8994-codec",
3783                    .owner = THIS_MODULE,
3784                    },
3785         .probe = wm8994_probe,
3786         .remove = __devexit_p(wm8994_remove),
3787 };
3788
3789 static __init int wm8994_init(void)
3790 {
3791         return platform_driver_register(&wm8994_codec_driver);
3792 }
3793 module_init(wm8994_init);
3794
3795 static __exit void wm8994_exit(void)
3796 {
3797         platform_driver_unregister(&wm8994_codec_driver);
3798 }
3799 module_exit(wm8994_exit);
3800
3801
3802 MODULE_DESCRIPTION("ASoC WM8994 driver");
3803 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3804 MODULE_LICENSE("GPL");
3805 MODULE_ALIAS("platform:wm8994-codec");