sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = codec->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110         case WM8994_DC_SERVO_4E:
 111                 return 1;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 118         unsigned int value)
 119 {
 120         int ret;
 121
 122         BUG_ON(reg > WM8994_MAX_REGISTER);
 123
 124         if (!wm8994_volatile(codec, reg)) {
 125                 ret = snd_soc_cache_write(codec, reg, value);
 126                 if (ret != 0)
 127                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 128                                 reg, ret);
 129         }
 130
 131         return wm8994_reg_write(codec->control_data, reg, value);
 132 }
 133
 134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 135                                 unsigned int reg)
 136 {
 137         unsigned int val;
 138         int ret;
 139
 140         BUG_ON(reg > WM8994_MAX_REGISTER);
 141
 142         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 143             reg < codec->driver->reg_cache_size) {
 144                 ret = snd_soc_cache_read(codec, reg, &val);
 145                 if (ret >= 0)
 146                         return val;
 147                 else
 148                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 149                                 reg, ret);
 150         }
 151
 152         return wm8994_reg_read(codec->control_data, reg);
 153 }
 154
 155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 156 {
 157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 158         int rate;
 159         int reg1 = 0;
 160         int offset;
 161
 162         if (aif)
 163                 offset = 4;
 164         else
 165                 offset = 0;
 166
 167         switch (wm8994->sysclk[aif]) {
 168         case WM8994_SYSCLK_MCLK1:
 169                 rate = wm8994->mclk[0];
 170                 break;
 171
 172         case WM8994_SYSCLK_MCLK2:
 173                 reg1 |= 0x8;
 174                 rate = wm8994->mclk[1];
 175                 break;
 176
 177         case WM8994_SYSCLK_FLL1:
 178                 reg1 |= 0x10;
 179                 rate = wm8994->fll[0].out;
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL2:
 183                 reg1 |= 0x18;
 184                 rate = wm8994->fll[1].out;
 185                 break;
 186
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         if (rate >= 13500000) {
 192                 rate /= 2;
 193                 reg1 |= WM8994_AIF1CLK_DIV;
 194
 195                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 196                         aif + 1, rate);
 197         }
 198
 199         wm8994->aifclk[aif] = rate;
 200
 201         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 202                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 203                             reg1);
 204
 205         return 0;
 206 }
 207
 208 static int configure_clock(struct snd_soc_codec *codec)
 209 {
 210         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 211         int change, new;
 212
 213         /* Bring up the AIF clocks first */
 214         configure_aif_clock(codec, 0);
 215         configure_aif_clock(codec, 1);
 216
 217         /* Then switch CLK_SYS over to the higher of them; a change
 218          * can only happen as a result of a clocking change which can
 219          * only be made outside of DAPM so we can safely redo the
 220          * clocking.
 221          */
 222
 223         /* If they're equal it doesn't matter which is used */
 224         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 225                 return 0;
 226
 227         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 228                 new = WM8994_SYSCLK_SRC;
 229         else
 230                 new = 0;
 231
 232         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 233                                      WM8994_SYSCLK_SRC, new);
 234         if (!change)
 235                 return 0;
 236
 237         snd_soc_dapm_sync(&codec->dapm);
 238
 239         return 0;
 240 }
 241
 242 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 243                          struct snd_soc_dapm_widget *sink)
 244 {
 245         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 246         const char *clk;
 247
 248         /* Check what we're currently using for CLK_SYS */
 249         if (reg & WM8994_SYSCLK_SRC)
 250                 clk = "AIF2CLK";
 251         else
 252                 clk = "AIF1CLK";
 253
 254         return strcmp(source->name, clk) == 0;
 255 }
 256
 257 static const char *sidetone_hpf_text[] = {
 258         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 259 };
 260
 261 static const struct soc_enum sidetone_hpf =
 262         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 263
 264 static const char *adc_hpf_text[] = {
 265         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 266 };
 267
 268 static const struct soc_enum aif1adc1_hpf =
 269         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 270
 271 static const struct soc_enum aif1adc2_hpf =
 272         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 273
 274 static const struct soc_enum aif2adc_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 279 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 280 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 281 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 282 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 283 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 284
 285 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 287         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 288         .put = wm8994_put_drc_sw, \
 289         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 290
 291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 292                              struct snd_ctl_elem_value *ucontrol)
 293 {
 294         struct soc_mixer_control *mc =
 295                 (struct soc_mixer_control *)kcontrol->private_value;
 296         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 297         int mask, ret;
 298
 299         /* Can't enable both ADC and DAC paths simultaneously */
 300         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 301                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 302                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 303         else
 304                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 305
 306         ret = snd_soc_read(codec, mc->reg);
 307         if (ret < 0)
 308                 return ret;
 309         if (ret & mask)
 310                 return -EINVAL;
 311
 312         return snd_soc_put_volsw(kcontrol, ucontrol);
 313 }
 314
 315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 316 {
 317         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 318         struct wm8994_pdata *pdata = wm8994->pdata;
 319         int base = wm8994_drc_base[drc];
 320         int cfg = wm8994->drc_cfg[drc];
 321         int save, i;
 322
 323         /* Save any enables; the configuration should clear them. */
 324         save = snd_soc_read(codec, base);
 325         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 326                 WM8994_AIF1ADC1R_DRC_ENA;
 327
 328         for (i = 0; i < WM8994_DRC_REGS; i++)
 329                 snd_soc_update_bits(codec, base + i, 0xffff,
 330                                     pdata->drc_cfgs[cfg].regs[i]);
 331
 332         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 333                              WM8994_AIF1ADC1L_DRC_ENA |
 334                              WM8994_AIF1ADC1R_DRC_ENA, save);
 335 }
 336
 337 /* Icky as hell but saves code duplication */
 338 static int wm8994_get_drc(const char *name)
 339 {
 340         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 341                 return 0;
 342         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 343                 return 1;
 344         if (strcmp(name, "AIF2DRC Mode") == 0)
 345                 return 2;
 346         return -EINVAL;
 347 }
 348
 349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 350                                struct snd_ctl_elem_value *ucontrol)
 351 {
 352         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 353         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 354         struct wm8994_pdata *pdata = wm8994->pdata;
 355         int drc = wm8994_get_drc(kcontrol->id.name);
 356         int value = ucontrol->value.integer.value[0];
 357
 358         if (drc < 0)
 359                 return drc;
 360
 361         if (value >= pdata->num_drc_cfgs)
 362                 return -EINVAL;
 363
 364         wm8994->drc_cfg[drc] = value;
 365
 366         wm8994_set_drc(codec, drc);
 367
 368         return 0;
 369 }
 370
 371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 372                                struct snd_ctl_elem_value *ucontrol)
 373 {
 374         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 375         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 376         int drc = wm8994_get_drc(kcontrol->id.name);
 377
 378         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 379
 380         return 0;
 381 }
 382
 383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 384 {
 385         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 386         struct wm8994_pdata *pdata = wm8994->pdata;
 387         int base = wm8994_retune_mobile_base[block];
 388         int iface, best, best_val, save, i, cfg;
 389
 390         if (!pdata || !wm8994->num_retune_mobile_texts)
 391                 return;
 392
 393         switch (block) {
 394         case 0:
 395         case 1:
 396                 iface = 0;
 397                 break;
 398         case 2:
 399                 iface = 1;
 400                 break;
 401         default:
 402                 return;
 403         }
 404
 405         /* Find the version of the currently selected configuration
 406          * with the nearest sample rate. */
 407         cfg = wm8994->retune_mobile_cfg[block];
 408         best = 0;
 409         best_val = INT_MAX;
 410         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 411                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 412                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 413                     abs(pdata->retune_mobile_cfgs[i].rate
 414                         - wm8994->dac_rates[iface]) < best_val) {
 415                         best = i;
 416                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 417                                        - wm8994->dac_rates[iface]);
 418                 }
 419         }
 420
 421         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 422                 block,
 423                 pdata->retune_mobile_cfgs[best].name,
 424                 pdata->retune_mobile_cfgs[best].rate,
 425                 wm8994->dac_rates[iface]);
 426
 427         /* The EQ will be disabled while reconfiguring it, remember the
 428          * current configuration.
 429          */
 430         save = snd_soc_read(codec, base);
 431         save &= WM8994_AIF1DAC1_EQ_ENA;
 432
 433         for (i = 0; i < WM8994_EQ_REGS; i++)
 434                 snd_soc_update_bits(codec, base + i, 0xffff,
 435                                 pdata->retune_mobile_cfgs[best].regs[i]);
 436
 437         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 438 }
 439
 440 /* Icky as hell but saves code duplication */
 441 static int wm8994_get_retune_mobile_block(const char *name)
 442 {
 443         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 444                 return 0;
 445         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 446                 return 1;
 447         if (strcmp(name, "AIF2 EQ Mode") == 0)
 448                 return 2;
 449         return -EINVAL;
 450 }
 451
 452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 453                                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 457         struct wm8994_pdata *pdata = wm8994->pdata;
 458         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 459         int value = ucontrol->value.integer.value[0];
 460
 461         if (block < 0)
 462                 return block;
 463
 464         if (value >= pdata->num_retune_mobile_cfgs)
 465                 return -EINVAL;
 466
 467         wm8994->retune_mobile_cfg[block] = value;
 468
 469         wm8994_set_retune_mobile(codec, block);
 470
 471         return 0;
 472 }
 473
 474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 475                                          struct snd_ctl_elem_value *ucontrol)
 476 {
 477         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 478         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 479         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 480
 481         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 482
 483         return 0;
 484 }
 485
 486 static const char *aif_chan_src_text[] = {
 487         "Left", "Right"
 488 };
 489
 490 static const struct soc_enum aif1adcl_src =
 491         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 492
 493 static const struct soc_enum aif1adcr_src =
 494         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 495
 496 static const struct soc_enum aif2adcl_src =
 497         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 498
 499 static const struct soc_enum aif2adcr_src =
 500         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 501
 502 static const struct soc_enum aif1dacl_src =
 503         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 504
 505 static const struct soc_enum aif1dacr_src =
 506         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 507
 508 static const struct soc_enum aif2dacl_src =
 509         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 510
 511 static const struct soc_enum aif2dacr_src =
 512         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 513
 514 static const char *osr_text[] = {
 515         "Low Power", "High Performance",
 516 };
 517
 518 static const struct soc_enum dac_osr =
 519         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 520
 521 static const struct soc_enum adc_osr =
 522         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 523
 524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 526                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 527                  1, 119, 0, digital_tlv),
 528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 529                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 530                  1, 119, 0, digital_tlv),
 531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 532                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 533                  1, 119, 0, digital_tlv),
 534
 535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 539
 540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 542 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 543 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 544
 545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 546                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 548                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 550                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551
 552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 554
 555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 558
 559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 570
 571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 572                5, 12, 0, st_tlv),
 573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 574                0, 12, 0, st_tlv),
 575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 581
 582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 584
 585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 587
 588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 590
 591 SOC_ENUM("ADC OSR", adc_osr),
 592 SOC_ENUM("DAC OSR", dac_osr),
 593
 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 595                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 597              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 598
 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 600                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 602              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 603
 604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 605                6, 1, 1, wm_hubs_spkmix_tlv),
 606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 607                2, 1, 1, wm_hubs_spkmix_tlv),
 608
 609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 610                6, 1, 1, wm_hubs_spkmix_tlv),
 611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 612                2, 1, 1, wm_hubs_spkmix_tlv),
 613
 614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 615                10, 15, 0, wm8994_3d_tlv),
 616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 617            8, 1, 0),
 618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 625            8, 1, 0),
 626 };
 627
 628 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 630                eq_tlv),
 631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 632                eq_tlv),
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 638                eq_tlv),
 639
 640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661 };
 662
 663 static const char *wm8958_ng_text[] = {
 664         "30ms", "125ms", "250ms", "500ms",
 665 };
 666
 667 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 668         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 669                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 670
 671 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 672         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 673                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 674
 675 static const struct soc_enum wm8958_aif2dac_ng_hold =
 676         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 677                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 678
 679 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 680 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 681
 682 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 683            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 684 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 685 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 686                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 687                7, 1, ng_tlv),
 688
 689 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 690            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 691 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 692 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 693                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 694                7, 1, ng_tlv),
 695
 696 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 697            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 698 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 699 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 700                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 701                7, 1, ng_tlv),
 702 };
 703
 704 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 705 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 706                mixin_boost_tlv),
 707 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 708                mixin_boost_tlv),
 709 };
 710
 711 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 712                          struct snd_kcontrol *kcontrol, int event)
 713 {
 714         struct snd_soc_codec *codec = w->codec;
 715
 716         switch (event) {
 717         case SND_SOC_DAPM_PRE_PMU:
 718                 return configure_clock(codec);
 719
 720         case SND_SOC_DAPM_POST_PMD:
 721                 configure_clock(codec);
 722                 break;
 723         }
 724
 725         return 0;
 726 }
 727
 728 static void vmid_reference(struct snd_soc_codec *codec)
 729 {
 730         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 731
 732         wm8994->vmid_refcount++;
 733
 734         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 735                 wm8994->vmid_refcount);
 736
 737         if (wm8994->vmid_refcount == 1) {
 738                 /* Startup bias, VMID ramp & buffer */
 739                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 740                                     WM8994_STARTUP_BIAS_ENA |
 741                                     WM8994_VMID_BUF_ENA |
 742                                     WM8994_VMID_RAMP_MASK,
 743                                     WM8994_STARTUP_BIAS_ENA |
 744                                     WM8994_VMID_BUF_ENA |
 745                                     (0x11 << WM8994_VMID_RAMP_SHIFT));
 746
 747                 /* Main bias enable, VMID=2x40k */
 748                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 749                                     WM8994_BIAS_ENA |
 750                                     WM8994_VMID_SEL_MASK,
 751                                     WM8994_BIAS_ENA | 0x2);
 752
 753                 msleep(20);
 754         }
 755 }
 756
 757 static void vmid_dereference(struct snd_soc_codec *codec)
 758 {
 759         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 760
 761         wm8994->vmid_refcount--;
 762
 763         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 764                 wm8994->vmid_refcount);
 765
 766         if (wm8994->vmid_refcount == 0) {
 767                 /* Switch over to startup biases */
 768                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 769                                     WM8994_BIAS_SRC |
 770                                     WM8994_STARTUP_BIAS_ENA |
 771                                     WM8994_VMID_BUF_ENA |
 772                                     WM8994_VMID_RAMP_MASK,
 773                                     WM8994_BIAS_SRC |
 774                                     WM8994_STARTUP_BIAS_ENA |
 775                                     WM8994_VMID_BUF_ENA |
 776                                     (1 << WM8994_VMID_RAMP_SHIFT));
 777
 778                 /* Disable main biases */
 779                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 780                                     WM8994_BIAS_ENA |
 781                                     WM8994_VMID_SEL_MASK, 0);
 782
 783                 /* Discharge line */
 784                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 785                                     WM8994_LINEOUT1_DISCH |
 786                                     WM8994_LINEOUT2_DISCH,
 787                                     WM8994_LINEOUT1_DISCH |
 788                                     WM8994_LINEOUT2_DISCH);
 789
 790                 msleep(5);
 791
 792                 /* Switch off startup biases */
 793                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 794                                     WM8994_BIAS_SRC |
 795                                     WM8994_STARTUP_BIAS_ENA |
 796                                     WM8994_VMID_BUF_ENA |
 797                                     WM8994_VMID_RAMP_MASK, 0);
 798         }
 799 }
 800
 801 static int vmid_event(struct snd_soc_dapm_widget *w,
 802                       struct snd_kcontrol *kcontrol, int event)
 803 {
 804         struct snd_soc_codec *codec = w->codec;
 805
 806         switch (event) {
 807         case SND_SOC_DAPM_PRE_PMU:
 808                 vmid_reference(codec);
 809                 break;
 810
 811         case SND_SOC_DAPM_POST_PMD:
 812                 vmid_dereference(codec);
 813                 break;
 814         }
 815
 816         return 0;
 817 }
 818
 819 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 820 {
 821         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 822         int enable = 1;
 823         int source = 0;  /* GCC flow analysis can't track enable */
 824         int reg, reg_r;
 825
 826         /* Only support direct DAC->headphone paths */
 827         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 828         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 829                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 830                 enable = 0;
 831         }
 832
 833         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 834         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 835                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 836                 enable = 0;
 837         }
 838
 839         /* We also need the same setting for L/R and only one path */
 840         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 841         switch (reg) {
 842         case WM8994_AIF2DACL_TO_DAC1L:
 843                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 844                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 845                 break;
 846         case WM8994_AIF1DAC2L_TO_DAC1L:
 847                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 848                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 849                 break;
 850         case WM8994_AIF1DAC1L_TO_DAC1L:
 851                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 852                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 853                 break;
 854         default:
 855                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 856                 enable = 0;
 857                 break;
 858         }
 859
 860         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 861         if (reg_r != reg) {
 862                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 863                 enable = 0;
 864         }
 865
 866         if (enable) {
 867                 dev_dbg(codec->dev, "Class W enabled\n");
 868                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 869                                     WM8994_CP_DYN_PWR |
 870                                     WM8994_CP_DYN_SRC_SEL_MASK,
 871                                     source | WM8994_CP_DYN_PWR);
 872                 wm8994->hubs.class_w = true;
 873
 874         } else {
 875                 dev_dbg(codec->dev, "Class W disabled\n");
 876                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 877                                     WM8994_CP_DYN_PWR, 0);
 878                 wm8994->hubs.class_w = false;
 879         }
 880 }
 881
 882 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 883                           struct snd_kcontrol *kcontrol, int event)
 884 {
 885         struct snd_soc_codec *codec = w->codec;
 886         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 887
 888         switch (event) {
 889         case SND_SOC_DAPM_PRE_PMU:
 890                 if (wm8994->aif1clk_enable) {
 891                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 892                                             WM8994_AIF1CLK_ENA_MASK,
 893                                             WM8994_AIF1CLK_ENA);
 894                         wm8994->aif1clk_enable = 0;
 895                 }
 896                 if (wm8994->aif2clk_enable) {
 897                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 898                                             WM8994_AIF2CLK_ENA_MASK,
 899                                             WM8994_AIF2CLK_ENA);
 900                         wm8994->aif2clk_enable = 0;
 901                 }
 902                 break;
 903         }
 904
 905         /* We may also have postponed startup of DSP, handle that. */
 906         wm8958_aif_ev(w, kcontrol, event);
 907
 908         return 0;
 909 }
 910
 911 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 912                            struct snd_kcontrol *kcontrol, int event)
 913 {
 914         struct snd_soc_codec *codec = w->codec;
 915         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 916
 917         switch (event) {
 918         case SND_SOC_DAPM_POST_PMD:
 919                 if (wm8994->aif1clk_disable) {
 920                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 921                                             WM8994_AIF1CLK_ENA_MASK, 0);
 922                         wm8994->aif1clk_disable = 0;
 923                 }
 924                 if (wm8994->aif2clk_disable) {
 925                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 926                                             WM8994_AIF2CLK_ENA_MASK, 0);
 927                         wm8994->aif2clk_disable = 0;
 928                 }
 929                 break;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 936                       struct snd_kcontrol *kcontrol, int event)
 937 {
 938         struct snd_soc_codec *codec = w->codec;
 939         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 940
 941         switch (event) {
 942         case SND_SOC_DAPM_PRE_PMU:
 943                 wm8994->aif1clk_enable = 1;
 944                 break;
 945         case SND_SOC_DAPM_POST_PMD:
 946                 wm8994->aif1clk_disable = 1;
 947                 break;
 948         }
 949
 950         return 0;
 951 }
 952
 953 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 954                       struct snd_kcontrol *kcontrol, int event)
 955 {
 956         struct snd_soc_codec *codec = w->codec;
 957         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 958
 959         switch (event) {
 960         case SND_SOC_DAPM_PRE_PMU:
 961                 wm8994->aif2clk_enable = 1;
 962                 break;
 963         case SND_SOC_DAPM_POST_PMD:
 964                 wm8994->aif2clk_disable = 1;
 965                 break;
 966         }
 967
 968         return 0;
 969 }
 970
 971 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 972                       struct snd_kcontrol *kcontrol, int event)
 973 {
 974         late_enable_ev(w, kcontrol, event);
 975         return 0;
 976 }
 977
 978 static int micbias_ev(struct snd_soc_dapm_widget *w,
 979                       struct snd_kcontrol *kcontrol, int event)
 980 {
 981         late_enable_ev(w, kcontrol, event);
 982         return 0;
 983 }
 984
 985 static int dac_ev(struct snd_soc_dapm_widget *w,
 986                   struct snd_kcontrol *kcontrol, int event)
 987 {
 988         struct snd_soc_codec *codec = w->codec;
 989         unsigned int mask = 1 << w->shift;
 990
 991         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 992                             mask, mask);
 993         return 0;
 994 }
 995
 996 static const char *hp_mux_text[] = {
 997         "Mixer",
 998         "DAC",
 999 };
1000
1001 #define WM8994_HP_ENUM(xname, xenum) \
1002 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1003         .info = snd_soc_info_enum_double, \
1004         .get = snd_soc_dapm_get_enum_double, \
1005         .put = wm8994_put_hp_enum, \
1006         .private_value = (unsigned long)&xenum }
1007
1008 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1009                               struct snd_ctl_elem_value *ucontrol)
1010 {
1011         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1012         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1013         struct snd_soc_codec *codec = w->codec;
1014         int ret;
1015
1016         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1017
1018         wm8994_update_class_w(codec);
1019
1020         return ret;
1021 }
1022
1023 static const struct soc_enum hpl_enum =
1024         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1025
1026 static const struct snd_kcontrol_new hpl_mux =
1027         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1028
1029 static const struct soc_enum hpr_enum =
1030         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1031
1032 static const struct snd_kcontrol_new hpr_mux =
1033         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1034
1035 static const char *adc_mux_text[] = {
1036         "ADC",
1037         "DMIC",
1038 };
1039
1040 static const struct soc_enum adc_enum =
1041         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1042
1043 static const struct snd_kcontrol_new adcl_mux =
1044         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1045
1046 static const struct snd_kcontrol_new adcr_mux =
1047         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1048
1049 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1050 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1051 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1052 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1053 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1054 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1055 };
1056
1057 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1058 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1059 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1060 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1061 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1062 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1063 };
1064
1065 /* Debugging; dump chip status after DAPM transitions */
1066 static int post_ev(struct snd_soc_dapm_widget *w,
1067             struct snd_kcontrol *kcontrol, int event)
1068 {
1069         struct snd_soc_codec *codec = w->codec;
1070         dev_dbg(codec->dev, "SRC status: %x\n",
1071                 snd_soc_read(codec,
1072                              WM8994_RATE_STATUS));
1073         return 0;
1074 }
1075
1076 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1077 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1078                 1, 1, 0),
1079 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1080                 0, 1, 0),
1081 };
1082
1083 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1084 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1085                 1, 1, 0),
1086 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1087                 0, 1, 0),
1088 };
1089
1090 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1091 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1092                 1, 1, 0),
1093 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1094                 0, 1, 0),
1095 };
1096
1097 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1098 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1099                 1, 1, 0),
1100 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1101                 0, 1, 0),
1102 };
1103
1104 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1105 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1106                 5, 1, 0),
1107 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1108                 4, 1, 0),
1109 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1110                 2, 1, 0),
1111 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1112                 1, 1, 0),
1113 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1114                 0, 1, 0),
1115 };
1116
1117 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1118 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1119                 5, 1, 0),
1120 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1121                 4, 1, 0),
1122 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1123                 2, 1, 0),
1124 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1125                 1, 1, 0),
1126 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1127                 0, 1, 0),
1128 };
1129
1130 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1131 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1132         .info = snd_soc_info_volsw, \
1133         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1134         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1135
1136 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1137                               struct snd_ctl_elem_value *ucontrol)
1138 {
1139         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1140         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1141         struct snd_soc_codec *codec = w->codec;
1142         int ret;
1143
1144         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1145
1146         wm8994_update_class_w(codec);
1147
1148         return ret;
1149 }
1150
1151 static const struct snd_kcontrol_new dac1l_mix[] = {
1152 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1153                       5, 1, 0),
1154 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1155                       4, 1, 0),
1156 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1157                       2, 1, 0),
1158 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1159                       1, 1, 0),
1160 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1161                       0, 1, 0),
1162 };
1163
1164 static const struct snd_kcontrol_new dac1r_mix[] = {
1165 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1166                       5, 1, 0),
1167 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1168                       4, 1, 0),
1169 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1170                       2, 1, 0),
1171 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1172                       1, 1, 0),
1173 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1174                       0, 1, 0),
1175 };
1176
1177 static const char *sidetone_text[] = {
1178         "ADC/DMIC1", "DMIC2",
1179 };
1180
1181 static const struct soc_enum sidetone1_enum =
1182         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1183
1184 static const struct snd_kcontrol_new sidetone1_mux =
1185         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1186
1187 static const struct soc_enum sidetone2_enum =
1188         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1189
1190 static const struct snd_kcontrol_new sidetone2_mux =
1191         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1192
1193 static const char *aif1dac_text[] = {
1194         "AIF1DACDAT", "AIF3DACDAT",
1195 };
1196
1197 static const struct soc_enum aif1dac_enum =
1198         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1199
1200 static const struct snd_kcontrol_new aif1dac_mux =
1201         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1202
1203 static const char *aif2dac_text[] = {
1204         "AIF2DACDAT", "AIF3DACDAT",
1205 };
1206
1207 static const struct soc_enum aif2dac_enum =
1208         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1209
1210 static const struct snd_kcontrol_new aif2dac_mux =
1211         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1212
1213 static const char *aif2adc_text[] = {
1214         "AIF2ADCDAT", "AIF3DACDAT",
1215 };
1216
1217 static const struct soc_enum aif2adc_enum =
1218         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1219
1220 static const struct snd_kcontrol_new aif2adc_mux =
1221         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1222
1223 static const char *aif3adc_text[] = {
1224         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1225 };
1226
1227 static const struct soc_enum wm8994_aif3adc_enum =
1228         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1229
1230 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1231         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1232
1233 static const struct soc_enum wm8958_aif3adc_enum =
1234         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1235
1236 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1237         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1238
1239 static const char *mono_pcm_out_text[] = {
1240         "None", "AIF2ADCL", "AIF2ADCR",
1241 };
1242
1243 static const struct soc_enum mono_pcm_out_enum =
1244         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1245
1246 static const struct snd_kcontrol_new mono_pcm_out_mux =
1247         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1248
1249 static const char *aif2dac_src_text[] = {
1250         "AIF2", "AIF3",
1251 };
1252
1253 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1254 static const struct soc_enum aif2dacl_src_enum =
1255         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1256
1257 static const struct snd_kcontrol_new aif2dacl_src_mux =
1258         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1259
1260 static const struct soc_enum aif2dacr_src_enum =
1261         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1262
1263 static const struct snd_kcontrol_new aif2dacr_src_mux =
1264         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1265
1266 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1267 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1268         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1269 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1270         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1271
1272 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1273         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1274 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1275         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1276 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1277         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1278 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1279         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1280 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1281         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1282
1283 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1284                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1285                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1286 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1287                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1288                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1289 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1290                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1291 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1292                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1293
1294 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1295 };
1296
1297 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1298 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1299 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1300 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1301 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1302                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1303 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1304                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1305 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1306 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1307 };
1308
1309 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1310 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1311         dac_ev, SND_SOC_DAPM_PRE_PMU),
1312 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1313         dac_ev, SND_SOC_DAPM_PRE_PMU),
1314 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1315         dac_ev, SND_SOC_DAPM_PRE_PMU),
1316 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1317         dac_ev, SND_SOC_DAPM_PRE_PMU),
1318 };
1319
1320 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1321 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1322 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1323 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1324 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1325 };
1326
1327 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1328 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1329                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1330 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1331                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1332 };
1333
1334 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1335 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1336 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1337 };
1338
1339 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1340 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1341 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1342 SND_SOC_DAPM_INPUT("Clock"),
1343
1344 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1345                       SND_SOC_DAPM_PRE_PMU),
1346 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1347                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1348
1349 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1350                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1351
1352 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1353 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1354 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1355
1356 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1357                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1358 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1359                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1360 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1361                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1362                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1363 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1364                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1365                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1366
1367 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1368                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1369 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1370                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1371 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1372                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1373                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1374 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1375                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1376                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1377
1378 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1379                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1380 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1381                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1382
1383 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1384                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1385 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1386                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1387
1388 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1389                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1390 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1391                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1392
1393 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1394 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1395
1396 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1397                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1398 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1399                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1400
1401 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1402                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1403 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1404                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1405 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1406                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1407                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1408 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1409                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1410                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1411
1412 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1413 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1414 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1415 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1416
1417 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1418 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1419 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1420
1421 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1422 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1423
1424 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1425
1426 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1427 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1428 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1429 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1430
1431 /* Power is done with the muxes since the ADC power also controls the
1432  * downsampling chain, the chip will automatically manage the analogue
1433  * specific portions.
1434  */
1435 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1436 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1437
1438 SND_SOC_DAPM_POST("Debug log", post_ev),
1439 };
1440
1441 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1442 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1443 };
1444
1445 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1446 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1447 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1448 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1449 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1450 };
1451
1452 static const struct snd_soc_dapm_route intercon[] = {
1453         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1454         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1455
1456         { "DSP1CLK", NULL, "CLK_SYS" },
1457         { "DSP2CLK", NULL, "CLK_SYS" },
1458         { "DSPINTCLK", NULL, "CLK_SYS" },
1459
1460         { "AIF1ADC1L", NULL, "AIF1CLK" },
1461         { "AIF1ADC1L", NULL, "DSP1CLK" },
1462         { "AIF1ADC1R", NULL, "AIF1CLK" },
1463         { "AIF1ADC1R", NULL, "DSP1CLK" },
1464         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1465
1466         { "AIF1DAC1L", NULL, "AIF1CLK" },
1467         { "AIF1DAC1L", NULL, "DSP1CLK" },
1468         { "AIF1DAC1R", NULL, "AIF1CLK" },
1469         { "AIF1DAC1R", NULL, "DSP1CLK" },
1470         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1471
1472         { "AIF1ADC2L", NULL, "AIF1CLK" },
1473         { "AIF1ADC2L", NULL, "DSP1CLK" },
1474         { "AIF1ADC2R", NULL, "AIF1CLK" },
1475         { "AIF1ADC2R", NULL, "DSP1CLK" },
1476         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1477
1478         { "AIF1DAC2L", NULL, "AIF1CLK" },
1479         { "AIF1DAC2L", NULL, "DSP1CLK" },
1480         { "AIF1DAC2R", NULL, "AIF1CLK" },
1481         { "AIF1DAC2R", NULL, "DSP1CLK" },
1482         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1483
1484         { "AIF2ADCL", NULL, "AIF2CLK" },
1485         { "AIF2ADCL", NULL, "DSP2CLK" },
1486         { "AIF2ADCR", NULL, "AIF2CLK" },
1487         { "AIF2ADCR", NULL, "DSP2CLK" },
1488         { "AIF2ADCR", NULL, "DSPINTCLK" },
1489
1490         { "AIF2DACL", NULL, "AIF2CLK" },
1491         { "AIF2DACL", NULL, "DSP2CLK" },
1492         { "AIF2DACR", NULL, "AIF2CLK" },
1493         { "AIF2DACR", NULL, "DSP2CLK" },
1494         { "AIF2DACR", NULL, "DSPINTCLK" },
1495
1496         { "DMIC1L", NULL, "DMIC1DAT" },
1497         { "DMIC1L", NULL, "CLK_SYS" },
1498         { "DMIC1R", NULL, "DMIC1DAT" },
1499         { "DMIC1R", NULL, "CLK_SYS" },
1500         { "DMIC2L", NULL, "DMIC2DAT" },
1501         { "DMIC2L", NULL, "CLK_SYS" },
1502         { "DMIC2R", NULL, "DMIC2DAT" },
1503         { "DMIC2R", NULL, "CLK_SYS" },
1504
1505         { "ADCL", NULL, "AIF1CLK" },
1506         { "ADCL", NULL, "DSP1CLK" },
1507         { "ADCL", NULL, "DSPINTCLK" },
1508
1509         { "ADCR", NULL, "AIF1CLK" },
1510         { "ADCR", NULL, "DSP1CLK" },
1511         { "ADCR", NULL, "DSPINTCLK" },
1512
1513         { "ADCL Mux", "ADC", "ADCL" },
1514         { "ADCL Mux", "DMIC", "DMIC1L" },
1515         { "ADCR Mux", "ADC", "ADCR" },
1516         { "ADCR Mux", "DMIC", "DMIC1R" },
1517
1518         { "DAC1L", NULL, "AIF1CLK" },
1519         { "DAC1L", NULL, "DSP1CLK" },
1520         { "DAC1L", NULL, "DSPINTCLK" },
1521
1522         { "DAC1R", NULL, "AIF1CLK" },
1523         { "DAC1R", NULL, "DSP1CLK" },
1524         { "DAC1R", NULL, "DSPINTCLK" },
1525
1526         { "DAC2L", NULL, "AIF2CLK" },
1527         { "DAC2L", NULL, "DSP2CLK" },
1528         { "DAC2L", NULL, "DSPINTCLK" },
1529
1530         { "DAC2R", NULL, "AIF2DACR" },
1531         { "DAC2R", NULL, "AIF2CLK" },
1532         { "DAC2R", NULL, "DSP2CLK" },
1533         { "DAC2R", NULL, "DSPINTCLK" },
1534
1535         { "TOCLK", NULL, "CLK_SYS" },
1536
1537         /* AIF1 outputs */
1538         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1539         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1540         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1541
1542         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1543         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1544         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1545
1546         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1547         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1548         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1549
1550         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1551         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1552         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1553
1554         /* Pin level routing for AIF3 */
1555         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1556         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1557         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1558         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1559
1560         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1561         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1562         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1563         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1564         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1565         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1566         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1567
1568         /* DAC1 inputs */
1569         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1570         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1571         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1572         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1573         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1574
1575         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1576         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1577         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1578         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1579         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1580
1581         /* DAC2/AIF2 outputs  */
1582         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1583         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1584         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1585         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1586         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1587         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1588
1589         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1590         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1591         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1592         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1593         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1594         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1595
1596         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1597         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1598         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1599         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1600
1601         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1602
1603         /* AIF3 output */
1604         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1605         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1606         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1607         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1608         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1609         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1610         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1611         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1612
1613         /* Sidetone */
1614         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1615         { "Left Sidetone", "DMIC2", "DMIC2L" },
1616         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1617         { "Right Sidetone", "DMIC2", "DMIC2R" },
1618
1619         /* Output stages */
1620         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1621         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1622
1623         { "SPKL", "DAC1 Switch", "DAC1L" },
1624         { "SPKL", "DAC2 Switch", "DAC2L" },
1625
1626         { "SPKR", "DAC1 Switch", "DAC1R" },
1627         { "SPKR", "DAC2 Switch", "DAC2R" },
1628
1629         { "Left Headphone Mux", "DAC", "DAC1L" },
1630         { "Right Headphone Mux", "DAC", "DAC1R" },
1631 };
1632
1633 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1634         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1635         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1636         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1637         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1638         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1639         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1640         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1641         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1642 };
1643
1644 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1645         { "DAC1L", NULL, "DAC1L Mixer" },
1646         { "DAC1R", NULL, "DAC1R Mixer" },
1647         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1648         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1649 };
1650
1651 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1652         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1653         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1654         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1655         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1656         { "MICBIAS1", NULL, "CLK_SYS" },
1657         { "MICBIAS1", NULL, "MICBIAS Supply" },
1658         { "MICBIAS2", NULL, "CLK_SYS" },
1659         { "MICBIAS2", NULL, "MICBIAS Supply" },
1660 };
1661
1662 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1663         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1664         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1665         { "MICBIAS1", NULL, "VMID" },
1666         { "MICBIAS2", NULL, "VMID" },
1667 };
1668
1669 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1670         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1671         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1672
1673         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1674         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1675         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1676         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1677
1678         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1679         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1680
1681         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1682 };
1683
1684 /* The size in bits of the FLL divide multiplied by 10
1685  * to allow rounding later */
1686 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1687
1688 struct fll_div {
1689         u16 outdiv;
1690         u16 n;
1691         u16 k;
1692         u16 clk_ref_div;
1693         u16 fll_fratio;
1694 };
1695
1696 static int wm8994_get_fll_config(struct fll_div *fll,
1697                                  int freq_in, int freq_out)
1698 {
1699         u64 Kpart;
1700         unsigned int K, Ndiv, Nmod;
1701
1702         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1703
1704         /* Scale the input frequency down to <= 13.5MHz */
1705         fll->clk_ref_div = 0;
1706         while (freq_in > 13500000) {
1707                 fll->clk_ref_div++;
1708                 freq_in /= 2;
1709
1710                 if (fll->clk_ref_div > 3)
1711                         return -EINVAL;
1712         }
1713         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1714
1715         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1716         fll->outdiv = 3;
1717         while (freq_out * (fll->outdiv + 1) < 90000000) {
1718                 fll->outdiv++;
1719                 if (fll->outdiv > 63)
1720                         return -EINVAL;
1721         }
1722         freq_out *= fll->outdiv + 1;
1723         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1724
1725         if (freq_in > 1000000) {
1726                 fll->fll_fratio = 0;
1727         } else if (freq_in > 256000) {
1728                 fll->fll_fratio = 1;
1729                 freq_in *= 2;
1730         } else if (freq_in > 128000) {
1731                 fll->fll_fratio = 2;
1732                 freq_in *= 4;
1733         } else if (freq_in > 64000) {
1734                 fll->fll_fratio = 3;
1735                 freq_in *= 8;
1736         } else {
1737                 fll->fll_fratio = 4;
1738                 freq_in *= 16;
1739         }
1740         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1741
1742         /* Now, calculate N.K */
1743         Ndiv = freq_out / freq_in;
1744
1745         fll->n = Ndiv;
1746         Nmod = freq_out % freq_in;
1747         pr_debug("Nmod=%d\n", Nmod);
1748
1749         /* Calculate fractional part - scale up so we can round. */
1750         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1751
1752         do_div(Kpart, freq_in);
1753
1754         K = Kpart & 0xFFFFFFFF;
1755
1756         if ((K % 10) >= 5)
1757                 K += 5;
1758
1759         /* Move down to proper range now rounding is done */
1760         fll->k = K / 10;
1761
1762         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1763
1764         return 0;
1765 }
1766
1767 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1768                           unsigned int freq_in, unsigned int freq_out)
1769 {
1770         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1771         struct wm8994 *control = codec->control_data;
1772         int reg_offset, ret;
1773         struct fll_div fll;
1774         u16 reg, aif1, aif2;
1775         unsigned long timeout;
1776         bool was_enabled;
1777
1778         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1779                 & WM8994_AIF1CLK_ENA;
1780
1781         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1782                 & WM8994_AIF2CLK_ENA;
1783
1784         switch (id) {
1785         case WM8994_FLL1:
1786                 reg_offset = 0;
1787                 id = 0;
1788                 break;
1789         case WM8994_FLL2:
1790                 reg_offset = 0x20;
1791                 id = 1;
1792                 break;
1793         default:
1794                 return -EINVAL;
1795         }
1796
1797         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1798         was_enabled = reg & WM8994_FLL1_ENA;
1799
1800         switch (src) {
1801         case 0:
1802                 /* Allow no source specification when stopping */
1803                 if (freq_out)
1804                         return -EINVAL;
1805                 src = wm8994->fll[id].src;
1806                 break;
1807         case WM8994_FLL_SRC_MCLK1:
1808         case WM8994_FLL_SRC_MCLK2:
1809         case WM8994_FLL_SRC_LRCLK:
1810         case WM8994_FLL_SRC_BCLK:
1811                 break;
1812         default:
1813                 return -EINVAL;
1814         }
1815
1816         /* Are we changing anything? */
1817         if (wm8994->fll[id].src == src &&
1818             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1819                 return 0;
1820
1821         /* If we're stopping the FLL redo the old config - no
1822          * registers will actually be written but we avoid GCC flow
1823          * analysis bugs spewing warnings.
1824          */
1825         if (freq_out)
1826                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1827         else
1828                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1829                                             wm8994->fll[id].out);
1830         if (ret < 0)
1831                 return ret;
1832
1833         /* Gate the AIF clocks while we reclock */
1834         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1835                             WM8994_AIF1CLK_ENA, 0);
1836         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1837                             WM8994_AIF2CLK_ENA, 0);
1838
1839         /* We always need to disable the FLL while reconfiguring */
1840         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1841                             WM8994_FLL1_ENA, 0);
1842
1843         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1844                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1845         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1846                             WM8994_FLL1_OUTDIV_MASK |
1847                             WM8994_FLL1_FRATIO_MASK, reg);
1848
1849         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1850
1851         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1852                             WM8994_FLL1_N_MASK,
1853                                     fll.n << WM8994_FLL1_N_SHIFT);
1854
1855         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1856                             WM8994_FLL1_REFCLK_DIV_MASK |
1857                             WM8994_FLL1_REFCLK_SRC_MASK,
1858                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1859                             (src - 1));
1860
1861         /* Clear any pending completion from a previous failure */
1862         try_wait_for_completion(&wm8994->fll_locked[id]);
1863
1864         /* Enable (with fractional mode if required) */
1865         if (freq_out) {
1866                 /* Enable VMID if we need it */
1867                 if (!was_enabled) {
1868                         switch (control->type) {
1869                         case WM8994:
1870                                 vmid_reference(codec);
1871                                 break;
1872                         case WM8958:
1873                                 if (wm8994->revision < 1)
1874                                         vmid_reference(codec);
1875                                 break;
1876                         default:
1877                                 break;
1878                         }
1879                 }
1880
1881                 if (fll.k)
1882                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1883                 else
1884                         reg = WM8994_FLL1_ENA;
1885                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1886                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1887                                     reg);
1888
1889                 if (wm8994->fll_locked_irq) {
1890                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1891                                                               msecs_to_jiffies(10));
1892                         if (timeout == 0)
1893                                 dev_warn(codec->dev,
1894                                          "Timed out waiting for FLL lock\n");
1895                 } else {
1896                         msleep(5);
1897                 }
1898         } else {
1899                 if (was_enabled) {
1900                         switch (control->type) {
1901                         case WM8994:
1902                                 vmid_dereference(codec);
1903                                 break;
1904                         case WM8958:
1905                                 if (wm8994->revision < 1)
1906                                         vmid_dereference(codec);
1907                                 break;
1908                         default:
1909                                 break;
1910                         }
1911                 }
1912         }
1913
1914         wm8994->fll[id].in = freq_in;
1915         wm8994->fll[id].out = freq_out;
1916         wm8994->fll[id].src = src;
1917
1918         /* Enable any gated AIF clocks */
1919         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1920                             WM8994_AIF1CLK_ENA, aif1);
1921         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1922                             WM8994_AIF2CLK_ENA, aif2);
1923
1924         configure_clock(codec);
1925
1926         return 0;
1927 }
1928
1929 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1930 {
1931         struct completion *completion = data;
1932
1933         complete(completion);
1934
1935         return IRQ_HANDLED;
1936 }
1937
1938 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1939
1940 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1941                           unsigned int freq_in, unsigned int freq_out)
1942 {
1943         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1944 }
1945
1946 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1947                 int clk_id, unsigned int freq, int dir)
1948 {
1949         struct snd_soc_codec *codec = dai->codec;
1950         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1951         int i;
1952
1953         switch (dai->id) {
1954         case 1:
1955         case 2:
1956                 break;
1957
1958         default:
1959                 /* AIF3 shares clocking with AIF1/2 */
1960                 return -EINVAL;
1961         }
1962
1963         switch (clk_id) {
1964         case WM8994_SYSCLK_MCLK1:
1965                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1966                 wm8994->mclk[0] = freq;
1967                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1968                         dai->id, freq);
1969                 break;
1970
1971         case WM8994_SYSCLK_MCLK2:
1972                 /* TODO: Set GPIO AF */
1973                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1974                 wm8994->mclk[1] = freq;
1975                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1976                         dai->id, freq);
1977                 break;
1978
1979         case WM8994_SYSCLK_FLL1:
1980                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1981                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1982                 break;
1983
1984         case WM8994_SYSCLK_FLL2:
1985                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1986                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1987                 break;
1988
1989         case WM8994_SYSCLK_OPCLK:
1990                 /* Special case - a division (times 10) is given and
1991                  * no effect on main clocking.
1992                  */
1993                 if (freq) {
1994                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1995                                 if (opclk_divs[i] == freq)
1996                                         break;
1997                         if (i == ARRAY_SIZE(opclk_divs))
1998                                 return -EINVAL;
1999                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2000                                             WM8994_OPCLK_DIV_MASK, i);
2001                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2002                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2003                 } else {
2004                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2005                                             WM8994_OPCLK_ENA, 0);
2006                 }
2007
2008         default:
2009                 return -EINVAL;
2010         }
2011
2012         configure_clock(codec);
2013
2014         return 0;
2015 }
2016
2017 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2018                                  enum snd_soc_bias_level level)
2019 {
2020         struct wm8994 *control = codec->control_data;
2021         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2022
2023         switch (level) {
2024         case SND_SOC_BIAS_ON:
2025                 break;
2026
2027         case SND_SOC_BIAS_PREPARE:
2028                 break;
2029
2030         case SND_SOC_BIAS_STANDBY:
2031                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2032                         pm_runtime_get_sync(codec->dev);
2033
2034                         switch (control->type) {
2035                         case WM8994:
2036                                 if (wm8994->revision < 4) {
2037                                         /* Tweak DC servo and DSP
2038                                          * configuration for improved
2039                                          * performance. */
2040                                         snd_soc_write(codec, 0x102, 0x3);
2041                                         snd_soc_write(codec, 0x56, 0x3);
2042                                         snd_soc_write(codec, 0x817, 0);
2043                                         snd_soc_write(codec, 0x102, 0);
2044                                 }
2045                                 break;
2046
2047                         case WM8958:
2048                                 if (wm8994->revision == 0) {
2049                                         /* Optimise performance for rev A */
2050                                         snd_soc_write(codec, 0x102, 0x3);
2051                                         snd_soc_write(codec, 0xcb, 0x81);
2052                                         snd_soc_write(codec, 0x817, 0);
2053                                         snd_soc_write(codec, 0x102, 0);
2054
2055                                         snd_soc_update_bits(codec,
2056                                                             WM8958_CHARGE_PUMP_2,
2057                                                             WM8958_CP_DISCH,
2058                                                             WM8958_CP_DISCH);
2059                                 }
2060                                 break;
2061
2062                         case WM1811:
2063                                 if (wm8994->revision < 2) {
2064                                         snd_soc_write(codec, 0x102, 0x3);
2065                                         snd_soc_write(codec, 0x5d, 0x7e);
2066                                         snd_soc_write(codec, 0x5e, 0x0);
2067                                         snd_soc_write(codec, 0x102, 0x0);
2068                                 }
2069                                 break;
2070                         }
2071
2072                         /* Discharge LINEOUT1 & 2 */
2073                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2074                                             WM8994_LINEOUT1_DISCH |
2075                                             WM8994_LINEOUT2_DISCH,
2076                                             WM8994_LINEOUT1_DISCH |
2077                                             WM8994_LINEOUT2_DISCH);
2078                 }
2079
2080
2081                 break;
2082
2083         case SND_SOC_BIAS_OFF:
2084                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2085                         wm8994->cur_fw = NULL;
2086
2087                         pm_runtime_put(codec->dev);
2088                 }
2089                 break;
2090         }
2091         codec->dapm.bias_level = level;
2092         return 0;
2093 }
2094
2095 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2096 {
2097         struct snd_soc_codec *codec = dai->codec;
2098         struct wm8994 *control = codec->control_data;
2099         int ms_reg;
2100         int aif1_reg;
2101         int ms = 0;
2102         int aif1 = 0;
2103
2104         switch (dai->id) {
2105         case 1:
2106                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2107                 aif1_reg = WM8994_AIF1_CONTROL_1;
2108                 break;
2109         case 2:
2110                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2111                 aif1_reg = WM8994_AIF2_CONTROL_1;
2112                 break;
2113         default:
2114                 return -EINVAL;
2115         }
2116
2117         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2118         case SND_SOC_DAIFMT_CBS_CFS:
2119                 break;
2120         case SND_SOC_DAIFMT_CBM_CFM:
2121                 ms = WM8994_AIF1_MSTR;
2122                 break;
2123         default:
2124                 return -EINVAL;
2125         }
2126
2127         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2128         case SND_SOC_DAIFMT_DSP_B:
2129                 aif1 |= WM8994_AIF1_LRCLK_INV;
2130         case SND_SOC_DAIFMT_DSP_A:
2131                 aif1 |= 0x18;
2132                 break;
2133         case SND_SOC_DAIFMT_I2S:
2134                 aif1 |= 0x10;
2135                 break;
2136         case SND_SOC_DAIFMT_RIGHT_J:
2137                 break;
2138         case SND_SOC_DAIFMT_LEFT_J:
2139                 aif1 |= 0x8;
2140                 break;
2141         default:
2142                 return -EINVAL;
2143         }
2144
2145         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2146         case SND_SOC_DAIFMT_DSP_A:
2147         case SND_SOC_DAIFMT_DSP_B:
2148                 /* frame inversion not valid for DSP modes */
2149                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2150                 case SND_SOC_DAIFMT_NB_NF:
2151                         break;
2152                 case SND_SOC_DAIFMT_IB_NF:
2153                         aif1 |= WM8994_AIF1_BCLK_INV;
2154                         break;
2155                 default:
2156                         return -EINVAL;
2157                 }
2158                 break;
2159
2160         case SND_SOC_DAIFMT_I2S:
2161         case SND_SOC_DAIFMT_RIGHT_J:
2162         case SND_SOC_DAIFMT_LEFT_J:
2163                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2164                 case SND_SOC_DAIFMT_NB_NF:
2165                         break;
2166                 case SND_SOC_DAIFMT_IB_IF:
2167                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2168                         break;
2169                 case SND_SOC_DAIFMT_IB_NF:
2170                         aif1 |= WM8994_AIF1_BCLK_INV;
2171                         break;
2172                 case SND_SOC_DAIFMT_NB_IF:
2173                         aif1 |= WM8994_AIF1_LRCLK_INV;
2174                         break;
2175                 default:
2176                         return -EINVAL;
2177                 }
2178                 break;
2179         default:
2180                 return -EINVAL;
2181         }
2182
2183         /* The AIF2 format configuration needs to be mirrored to AIF3
2184          * on WM8958 if it's in use so just do it all the time. */
2185         switch (control->type) {
2186         case WM1811:
2187         case WM8958:
2188                 if (dai->id == 2)
2189                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2190                                             WM8994_AIF1_LRCLK_INV |
2191                                             WM8958_AIF3_FMT_MASK, aif1);
2192                 break;
2193
2194         default:
2195                 break;
2196         }
2197
2198         snd_soc_update_bits(codec, aif1_reg,
2199                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2200                             WM8994_AIF1_FMT_MASK,
2201                             aif1);
2202         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2203                             ms);
2204
2205         return 0;
2206 }
2207
2208 static struct {
2209         int val, rate;
2210 } srs[] = {
2211         { 0,   8000 },
2212         { 1,  11025 },
2213         { 2,  12000 },
2214         { 3,  16000 },
2215         { 4,  22050 },
2216         { 5,  24000 },
2217         { 6,  32000 },
2218         { 7,  44100 },
2219         { 8,  48000 },
2220         { 9,  88200 },
2221         { 10, 96000 },
2222 };
2223
2224 static int fs_ratios[] = {
2225         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2226 };
2227
2228 static int bclk_divs[] = {
2229         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2230         640, 880, 960, 1280, 1760, 1920
2231 };
2232
2233 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2234                             struct snd_pcm_hw_params *params,
2235                             struct snd_soc_dai *dai)
2236 {
2237         struct snd_soc_codec *codec = dai->codec;
2238         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2239         int aif1_reg;
2240         int aif2_reg;
2241         int bclk_reg;
2242         int lrclk_reg;
2243         int rate_reg;
2244         int aif1 = 0;
2245         int aif2 = 0;
2246         int bclk = 0;
2247         int lrclk = 0;
2248         int rate_val = 0;
2249         int id = dai->id - 1;
2250
2251         int i, cur_val, best_val, bclk_rate, best;
2252
2253         switch (dai->id) {
2254         case 1:
2255                 aif1_reg = WM8994_AIF1_CONTROL_1;
2256                 aif2_reg = WM8994_AIF1_CONTROL_2;
2257                 bclk_reg = WM8994_AIF1_BCLK;
2258                 rate_reg = WM8994_AIF1_RATE;
2259                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2260                     wm8994->lrclk_shared[0]) {
2261                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2262                 } else {
2263                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2264                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2265                 }
2266                 break;
2267         case 2:
2268                 aif1_reg = WM8994_AIF2_CONTROL_1;
2269                 aif2_reg = WM8994_AIF2_CONTROL_2;
2270                 bclk_reg = WM8994_AIF2_BCLK;
2271                 rate_reg = WM8994_AIF2_RATE;
2272                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2273                     wm8994->lrclk_shared[1]) {
2274                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2275                 } else {
2276                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2277                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2278                 }
2279                 break;
2280         default:
2281                 return -EINVAL;
2282         }
2283
2284         bclk_rate = params_rate(params) * 2;
2285         switch (params_format(params)) {
2286         case SNDRV_PCM_FORMAT_S16_LE:
2287                 bclk_rate *= 16;
2288                 break;
2289         case SNDRV_PCM_FORMAT_S20_3LE:
2290                 bclk_rate *= 20;
2291                 aif1 |= 0x20;
2292                 break;
2293         case SNDRV_PCM_FORMAT_S24_LE:
2294                 bclk_rate *= 24;
2295                 aif1 |= 0x40;
2296                 break;
2297         case SNDRV_PCM_FORMAT_S32_LE:
2298                 bclk_rate *= 32;
2299                 aif1 |= 0x60;
2300                 break;
2301         default:
2302                 return -EINVAL;
2303         }
2304
2305         /* Try to find an appropriate sample rate; look for an exact match. */
2306         for (i = 0; i < ARRAY_SIZE(srs); i++)
2307                 if (srs[i].rate == params_rate(params))
2308                         break;
2309         if (i == ARRAY_SIZE(srs))
2310                 return -EINVAL;
2311         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2312
2313         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2314         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2315                 dai->id, wm8994->aifclk[id], bclk_rate);
2316
2317         if (params_channels(params) == 1 &&
2318             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2319                 aif2 |= WM8994_AIF1_MONO;
2320
2321         if (wm8994->aifclk[id] == 0) {
2322                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2323                 return -EINVAL;
2324         }
2325
2326         /* AIFCLK/fs ratio; look for a close match in either direction */
2327         best = 0;
2328         best_val = abs((fs_ratios[0] * params_rate(params))
2329                        - wm8994->aifclk[id]);
2330         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2331                 cur_val = abs((fs_ratios[i] * params_rate(params))
2332                               - wm8994->aifclk[id]);
2333                 if (cur_val >= best_val)
2334                         continue;
2335                 best = i;
2336                 best_val = cur_val;
2337         }
2338         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2339                 dai->id, fs_ratios[best]);
2340         rate_val |= best;
2341
2342         /* We may not get quite the right frequency if using
2343          * approximate clocks so look for the closest match that is
2344          * higher than the target (we need to ensure that there enough
2345          * BCLKs to clock out the samples).
2346          */
2347         best = 0;
2348         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2349                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2350                 if (cur_val < 0) /* BCLK table is sorted */
2351                         break;
2352                 best = i;
2353         }
2354         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2355         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2356                 bclk_divs[best], bclk_rate);
2357         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2358
2359         lrclk = bclk_rate / params_rate(params);
2360         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2361                 lrclk, bclk_rate / lrclk);
2362
2363         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2364         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2365         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2366         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2367                             lrclk);
2368         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2369                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2370
2371         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2372                 switch (dai->id) {
2373                 case 1:
2374                         wm8994->dac_rates[0] = params_rate(params);
2375                         wm8994_set_retune_mobile(codec, 0);
2376                         wm8994_set_retune_mobile(codec, 1);
2377                         break;
2378                 case 2:
2379                         wm8994->dac_rates[1] = params_rate(params);
2380                         wm8994_set_retune_mobile(codec, 2);
2381                         break;
2382                 }
2383         }
2384
2385         return 0;
2386 }
2387
2388 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2389                                  struct snd_pcm_hw_params *params,
2390                                  struct snd_soc_dai *dai)
2391 {
2392         struct snd_soc_codec *codec = dai->codec;
2393         struct wm8994 *control = codec->control_data;
2394         int aif1_reg;
2395         int aif1 = 0;
2396
2397         switch (dai->id) {
2398         case 3:
2399                 switch (control->type) {
2400                 case WM1811:
2401                 case WM8958:
2402                         aif1_reg = WM8958_AIF3_CONTROL_1;
2403                         break;
2404                 default:
2405                         return 0;
2406                 }
2407         default:
2408                 return 0;
2409         }
2410
2411         switch (params_format(params)) {
2412         case SNDRV_PCM_FORMAT_S16_LE:
2413                 break;
2414         case SNDRV_PCM_FORMAT_S20_3LE:
2415                 aif1 |= 0x20;
2416                 break;
2417         case SNDRV_PCM_FORMAT_S24_LE:
2418                 aif1 |= 0x40;
2419                 break;
2420         case SNDRV_PCM_FORMAT_S32_LE:
2421                 aif1 |= 0x60;
2422                 break;
2423         default:
2424                 return -EINVAL;
2425         }
2426
2427         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2428 }
2429
2430 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2431                                 struct snd_soc_dai *dai)
2432 {
2433         struct snd_soc_codec *codec = dai->codec;
2434         int rate_reg = 0;
2435
2436         switch (dai->id) {
2437         case 1:
2438                 rate_reg = WM8994_AIF1_RATE;
2439                 break;
2440         case 2:
2441                 rate_reg = WM8994_AIF2_RATE;
2442                 break;
2443         default:
2444                 break;
2445         }
2446
2447         /* If the DAI is idle then configure the divider tree for the
2448          * lowest output rate to save a little power if the clock is
2449          * still active (eg, because it is system clock).
2450          */
2451         if (rate_reg && !dai->playback_active && !dai->capture_active)
2452                 snd_soc_update_bits(codec, rate_reg,
2453                                     WM8994_AIF1_SR_MASK |
2454                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2455 }
2456
2457 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2458 {
2459         struct snd_soc_codec *codec = codec_dai->codec;
2460         int mute_reg;
2461         int reg;
2462
2463         switch (codec_dai->id) {
2464         case 1:
2465                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2466                 break;
2467         case 2:
2468                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2469                 break;
2470         default:
2471                 return -EINVAL;
2472         }
2473
2474         if (mute)
2475                 reg = WM8994_AIF1DAC1_MUTE;
2476         else
2477                 reg = 0;
2478
2479         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2480
2481         return 0;
2482 }
2483
2484 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2485 {
2486         struct snd_soc_codec *codec = codec_dai->codec;
2487         int reg, val, mask;
2488
2489         switch (codec_dai->id) {
2490         case 1:
2491                 reg = WM8994_AIF1_MASTER_SLAVE;
2492                 mask = WM8994_AIF1_TRI;
2493                 break;
2494         case 2:
2495                 reg = WM8994_AIF2_MASTER_SLAVE;
2496                 mask = WM8994_AIF2_TRI;
2497                 break;
2498         case 3:
2499                 reg = WM8994_POWER_MANAGEMENT_6;
2500                 mask = WM8994_AIF3_TRI;
2501                 break;
2502         default:
2503                 return -EINVAL;
2504         }
2505
2506         if (tristate)
2507                 val = mask;
2508         else
2509                 val = 0;
2510
2511         return snd_soc_update_bits(codec, reg, mask, val);
2512 }
2513
2514 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2515 {
2516         struct snd_soc_codec *codec = dai->codec;
2517
2518         /* Disable the pulls on the AIF if we're using it to save power. */
2519         snd_soc_update_bits(codec, WM8994_GPIO_3,
2520                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2521         snd_soc_update_bits(codec, WM8994_GPIO_4,
2522                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2523         snd_soc_update_bits(codec, WM8994_GPIO_5,
2524                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2525
2526         return 0;
2527 }
2528
2529 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2530
2531 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2532                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2533
2534 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2535         .set_sysclk     = wm8994_set_dai_sysclk,
2536         .set_fmt        = wm8994_set_dai_fmt,
2537         .hw_params      = wm8994_hw_params,
2538         .shutdown       = wm8994_aif_shutdown,
2539         .digital_mute   = wm8994_aif_mute,
2540         .set_pll        = wm8994_set_fll,
2541         .set_tristate   = wm8994_set_tristate,
2542 };
2543
2544 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2545         .set_sysclk     = wm8994_set_dai_sysclk,
2546         .set_fmt        = wm8994_set_dai_fmt,
2547         .hw_params      = wm8994_hw_params,
2548         .shutdown       = wm8994_aif_shutdown,
2549         .digital_mute   = wm8994_aif_mute,
2550         .set_pll        = wm8994_set_fll,
2551         .set_tristate   = wm8994_set_tristate,
2552 };
2553
2554 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2555         .hw_params      = wm8994_aif3_hw_params,
2556         .set_tristate   = wm8994_set_tristate,
2557 };
2558
2559 static struct snd_soc_dai_driver wm8994_dai[] = {
2560         {
2561                 .name = "wm8994-aif1",
2562                 .id = 1,
2563                 .playback = {
2564                         .stream_name = "AIF1 Playback",
2565                         .channels_min = 1,
2566                         .channels_max = 2,
2567                         .rates = WM8994_RATES,
2568                         .formats = WM8994_FORMATS,
2569                 },
2570                 .capture = {
2571                         .stream_name = "AIF1 Capture",
2572                         .channels_min = 1,
2573                         .channels_max = 2,
2574                         .rates = WM8994_RATES,
2575                         .formats = WM8994_FORMATS,
2576                  },
2577                 .ops = &wm8994_aif1_dai_ops,
2578         },
2579         {
2580                 .name = "wm8994-aif2",
2581                 .id = 2,
2582                 .playback = {
2583                         .stream_name = "AIF2 Playback",
2584                         .channels_min = 1,
2585                         .channels_max = 2,
2586                         .rates = WM8994_RATES,
2587                         .formats = WM8994_FORMATS,
2588                 },
2589                 .capture = {
2590                         .stream_name = "AIF2 Capture",
2591                         .channels_min = 1,
2592                         .channels_max = 2,
2593                         .rates = WM8994_RATES,
2594                         .formats = WM8994_FORMATS,
2595                 },
2596                 .probe = wm8994_aif2_probe,
2597                 .ops = &wm8994_aif2_dai_ops,
2598         },
2599         {
2600                 .name = "wm8994-aif3",
2601                 .id = 3,
2602                 .playback = {
2603                         .stream_name = "AIF3 Playback",
2604                         .channels_min = 1,
2605                         .channels_max = 2,
2606                         .rates = WM8994_RATES,
2607                         .formats = WM8994_FORMATS,
2608                 },
2609                 .capture = {
2610                         .stream_name = "AIF3 Capture",
2611                         .channels_min = 1,
2612                         .channels_max = 2,
2613                         .rates = WM8994_RATES,
2614                         .formats = WM8994_FORMATS,
2615                 },
2616                 .ops = &wm8994_aif3_dai_ops,
2617         }
2618 };
2619
2620 #ifdef CONFIG_PM
2621 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2622 {
2623         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2624         struct wm8994 *control = codec->control_data;
2625         int i, ret;
2626
2627         switch (control->type) {
2628         case WM8994:
2629                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2630                 break;
2631         case WM1811:
2632         case WM8958:
2633                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2634                                     WM8958_MICD_ENA, 0);
2635                 break;
2636         }
2637
2638         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2639                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2640                        sizeof(struct wm8994_fll_config));
2641                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2642                 if (ret < 0)
2643                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2644                                  i + 1, ret);
2645         }
2646
2647         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2648
2649         return 0;
2650 }
2651
2652 static int wm8994_resume(struct snd_soc_codec *codec)
2653 {
2654         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2655         struct wm8994 *control = codec->control_data;
2656         int i, ret;
2657         unsigned int val, mask;
2658
2659         if (wm8994->revision < 4) {
2660                 /* force a HW read */
2661                 val = wm8994_reg_read(codec->control_data,
2662                                       WM8994_POWER_MANAGEMENT_5);
2663
2664                 /* modify the cache only */
2665                 codec->cache_only = 1;
2666                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2667                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2668                 val &= mask;
2669                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2670                                     mask, val);
2671                 codec->cache_only = 0;
2672         }
2673
2674         /* Restore the registers */
2675         ret = snd_soc_cache_sync(codec);
2676         if (ret != 0)
2677                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2678
2679         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2680
2681         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2682                 if (!wm8994->fll_suspend[i].out)
2683                         continue;
2684
2685                 ret = _wm8994_set_fll(codec, i + 1,
2686                                      wm8994->fll_suspend[i].src,
2687                                      wm8994->fll_suspend[i].in,
2688                                      wm8994->fll_suspend[i].out);
2689                 if (ret < 0)
2690                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2691                                  i + 1, ret);
2692         }
2693
2694         switch (control->type) {
2695         case WM8994:
2696                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2697                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2698                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2699                 break;
2700         case WM1811:
2701         case WM8958:
2702                 if (wm8994->jack_cb)
2703                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2704                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2705                 break;
2706         }
2707
2708         return 0;
2709 }
2710 #else
2711 #define wm8994_suspend NULL
2712 #define wm8994_resume NULL
2713 #endif
2714
2715 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2716 {
2717         struct snd_soc_codec *codec = wm8994->codec;
2718         struct wm8994_pdata *pdata = wm8994->pdata;
2719         struct snd_kcontrol_new controls[] = {
2720                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2721                              wm8994->retune_mobile_enum,
2722                              wm8994_get_retune_mobile_enum,
2723                              wm8994_put_retune_mobile_enum),
2724                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2725                              wm8994->retune_mobile_enum,
2726                              wm8994_get_retune_mobile_enum,
2727                              wm8994_put_retune_mobile_enum),
2728                 SOC_ENUM_EXT("AIF2 EQ Mode",
2729                              wm8994->retune_mobile_enum,
2730                              wm8994_get_retune_mobile_enum,
2731                              wm8994_put_retune_mobile_enum),
2732         };
2733         int ret, i, j;
2734         const char **t;
2735
2736         /* We need an array of texts for the enum API but the number
2737          * of texts is likely to be less than the number of
2738          * configurations due to the sample rate dependency of the
2739          * configurations. */
2740         wm8994->num_retune_mobile_texts = 0;
2741         wm8994->retune_mobile_texts = NULL;
2742         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2743                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2744                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2745                                    wm8994->retune_mobile_texts[j]) == 0)
2746                                 break;
2747                 }
2748
2749                 if (j != wm8994->num_retune_mobile_texts)
2750                         continue;
2751
2752                 /* Expand the array... */
2753                 t = krealloc(wm8994->retune_mobile_texts,
2754                              sizeof(char *) *
2755                              (wm8994->num_retune_mobile_texts + 1),
2756                              GFP_KERNEL);
2757                 if (t == NULL)
2758                         continue;
2759
2760                 /* ...store the new entry... */
2761                 t[wm8994->num_retune_mobile_texts] =
2762                         pdata->retune_mobile_cfgs[i].name;
2763
2764                 /* ...and remember the new version. */
2765                 wm8994->num_retune_mobile_texts++;
2766                 wm8994->retune_mobile_texts = t;
2767         }
2768
2769         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2770                 wm8994->num_retune_mobile_texts);
2771
2772         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2773         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2774
2775         ret = snd_soc_add_controls(wm8994->codec, controls,
2776                                    ARRAY_SIZE(controls));
2777         if (ret != 0)
2778                 dev_err(wm8994->codec->dev,
2779                         "Failed to add ReTune Mobile controls: %d\n", ret);
2780 }
2781
2782 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2783 {
2784         struct snd_soc_codec *codec = wm8994->codec;
2785         struct wm8994_pdata *pdata = wm8994->pdata;
2786         int ret, i;
2787
2788         if (!pdata)
2789                 return;
2790
2791         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2792                                       pdata->lineout2_diff,
2793                                       pdata->lineout1fb,
2794                                       pdata->lineout2fb,
2795                                       pdata->jd_scthr,
2796                                       pdata->jd_thr,
2797                                       pdata->micbias1_lvl,
2798                                       pdata->micbias2_lvl);
2799
2800         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2801
2802         if (pdata->num_drc_cfgs) {
2803                 struct snd_kcontrol_new controls[] = {
2804                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2805                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2806                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2807                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2808                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2809                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2810                 };
2811
2812                 /* We need an array of texts for the enum API */
2813                 wm8994->drc_texts = kmalloc(sizeof(char *)
2814                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2815                 if (!wm8994->drc_texts) {
2816                         dev_err(wm8994->codec->dev,
2817                                 "Failed to allocate %d DRC config texts\n",
2818                                 pdata->num_drc_cfgs);
2819                         return;
2820                 }
2821
2822                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2823                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2824
2825                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2826                 wm8994->drc_enum.texts = wm8994->drc_texts;
2827
2828                 ret = snd_soc_add_controls(wm8994->codec, controls,
2829                                            ARRAY_SIZE(controls));
2830                 if (ret != 0)
2831                         dev_err(wm8994->codec->dev,
2832                                 "Failed to add DRC mode controls: %d\n", ret);
2833
2834                 for (i = 0; i < WM8994_NUM_DRC; i++)
2835                         wm8994_set_drc(codec, i);
2836         }
2837
2838         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2839                 pdata->num_retune_mobile_cfgs);
2840
2841         if (pdata->num_retune_mobile_cfgs)
2842                 wm8994_handle_retune_mobile_pdata(wm8994);
2843         else
2844                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2845                                      ARRAY_SIZE(wm8994_eq_controls));
2846
2847         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2848                 if (pdata->micbias[i]) {
2849                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2850                                 pdata->micbias[i] & 0xffff);
2851                 }
2852         }
2853 }
2854
2855 /**
2856  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2857  *
2858  * @codec:   WM8994 codec
2859  * @jack:    jack to report detection events on
2860  * @micbias: microphone bias to detect on
2861  * @det:     value to report for presence detection
2862  * @shrt:    value to report for short detection
2863  *
2864  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2865  * being used to bring out signals to the processor then only platform
2866  * data configuration is needed for WM8994 and processor GPIOs should
2867  * be configured using snd_soc_jack_add_gpios() instead.
2868  *
2869  * Configuration of detection levels is available via the micbias1_lvl
2870  * and micbias2_lvl platform data members.
2871  */
2872 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2873                       int micbias, int det, int shrt)
2874 {
2875         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2876         struct wm8994_micdet *micdet;
2877         struct wm8994 *control = codec->control_data;
2878         int reg;
2879
2880         if (control->type != WM8994)
2881                 return -EINVAL;
2882
2883         switch (micbias) {
2884         case 1:
2885                 micdet = &wm8994->micdet[0];
2886                 break;
2887         case 2:
2888                 micdet = &wm8994->micdet[1];
2889                 break;
2890         default:
2891                 return -EINVAL;
2892         }
2893
2894         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2895                 micbias, det, shrt);
2896
2897         /* Store the configuration */
2898         micdet->jack = jack;
2899         micdet->det = det;
2900         micdet->shrt = shrt;
2901
2902         /* If either of the jacks is set up then enable detection */
2903         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2904                 reg = WM8994_MICD_ENA;
2905         else
2906                 reg = 0;
2907
2908         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2909
2910         return 0;
2911 }
2912 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2913
2914 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2915 {
2916         struct wm8994_priv *priv = data;
2917         struct snd_soc_codec *codec = priv->codec;
2918         int reg;
2919         int report;
2920
2921 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2922         trace_snd_soc_jack_irq(dev_name(codec->dev));
2923 #endif
2924
2925         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2926         if (reg < 0) {
2927                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2928                         reg);
2929                 return IRQ_HANDLED;
2930         }
2931
2932         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2933
2934         report = 0;
2935         if (reg & WM8994_MIC1_DET_STS)
2936                 report |= priv->micdet[0].det;
2937         if (reg & WM8994_MIC1_SHRT_STS)
2938                 report |= priv->micdet[0].shrt;
2939         snd_soc_jack_report(priv->micdet[0].jack, report,
2940                             priv->micdet[0].det | priv->micdet[0].shrt);
2941
2942         report = 0;
2943         if (reg & WM8994_MIC2_DET_STS)
2944                 report |= priv->micdet[1].det;
2945         if (reg & WM8994_MIC2_SHRT_STS)
2946                 report |= priv->micdet[1].shrt;
2947         snd_soc_jack_report(priv->micdet[1].jack, report,
2948                             priv->micdet[1].det | priv->micdet[1].shrt);
2949
2950         return IRQ_HANDLED;
2951 }
2952
2953 /* Default microphone detection handler for WM8958 - the user can
2954  * override this if they wish.
2955  */
2956 static void wm8958_default_micdet(u16 status, void *data)
2957 {
2958         struct snd_soc_codec *codec = data;
2959         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2960         int report = 0;
2961
2962         /* If nothing present then clear our statuses */
2963         if (!(status & WM8958_MICD_STS))
2964                 goto done;
2965
2966         report = SND_JACK_MICROPHONE;
2967
2968         /* Everything else is buttons; just assign slots */
2969         if (status & 0x1c)
2970                 report |= SND_JACK_BTN_0;
2971
2972 done:
2973         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2974                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2975 }
2976
2977 /**
2978  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2979  *
2980  * @codec:   WM8958 codec
2981  * @jack:    jack to report detection events on
2982  *
2983  * Enable microphone detection functionality for the WM8958.  By
2984  * default simple detection which supports the detection of up to 6
2985  * buttons plus video and microphone functionality is supported.
2986  *
2987  * The WM8958 has an advanced jack detection facility which is able to
2988  * support complex accessory detection, especially when used in
2989  * conjunction with external circuitry.  In order to provide maximum
2990  * flexiblity a callback is provided which allows a completely custom
2991  * detection algorithm.
2992  */
2993 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2994                       wm8958_micdet_cb cb, void *cb_data)
2995 {
2996         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2997         struct wm8994 *control = codec->control_data;
2998
2999         switch (control->type) {
3000         case WM1811:
3001         case WM8958:
3002                 break;
3003         default:
3004                 return -EINVAL;
3005         }
3006
3007         if (jack) {
3008                 if (!cb) {
3009                         dev_dbg(codec->dev, "Using default micdet callback\n");
3010                         cb = wm8958_default_micdet;
3011                         cb_data = codec;
3012                 }
3013
3014                 wm8994->micdet[0].jack = jack;
3015                 wm8994->jack_cb = cb;
3016                 wm8994->jack_cb_data = cb_data;
3017
3018                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3019                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3020         } else {
3021                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3022                                     WM8958_MICD_ENA, 0);
3023         }
3024
3025         return 0;
3026 }
3027 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3028
3029 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3030 {
3031         struct wm8994_priv *wm8994 = data;
3032         struct snd_soc_codec *codec = wm8994->codec;
3033         int reg, count;
3034
3035         /* We may occasionally read a detection without an impedence
3036          * range being provided - if that happens loop again.
3037          */
3038         count = 10;
3039         do {
3040                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3041                 if (reg < 0) {
3042                         dev_err(codec->dev,
3043                                 "Failed to read mic detect status: %d\n",
3044                                 reg);
3045                         return IRQ_NONE;
3046                 }
3047
3048                 if (!(reg & WM8958_MICD_VALID)) {
3049                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3050                         goto out;
3051                 }
3052
3053                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3054                         break;
3055
3056                 msleep(1);
3057         } while (count--);
3058
3059         if (count == 0)
3060                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3061
3062 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3063         trace_snd_soc_jack_irq(dev_name(codec->dev));
3064 #endif
3065
3066         if (wm8994->jack_cb)
3067                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3068         else
3069                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3070
3071 out:
3072         return IRQ_HANDLED;
3073 }
3074
3075 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3076 {
3077         struct snd_soc_codec *codec = data;
3078
3079         dev_err(codec->dev, "FIFO error\n");
3080
3081         return IRQ_HANDLED;
3082 }
3083
3084 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3085 {
3086         struct snd_soc_codec *codec = data;
3087
3088         dev_err(codec->dev, "Thermal warning\n");
3089
3090         return IRQ_HANDLED;
3091 }
3092
3093 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3094 {
3095         struct snd_soc_codec *codec = data;
3096
3097         dev_crit(codec->dev, "Thermal shutdown\n");
3098
3099         return IRQ_HANDLED;
3100 }
3101
3102 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3103 {
3104         struct wm8994 *control;
3105         struct wm8994_priv *wm8994;
3106         struct snd_soc_dapm_context *dapm = &codec->dapm;
3107         int ret, i;
3108
3109         codec->control_data = dev_get_drvdata(codec->dev->parent);
3110         control = codec->control_data;
3111
3112         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3113         if (wm8994 == NULL)
3114                 return -ENOMEM;
3115         snd_soc_codec_set_drvdata(codec, wm8994);
3116
3117         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3118         wm8994->codec = codec;
3119
3120         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3121                 init_completion(&wm8994->fll_locked[i]);
3122
3123         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3124                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3125         else if (wm8994->pdata && wm8994->pdata->irq_base)
3126                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3127                                      WM8994_IRQ_MIC1_DET;
3128
3129         pm_runtime_enable(codec->dev);
3130         pm_runtime_resume(codec->dev);
3131
3132         /* Read our current status back from the chip - we don't want to
3133          * reset as this may interfere with the GPIO or LDO operation. */
3134         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3135                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3136                         continue;
3137
3138                 ret = wm8994_reg_read(codec->control_data, i);
3139                 if (ret <= 0)
3140                         continue;
3141
3142                 ret = snd_soc_cache_write(codec, i, ret);
3143                 if (ret != 0) {
3144                         dev_err(codec->dev,
3145                                 "Failed to initialise cache for 0x%x: %d\n",
3146                                 i, ret);
3147                         goto err;
3148                 }
3149         }
3150
3151         /* Set revision-specific configuration */
3152         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3153         switch (control->type) {
3154         case WM8994:
3155                 switch (wm8994->revision) {
3156                 case 2:
3157                 case 3:
3158                         wm8994->hubs.dcs_codes_l = -5;
3159                         wm8994->hubs.dcs_codes_r = -5;
3160                         wm8994->hubs.hp_startup_mode = 1;
3161                         wm8994->hubs.dcs_readback_mode = 1;
3162                         wm8994->hubs.series_startup = 1;
3163                         break;
3164                 default:
3165                         wm8994->hubs.dcs_readback_mode = 2;
3166                         break;
3167                 }
3168                 break;
3169
3170         case WM8958:
3171                 wm8994->hubs.dcs_readback_mode = 1;
3172                 break;
3173
3174         case WM1811:
3175                 wm8994->hubs.dcs_readback_mode = 2;
3176                 wm8994->hubs.no_series_update = 1;
3177
3178                 switch (wm8994->revision) {
3179                 case 0:
3180                 case 1:
3181                         wm8994->hubs.dcs_codes_l = -9;
3182                         wm8994->hubs.dcs_codes_r = -5;
3183                         break;
3184                 default:
3185                         break;
3186                 }
3187
3188                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3189                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3190                 break;
3191
3192         default:
3193                 break;
3194         }
3195
3196         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3197                            wm8994_fifo_error, "FIFO error", codec);
3198         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_WARN,
3199                            wm8994_temp_warn, "Thermal warning", codec);
3200         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT,
3201                            wm8994_temp_shut, "Thermal shutdown", codec);
3202
3203         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3204                                  wm_hubs_dcs_done, "DC servo done",
3205                                  &wm8994->hubs);
3206         if (ret == 0)
3207                 wm8994->hubs.dcs_done_irq = true;
3208
3209         switch (control->type) {
3210         case WM8994:
3211                 if (wm8994->micdet_irq) {
3212                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3213                                                    wm8994_mic_irq,
3214                                                    IRQF_TRIGGER_RISING,
3215                                                    "Mic1 detect",
3216                                                    wm8994);
3217                         if (ret != 0)
3218                                 dev_warn(codec->dev,
3219                                          "Failed to request Mic1 detect IRQ: %d\n",
3220                                          ret);
3221                 }
3222
3223                 ret = wm8994_request_irq(codec->control_data,
3224                                          WM8994_IRQ_MIC1_SHRT,
3225                                          wm8994_mic_irq, "Mic 1 short",
3226                                          wm8994);
3227                 if (ret != 0)
3228                         dev_warn(codec->dev,
3229                                  "Failed to request Mic1 short IRQ: %d\n",
3230                                  ret);
3231
3232                 ret = wm8994_request_irq(codec->control_data,
3233                                          WM8994_IRQ_MIC2_DET,
3234                                          wm8994_mic_irq, "Mic 2 detect",
3235                                          wm8994);
3236                 if (ret != 0)
3237                         dev_warn(codec->dev,
3238                                  "Failed to request Mic2 detect IRQ: %d\n",
3239                                  ret);
3240
3241                 ret = wm8994_request_irq(codec->control_data,
3242                                          WM8994_IRQ_MIC2_SHRT,
3243                                          wm8994_mic_irq, "Mic 2 short",
3244                                          wm8994);
3245                 if (ret != 0)
3246                         dev_warn(codec->dev,
3247                                  "Failed to request Mic2 short IRQ: %d\n",
3248                                  ret);
3249                 break;
3250
3251         case WM8958:
3252         case WM1811:
3253                 if (wm8994->micdet_irq) {
3254                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3255                                                    wm8958_mic_irq,
3256                                                    IRQF_TRIGGER_RISING,
3257                                                    "Mic detect",
3258                                                    wm8994);
3259                         if (ret != 0)
3260                                 dev_warn(codec->dev,
3261                                          "Failed to request Mic detect IRQ: %d\n",
3262                                          ret);
3263                 }
3264         }
3265
3266         wm8994->fll_locked_irq = true;
3267         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3268                 ret = wm8994_request_irq(codec->control_data,
3269                                          WM8994_IRQ_FLL1_LOCK + i,
3270                                          wm8994_fll_locked_irq, "FLL lock",
3271                                          &wm8994->fll_locked[i]);
3272                 if (ret != 0)
3273                         wm8994->fll_locked_irq = false;
3274         }
3275
3276         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3277          * configured on init - if a system wants to do this dynamically
3278          * at runtime we can deal with that then.
3279          */
3280         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3281         if (ret < 0) {
3282                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3283                 goto err_irq;
3284         }
3285         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3286                 wm8994->lrclk_shared[0] = 1;
3287                 wm8994_dai[0].symmetric_rates = 1;
3288         } else {
3289                 wm8994->lrclk_shared[0] = 0;
3290         }
3291
3292         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3293         if (ret < 0) {
3294                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3295                 goto err_irq;
3296         }
3297         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3298                 wm8994->lrclk_shared[1] = 1;
3299                 wm8994_dai[1].symmetric_rates = 1;
3300         } else {
3301                 wm8994->lrclk_shared[1] = 0;
3302         }
3303
3304         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3305
3306         /* Latch volume updates (right only; we always do left then right). */
3307         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3308                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3309         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3310                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3311         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3312                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3313         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3314                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3315         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3316                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3317         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3318                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3319         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3320                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3321         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3322                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3323         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3324                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3325         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3326                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3327         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3328                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3329         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3330                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3331         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3332                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3333         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3334                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3335         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3336                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3337         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3338                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3339
3340         /* Set the low bit of the 3D stereo depth so TLV matches */
3341         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3342                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3343                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3344         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3345                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3346                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3347         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3348                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3349                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3350
3351         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3352          * use this; it only affects behaviour on idle TDM clock
3353          * cycles. */
3354         switch (control->type) {
3355         case WM8994:
3356         case WM8958:
3357                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3358                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3359                 break;
3360         default:
3361                 break;
3362         }
3363
3364         wm8994_update_class_w(codec);
3365
3366         wm8994_handle_pdata(wm8994);
3367
3368         wm_hubs_add_analogue_controls(codec);
3369         snd_soc_add_controls(codec, wm8994_snd_controls,
3370                              ARRAY_SIZE(wm8994_snd_controls));
3371         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3372                                   ARRAY_SIZE(wm8994_dapm_widgets));
3373
3374         switch (control->type) {
3375         case WM8994:
3376                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3377                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3378                 if (wm8994->revision < 4) {
3379                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3380                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3381                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3382                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3383                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3384                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3385                 } else {
3386                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3387                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3388                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3389                                                   ARRAY_SIZE(wm8994_adc_widgets));
3390                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3391                                                   ARRAY_SIZE(wm8994_dac_widgets));
3392                 }
3393                 break;
3394         case WM8958:
3395                 snd_soc_add_controls(codec, wm8958_snd_controls,
3396                                      ARRAY_SIZE(wm8958_snd_controls));
3397                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3398                                           ARRAY_SIZE(wm8958_dapm_widgets));
3399                 if (wm8994->revision < 1) {
3400                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3401                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3402                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3403                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3404                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3405                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3406                 } else {
3407                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3408                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3409                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3410                                                   ARRAY_SIZE(wm8994_adc_widgets));
3411                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3412                                                   ARRAY_SIZE(wm8994_dac_widgets));
3413                 }
3414                 break;
3415
3416         case WM1811:
3417                 snd_soc_add_controls(codec, wm8958_snd_controls,
3418                                      ARRAY_SIZE(wm8958_snd_controls));
3419                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3420                                           ARRAY_SIZE(wm8958_dapm_widgets));
3421                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3422                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3423                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3424                                           ARRAY_SIZE(wm8994_adc_widgets));
3425                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3426                                           ARRAY_SIZE(wm8994_dac_widgets));
3427                 break;
3428         }
3429
3430
3431         wm_hubs_add_analogue_routes(codec, 0, 0);
3432         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3433
3434         switch (control->type) {
3435         case WM8994:
3436                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3437                                         ARRAY_SIZE(wm8994_intercon));
3438
3439                 if (wm8994->revision < 4) {
3440                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3441                                                 ARRAY_SIZE(wm8994_revd_intercon));
3442                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3443                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3444                 } else {
3445                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3446                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3447                 }
3448                 break;
3449         case WM8958:
3450                 if (wm8994->revision < 1) {
3451                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3452                                                 ARRAY_SIZE(wm8994_revd_intercon));
3453                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3454                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3455                 } else {
3456                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3457                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3458                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3459                                                 ARRAY_SIZE(wm8958_intercon));
3460                 }
3461
3462                 wm8958_dsp2_init(codec);
3463                 break;
3464         case WM1811:
3465                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3466                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3467                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3468                                         ARRAY_SIZE(wm8958_intercon));
3469                 break;
3470         }
3471
3472         return 0;
3473
3474 err_irq:
3475         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3476         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3477         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3478         if (wm8994->micdet_irq)
3479                 free_irq(wm8994->micdet_irq, wm8994);
3480         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3481                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3482                                 &wm8994->fll_locked[i]);
3483         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3484                         &wm8994->hubs);
3485         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3486         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3487         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3488 err:
3489         kfree(wm8994);
3490         return ret;
3491 }
3492
3493 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3494 {
3495         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3496         struct wm8994 *control = codec->control_data;
3497         int i;
3498
3499         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3500
3501         pm_runtime_disable(codec->dev);
3502
3503         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3504                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3505                                 &wm8994->fll_locked[i]);
3506
3507         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3508                         &wm8994->hubs);
3509         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3510         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3511         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3512
3513         switch (control->type) {
3514         case WM8994:
3515                 if (wm8994->micdet_irq)
3516                         free_irq(wm8994->micdet_irq, wm8994);
3517                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3518                                 wm8994);
3519                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3520                                 wm8994);
3521                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3522                                 wm8994);
3523                 break;
3524
3525         case WM1811:
3526         case WM8958:
3527                 if (wm8994->micdet_irq)
3528                         free_irq(wm8994->micdet_irq, wm8994);
3529                 break;
3530         }
3531         if (wm8994->mbc)
3532                 release_firmware(wm8994->mbc);
3533         if (wm8994->mbc_vss)
3534                 release_firmware(wm8994->mbc_vss);
3535         if (wm8994->enh_eq)
3536                 release_firmware(wm8994->enh_eq);
3537         kfree(wm8994->retune_mobile_texts);
3538         kfree(wm8994->drc_texts);
3539         kfree(wm8994);
3540
3541         return 0;
3542 }
3543
3544 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3545         .probe =        wm8994_codec_probe,
3546         .remove =       wm8994_codec_remove,
3547         .suspend =      wm8994_suspend,
3548         .resume =       wm8994_resume,
3549         .read =         wm8994_read,
3550         .write =        wm8994_write,
3551         .readable_register = wm8994_readable,
3552         .volatile_register = wm8994_volatile,
3553         .set_bias_level = wm8994_set_bias_level,
3554
3555         .reg_cache_size = WM8994_CACHE_SIZE,
3556         .reg_cache_default = wm8994_reg_defaults,
3557         .reg_word_size = 2,
3558         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3559 };
3560
3561 static int __devinit wm8994_probe(struct platform_device *pdev)
3562 {
3563         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3564                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3565 }
3566
3567 static int __devexit wm8994_remove(struct platform_device *pdev)
3568 {
3569         snd_soc_unregister_codec(&pdev->dev);
3570         return 0;
3571 }
3572
3573 static struct platform_driver wm8994_codec_driver = {
3574         .driver = {
3575                    .name = "wm8994-codec",
3576                    .owner = THIS_MODULE,
3577                    },
3578         .probe = wm8994_probe,
3579         .remove = __devexit_p(wm8994_remove),
3580 };
3581
3582 static __init int wm8994_init(void)
3583 {
3584         return platform_driver_register(&wm8994_codec_driver);
3585 }
3586 module_init(wm8994_init);
3587
3588 static __exit void wm8994_exit(void)
3589 {
3590         platform_driver_unregister(&wm8994_codec_driver);
3591 }
3592 module_exit(wm8994_exit);
3593
3594
3595 MODULE_DESCRIPTION("ASoC WM8994 driver");
3596 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3597 MODULE_LICENSE("GPL");
3598 MODULE_ALIAS("platform:wm8994-codec");