sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 struct fll_config {
  42         int src;
  43         int in;
  44         int out;
  45 };
  46
  47 #define WM8994_NUM_DRC 3
  48 #define WM8994_NUM_EQ  3
  49
  50 static int wm8994_drc_base[] = {
  51         WM8994_AIF1_DRC1_1,
  52         WM8994_AIF1_DRC2_1,
  53         WM8994_AIF2_DRC_1,
  54 };
  55
  56 static int wm8994_retune_mobile_base[] = {
  57         WM8994_AIF1_DAC1_EQ_GAINS_1,
  58         WM8994_AIF1_DAC2_EQ_GAINS_1,
  59         WM8994_AIF2_EQ_GAINS_1,
  60 };
  61
  62 struct wm8994_micdet {
  63         struct snd_soc_jack *jack;
  64         int det;
  65         int shrt;
  66 };
  67
  68 /* codec private data */
  69 struct wm8994_priv {
  70         struct wm_hubs_data hubs;
  71         enum snd_soc_control_type control_type;
  72         void *control_data;
  73         struct snd_soc_codec *codec;
  74         int sysclk[2];
  75         int sysclk_rate[2];
  76         int mclk[2];
  77         int aifclk[2];
  78         struct fll_config fll[2], fll_suspend[2];
  79
  80         int dac_rates[2];
  81         int lrclk_shared[2];
  82
  83         int mbc_ena[3];
  84
  85         /* Platform dependent DRC configuration */
  86         const char **drc_texts;
  87         int drc_cfg[WM8994_NUM_DRC];
  88         struct soc_enum drc_enum;
  89
  90         /* Platform dependent ReTune mobile configuration */
  91         int num_retune_mobile_texts;
  92         const char **retune_mobile_texts;
  93         int retune_mobile_cfg[WM8994_NUM_EQ];
  94         struct soc_enum retune_mobile_enum;
  95
  96         /* Platform dependent MBC configuration */
  97         int mbc_cfg;
  98         const char **mbc_texts;
  99         struct soc_enum mbc_enum;
 100
 101         struct wm8994_micdet micdet[2];
 102
 103         wm8958_micdet_cb jack_cb;
 104         void *jack_cb_data;
 105         int micdet_irq;
 106
 107         int revision;
 108         struct wm8994_pdata *pdata;
 109
 110         unsigned int aif1clk_enable:1;
 111         unsigned int aif2clk_enable:1;
 112
 113         unsigned int aif1clk_disable:1;
 114         unsigned int aif2clk_disable:1;
 115 };
 116
 117 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
 118 {
 119         switch (reg) {
 120         case WM8994_GPIO_1:
 121         case WM8994_GPIO_2:
 122         case WM8994_GPIO_3:
 123         case WM8994_GPIO_4:
 124         case WM8994_GPIO_5:
 125         case WM8994_GPIO_6:
 126         case WM8994_GPIO_7:
 127         case WM8994_GPIO_8:
 128         case WM8994_GPIO_9:
 129         case WM8994_GPIO_10:
 130         case WM8994_GPIO_11:
 131         case WM8994_INTERRUPT_STATUS_1:
 132         case WM8994_INTERRUPT_STATUS_2:
 133         case WM8994_INTERRUPT_RAW_STATUS_2:
 134                 return 1;
 135         default:
 136                 break;
 137         }
 138
 139         if (reg >= WM8994_CACHE_SIZE)
 140                 return 0;
 141         return wm8994_access_masks[reg].readable != 0;
 142 }
 143
 144 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
 145 {
 146         if (reg >= WM8994_CACHE_SIZE)
 147                 return 1;
 148
 149         switch (reg) {
 150         case WM8994_SOFTWARE_RESET:
 151         case WM8994_CHIP_REVISION:
 152         case WM8994_DC_SERVO_1:
 153         case WM8994_DC_SERVO_READBACK:
 154         case WM8994_RATE_STATUS:
 155         case WM8994_LDO_1:
 156         case WM8994_LDO_2:
 157         case WM8958_DSP2_EXECCONTROL:
 158         case WM8958_MIC_DETECT_3:
 159                 return 1;
 160         default:
 161                 return 0;
 162         }
 163 }
 164
 165 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 166         unsigned int value)
 167 {
 168         int ret;
 169
 170         BUG_ON(reg > WM8994_MAX_REGISTER);
 171
 172         if (!wm8994_volatile(codec, reg)) {
 173                 ret = snd_soc_cache_write(codec, reg, value);
 174                 if (ret != 0)
 175                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 176                                 reg, ret);
 177         }
 178
 179         return wm8994_reg_write(codec->control_data, reg, value);
 180 }
 181
 182 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 183                                 unsigned int reg)
 184 {
 185         unsigned int val;
 186         int ret;
 187
 188         BUG_ON(reg > WM8994_MAX_REGISTER);
 189
 190         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 191             reg < codec->driver->reg_cache_size) {
 192                 ret = snd_soc_cache_read(codec, reg, &val);
 193                 if (ret >= 0)
 194                         return val;
 195                 else
 196                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 197                                 reg, ret);
 198         }
 199
 200         return wm8994_reg_read(codec->control_data, reg);
 201 }
 202
 203 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 204 {
 205         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 206         int rate;
 207         int reg1 = 0;
 208         int offset;
 209
 210         if (aif)
 211                 offset = 4;
 212         else
 213                 offset = 0;
 214
 215         switch (wm8994->sysclk[aif]) {
 216         case WM8994_SYSCLK_MCLK1:
 217                 rate = wm8994->mclk[0];
 218                 break;
 219
 220         case WM8994_SYSCLK_MCLK2:
 221                 reg1 |= 0x8;
 222                 rate = wm8994->mclk[1];
 223                 break;
 224
 225         case WM8994_SYSCLK_FLL1:
 226                 reg1 |= 0x10;
 227                 rate = wm8994->fll[0].out;
 228                 break;
 229
 230         case WM8994_SYSCLK_FLL2:
 231                 reg1 |= 0x18;
 232                 rate = wm8994->fll[1].out;
 233                 break;
 234
 235         default:
 236                 return -EINVAL;
 237         }
 238
 239         if (rate >= 13500000) {
 240                 rate /= 2;
 241                 reg1 |= WM8994_AIF1CLK_DIV;
 242
 243                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 244                         aif + 1, rate);
 245         }
 246
 247         if (rate && rate < 3000000)
 248                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 249                          aif + 1, rate);
 250
 251         wm8994->aifclk[aif] = rate;
 252
 253         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 254                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 255                             reg1);
 256
 257         return 0;
 258 }
 259
 260 static int configure_clock(struct snd_soc_codec *codec)
 261 {
 262         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 263         int old, new;
 264
 265         /* Bring up the AIF clocks first */
 266         configure_aif_clock(codec, 0);
 267         configure_aif_clock(codec, 1);
 268
 269         /* Then switch CLK_SYS over to the higher of them; a change
 270          * can only happen as a result of a clocking change which can
 271          * only be made outside of DAPM so we can safely redo the
 272          * clocking.
 273          */
 274
 275         /* If they're equal it doesn't matter which is used */
 276         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 277                 return 0;
 278
 279         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 280                 new = WM8994_SYSCLK_SRC;
 281         else
 282                 new = 0;
 283
 284         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 285
 286         /* If there's no change then we're done. */
 287         if (old == new)
 288                 return 0;
 289
 290         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 291
 292         snd_soc_dapm_sync(&codec->dapm);
 293
 294         return 0;
 295 }
 296
 297 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 298                          struct snd_soc_dapm_widget *sink)
 299 {
 300         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 301         const char *clk;
 302
 303         /* Check what we're currently using for CLK_SYS */
 304         if (reg & WM8994_SYSCLK_SRC)
 305                 clk = "AIF2CLK";
 306         else
 307                 clk = "AIF1CLK";
 308
 309         return strcmp(source->name, clk) == 0;
 310 }
 311
 312 static const char *sidetone_hpf_text[] = {
 313         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 314 };
 315
 316 static const struct soc_enum sidetone_hpf =
 317         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 318
 319 static const char *adc_hpf_text[] = {
 320         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 321 };
 322
 323 static const struct soc_enum aif1adc1_hpf =
 324         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 325
 326 static const struct soc_enum aif1adc2_hpf =
 327         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 328
 329 static const struct soc_enum aif2adc_hpf =
 330         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 331
 332 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 333 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 334 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 335 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 336 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 337
 338 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 339 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 340         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 341         .put = wm8994_put_drc_sw, \
 342         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 343
 344 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 345                              struct snd_ctl_elem_value *ucontrol)
 346 {
 347         struct soc_mixer_control *mc =
 348                 (struct soc_mixer_control *)kcontrol->private_value;
 349         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 350         int mask, ret;
 351
 352         /* Can't enable both ADC and DAC paths simultaneously */
 353         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 354                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 355                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 356         else
 357                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 358
 359         ret = snd_soc_read(codec, mc->reg);
 360         if (ret < 0)
 361                 return ret;
 362         if (ret & mask)
 363                 return -EINVAL;
 364
 365         return snd_soc_put_volsw(kcontrol, ucontrol);
 366 }
 367
 368 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 369 {
 370         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 371         struct wm8994_pdata *pdata = wm8994->pdata;
 372         int base = wm8994_drc_base[drc];
 373         int cfg = wm8994->drc_cfg[drc];
 374         int save, i;
 375
 376         /* Save any enables; the configuration should clear them. */
 377         save = snd_soc_read(codec, base);
 378         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 379                 WM8994_AIF1ADC1R_DRC_ENA;
 380
 381         for (i = 0; i < WM8994_DRC_REGS; i++)
 382                 snd_soc_update_bits(codec, base + i, 0xffff,
 383                                     pdata->drc_cfgs[cfg].regs[i]);
 384
 385         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 386                              WM8994_AIF1ADC1L_DRC_ENA |
 387                              WM8994_AIF1ADC1R_DRC_ENA, save);
 388 }
 389
 390 /* Icky as hell but saves code duplication */
 391 static int wm8994_get_drc(const char *name)
 392 {
 393         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 394                 return 0;
 395         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 396                 return 1;
 397         if (strcmp(name, "AIF2DRC Mode") == 0)
 398                 return 2;
 399         return -EINVAL;
 400 }
 401
 402 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 403                                struct snd_ctl_elem_value *ucontrol)
 404 {
 405         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 406         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 407         struct wm8994_pdata *pdata = wm8994->pdata;
 408         int drc = wm8994_get_drc(kcontrol->id.name);
 409         int value = ucontrol->value.integer.value[0];
 410
 411         if (drc < 0)
 412                 return drc;
 413
 414         if (value >= pdata->num_drc_cfgs)
 415                 return -EINVAL;
 416
 417         wm8994->drc_cfg[drc] = value;
 418
 419         wm8994_set_drc(codec, drc);
 420
 421         return 0;
 422 }
 423
 424 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 425                                struct snd_ctl_elem_value *ucontrol)
 426 {
 427         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 428         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 429         int drc = wm8994_get_drc(kcontrol->id.name);
 430
 431         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 432
 433         return 0;
 434 }
 435
 436 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 437 {
 438         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 439         struct wm8994_pdata *pdata = wm8994->pdata;
 440         int base = wm8994_retune_mobile_base[block];
 441         int iface, best, best_val, save, i, cfg;
 442
 443         if (!pdata || !wm8994->num_retune_mobile_texts)
 444                 return;
 445
 446         switch (block) {
 447         case 0:
 448         case 1:
 449                 iface = 0;
 450                 break;
 451         case 2:
 452                 iface = 1;
 453                 break;
 454         default:
 455                 return;
 456         }
 457
 458         /* Find the version of the currently selected configuration
 459          * with the nearest sample rate. */
 460         cfg = wm8994->retune_mobile_cfg[block];
 461         best = 0;
 462         best_val = INT_MAX;
 463         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 464                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 465                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 466                     abs(pdata->retune_mobile_cfgs[i].rate
 467                         - wm8994->dac_rates[iface]) < best_val) {
 468                         best = i;
 469                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 470                                        - wm8994->dac_rates[iface]);
 471                 }
 472         }
 473
 474         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 475                 block,
 476                 pdata->retune_mobile_cfgs[best].name,
 477                 pdata->retune_mobile_cfgs[best].rate,
 478                 wm8994->dac_rates[iface]);
 479
 480         /* The EQ will be disabled while reconfiguring it, remember the
 481          * current configuration.
 482          */
 483         save = snd_soc_read(codec, base);
 484         save &= WM8994_AIF1DAC1_EQ_ENA;
 485
 486         for (i = 0; i < WM8994_EQ_REGS; i++)
 487                 snd_soc_update_bits(codec, base + i, 0xffff,
 488                                 pdata->retune_mobile_cfgs[best].regs[i]);
 489
 490         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 491 }
 492
 493 /* Icky as hell but saves code duplication */
 494 static int wm8994_get_retune_mobile_block(const char *name)
 495 {
 496         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 497                 return 0;
 498         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 499                 return 1;
 500         if (strcmp(name, "AIF2 EQ Mode") == 0)
 501                 return 2;
 502         return -EINVAL;
 503 }
 504
 505 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 506                                          struct snd_ctl_elem_value *ucontrol)
 507 {
 508         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 509         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 510         struct wm8994_pdata *pdata = wm8994->pdata;
 511         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 512         int value = ucontrol->value.integer.value[0];
 513
 514         if (block < 0)
 515                 return block;
 516
 517         if (value >= pdata->num_retune_mobile_cfgs)
 518                 return -EINVAL;
 519
 520         wm8994->retune_mobile_cfg[block] = value;
 521
 522         wm8994_set_retune_mobile(codec, block);
 523
 524         return 0;
 525 }
 526
 527 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 528                                          struct snd_ctl_elem_value *ucontrol)
 529 {
 530         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 531         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 532         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 533
 534         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 535
 536         return 0;
 537 }
 538
 539 static const char *aif_chan_src_text[] = {
 540         "Left", "Right"
 541 };
 542
 543 static const struct soc_enum aif1adcl_src =
 544         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 545
 546 static const struct soc_enum aif1adcr_src =
 547         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 548
 549 static const struct soc_enum aif2adcl_src =
 550         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 551
 552 static const struct soc_enum aif2adcr_src =
 553         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 554
 555 static const struct soc_enum aif1dacl_src =
 556         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 557
 558 static const struct soc_enum aif1dacr_src =
 559         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 560
 561 static const struct soc_enum aif2dacl_src =
 562         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 563
 564 static const struct soc_enum aif2dacr_src =
 565         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 566
 567 static const char *osr_text[] = {
 568         "Low Power", "High Performance",
 569 };
 570
 571 static const struct soc_enum dac_osr =
 572         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 573
 574 static const struct soc_enum adc_osr =
 575         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 576
 577 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
 578 {
 579         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 580         struct wm8994_pdata *pdata = wm8994->pdata;
 581         int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
 582         int ena, reg, aif, i;
 583
 584         switch (mbc) {
 585         case 0:
 586                 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
 587                 aif = 0;
 588                 break;
 589         case 1:
 590                 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
 591                 aif = 0;
 592                 break;
 593         case 2:
 594                 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
 595                 aif = 1;
 596                 break;
 597         default:
 598                 BUG();
 599                 return;
 600         }
 601
 602         /* We can only enable the MBC if the AIF is enabled and we
 603          * want it to be enabled. */
 604         ena = pwr_reg && wm8994->mbc_ena[mbc];
 605
 606         reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
 607
 608         dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
 609                 mbc, start, pwr_reg, reg);
 610
 611         if (start && ena) {
 612                 /* If the DSP is already running then noop */
 613                 if (reg & WM8958_DSP2_ENA)
 614                         return;
 615
 616                 /* Switch the clock over to the appropriate AIF */
 617                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 618                                     WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
 619                                     aif << WM8958_DSP2CLK_SRC_SHIFT |
 620                                     WM8958_DSP2CLK_ENA);
 621
 622                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 623                                     WM8958_DSP2_ENA, WM8958_DSP2_ENA);
 624
 625                 /* If we've got user supplied MBC settings use them */
 626                 if (pdata && pdata->num_mbc_cfgs) {
 627                         struct wm8958_mbc_cfg *cfg
 628                                 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
 629
 630                         for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
 631                                 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
 632                                               cfg->coeff_regs[i]);
 633
 634                         for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
 635                                 snd_soc_write(codec,
 636                                               i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
 637                                               cfg->cutoff_regs[i]);
 638                 }
 639
 640                 /* Run the DSP */
 641                 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
 642                               WM8958_DSP2_RUNR);
 643
 644                 /* And we're off! */
 645                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 646                                     WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
 647                                     mbc << WM8958_MBC_SEL_SHIFT |
 648                                     WM8958_MBC_ENA);
 649         } else {
 650                 /* If the DSP is already stopped then noop */
 651                 if (!(reg & WM8958_DSP2_ENA))
 652                         return;
 653
 654                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 655                                     WM8958_MBC_ENA, 0);
 656                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 657                                     WM8958_DSP2_ENA, 0);
 658                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 659                                     WM8958_DSP2CLK_ENA, 0);
 660         }
 661 }
 662
 663 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
 664                     struct snd_kcontrol *kcontrol, int event)
 665 {
 666         struct snd_soc_codec *codec = w->codec;
 667         int mbc;
 668
 669         switch (w->shift) {
 670         case 13:
 671         case 12:
 672                 mbc = 2;
 673                 break;
 674         case 11:
 675         case 10:
 676                 mbc = 1;
 677                 break;
 678         case 9:
 679         case 8:
 680                 mbc = 0;
 681                 break;
 682         default:
 683                 BUG();
 684                 return -EINVAL;
 685         }
 686
 687         switch (event) {
 688         case SND_SOC_DAPM_POST_PMU:
 689                 wm8958_mbc_apply(codec, mbc, 1);
 690                 break;
 691         case SND_SOC_DAPM_POST_PMD:
 692                 wm8958_mbc_apply(codec, mbc, 0);
 693                 break;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
 700                                struct snd_ctl_elem_value *ucontrol)
 701 {
 702         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 703         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 704         struct wm8994_pdata *pdata = wm8994->pdata;
 705         int value = ucontrol->value.integer.value[0];
 706         int reg;
 707
 708         /* Don't allow on the fly reconfiguration */
 709         reg = snd_soc_read(codec, WM8994_CLOCKING_1);
 710         if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
 711                 return -EBUSY;
 712
 713         if (value >= pdata->num_mbc_cfgs)
 714                 return -EINVAL;
 715
 716         wm8994->mbc_cfg = value;
 717
 718         return 0;
 719 }
 720
 721 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
 722                                struct snd_ctl_elem_value *ucontrol)
 723 {
 724         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726
 727         ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
 728
 729         return 0;
 730 }
 731
 732 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
 733                            struct snd_ctl_elem_info *uinfo)
 734 {
 735         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 736         uinfo->count = 1;
 737         uinfo->value.integer.min = 0;
 738         uinfo->value.integer.max = 1;
 739         return 0;
 740 }
 741
 742 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
 743                           struct snd_ctl_elem_value *ucontrol)
 744 {
 745         int mbc = kcontrol->private_value;
 746         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 747         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 748
 749         ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
 750
 751         return 0;
 752 }
 753
 754 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
 755                           struct snd_ctl_elem_value *ucontrol)
 756 {
 757         int mbc = kcontrol->private_value;
 758         int i;
 759         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 760         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 761
 762         if (ucontrol->value.integer.value[0] > 1)
 763                 return -EINVAL;
 764
 765         for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
 766                 if (mbc != i && wm8994->mbc_ena[i]) {
 767                         dev_dbg(codec->dev, "MBC %d active already\n", mbc);
 768                         return -EBUSY;
 769                 }
 770         }
 771
 772         wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
 773
 774         wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
 775
 776         return 0;
 777 }
 778
 779 #define WM8958_MBC_SWITCH(xname, xval) {\
 780         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 781         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 782         .info = wm8958_mbc_info, \
 783         .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
 784         .private_value = xval }
 785
 786 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 787 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 788                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 789                  1, 119, 0, digital_tlv),
 790 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 791                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 792                  1, 119, 0, digital_tlv),
 793 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 794                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 795                  1, 119, 0, digital_tlv),
 796
 797 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 798 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 799 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 800 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 801
 802 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 803 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 804 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 805 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 806
 807 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 808                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 809 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 810                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 811 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 812                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 813
 814 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 815 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 816
 817 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 818 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 819 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 820
 821 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 822 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 823 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 824
 825 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 826 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 827 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 828
 829 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 830 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 831 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 832
 833 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 834                5, 12, 0, st_tlv),
 835 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 836                0, 12, 0, st_tlv),
 837 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 838                5, 12, 0, st_tlv),
 839 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 840                0, 12, 0, st_tlv),
 841 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 842 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 843
 844 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 845 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 846
 847 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 848 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 849
 850 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 851 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 852
 853 SOC_ENUM("ADC OSR", adc_osr),
 854 SOC_ENUM("DAC OSR", dac_osr),
 855
 856 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 857                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 858 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 859              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 860
 861 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 862                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 863 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 864              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 865
 866 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 867                6, 1, 1, wm_hubs_spkmix_tlv),
 868 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 869                2, 1, 1, wm_hubs_spkmix_tlv),
 870
 871 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 872                6, 1, 1, wm_hubs_spkmix_tlv),
 873 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 874                2, 1, 1, wm_hubs_spkmix_tlv),
 875
 876 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 877                10, 15, 0, wm8994_3d_tlv),
 878 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 879            8, 1, 0),
 880 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 881                10, 15, 0, wm8994_3d_tlv),
 882 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 883            8, 1, 0),
 884 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 885                10, 15, 0, wm8994_3d_tlv),
 886 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 887            8, 1, 0),
 888 };
 889
 890 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 891 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 892                eq_tlv),
 893 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 894                eq_tlv),
 895 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 896                eq_tlv),
 897 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 898                eq_tlv),
 899 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 900                eq_tlv),
 901
 902 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 903                eq_tlv),
 904 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 905                eq_tlv),
 906 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 907                eq_tlv),
 908 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 909                eq_tlv),
 910 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 911                eq_tlv),
 912
 913 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 914                eq_tlv),
 915 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 916                eq_tlv),
 917 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 918                eq_tlv),
 919 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 920                eq_tlv),
 921 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 922                eq_tlv),
 923 };
 924
 925 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 926 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 927 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
 928 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
 929 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
 930 };
 931
 932 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 933                          struct snd_kcontrol *kcontrol, int event)
 934 {
 935         struct snd_soc_codec *codec = w->codec;
 936
 937         switch (event) {
 938         case SND_SOC_DAPM_PRE_PMU:
 939                 return configure_clock(codec);
 940
 941         case SND_SOC_DAPM_POST_PMD:
 942                 configure_clock(codec);
 943                 break;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 950 {
 951         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 952         int enable = 1;
 953         int source = 0;  /* GCC flow analysis can't track enable */
 954         int reg, reg_r;
 955
 956         /* Only support direct DAC->headphone paths */
 957         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 958         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 959                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 960                 enable = 0;
 961         }
 962
 963         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 964         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 965                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 966                 enable = 0;
 967         }
 968
 969         /* We also need the same setting for L/R and only one path */
 970         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 971         switch (reg) {
 972         case WM8994_AIF2DACL_TO_DAC1L:
 973                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 974                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 975                 break;
 976         case WM8994_AIF1DAC2L_TO_DAC1L:
 977                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 978                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 979                 break;
 980         case WM8994_AIF1DAC1L_TO_DAC1L:
 981                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 982                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 983                 break;
 984         default:
 985                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 986                 enable = 0;
 987                 break;
 988         }
 989
 990         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 991         if (reg_r != reg) {
 992                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 993                 enable = 0;
 994         }
 995
 996         if (enable) {
 997                 dev_dbg(codec->dev, "Class W enabled\n");
 998                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 999                                     WM8994_CP_DYN_PWR |
1000                                     WM8994_CP_DYN_SRC_SEL_MASK,
1001                                     source | WM8994_CP_DYN_PWR);
1002                 wm8994->hubs.class_w = true;
1003
1004         } else {
1005                 dev_dbg(codec->dev, "Class W disabled\n");
1006                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1007                                     WM8994_CP_DYN_PWR, 0);
1008                 wm8994->hubs.class_w = false;
1009         }
1010 }
1011
1012 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1013                           struct snd_kcontrol *kcontrol, int event)
1014 {
1015         struct snd_soc_codec *codec = w->codec;
1016         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1017
1018         switch (event) {
1019         case SND_SOC_DAPM_PRE_PMU:
1020                 if (wm8994->aif1clk_enable) {
1021                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1022                                             WM8994_AIF1CLK_ENA_MASK,
1023                                             WM8994_AIF1CLK_ENA);
1024                         wm8994->aif1clk_enable = 0;
1025                 }
1026                 if (wm8994->aif2clk_enable) {
1027                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1028                                             WM8994_AIF2CLK_ENA_MASK,
1029                                             WM8994_AIF2CLK_ENA);
1030                         wm8994->aif2clk_enable = 0;
1031                 }
1032                 break;
1033         }
1034
1035         return 0;
1036 }
1037
1038 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1039                            struct snd_kcontrol *kcontrol, int event)
1040 {
1041         struct snd_soc_codec *codec = w->codec;
1042         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1043
1044         switch (event) {
1045         case SND_SOC_DAPM_POST_PMD:
1046                 if (wm8994->aif1clk_disable) {
1047                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1048                                             WM8994_AIF1CLK_ENA_MASK, 0);
1049                         wm8994->aif1clk_disable = 0;
1050                 }
1051                 if (wm8994->aif2clk_disable) {
1052                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1053                                             WM8994_AIF2CLK_ENA_MASK, 0);
1054                         wm8994->aif2clk_disable = 0;
1055                 }
1056                 break;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1063                       struct snd_kcontrol *kcontrol, int event)
1064 {
1065         struct snd_soc_codec *codec = w->codec;
1066         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1067
1068         switch (event) {
1069         case SND_SOC_DAPM_PRE_PMU:
1070                 wm8994->aif1clk_enable = 1;
1071                 break;
1072         case SND_SOC_DAPM_POST_PMD:
1073                 wm8994->aif1clk_disable = 1;
1074                 break;
1075         }
1076
1077         return 0;
1078 }
1079
1080 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1081                       struct snd_kcontrol *kcontrol, int event)
1082 {
1083         struct snd_soc_codec *codec = w->codec;
1084         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1085
1086         switch (event) {
1087         case SND_SOC_DAPM_PRE_PMU:
1088                 wm8994->aif2clk_enable = 1;
1089                 break;
1090         case SND_SOC_DAPM_POST_PMD:
1091                 wm8994->aif2clk_disable = 1;
1092                 break;
1093         }
1094
1095         return 0;
1096 }
1097
1098 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1099                       struct snd_kcontrol *kcontrol, int event)
1100 {
1101         late_enable_ev(w, kcontrol, event);
1102         return 0;
1103 }
1104
1105 static int micbias_ev(struct snd_soc_dapm_widget *w,
1106                       struct snd_kcontrol *kcontrol, int event)
1107 {
1108         late_enable_ev(w, kcontrol, event);
1109         return 0;
1110 }
1111
1112 static int dac_ev(struct snd_soc_dapm_widget *w,
1113                   struct snd_kcontrol *kcontrol, int event)
1114 {
1115         struct snd_soc_codec *codec = w->codec;
1116         unsigned int mask = 1 << w->shift;
1117
1118         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1119                             mask, mask);
1120         return 0;
1121 }
1122
1123 static const char *hp_mux_text[] = {
1124         "Mixer",
1125         "DAC",
1126 };
1127
1128 #define WM8994_HP_ENUM(xname, xenum) \
1129 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1130         .info = snd_soc_info_enum_double, \
1131         .get = snd_soc_dapm_get_enum_double, \
1132         .put = wm8994_put_hp_enum, \
1133         .private_value = (unsigned long)&xenum }
1134
1135 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1136                               struct snd_ctl_elem_value *ucontrol)
1137 {
1138         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1139         struct snd_soc_codec *codec = w->codec;
1140         int ret;
1141
1142         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1143
1144         wm8994_update_class_w(codec);
1145
1146         return ret;
1147 }
1148
1149 static const struct soc_enum hpl_enum =
1150         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1151
1152 static const struct snd_kcontrol_new hpl_mux =
1153         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1154
1155 static const struct soc_enum hpr_enum =
1156         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1157
1158 static const struct snd_kcontrol_new hpr_mux =
1159         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1160
1161 static const char *adc_mux_text[] = {
1162         "ADC",
1163         "DMIC",
1164 };
1165
1166 static const struct soc_enum adc_enum =
1167         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1168
1169 static const struct snd_kcontrol_new adcl_mux =
1170         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1171
1172 static const struct snd_kcontrol_new adcr_mux =
1173         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1174
1175 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1176 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1177 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1178 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1179 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1180 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1181 };
1182
1183 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1184 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1185 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1186 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1187 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1188 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1189 };
1190
1191 /* Debugging; dump chip status after DAPM transitions */
1192 static int post_ev(struct snd_soc_dapm_widget *w,
1193             struct snd_kcontrol *kcontrol, int event)
1194 {
1195         struct snd_soc_codec *codec = w->codec;
1196         dev_dbg(codec->dev, "SRC status: %x\n",
1197                 snd_soc_read(codec,
1198                              WM8994_RATE_STATUS));
1199         return 0;
1200 }
1201
1202 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1203 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1204                 1, 1, 0),
1205 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1206                 0, 1, 0),
1207 };
1208
1209 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1210 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1211                 1, 1, 0),
1212 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1213                 0, 1, 0),
1214 };
1215
1216 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1217 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1218                 1, 1, 0),
1219 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1220                 0, 1, 0),
1221 };
1222
1223 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1224 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1225                 1, 1, 0),
1226 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1227                 0, 1, 0),
1228 };
1229
1230 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1231 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1232                 5, 1, 0),
1233 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1234                 4, 1, 0),
1235 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1236                 2, 1, 0),
1237 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1238                 1, 1, 0),
1239 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1240                 0, 1, 0),
1241 };
1242
1243 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1244 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1245                 5, 1, 0),
1246 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1247                 4, 1, 0),
1248 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1249                 2, 1, 0),
1250 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1251                 1, 1, 0),
1252 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1253                 0, 1, 0),
1254 };
1255
1256 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1257 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1258         .info = snd_soc_info_volsw, \
1259         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1260         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1261
1262 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1263                               struct snd_ctl_elem_value *ucontrol)
1264 {
1265         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1266         struct snd_soc_codec *codec = w->codec;
1267         int ret;
1268
1269         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1270
1271         wm8994_update_class_w(codec);
1272
1273         return ret;
1274 }
1275
1276 static const struct snd_kcontrol_new dac1l_mix[] = {
1277 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1278                       5, 1, 0),
1279 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1280                       4, 1, 0),
1281 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1282                       2, 1, 0),
1283 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1284                       1, 1, 0),
1285 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1286                       0, 1, 0),
1287 };
1288
1289 static const struct snd_kcontrol_new dac1r_mix[] = {
1290 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1291                       5, 1, 0),
1292 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1293                       4, 1, 0),
1294 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1295                       2, 1, 0),
1296 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1297                       1, 1, 0),
1298 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1299                       0, 1, 0),
1300 };
1301
1302 static const char *sidetone_text[] = {
1303         "ADC/DMIC1", "DMIC2",
1304 };
1305
1306 static const struct soc_enum sidetone1_enum =
1307         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1308
1309 static const struct snd_kcontrol_new sidetone1_mux =
1310         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1311
1312 static const struct soc_enum sidetone2_enum =
1313         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1314
1315 static const struct snd_kcontrol_new sidetone2_mux =
1316         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1317
1318 static const char *aif1dac_text[] = {
1319         "AIF1DACDAT", "AIF3DACDAT",
1320 };
1321
1322 static const struct soc_enum aif1dac_enum =
1323         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1324
1325 static const struct snd_kcontrol_new aif1dac_mux =
1326         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1327
1328 static const char *aif2dac_text[] = {
1329         "AIF2DACDAT", "AIF3DACDAT",
1330 };
1331
1332 static const struct soc_enum aif2dac_enum =
1333         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1334
1335 static const struct snd_kcontrol_new aif2dac_mux =
1336         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1337
1338 static const char *aif2adc_text[] = {
1339         "AIF2ADCDAT", "AIF3DACDAT",
1340 };
1341
1342 static const struct soc_enum aif2adc_enum =
1343         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1344
1345 static const struct snd_kcontrol_new aif2adc_mux =
1346         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1347
1348 static const char *aif3adc_text[] = {
1349         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1350 };
1351
1352 static const struct soc_enum wm8994_aif3adc_enum =
1353         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1354
1355 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1356         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1357
1358 static const struct soc_enum wm8958_aif3adc_enum =
1359         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1360
1361 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1362         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1363
1364 static const char *mono_pcm_out_text[] = {
1365         "None", "AIF2ADCL", "AIF2ADCR",
1366 };
1367
1368 static const struct soc_enum mono_pcm_out_enum =
1369         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1370
1371 static const struct snd_kcontrol_new mono_pcm_out_mux =
1372         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1373
1374 static const char *aif2dac_src_text[] = {
1375         "AIF2", "AIF3",
1376 };
1377
1378 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1379 static const struct soc_enum aif2dacl_src_enum =
1380         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1381
1382 static const struct snd_kcontrol_new aif2dacl_src_mux =
1383         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1384
1385 static const struct soc_enum aif2dacr_src_enum =
1386         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1387
1388 static const struct snd_kcontrol_new aif2dacr_src_mux =
1389         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1390
1391 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1392 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1393         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1394 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1395         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1396
1397 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1398         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1399 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1400         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1401 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1402         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1403 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1404         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1405
1406 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1407 };
1408
1409 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1410 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1411 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1412 };
1413
1414 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1415 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1416         dac_ev, SND_SOC_DAPM_PRE_PMU),
1417 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1418         dac_ev, SND_SOC_DAPM_PRE_PMU),
1419 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1420         dac_ev, SND_SOC_DAPM_PRE_PMU),
1421 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1422         dac_ev, SND_SOC_DAPM_PRE_PMU),
1423 };
1424
1425 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1426 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1427 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1428 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1429 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1430 };
1431
1432 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1433 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1434                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1435 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1436                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1437 };
1438
1439 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1440 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1441 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1442 };
1443
1444 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1445 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1446 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1447 SND_SOC_DAPM_INPUT("Clock"),
1448
1449 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1450 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1451                       SND_SOC_DAPM_PRE_PMU),
1452
1453 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1454                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1455
1456 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1457 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1458 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1459
1460 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1461                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1462 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1463                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1464 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1465                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1466                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1467 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1468                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1469                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1470
1471 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1472                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1473 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1474                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1475 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1476                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1477                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1478 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1479                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1480                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1481
1482 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1483                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1484 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1485                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1486
1487 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1488                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1489 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1490                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1491
1492 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1493                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1494 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1495                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1496
1497 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1498 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1499
1500 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1501                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1502 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1503                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1504
1505 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1506                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1507 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1508                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1509 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1510                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1511                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1512 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1513                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1514                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1515
1516 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1517 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1518 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1519 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1520
1521 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1522 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1523 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1524
1525 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1526 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1527
1528 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1529
1530 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1531 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1532 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1533 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1534
1535 /* Power is done with the muxes since the ADC power also controls the
1536  * downsampling chain, the chip will automatically manage the analogue
1537  * specific portions.
1538  */
1539 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1540 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1541
1542 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1543 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1544
1545 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1546                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1547 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1548                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1549
1550 SND_SOC_DAPM_POST("Debug log", post_ev),
1551 };
1552
1553 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1554 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1555 };
1556
1557 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1558 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1559 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1560 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1561 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1562 };
1563
1564 static const struct snd_soc_dapm_route intercon[] = {
1565         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1566         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1567
1568         { "DSP1CLK", NULL, "CLK_SYS" },
1569         { "DSP2CLK", NULL, "CLK_SYS" },
1570         { "DSPINTCLK", NULL, "CLK_SYS" },
1571
1572         { "AIF1ADC1L", NULL, "AIF1CLK" },
1573         { "AIF1ADC1L", NULL, "DSP1CLK" },
1574         { "AIF1ADC1R", NULL, "AIF1CLK" },
1575         { "AIF1ADC1R", NULL, "DSP1CLK" },
1576         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1577
1578         { "AIF1DAC1L", NULL, "AIF1CLK" },
1579         { "AIF1DAC1L", NULL, "DSP1CLK" },
1580         { "AIF1DAC1R", NULL, "AIF1CLK" },
1581         { "AIF1DAC1R", NULL, "DSP1CLK" },
1582         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1583
1584         { "AIF1ADC2L", NULL, "AIF1CLK" },
1585         { "AIF1ADC2L", NULL, "DSP1CLK" },
1586         { "AIF1ADC2R", NULL, "AIF1CLK" },
1587         { "AIF1ADC2R", NULL, "DSP1CLK" },
1588         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1589
1590         { "AIF1DAC2L", NULL, "AIF1CLK" },
1591         { "AIF1DAC2L", NULL, "DSP1CLK" },
1592         { "AIF1DAC2R", NULL, "AIF1CLK" },
1593         { "AIF1DAC2R", NULL, "DSP1CLK" },
1594         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1595
1596         { "AIF2ADCL", NULL, "AIF2CLK" },
1597         { "AIF2ADCL", NULL, "DSP2CLK" },
1598         { "AIF2ADCR", NULL, "AIF2CLK" },
1599         { "AIF2ADCR", NULL, "DSP2CLK" },
1600         { "AIF2ADCR", NULL, "DSPINTCLK" },
1601
1602         { "AIF2DACL", NULL, "AIF2CLK" },
1603         { "AIF2DACL", NULL, "DSP2CLK" },
1604         { "AIF2DACR", NULL, "AIF2CLK" },
1605         { "AIF2DACR", NULL, "DSP2CLK" },
1606         { "AIF2DACR", NULL, "DSPINTCLK" },
1607
1608         { "DMIC1L", NULL, "DMIC1DAT" },
1609         { "DMIC1L", NULL, "CLK_SYS" },
1610         { "DMIC1R", NULL, "DMIC1DAT" },
1611         { "DMIC1R", NULL, "CLK_SYS" },
1612         { "DMIC2L", NULL, "DMIC2DAT" },
1613         { "DMIC2L", NULL, "CLK_SYS" },
1614         { "DMIC2R", NULL, "DMIC2DAT" },
1615         { "DMIC2R", NULL, "CLK_SYS" },
1616
1617         { "ADCL", NULL, "AIF1CLK" },
1618         { "ADCL", NULL, "DSP1CLK" },
1619         { "ADCL", NULL, "DSPINTCLK" },
1620
1621         { "ADCR", NULL, "AIF1CLK" },
1622         { "ADCR", NULL, "DSP1CLK" },
1623         { "ADCR", NULL, "DSPINTCLK" },
1624
1625         { "ADCL Mux", "ADC", "ADCL" },
1626         { "ADCL Mux", "DMIC", "DMIC1L" },
1627         { "ADCR Mux", "ADC", "ADCR" },
1628         { "ADCR Mux", "DMIC", "DMIC1R" },
1629
1630         { "DAC1L", NULL, "AIF1CLK" },
1631         { "DAC1L", NULL, "DSP1CLK" },
1632         { "DAC1L", NULL, "DSPINTCLK" },
1633
1634         { "DAC1R", NULL, "AIF1CLK" },
1635         { "DAC1R", NULL, "DSP1CLK" },
1636         { "DAC1R", NULL, "DSPINTCLK" },
1637
1638         { "DAC2L", NULL, "AIF2CLK" },
1639         { "DAC2L", NULL, "DSP2CLK" },
1640         { "DAC2L", NULL, "DSPINTCLK" },
1641
1642         { "DAC2R", NULL, "AIF2DACR" },
1643         { "DAC2R", NULL, "AIF2CLK" },
1644         { "DAC2R", NULL, "DSP2CLK" },
1645         { "DAC2R", NULL, "DSPINTCLK" },
1646
1647         { "TOCLK", NULL, "CLK_SYS" },
1648
1649         /* AIF1 outputs */
1650         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1651         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1652         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1653
1654         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1655         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1656         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1657
1658         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1659         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1660         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1661
1662         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1663         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1664         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1665
1666         /* Pin level routing for AIF3 */
1667         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1668         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1669         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1670         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1671
1672         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1673         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1674         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1675         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1676         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1677         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1678         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1679
1680         /* DAC1 inputs */
1681         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1682         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1683         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1684         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1685         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1686
1687         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1688         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1689         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1690         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1691         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1692
1693         /* DAC2/AIF2 outputs  */
1694         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1695         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1696         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1697         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1698         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1699         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1700
1701         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1702         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1703         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1704         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1705         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1706         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1707
1708         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1709         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1710         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1711         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1712
1713         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1714
1715         /* AIF3 output */
1716         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1717         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1718         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1719         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1720         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1721         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1722         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1723         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1724
1725         /* Sidetone */
1726         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1727         { "Left Sidetone", "DMIC2", "DMIC2L" },
1728         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1729         { "Right Sidetone", "DMIC2", "DMIC2R" },
1730
1731         /* Output stages */
1732         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1733         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1734
1735         { "SPKL", "DAC1 Switch", "DAC1L" },
1736         { "SPKL", "DAC2 Switch", "DAC2L" },
1737
1738         { "SPKR", "DAC1 Switch", "DAC1R" },
1739         { "SPKR", "DAC2 Switch", "DAC2R" },
1740
1741         { "Left Headphone Mux", "DAC", "DAC1L" },
1742         { "Right Headphone Mux", "DAC", "DAC1R" },
1743 };
1744
1745 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1746         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1747         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1748         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1749         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1750         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1751         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1752         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1753         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1754 };
1755
1756 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1757         { "DAC1L", NULL, "DAC1L Mixer" },
1758         { "DAC1R", NULL, "DAC1R Mixer" },
1759         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1760         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1761 };
1762
1763 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1764         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1765         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1766         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1767         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1768         { "MICBIAS", NULL, "CLK_SYS" },
1769         { "MICBIAS", NULL, "MICBIAS Supply" },
1770 };
1771
1772 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1773         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1774         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1775 };
1776
1777 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1778         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1779         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1780
1781         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1782         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1783         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1784         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1785
1786         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1787         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1788
1789         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1790 };
1791
1792 /* The size in bits of the FLL divide multiplied by 10
1793  * to allow rounding later */
1794 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1795
1796 struct fll_div {
1797         u16 outdiv;
1798         u16 n;
1799         u16 k;
1800         u16 clk_ref_div;
1801         u16 fll_fratio;
1802 };
1803
1804 static int wm8994_get_fll_config(struct fll_div *fll,
1805                                  int freq_in, int freq_out)
1806 {
1807         u64 Kpart;
1808         unsigned int K, Ndiv, Nmod;
1809
1810         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1811
1812         /* Scale the input frequency down to <= 13.5MHz */
1813         fll->clk_ref_div = 0;
1814         while (freq_in > 13500000) {
1815                 fll->clk_ref_div++;
1816                 freq_in /= 2;
1817
1818                 if (fll->clk_ref_div > 3)
1819                         return -EINVAL;
1820         }
1821         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1822
1823         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1824         fll->outdiv = 3;
1825         while (freq_out * (fll->outdiv + 1) < 90000000) {
1826                 fll->outdiv++;
1827                 if (fll->outdiv > 63)
1828                         return -EINVAL;
1829         }
1830         freq_out *= fll->outdiv + 1;
1831         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1832
1833         if (freq_in > 1000000) {
1834                 fll->fll_fratio = 0;
1835         } else if (freq_in > 256000) {
1836                 fll->fll_fratio = 1;
1837                 freq_in *= 2;
1838         } else if (freq_in > 128000) {
1839                 fll->fll_fratio = 2;
1840                 freq_in *= 4;
1841         } else if (freq_in > 64000) {
1842                 fll->fll_fratio = 3;
1843                 freq_in *= 8;
1844         } else {
1845                 fll->fll_fratio = 4;
1846                 freq_in *= 16;
1847         }
1848         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1849
1850         /* Now, calculate N.K */
1851         Ndiv = freq_out / freq_in;
1852
1853         fll->n = Ndiv;
1854         Nmod = freq_out % freq_in;
1855         pr_debug("Nmod=%d\n", Nmod);
1856
1857         /* Calculate fractional part - scale up so we can round. */
1858         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1859
1860         do_div(Kpart, freq_in);
1861
1862         K = Kpart & 0xFFFFFFFF;
1863
1864         if ((K % 10) >= 5)
1865                 K += 5;
1866
1867         /* Move down to proper range now rounding is done */
1868         fll->k = K / 10;
1869
1870         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1871
1872         return 0;
1873 }
1874
1875 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1876                           unsigned int freq_in, unsigned int freq_out)
1877 {
1878         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1879         int reg_offset, ret;
1880         struct fll_div fll;
1881         u16 reg, aif1, aif2;
1882
1883         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1884                 & WM8994_AIF1CLK_ENA;
1885
1886         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1887                 & WM8994_AIF2CLK_ENA;
1888
1889         switch (id) {
1890         case WM8994_FLL1:
1891                 reg_offset = 0;
1892                 id = 0;
1893                 break;
1894         case WM8994_FLL2:
1895                 reg_offset = 0x20;
1896                 id = 1;
1897                 break;
1898         default:
1899                 return -EINVAL;
1900         }
1901
1902         switch (src) {
1903         case 0:
1904                 /* Allow no source specification when stopping */
1905                 if (freq_out)
1906                         return -EINVAL;
1907                 src = wm8994->fll[id].src;
1908                 break;
1909         case WM8994_FLL_SRC_MCLK1:
1910         case WM8994_FLL_SRC_MCLK2:
1911         case WM8994_FLL_SRC_LRCLK:
1912         case WM8994_FLL_SRC_BCLK:
1913                 break;
1914         default:
1915                 return -EINVAL;
1916         }
1917
1918         /* Are we changing anything? */
1919         if (wm8994->fll[id].src == src &&
1920             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1921                 return 0;
1922
1923         /* If we're stopping the FLL redo the old config - no
1924          * registers will actually be written but we avoid GCC flow
1925          * analysis bugs spewing warnings.
1926          */
1927         if (freq_out)
1928                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1929         else
1930                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1931                                             wm8994->fll[id].out);
1932         if (ret < 0)
1933                 return ret;
1934
1935         /* Gate the AIF clocks while we reclock */
1936         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1937                             WM8994_AIF1CLK_ENA, 0);
1938         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1939                             WM8994_AIF2CLK_ENA, 0);
1940
1941         /* We always need to disable the FLL while reconfiguring */
1942         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1943                             WM8994_FLL1_ENA, 0);
1944
1945         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1946                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1947         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1948                             WM8994_FLL1_OUTDIV_MASK |
1949                             WM8994_FLL1_FRATIO_MASK, reg);
1950
1951         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1952
1953         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1954                             WM8994_FLL1_N_MASK,
1955                                     fll.n << WM8994_FLL1_N_SHIFT);
1956
1957         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1958                             WM8994_FLL1_REFCLK_DIV_MASK |
1959                             WM8994_FLL1_REFCLK_SRC_MASK,
1960                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1961                             (src - 1));
1962
1963         /* Enable (with fractional mode if required) */
1964         if (freq_out) {
1965                 if (fll.k)
1966                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1967                 else
1968                         reg = WM8994_FLL1_ENA;
1969                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1970                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1971                                     reg);
1972         }
1973
1974         wm8994->fll[id].in = freq_in;
1975         wm8994->fll[id].out = freq_out;
1976         wm8994->fll[id].src = src;
1977
1978         /* Enable any gated AIF clocks */
1979         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1980                             WM8994_AIF1CLK_ENA, aif1);
1981         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1982                             WM8994_AIF2CLK_ENA, aif2);
1983
1984         configure_clock(codec);
1985
1986         return 0;
1987 }
1988
1989
1990 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1991
1992 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1993                           unsigned int freq_in, unsigned int freq_out)
1994 {
1995         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1996 }
1997
1998 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1999                 int clk_id, unsigned int freq, int dir)
2000 {
2001         struct snd_soc_codec *codec = dai->codec;
2002         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2003         int i;
2004
2005         switch (dai->id) {
2006         case 1:
2007         case 2:
2008                 break;
2009
2010         default:
2011                 /* AIF3 shares clocking with AIF1/2 */
2012                 return -EINVAL;
2013         }
2014
2015         switch (clk_id) {
2016         case WM8994_SYSCLK_MCLK1:
2017                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2018                 wm8994->mclk[0] = freq;
2019                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2020                         dai->id, freq);
2021                 break;
2022
2023         case WM8994_SYSCLK_MCLK2:
2024                 /* TODO: Set GPIO AF */
2025                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2026                 wm8994->mclk[1] = freq;
2027                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2028                         dai->id, freq);
2029                 break;
2030
2031         case WM8994_SYSCLK_FLL1:
2032                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2033                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2034                 break;
2035
2036         case WM8994_SYSCLK_FLL2:
2037                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2038                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2039                 break;
2040
2041         case WM8994_SYSCLK_OPCLK:
2042                 /* Special case - a division (times 10) is given and
2043                  * no effect on main clocking.
2044                  */
2045                 if (freq) {
2046                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2047                                 if (opclk_divs[i] == freq)
2048                                         break;
2049                         if (i == ARRAY_SIZE(opclk_divs))
2050                                 return -EINVAL;
2051                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2052                                             WM8994_OPCLK_DIV_MASK, i);
2053                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2054                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2055                 } else {
2056                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2057                                             WM8994_OPCLK_ENA, 0);
2058                 }
2059
2060         default:
2061                 return -EINVAL;
2062         }
2063
2064         configure_clock(codec);
2065
2066         return 0;
2067 }
2068
2069 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2070                                  enum snd_soc_bias_level level)
2071 {
2072         struct wm8994 *control = codec->control_data;
2073         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2074
2075         switch (level) {
2076         case SND_SOC_BIAS_ON:
2077                 break;
2078
2079         case SND_SOC_BIAS_PREPARE:
2080                 /* VMID=2x40k */
2081                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2082                                     WM8994_VMID_SEL_MASK, 0x2);
2083                 break;
2084
2085         case SND_SOC_BIAS_STANDBY:
2086                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2087                         pm_runtime_get_sync(codec->dev);
2088
2089                         switch (control->type) {
2090                         case WM8994:
2091                                 if (wm8994->revision < 4) {
2092                                         /* Tweak DC servo and DSP
2093                                          * configuration for improved
2094                                          * performance. */
2095                                         snd_soc_write(codec, 0x102, 0x3);
2096                                         snd_soc_write(codec, 0x56, 0x3);
2097                                         snd_soc_write(codec, 0x817, 0);
2098                                         snd_soc_write(codec, 0x102, 0);
2099                                 }
2100                                 break;
2101
2102                         case WM8958:
2103                                 if (wm8994->revision == 0) {
2104                                         /* Optimise performance for rev A */
2105                                         snd_soc_write(codec, 0x102, 0x3);
2106                                         snd_soc_write(codec, 0xcb, 0x81);
2107                                         snd_soc_write(codec, 0x817, 0);
2108                                         snd_soc_write(codec, 0x102, 0);
2109
2110                                         snd_soc_update_bits(codec,
2111                                                             WM8958_CHARGE_PUMP_2,
2112                                                             WM8958_CP_DISCH,
2113                                                             WM8958_CP_DISCH);
2114                                 }
2115                                 break;
2116                         }
2117
2118                         /* Discharge LINEOUT1 & 2 */
2119                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2120                                             WM8994_LINEOUT1_DISCH |
2121                                             WM8994_LINEOUT2_DISCH,
2122                                             WM8994_LINEOUT1_DISCH |
2123                                             WM8994_LINEOUT2_DISCH);
2124
2125                         /* Startup bias, VMID ramp & buffer */
2126                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2127                                             WM8994_STARTUP_BIAS_ENA |
2128                                             WM8994_VMID_BUF_ENA |
2129                                             WM8994_VMID_RAMP_MASK,
2130                                             WM8994_STARTUP_BIAS_ENA |
2131                                             WM8994_VMID_BUF_ENA |
2132                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
2133
2134                         /* Main bias enable, VMID=2x40k */
2135                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2136                                             WM8994_BIAS_ENA |
2137                                             WM8994_VMID_SEL_MASK,
2138                                             WM8994_BIAS_ENA | 0x2);
2139
2140                         msleep(20);
2141                 }
2142
2143                 /* VMID=2x500k */
2144                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2145                                     WM8994_VMID_SEL_MASK, 0x4);
2146
2147                 break;
2148
2149         case SND_SOC_BIAS_OFF:
2150                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2151                         /* Switch over to startup biases */
2152                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2153                                             WM8994_BIAS_SRC |
2154                                             WM8994_STARTUP_BIAS_ENA |
2155                                             WM8994_VMID_BUF_ENA |
2156                                             WM8994_VMID_RAMP_MASK,
2157                                             WM8994_BIAS_SRC |
2158                                             WM8994_STARTUP_BIAS_ENA |
2159                                             WM8994_VMID_BUF_ENA |
2160                                             (1 << WM8994_VMID_RAMP_SHIFT));
2161
2162                         /* Disable main biases */
2163                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2164                                             WM8994_BIAS_ENA |
2165                                             WM8994_VMID_SEL_MASK, 0);
2166
2167                         /* Discharge line */
2168                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2169                                             WM8994_LINEOUT1_DISCH |
2170                                             WM8994_LINEOUT2_DISCH,
2171                                             WM8994_LINEOUT1_DISCH |
2172                                             WM8994_LINEOUT2_DISCH);
2173
2174                         msleep(5);
2175
2176                         /* Switch off startup biases */
2177                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2178                                             WM8994_BIAS_SRC |
2179                                             WM8994_STARTUP_BIAS_ENA |
2180                                             WM8994_VMID_BUF_ENA |
2181                                             WM8994_VMID_RAMP_MASK, 0);
2182
2183                         pm_runtime_put(codec->dev);
2184                 }
2185                 break;
2186         }
2187         codec->dapm.bias_level = level;
2188         return 0;
2189 }
2190
2191 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2192 {
2193         struct snd_soc_codec *codec = dai->codec;
2194         struct wm8994 *control = codec->control_data;
2195         int ms_reg;
2196         int aif1_reg;
2197         int ms = 0;
2198         int aif1 = 0;
2199
2200         switch (dai->id) {
2201         case 1:
2202                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2203                 aif1_reg = WM8994_AIF1_CONTROL_1;
2204                 break;
2205         case 2:
2206                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2207                 aif1_reg = WM8994_AIF2_CONTROL_1;
2208                 break;
2209         default:
2210                 return -EINVAL;
2211         }
2212
2213         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2214         case SND_SOC_DAIFMT_CBS_CFS:
2215                 break;
2216         case SND_SOC_DAIFMT_CBM_CFM:
2217                 ms = WM8994_AIF1_MSTR;
2218                 break;
2219         default:
2220                 return -EINVAL;
2221         }
2222
2223         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2224         case SND_SOC_DAIFMT_DSP_B:
2225                 aif1 |= WM8994_AIF1_LRCLK_INV;
2226         case SND_SOC_DAIFMT_DSP_A:
2227                 aif1 |= 0x18;
2228                 break;
2229         case SND_SOC_DAIFMT_I2S:
2230                 aif1 |= 0x10;
2231                 break;
2232         case SND_SOC_DAIFMT_RIGHT_J:
2233                 break;
2234         case SND_SOC_DAIFMT_LEFT_J:
2235                 aif1 |= 0x8;
2236                 break;
2237         default:
2238                 return -EINVAL;
2239         }
2240
2241         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2242         case SND_SOC_DAIFMT_DSP_A:
2243         case SND_SOC_DAIFMT_DSP_B:
2244                 /* frame inversion not valid for DSP modes */
2245                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2246                 case SND_SOC_DAIFMT_NB_NF:
2247                         break;
2248                 case SND_SOC_DAIFMT_IB_NF:
2249                         aif1 |= WM8994_AIF1_BCLK_INV;
2250                         break;
2251                 default:
2252                         return -EINVAL;
2253                 }
2254                 break;
2255
2256         case SND_SOC_DAIFMT_I2S:
2257         case SND_SOC_DAIFMT_RIGHT_J:
2258         case SND_SOC_DAIFMT_LEFT_J:
2259                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2260                 case SND_SOC_DAIFMT_NB_NF:
2261                         break;
2262                 case SND_SOC_DAIFMT_IB_IF:
2263                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2264                         break;
2265                 case SND_SOC_DAIFMT_IB_NF:
2266                         aif1 |= WM8994_AIF1_BCLK_INV;
2267                         break;
2268                 case SND_SOC_DAIFMT_NB_IF:
2269                         aif1 |= WM8994_AIF1_LRCLK_INV;
2270                         break;
2271                 default:
2272                         return -EINVAL;
2273                 }
2274                 break;
2275         default:
2276                 return -EINVAL;
2277         }
2278
2279         /* The AIF2 format configuration needs to be mirrored to AIF3
2280          * on WM8958 if it's in use so just do it all the time. */
2281         if (control->type == WM8958 && dai->id == 2)
2282                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2283                                     WM8994_AIF1_LRCLK_INV |
2284                                     WM8958_AIF3_FMT_MASK, aif1);
2285
2286         snd_soc_update_bits(codec, aif1_reg,
2287                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2288                             WM8994_AIF1_FMT_MASK,
2289                             aif1);
2290         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2291                             ms);
2292
2293         return 0;
2294 }
2295
2296 static struct {
2297         int val, rate;
2298 } srs[] = {
2299         { 0,   8000 },
2300         { 1,  11025 },
2301         { 2,  12000 },
2302         { 3,  16000 },
2303         { 4,  22050 },
2304         { 5,  24000 },
2305         { 6,  32000 },
2306         { 7,  44100 },
2307         { 8,  48000 },
2308         { 9,  88200 },
2309         { 10, 96000 },
2310 };
2311
2312 static int fs_ratios[] = {
2313         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2314 };
2315
2316 static int bclk_divs[] = {
2317         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2318         640, 880, 960, 1280, 1760, 1920
2319 };
2320
2321 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2322                             struct snd_pcm_hw_params *params,
2323                             struct snd_soc_dai *dai)
2324 {
2325         struct snd_soc_codec *codec = dai->codec;
2326         struct wm8994 *control = codec->control_data;
2327         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2328         int aif1_reg;
2329         int aif2_reg;
2330         int bclk_reg;
2331         int lrclk_reg;
2332         int rate_reg;
2333         int aif1 = 0;
2334         int aif2 = 0;
2335         int bclk = 0;
2336         int lrclk = 0;
2337         int rate_val = 0;
2338         int id = dai->id - 1;
2339
2340         int i, cur_val, best_val, bclk_rate, best;
2341
2342         switch (dai->id) {
2343         case 1:
2344                 aif1_reg = WM8994_AIF1_CONTROL_1;
2345                 aif2_reg = WM8994_AIF1_CONTROL_2;
2346                 bclk_reg = WM8994_AIF1_BCLK;
2347                 rate_reg = WM8994_AIF1_RATE;
2348                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2349                     wm8994->lrclk_shared[0]) {
2350                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2351                 } else {
2352                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2353                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2354                 }
2355                 break;
2356         case 2:
2357                 aif1_reg = WM8994_AIF2_CONTROL_1;
2358                 aif2_reg = WM8994_AIF2_CONTROL_2;
2359                 bclk_reg = WM8994_AIF2_BCLK;
2360                 rate_reg = WM8994_AIF2_RATE;
2361                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2362                     wm8994->lrclk_shared[1]) {
2363                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2364                 } else {
2365                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2366                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2367                 }
2368                 break;
2369         case 3:
2370                 switch (control->type) {
2371                 case WM8958:
2372                         aif1_reg = WM8958_AIF3_CONTROL_1;
2373                         break;
2374                 default:
2375                         return 0;
2376                 }
2377         default:
2378                 return -EINVAL;
2379         }
2380
2381         bclk_rate = params_rate(params) * 2;
2382         switch (params_format(params)) {
2383         case SNDRV_PCM_FORMAT_S16_LE:
2384                 bclk_rate *= 16;
2385                 break;
2386         case SNDRV_PCM_FORMAT_S20_3LE:
2387                 bclk_rate *= 20;
2388                 aif1 |= 0x20;
2389                 break;
2390         case SNDRV_PCM_FORMAT_S24_LE:
2391                 bclk_rate *= 24;
2392                 aif1 |= 0x40;
2393                 break;
2394         case SNDRV_PCM_FORMAT_S32_LE:
2395                 bclk_rate *= 32;
2396                 aif1 |= 0x60;
2397                 break;
2398         default:
2399                 return -EINVAL;
2400         }
2401
2402         /* Try to find an appropriate sample rate; look for an exact match. */
2403         for (i = 0; i < ARRAY_SIZE(srs); i++)
2404                 if (srs[i].rate == params_rate(params))
2405                         break;
2406         if (i == ARRAY_SIZE(srs))
2407                 return -EINVAL;
2408         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2409
2410         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2411         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2412                 dai->id, wm8994->aifclk[id], bclk_rate);
2413
2414         if (params_channels(params) == 1 &&
2415             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2416                 aif2 |= WM8994_AIF1_MONO;
2417
2418         if (wm8994->aifclk[id] == 0) {
2419                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2420                 return -EINVAL;
2421         }
2422
2423         /* AIFCLK/fs ratio; look for a close match in either direction */
2424         best = 0;
2425         best_val = abs((fs_ratios[0] * params_rate(params))
2426                        - wm8994->aifclk[id]);
2427         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2428                 cur_val = abs((fs_ratios[i] * params_rate(params))
2429                               - wm8994->aifclk[id]);
2430                 if (cur_val >= best_val)
2431                         continue;
2432                 best = i;
2433                 best_val = cur_val;
2434         }
2435         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2436                 dai->id, fs_ratios[best]);
2437         rate_val |= best;
2438
2439         /* We may not get quite the right frequency if using
2440          * approximate clocks so look for the closest match that is
2441          * higher than the target (we need to ensure that there enough
2442          * BCLKs to clock out the samples).
2443          */
2444         best = 0;
2445         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2446                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2447                 if (cur_val < 0) /* BCLK table is sorted */
2448                         break;
2449                 best = i;
2450         }
2451         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2452         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2453                 bclk_divs[best], bclk_rate);
2454         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2455
2456         lrclk = bclk_rate / params_rate(params);
2457         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2458                 lrclk, bclk_rate / lrclk);
2459
2460         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2461         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2462         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2463         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2464                             lrclk);
2465         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2466                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2467
2468         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2469                 switch (dai->id) {
2470                 case 1:
2471                         wm8994->dac_rates[0] = params_rate(params);
2472                         wm8994_set_retune_mobile(codec, 0);
2473                         wm8994_set_retune_mobile(codec, 1);
2474                         break;
2475                 case 2:
2476                         wm8994->dac_rates[1] = params_rate(params);
2477                         wm8994_set_retune_mobile(codec, 2);
2478                         break;
2479                 }
2480         }
2481
2482         return 0;
2483 }
2484
2485 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2486                                  struct snd_pcm_hw_params *params,
2487                                  struct snd_soc_dai *dai)
2488 {
2489         struct snd_soc_codec *codec = dai->codec;
2490         struct wm8994 *control = codec->control_data;
2491         int aif1_reg;
2492         int aif1 = 0;
2493
2494         switch (dai->id) {
2495         case 3:
2496                 switch (control->type) {
2497                 case WM8958:
2498                         aif1_reg = WM8958_AIF3_CONTROL_1;
2499                         break;
2500                 default:
2501                         return 0;
2502                 }
2503         default:
2504                 return 0;
2505         }
2506
2507         switch (params_format(params)) {
2508         case SNDRV_PCM_FORMAT_S16_LE:
2509                 break;
2510         case SNDRV_PCM_FORMAT_S20_3LE:
2511                 aif1 |= 0x20;
2512                 break;
2513         case SNDRV_PCM_FORMAT_S24_LE:
2514                 aif1 |= 0x40;
2515                 break;
2516         case SNDRV_PCM_FORMAT_S32_LE:
2517                 aif1 |= 0x60;
2518                 break;
2519         default:
2520                 return -EINVAL;
2521         }
2522
2523         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2524 }
2525
2526 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2527 {
2528         struct snd_soc_codec *codec = codec_dai->codec;
2529         int mute_reg;
2530         int reg;
2531
2532         switch (codec_dai->id) {
2533         case 1:
2534                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2535                 break;
2536         case 2:
2537                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2538                 break;
2539         default:
2540                 return -EINVAL;
2541         }
2542
2543         if (mute)
2544                 reg = WM8994_AIF1DAC1_MUTE;
2545         else
2546                 reg = 0;
2547
2548         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2549
2550         return 0;
2551 }
2552
2553 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2554 {
2555         struct snd_soc_codec *codec = codec_dai->codec;
2556         int reg, val, mask;
2557
2558         switch (codec_dai->id) {
2559         case 1:
2560                 reg = WM8994_AIF1_MASTER_SLAVE;
2561                 mask = WM8994_AIF1_TRI;
2562                 break;
2563         case 2:
2564                 reg = WM8994_AIF2_MASTER_SLAVE;
2565                 mask = WM8994_AIF2_TRI;
2566                 break;
2567         case 3:
2568                 reg = WM8994_POWER_MANAGEMENT_6;
2569                 mask = WM8994_AIF3_TRI;
2570                 break;
2571         default:
2572                 return -EINVAL;
2573         }
2574
2575         if (tristate)
2576                 val = mask;
2577         else
2578                 val = 0;
2579
2580         return snd_soc_update_bits(codec, reg, mask, val);
2581 }
2582
2583 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2584
2585 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2586                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2587
2588 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2589         .set_sysclk     = wm8994_set_dai_sysclk,
2590         .set_fmt        = wm8994_set_dai_fmt,
2591         .hw_params      = wm8994_hw_params,
2592         .digital_mute   = wm8994_aif_mute,
2593         .set_pll        = wm8994_set_fll,
2594         .set_tristate   = wm8994_set_tristate,
2595 };
2596
2597 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2598         .set_sysclk     = wm8994_set_dai_sysclk,
2599         .set_fmt        = wm8994_set_dai_fmt,
2600         .hw_params      = wm8994_hw_params,
2601         .digital_mute   = wm8994_aif_mute,
2602         .set_pll        = wm8994_set_fll,
2603         .set_tristate   = wm8994_set_tristate,
2604 };
2605
2606 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2607         .hw_params      = wm8994_aif3_hw_params,
2608         .set_tristate   = wm8994_set_tristate,
2609 };
2610
2611 static struct snd_soc_dai_driver wm8994_dai[] = {
2612         {
2613                 .name = "wm8994-aif1",
2614                 .id = 1,
2615                 .playback = {
2616                         .stream_name = "AIF1 Playback",
2617                         .channels_min = 1,
2618                         .channels_max = 2,
2619                         .rates = WM8994_RATES,
2620                         .formats = WM8994_FORMATS,
2621                 },
2622                 .capture = {
2623                         .stream_name = "AIF1 Capture",
2624                         .channels_min = 1,
2625                         .channels_max = 2,
2626                         .rates = WM8994_RATES,
2627                         .formats = WM8994_FORMATS,
2628                  },
2629                 .ops = &wm8994_aif1_dai_ops,
2630         },
2631         {
2632                 .name = "wm8994-aif2",
2633                 .id = 2,
2634                 .playback = {
2635                         .stream_name = "AIF2 Playback",
2636                         .channels_min = 1,
2637                         .channels_max = 2,
2638                         .rates = WM8994_RATES,
2639                         .formats = WM8994_FORMATS,
2640                 },
2641                 .capture = {
2642                         .stream_name = "AIF2 Capture",
2643                         .channels_min = 1,
2644                         .channels_max = 2,
2645                         .rates = WM8994_RATES,
2646                         .formats = WM8994_FORMATS,
2647                 },
2648                 .ops = &wm8994_aif2_dai_ops,
2649         },
2650         {
2651                 .name = "wm8994-aif3",
2652                 .id = 3,
2653                 .playback = {
2654                         .stream_name = "AIF3 Playback",
2655                         .channels_min = 1,
2656                         .channels_max = 2,
2657                         .rates = WM8994_RATES,
2658                         .formats = WM8994_FORMATS,
2659                 },
2660                 .capture = {
2661                         .stream_name = "AIF3 Capture",
2662                         .channels_min = 1,
2663                         .channels_max = 2,
2664                         .rates = WM8994_RATES,
2665                         .formats = WM8994_FORMATS,
2666                 },
2667                 .ops = &wm8994_aif3_dai_ops,
2668         }
2669 };
2670
2671 #ifdef CONFIG_PM
2672 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2673 {
2674         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2675         int i, ret;
2676
2677         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2678                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2679                        sizeof(struct fll_config));
2680                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2681                 if (ret < 0)
2682                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2683                                  i + 1, ret);
2684         }
2685
2686         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2687
2688         return 0;
2689 }
2690
2691 static int wm8994_resume(struct snd_soc_codec *codec)
2692 {
2693         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2694         int i, ret;
2695         unsigned int val, mask;
2696
2697         if (wm8994->revision < 4) {
2698                 /* force a HW read */
2699                 val = wm8994_reg_read(codec->control_data,
2700                                       WM8994_POWER_MANAGEMENT_5);
2701
2702                 /* modify the cache only */
2703                 codec->cache_only = 1;
2704                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2705                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2706                 val &= mask;
2707                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2708                                     mask, val);
2709                 codec->cache_only = 0;
2710         }
2711
2712         /* Restore the registers */
2713         ret = snd_soc_cache_sync(codec);
2714         if (ret != 0)
2715                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2716
2717         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2718
2719         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2720                 if (!wm8994->fll_suspend[i].out)
2721                         continue;
2722
2723                 ret = _wm8994_set_fll(codec, i + 1,
2724                                      wm8994->fll_suspend[i].src,
2725                                      wm8994->fll_suspend[i].in,
2726                                      wm8994->fll_suspend[i].out);
2727                 if (ret < 0)
2728                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2729                                  i + 1, ret);
2730         }
2731
2732         return 0;
2733 }
2734 #else
2735 #define wm8994_suspend NULL
2736 #define wm8994_resume NULL
2737 #endif
2738
2739 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2740 {
2741         struct snd_soc_codec *codec = wm8994->codec;
2742         struct wm8994_pdata *pdata = wm8994->pdata;
2743         struct snd_kcontrol_new controls[] = {
2744                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2745                              wm8994->retune_mobile_enum,
2746                              wm8994_get_retune_mobile_enum,
2747                              wm8994_put_retune_mobile_enum),
2748                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2749                              wm8994->retune_mobile_enum,
2750                              wm8994_get_retune_mobile_enum,
2751                              wm8994_put_retune_mobile_enum),
2752                 SOC_ENUM_EXT("AIF2 EQ Mode",
2753                              wm8994->retune_mobile_enum,
2754                              wm8994_get_retune_mobile_enum,
2755                              wm8994_put_retune_mobile_enum),
2756         };
2757         int ret, i, j;
2758         const char **t;
2759
2760         /* We need an array of texts for the enum API but the number
2761          * of texts is likely to be less than the number of
2762          * configurations due to the sample rate dependency of the
2763          * configurations. */
2764         wm8994->num_retune_mobile_texts = 0;
2765         wm8994->retune_mobile_texts = NULL;
2766         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2767                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2768                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2769                                    wm8994->retune_mobile_texts[j]) == 0)
2770                                 break;
2771                 }
2772
2773                 if (j != wm8994->num_retune_mobile_texts)
2774                         continue;
2775
2776                 /* Expand the array... */
2777                 t = krealloc(wm8994->retune_mobile_texts,
2778                              sizeof(char *) *
2779                              (wm8994->num_retune_mobile_texts + 1),
2780                              GFP_KERNEL);
2781                 if (t == NULL)
2782                         continue;
2783
2784                 /* ...store the new entry... */
2785                 t[wm8994->num_retune_mobile_texts] =
2786                         pdata->retune_mobile_cfgs[i].name;
2787
2788                 /* ...and remember the new version. */
2789                 wm8994->num_retune_mobile_texts++;
2790                 wm8994->retune_mobile_texts = t;
2791         }
2792
2793         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2794                 wm8994->num_retune_mobile_texts);
2795
2796         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2797         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2798
2799         ret = snd_soc_add_controls(wm8994->codec, controls,
2800                                    ARRAY_SIZE(controls));
2801         if (ret != 0)
2802                 dev_err(wm8994->codec->dev,
2803                         "Failed to add ReTune Mobile controls: %d\n", ret);
2804 }
2805
2806 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2807 {
2808         struct snd_soc_codec *codec = wm8994->codec;
2809         struct wm8994_pdata *pdata = wm8994->pdata;
2810         int ret, i;
2811
2812         if (!pdata)
2813                 return;
2814
2815         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2816                                       pdata->lineout2_diff,
2817                                       pdata->lineout1fb,
2818                                       pdata->lineout2fb,
2819                                       pdata->jd_scthr,
2820                                       pdata->jd_thr,
2821                                       pdata->micbias1_lvl,
2822                                       pdata->micbias2_lvl);
2823
2824         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2825
2826         if (pdata->num_drc_cfgs) {
2827                 struct snd_kcontrol_new controls[] = {
2828                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2829                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2830                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2831                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2832                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2833                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2834                 };
2835
2836                 /* We need an array of texts for the enum API */
2837                 wm8994->drc_texts = kmalloc(sizeof(char *)
2838                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2839                 if (!wm8994->drc_texts) {
2840                         dev_err(wm8994->codec->dev,
2841                                 "Failed to allocate %d DRC config texts\n",
2842                                 pdata->num_drc_cfgs);
2843                         return;
2844                 }
2845
2846                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2847                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2848
2849                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2850                 wm8994->drc_enum.texts = wm8994->drc_texts;
2851
2852                 ret = snd_soc_add_controls(wm8994->codec, controls,
2853                                            ARRAY_SIZE(controls));
2854                 if (ret != 0)
2855                         dev_err(wm8994->codec->dev,
2856                                 "Failed to add DRC mode controls: %d\n", ret);
2857
2858                 for (i = 0; i < WM8994_NUM_DRC; i++)
2859                         wm8994_set_drc(codec, i);
2860         }
2861
2862         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2863                 pdata->num_retune_mobile_cfgs);
2864
2865         if (pdata->num_mbc_cfgs) {
2866                 struct snd_kcontrol_new control[] = {
2867                         SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2868                                      wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2869                 };
2870
2871                 /* We need an array of texts for the enum API */
2872                 wm8994->mbc_texts = kmalloc(sizeof(char *)
2873                                             * pdata->num_mbc_cfgs, GFP_KERNEL);
2874                 if (!wm8994->mbc_texts) {
2875                         dev_err(wm8994->codec->dev,
2876                                 "Failed to allocate %d MBC config texts\n",
2877                                 pdata->num_mbc_cfgs);
2878                         return;
2879                 }
2880
2881                 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2882                         wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2883
2884                 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2885                 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2886
2887                 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2888                 if (ret != 0)
2889                         dev_err(wm8994->codec->dev,
2890                                 "Failed to add MBC mode controls: %d\n", ret);
2891         }
2892
2893         if (pdata->num_retune_mobile_cfgs)
2894                 wm8994_handle_retune_mobile_pdata(wm8994);
2895         else
2896                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2897                                      ARRAY_SIZE(wm8994_eq_controls));
2898
2899         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2900                 if (pdata->micbias[i]) {
2901                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2902                                 pdata->micbias[i] & 0xffff);
2903                 }
2904         }
2905 }
2906
2907 /**
2908  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2909  *
2910  * @codec:   WM8994 codec
2911  * @jack:    jack to report detection events on
2912  * @micbias: microphone bias to detect on
2913  * @det:     value to report for presence detection
2914  * @shrt:    value to report for short detection
2915  *
2916  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2917  * being used to bring out signals to the processor then only platform
2918  * data configuration is needed for WM8994 and processor GPIOs should
2919  * be configured using snd_soc_jack_add_gpios() instead.
2920  *
2921  * Configuration of detection levels is available via the micbias1_lvl
2922  * and micbias2_lvl platform data members.
2923  */
2924 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2925                       int micbias, int det, int shrt)
2926 {
2927         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2928         struct wm8994_micdet *micdet;
2929         struct wm8994 *control = codec->control_data;
2930         int reg;
2931
2932         if (control->type != WM8994)
2933                 return -EINVAL;
2934
2935         switch (micbias) {
2936         case 1:
2937                 micdet = &wm8994->micdet[0];
2938                 break;
2939         case 2:
2940                 micdet = &wm8994->micdet[1];
2941                 break;
2942         default:
2943                 return -EINVAL;
2944         }
2945
2946         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2947                 micbias, det, shrt);
2948
2949         /* Store the configuration */
2950         micdet->jack = jack;
2951         micdet->det = det;
2952         micdet->shrt = shrt;
2953
2954         /* If either of the jacks is set up then enable detection */
2955         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2956                 reg = WM8994_MICD_ENA;
2957         else
2958                 reg = 0;
2959
2960         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2961
2962         return 0;
2963 }
2964 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2965
2966 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2967 {
2968         struct wm8994_priv *priv = data;
2969         struct snd_soc_codec *codec = priv->codec;
2970         int reg;
2971         int report;
2972
2973 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2974         trace_snd_soc_jack_irq(dev_name(codec->dev));
2975 #endif
2976
2977         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2978         if (reg < 0) {
2979                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2980                         reg);
2981                 return IRQ_HANDLED;
2982         }
2983
2984         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2985
2986         report = 0;
2987         if (reg & WM8994_MIC1_DET_STS)
2988                 report |= priv->micdet[0].det;
2989         if (reg & WM8994_MIC1_SHRT_STS)
2990                 report |= priv->micdet[0].shrt;
2991         snd_soc_jack_report(priv->micdet[0].jack, report,
2992                             priv->micdet[0].det | priv->micdet[0].shrt);
2993
2994         report = 0;
2995         if (reg & WM8994_MIC2_DET_STS)
2996                 report |= priv->micdet[1].det;
2997         if (reg & WM8994_MIC2_SHRT_STS)
2998                 report |= priv->micdet[1].shrt;
2999         snd_soc_jack_report(priv->micdet[1].jack, report,
3000                             priv->micdet[1].det | priv->micdet[1].shrt);
3001
3002         return IRQ_HANDLED;
3003 }
3004
3005 /* Default microphone detection handler for WM8958 - the user can
3006  * override this if they wish.
3007  */
3008 static void wm8958_default_micdet(u16 status, void *data)
3009 {
3010         struct snd_soc_codec *codec = data;
3011         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3012         int report = 0;
3013
3014         /* If nothing present then clear our statuses */
3015         if (!(status & WM8958_MICD_STS))
3016                 goto done;
3017
3018         report = SND_JACK_MICROPHONE;
3019
3020         /* Everything else is buttons; just assign slots */
3021         if (status & 0x1c0)
3022                 report |= SND_JACK_BTN_0;
3023
3024 done:
3025         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3026                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
3027 }
3028
3029 /**
3030  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3031  *
3032  * @codec:   WM8958 codec
3033  * @jack:    jack to report detection events on
3034  *
3035  * Enable microphone detection functionality for the WM8958.  By
3036  * default simple detection which supports the detection of up to 6
3037  * buttons plus video and microphone functionality is supported.
3038  *
3039  * The WM8958 has an advanced jack detection facility which is able to
3040  * support complex accessory detection, especially when used in
3041  * conjunction with external circuitry.  In order to provide maximum
3042  * flexiblity a callback is provided which allows a completely custom
3043  * detection algorithm.
3044  */
3045 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3046                       wm8958_micdet_cb cb, void *cb_data)
3047 {
3048         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3049         struct wm8994 *control = codec->control_data;
3050
3051         if (control->type != WM8958)
3052                 return -EINVAL;
3053
3054         if (jack) {
3055                 if (!cb) {
3056                         dev_dbg(codec->dev, "Using default micdet callback\n");
3057                         cb = wm8958_default_micdet;
3058                         cb_data = codec;
3059                 }
3060
3061                 wm8994->micdet[0].jack = jack;
3062                 wm8994->jack_cb = cb;
3063                 wm8994->jack_cb_data = cb_data;
3064
3065                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3066                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3067         } else {
3068                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3069                                     WM8958_MICD_ENA, 0);
3070         }
3071
3072         return 0;
3073 }
3074 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3075
3076 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3077 {
3078         struct wm8994_priv *wm8994 = data;
3079         struct snd_soc_codec *codec = wm8994->codec;
3080         int reg;
3081
3082         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3083         if (reg < 0) {
3084                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3085                         reg);
3086                 return IRQ_NONE;
3087         }
3088
3089         if (!(reg & WM8958_MICD_VALID)) {
3090                 dev_dbg(codec->dev, "Mic detect data not valid\n");
3091                 goto out;
3092         }
3093
3094 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3095         trace_snd_soc_jack_irq(dev_name(codec->dev));
3096 #endif
3097
3098         if (wm8994->jack_cb)
3099                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3100         else
3101                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3102
3103 out:
3104         return IRQ_HANDLED;
3105 }
3106
3107 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3108 {
3109         struct wm8994 *control;
3110         struct wm8994_priv *wm8994;
3111         struct snd_soc_dapm_context *dapm = &codec->dapm;
3112         int ret, i;
3113
3114         codec->control_data = dev_get_drvdata(codec->dev->parent);
3115         control = codec->control_data;
3116
3117         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3118         if (wm8994 == NULL)
3119                 return -ENOMEM;
3120         snd_soc_codec_set_drvdata(codec, wm8994);
3121
3122         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3123         wm8994->codec = codec;
3124
3125         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3126                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3127         else if (wm8994->pdata && wm8994->pdata->irq_base)
3128                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3129                                      WM8994_IRQ_MIC1_DET;
3130
3131         pm_runtime_enable(codec->dev);
3132         pm_runtime_resume(codec->dev);
3133
3134         /* Read our current status back from the chip - we don't want to
3135          * reset as this may interfere with the GPIO or LDO operation. */
3136         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3137                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3138                         continue;
3139
3140                 ret = wm8994_reg_read(codec->control_data, i);
3141                 if (ret <= 0)
3142                         continue;
3143
3144      &nb