sound/soc/codecs/wm8985.c

   1 /*
   2  * wm8985.c  --  WM8985 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * TODO:
  13  *  o Add OUT3/OUT4 mixer controls.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/pm.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/slab.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include "wm8985.h"
  33
  34 #define WM8985_NUM_SUPPLIES 4
  35 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
  36         "DCVDD",
  37         "DBVDD",
  38         "AVDD1",
  39         "AVDD2"
  40 };
  41
  42 static const u16 wm8985_reg_defs[] = {
  43         0x0000,     /* R0  - Software Reset */
  44         0x0000,     /* R1  - Power management 1 */
  45         0x0000,     /* R2  - Power management 2 */
  46         0x0000,     /* R3  - Power management 3 */
  47         0x0050,     /* R4  - Audio Interface */
  48         0x0000,     /* R5  - Companding control */
  49         0x0140,     /* R6  - Clock Gen control */
  50         0x0000,     /* R7  - Additional control */
  51         0x0000,     /* R8  - GPIO Control */
  52         0x0000,     /* R9  - Jack Detect Control 1 */
  53         0x0000,     /* R10 - DAC Control */
  54         0x00FF,     /* R11 - Left DAC digital Vol */
  55         0x00FF,     /* R12 - Right DAC digital vol */
  56         0x0000,     /* R13 - Jack Detect Control 2 */
  57         0x0100,     /* R14 - ADC Control */
  58         0x00FF,     /* R15 - Left ADC Digital Vol */
  59         0x00FF,     /* R16 - Right ADC Digital Vol */
  60         0x0000,     /* R17 */
  61         0x012C,     /* R18 - EQ1 - low shelf */
  62         0x002C,     /* R19 - EQ2 - peak 1 */
  63         0x002C,     /* R20 - EQ3 - peak 2 */
  64         0x002C,     /* R21 - EQ4 - peak 3 */
  65         0x002C,     /* R22 - EQ5 - high shelf */
  66         0x0000,     /* R23 */
  67         0x0032,     /* R24 - DAC Limiter 1 */
  68         0x0000,     /* R25 - DAC Limiter 2 */
  69         0x0000,     /* R26 */
  70         0x0000,     /* R27 - Notch Filter 1 */
  71         0x0000,     /* R28 - Notch Filter 2 */
  72         0x0000,     /* R29 - Notch Filter 3 */
  73         0x0000,     /* R30 - Notch Filter 4 */
  74         0x0000,     /* R31 */
  75         0x0038,     /* R32 - ALC control 1 */
  76         0x000B,     /* R33 - ALC control 2 */
  77         0x0032,     /* R34 - ALC control 3 */
  78         0x0000,     /* R35 - Noise Gate */
  79         0x0008,     /* R36 - PLL N */
  80         0x000C,     /* R37 - PLL K 1 */
  81         0x0093,     /* R38 - PLL K 2 */
  82         0x00E9,     /* R39 - PLL K 3 */
  83         0x0000,     /* R40 */
  84         0x0000,     /* R41 - 3D control */
  85         0x0000,     /* R42 - OUT4 to ADC */
  86         0x0000,     /* R43 - Beep control */
  87         0x0033,     /* R44 - Input ctrl */
  88         0x0010,     /* R45 - Left INP PGA gain ctrl */
  89         0x0010,     /* R46 - Right INP PGA gain ctrl */
  90         0x0100,     /* R47 - Left ADC BOOST ctrl */
  91         0x0100,     /* R48 - Right ADC BOOST ctrl */
  92         0x0002,     /* R49 - Output ctrl */
  93         0x0001,     /* R50 - Left mixer ctrl */
  94         0x0001,     /* R51 - Right mixer ctrl */
  95         0x0039,     /* R52 - LOUT1 (HP) volume ctrl */
  96         0x0039,     /* R53 - ROUT1 (HP) volume ctrl */
  97         0x0039,     /* R54 - LOUT2 (SPK) volume ctrl */
  98         0x0039,     /* R55 - ROUT2 (SPK) volume ctrl */
  99         0x0001,     /* R56 - OUT3 mixer ctrl */
 100         0x0001,     /* R57 - OUT4 (MONO) mix ctrl */
 101         0x0001,     /* R58 */
 102         0x0000,     /* R59 */
 103         0x0004,     /* R60 - OUTPUT ctrl */
 104         0x0000,     /* R61 - BIAS CTRL */
 105         0x0180,     /* R62 */
 106         0x0000      /* R63 */
 107 };
 108
 109 /*
 110  * latch bit 8 of these registers to ensure instant
 111  * volume updates
 112  */
 113 static const int volume_update_regs[] = {
 114         WM8985_LEFT_DAC_DIGITAL_VOL,
 115         WM8985_RIGHT_DAC_DIGITAL_VOL,
 116         WM8985_LEFT_ADC_DIGITAL_VOL,
 117         WM8985_RIGHT_ADC_DIGITAL_VOL,
 118         WM8985_LOUT2_SPK_VOLUME_CTRL,
 119         WM8985_ROUT2_SPK_VOLUME_CTRL,
 120         WM8985_LOUT1_HP_VOLUME_CTRL,
 121         WM8985_ROUT1_HP_VOLUME_CTRL,
 122         WM8985_LEFT_INP_PGA_GAIN_CTRL,
 123         WM8985_RIGHT_INP_PGA_GAIN_CTRL
 124 };
 125
 126 struct wm8985_priv {
 127         enum snd_soc_control_type control_type;
 128         struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
 129         unsigned int sysclk;
 130         unsigned int bclk;
 131 };
 132
 133 static const struct {
 134         int div;
 135         int ratio;
 136 } fs_ratios[] = {
 137         { 10, 128 },
 138         { 15, 192 },
 139         { 20, 256 },
 140         { 30, 384 },
 141         { 40, 512 },
 142         { 60, 768 },
 143         { 80, 1024 },
 144         { 120, 1536 }
 145 };
 146
 147 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
 148
 149 static const int bclk_divs[] = {
 150         1, 2, 4, 8, 16, 32
 151 };
 152
 153 static int eqmode_get(struct snd_kcontrol *kcontrol,
 154                       struct snd_ctl_elem_value *ucontrol);
 155 static int eqmode_put(struct snd_kcontrol *kcontrol,
 156                       struct snd_ctl_elem_value *ucontrol);
 157
 158 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
 159 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
 160 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
 161 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
 162 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
 163 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
 164 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
 165 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
 166 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
 167 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
 168 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 169 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
 170 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 171 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
 172
 173 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
 174 static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7,
 175                                   alc_sel_text);
 176
 177 static const char *alc_mode_text[] = { "ALC", "Limiter" };
 178 static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8,
 179                                   alc_mode_text);
 180
 181 static const char *filter_mode_text[] = { "Audio", "Application" };
 182 static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
 183                                   filter_mode_text);
 184
 185 static const char *eq_bw_text[] = { "Narrow", "Wide" };
 186 static const char *eqmode_text[] = { "Capture", "Playback" };
 187 static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
 188
 189 static const char *eq1_cutoff_text[] = {
 190         "80Hz", "105Hz", "135Hz", "175Hz"
 191 };
 192 static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
 193                                   eq1_cutoff_text);
 194 static const char *eq2_cutoff_text[] = {
 195         "230Hz", "300Hz", "385Hz", "500Hz"
 196 };
 197 static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
 198 static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5,
 199                                   eq2_cutoff_text);
 200 static const char *eq3_cutoff_text[] = {
 201         "650Hz", "850Hz", "1.1kHz", "1.4kHz"
 202 };
 203 static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
 204 static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
 205                                   eq3_cutoff_text);
 206 static const char *eq4_cutoff_text[] = {
 207         "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
 208 };
 209 static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
 210 static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5,
 211                                   eq4_cutoff_text);
 212 static const char *eq5_cutoff_text[] = {
 213         "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
 214 };
 215 static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
 216                                   eq5_cutoff_text);
 217
 218 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
 219 static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
 220
 221 static const char *depth_3d_text[] = {
 222         "Off",
 223         "6.67%",
 224         "13.3%",
 225         "20%",
 226         "26.7%",
 227         "33.3%",
 228         "40%",
 229         "46.6%",
 230         "53.3%",
 231         "60%",
 232         "66.7%",
 233         "73.3%",
 234         "80%",
 235         "86.7%",
 236         "93.3%",
 237         "100%"
 238 };
 239 static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0,
 240                                   depth_3d_text);
 241
 242 static const struct snd_kcontrol_new wm8985_snd_controls[] = {
 243         SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
 244                 0, 1, 0),
 245
 246         SOC_ENUM("ALC Capture Function", alc_sel),
 247         SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
 248                 3, 7, 0, alc_max_tlv),
 249         SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
 250                 0, 7, 0, alc_min_tlv),
 251         SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
 252                 0, 15, 0, alc_tar_tlv),
 253         SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
 254         SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
 255         SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
 256         SOC_ENUM("ALC Mode", alc_mode),
 257         SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
 258                 3, 1, 0),
 259         SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
 260                 0, 7, 1),
 261
 262         SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
 263                 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
 264         SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 265                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
 266         SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 267                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
 268
 269         SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
 270                 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
 271                 8, 1, 0, pga_boost_tlv),
 272
 273         SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
 274         SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 275
 276         SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
 277                 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
 278
 279         SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
 280         SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
 281         SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
 282         SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
 283                 4, 7, 1, lim_thresh_tlv),
 284         SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
 285                 0, 12, 0, lim_boost_tlv),
 286         SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
 287         SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
 288         SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
 289
 290         SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
 291                 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
 292         SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 293                 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
 294         SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 295                 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
 296
 297         SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
 298                 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
 299         SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 300                 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
 301         SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 302                 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
 303
 304         SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 305         SOC_ENUM("High Pass Filter Mode", filter_mode),
 306         SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
 307
 308         SOC_DOUBLE_R_TLV("Aux Bypass Volume",
 309                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
 310                 aux_tlv),
 311
 312         SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
 313                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
 314                 bypass_tlv),
 315
 316         SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
 317         SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
 318         SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
 319         SOC_ENUM("EQ2 Bandwith", eq2_bw),
 320         SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
 321         SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
 322         SOC_ENUM("EQ3 Bandwith", eq3_bw),
 323         SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
 324         SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
 325         SOC_ENUM("EQ4 Bandwith", eq4_bw),
 326         SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
 327         SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
 328         SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
 329         SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
 330
 331         SOC_ENUM("3D Depth", depth_3d),
 332
 333         SOC_ENUM("Speaker Mode", speaker_mode)
 334 };
 335
 336 static const struct snd_kcontrol_new left_out_mixer[] = {
 337         SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
 338         SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
 339         SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
 340 };
 341
 342 static const struct snd_kcontrol_new right_out_mixer[] = {
 343         SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
 344         SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
 345         SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
 346 };
 347
 348 static const struct snd_kcontrol_new left_input_mixer[] = {
 349         SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
 350         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
 351         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
 352 };
 353
 354 static const struct snd_kcontrol_new right_input_mixer[] = {
 355         SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
 356         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
 357         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
 358 };
 359
 360 static const struct snd_kcontrol_new left_boost_mixer[] = {
 361         SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 362                 4, 7, 0, boost_tlv),
 363         SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 364                 0, 7, 0, boost_tlv)
 365 };
 366
 367 static const struct snd_kcontrol_new right_boost_mixer[] = {
 368         SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 369                 4, 7, 0, boost_tlv),
 370         SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 371                 0, 7, 0, boost_tlv)
 372 };
 373
 374 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
 375         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
 376                 0, 0),
 377         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
 378                 1, 0),
 379         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
 380                 0, 0),
 381         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
 382                 1, 0),
 383
 384         SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
 385                 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
 386         SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
 387                 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
 388
 389         SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
 390                 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
 391         SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
 392                 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
 393
 394         SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 395                 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
 396         SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 397                 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
 398
 399         SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 400                 6, 1, NULL, 0),
 401         SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
 402                 6, 1, NULL, 0),
 403
 404         SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
 405                 7, 0, NULL, 0),
 406         SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
 407                 8, 0, NULL, 0),
 408
 409         SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
 410                 5, 0, NULL, 0),
 411         SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
 412                 6, 0, NULL, 0),
 413
 414         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0),
 415
 416         SND_SOC_DAPM_INPUT("LIN"),
 417         SND_SOC_DAPM_INPUT("LIP"),
 418         SND_SOC_DAPM_INPUT("RIN"),
 419         SND_SOC_DAPM_INPUT("RIP"),
 420         SND_SOC_DAPM_INPUT("AUXL"),
 421         SND_SOC_DAPM_INPUT("AUXR"),
 422         SND_SOC_DAPM_INPUT("L2"),
 423         SND_SOC_DAPM_INPUT("R2"),
 424         SND_SOC_DAPM_OUTPUT("HPL"),
 425         SND_SOC_DAPM_OUTPUT("HPR"),
 426         SND_SOC_DAPM_OUTPUT("SPKL"),
 427         SND_SOC_DAPM_OUTPUT("SPKR")
 428 };
 429
 430 static const struct snd_soc_dapm_route audio_map[] = {
 431         { "Right Output Mixer", "PCM Switch", "Right DAC" },
 432         { "Right Output Mixer", "Aux Switch", "AUXR" },
 433         { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
 434
 435         { "Left Output Mixer", "PCM Switch", "Left DAC" },
 436         { "Left Output Mixer", "Aux Switch", "AUXL" },
 437         { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
 438
 439         { "Right Headphone Out", NULL, "Right Output Mixer" },
 440         { "HPR", NULL, "Right Headphone Out" },
 441
 442         { "Left Headphone Out", NULL, "Left Output Mixer" },
 443         { "HPL", NULL, "Left Headphone Out" },
 444
 445         { "Right Speaker Out", NULL, "Right Output Mixer" },
 446         { "SPKR", NULL, "Right Speaker Out" },
 447
 448         { "Left Speaker Out", NULL, "Left Output Mixer" },
 449         { "SPKL", NULL, "Left Speaker Out" },
 450
 451         { "Right ADC", NULL, "Right Boost Mixer" },
 452
 453         { "Right Boost Mixer", "AUXR Volume", "AUXR" },
 454         { "Right Boost Mixer", NULL, "Right Capture PGA" },
 455         { "Right Boost Mixer", "R2 Volume", "R2" },
 456
 457         { "Left ADC", NULL, "Left Boost Mixer" },
 458
 459         { "Left Boost Mixer", "AUXL Volume", "AUXL" },
 460         { "Left Boost Mixer", NULL, "Left Capture PGA" },
 461         { "Left Boost Mixer", "L2 Volume", "L2" },
 462
 463         { "Right Capture PGA", NULL, "Right Input Mixer" },
 464         { "Left Capture PGA", NULL, "Left Input Mixer" },
 465
 466         { "Right Input Mixer", "R2 Switch", "R2" },
 467         { "Right Input Mixer", "MicN Switch", "RIN" },
 468         { "Right Input Mixer", "MicP Switch", "RIP" },
 469
 470         { "Left Input Mixer", "L2 Switch", "L2" },
 471         { "Left Input Mixer", "MicN Switch", "LIN" },
 472         { "Left Input Mixer", "MicP Switch", "LIP" },
 473 };
 474
 475 static int eqmode_get(struct snd_kcontrol *kcontrol,
 476                       struct snd_ctl_elem_value *ucontrol)
 477 {
 478         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 479         unsigned int reg;
 480
 481         reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 482         if (reg & WM8985_EQ3DMODE)
 483                 ucontrol->value.integer.value[0] = 1;
 484         else
 485                 ucontrol->value.integer.value[0] = 0;
 486
 487         return 0;
 488 }
 489
 490 static int eqmode_put(struct snd_kcontrol *kcontrol,
 491                       struct snd_ctl_elem_value *ucontrol)
 492 {
 493         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 494         unsigned int regpwr2, regpwr3;
 495         unsigned int reg_eq;
 496
 497         if (ucontrol->value.integer.value[0] != 0
 498                         && ucontrol->value.integer.value[0] != 1)
 499                 return -EINVAL;
 500
 501         reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 502         switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
 503         case 0:
 504                 if (!ucontrol->value.integer.value[0])
 505                         return 0;
 506                 break;
 507         case 1:
 508                 if (ucontrol->value.integer.value[0])
 509                         return 0;
 510                 break;
 511         }
 512
 513         regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
 514         regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
 515         /* disable the DACs and ADCs */
 516         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
 517                             WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
 518         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
 519                             WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
 520         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 521                             WM8985_M128ENB_MASK, WM8985_M128ENB);
 522         /* set the desired eqmode */
 523         snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
 524                             WM8985_EQ3DMODE_MASK,
 525                             ucontrol->value.integer.value[0]
 526                             << WM8985_EQ3DMODE_SHIFT);
 527         /* restore DAC/ADC configuration */
 528         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
 529         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
 530         return 0;
 531 }
 532
 533 static int wm8985_add_widgets(struct snd_soc_codec *codec)
 534 {
 535         struct snd_soc_dapm_context *dapm = &codec->dapm;
 536
 537         snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
 538                                   ARRAY_SIZE(wm8985_dapm_widgets));
 539         snd_soc_dapm_add_routes(dapm, audio_map,
 540                                 ARRAY_SIZE(audio_map));
 541         return 0;
 542 }
 543
 544 static int wm8985_reset(struct snd_soc_codec *codec)
 545 {
 546         return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
 547 }
 548
 549 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
 550 {
 551         struct snd_soc_codec *codec = dai->codec;
 552
 553         return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
 554                                    WM8985_SOFTMUTE_MASK,
 555                                    !!mute << WM8985_SOFTMUTE_SHIFT);
 556 }
 557
 558 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 559 {
 560         struct snd_soc_codec *codec;
 561         u16 format, master, bcp, lrp;
 562
 563         codec = dai->codec;
 564
 565         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 566         case SND_SOC_DAIFMT_I2S:
 567                 format = 0x2;
 568                 break;
 569         case SND_SOC_DAIFMT_RIGHT_J:
 570                 format = 0x0;
 571                 break;
 572         case SND_SOC_DAIFMT_LEFT_J:
 573                 format = 0x1;
 574                 break;
 575         case SND_SOC_DAIFMT_DSP_A:
 576         case SND_SOC_DAIFMT_DSP_B:
 577                 format = 0x3;
 578                 break;
 579         default:
 580                 dev_err(dai->dev, "Unknown dai format\n");
 581                 return -EINVAL;
 582         }
 583
 584         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 585                             WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
 586
 587         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 588         case SND_SOC_DAIFMT_CBM_CFM:
 589                 master = 1;
 590                 break;
 591         case SND_SOC_DAIFMT_CBS_CFS:
 592                 master = 0;
 593                 break;
 594         default:
 595                 dev_err(dai->dev, "Unknown master/slave configuration\n");
 596                 return -EINVAL;
 597         }
 598
 599         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 600                             WM8985_MS_MASK, master << WM8985_MS_SHIFT);
 601
 602         /* frame inversion is not valid for dsp modes */
 603         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 604         case SND_SOC_DAIFMT_DSP_A:
 605         case SND_SOC_DAIFMT_DSP_B:
 606                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 607                 case SND_SOC_DAIFMT_IB_IF:
 608                 case SND_SOC_DAIFMT_NB_IF:
 609                         return -EINVAL;
 610                 default:
 611                         break;
 612                 }
 613                 break;
 614         default:
 615                 break;
 616         }
 617
 618         bcp = lrp = 0;
 619         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 620         case SND_SOC_DAIFMT_NB_NF:
 621                 break;
 622         case SND_SOC_DAIFMT_IB_IF:
 623                 bcp = lrp = 1;
 624                 break;
 625         case SND_SOC_DAIFMT_IB_NF:
 626                 bcp = 1;
 627                 break;
 628         case SND_SOC_DAIFMT_NB_IF:
 629                 lrp = 1;
 630                 break;
 631         default:
 632                 dev_err(dai->dev, "Unknown polarity configuration\n");
 633                 return -EINVAL;
 634         }
 635
 636         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 637                             WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
 638         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 639                             WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
 640         return 0;
 641 }
 642
 643 static int wm8985_hw_params(struct snd_pcm_substream *substream,
 644                             struct snd_pcm_hw_params *params,
 645                             struct snd_soc_dai *dai)
 646 {
 647         int i;
 648         struct snd_soc_codec *codec;
 649         struct wm8985_priv *wm8985;
 650         u16 blen, srate_idx;
 651         unsigned int tmp;
 652         int srate_best;
 653
 654         codec = dai->codec;
 655         wm8985 = snd_soc_codec_get_drvdata(codec);
 656
 657         wm8985->bclk = snd_soc_params_to_bclk(params);
 658         if ((int)wm8985->bclk < 0)
 659                 return wm8985->bclk;
 660
 661         switch (params_format(params)) {
 662         case SNDRV_PCM_FORMAT_S16_LE:
 663                 blen = 0x0;
 664                 break;
 665         case SNDRV_PCM_FORMAT_S20_3LE:
 666                 blen = 0x1;
 667                 break;
 668         case SNDRV_PCM_FORMAT_S24_LE:
 669                 blen = 0x2;
 670                 break;
 671         case SNDRV_PCM_FORMAT_S32_LE:
 672                 blen = 0x3;
 673                 break;
 674         default:
 675                 dev_err(dai->dev, "Unsupported word length %u\n",
 676                         params_format(params));
 677                 return -EINVAL;
 678         }
 679
 680         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 681                             WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
 682
 683         /*
 684          * match to the nearest possible sample rate and rely
 685          * on the array index to configure the SR register
 686          */
 687         srate_idx = 0;
 688         srate_best = abs(srates[0] - params_rate(params));
 689         for (i = 1; i < ARRAY_SIZE(srates); ++i) {
 690                 if (abs(srates[i] - params_rate(params)) >= srate_best)
 691                         continue;
 692                 srate_idx = i;
 693                 srate_best = abs(srates[i] - params_rate(params));
 694         }
 695
 696         dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
 697         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 698                             WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
 699
 700         dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
 701         dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
 702
 703         for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
 704                 if (wm8985->sysclk / params_rate(params)
 705                                 == fs_ratios[i].ratio)
 706                         break;
 707         }
 708
 709         if (i == ARRAY_SIZE(fs_ratios)) {
 710                 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
 711                         wm8985->sysclk, params_rate(params));
 712                 return -EINVAL;
 713         }
 714
 715         dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
 716         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 717                             WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
 718
 719         /* select the appropriate bclk divider */
 720         tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
 721         for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
 722                 if (wm8985->bclk == tmp / bclk_divs[i])
 723                         break;
 724         }
 725
 726         if (i == ARRAY_SIZE(bclk_divs)) {
 727                 dev_err(dai->dev, "No matching BCLK divider found\n");
 728                 return -EINVAL;
 729         }
 730
 731         dev_dbg(dai->dev, "BCLK div = %d\n", i);
 732         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 733                             WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
 734         return 0;
 735 }
 736
 737 struct pll_div {
 738         u32 div2:1;
 739         u32 n:4;
 740         u32 k:24;
 741 };
 742
 743 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
 744 static int pll_factors(struct pll_div *pll_div, unsigned int target,
 745                        unsigned int source)
 746 {
 747         u64 Kpart;
 748         unsigned long int K, Ndiv, Nmod;
 749
 750         pll_div->div2 = 0;
 751         Ndiv = target / source;
 752         if (Ndiv < 6) {
 753                 source >>= 1;
 754                 pll_div->div2 = 1;
 755                 Ndiv = target / source;
 756         }
 757
 758         if (Ndiv < 6 || Ndiv > 12) {
 759                 printk(KERN_ERR "%s: WM8985 N value is not within"
 760                        " the recommended range: %lu\n", __func__, Ndiv);
 761                 return -EINVAL;
 762         }
 763         pll_div->n = Ndiv;
 764
 765         Nmod = target % source;
 766         Kpart = FIXED_PLL_SIZE * (u64)Nmod;
 767
 768         do_div(Kpart, source);
 769
 770         K = Kpart & 0xffffffff;
 771         if ((K % 10) >= 5)
 772                 K += 5;
 773         K /= 10;
 774         pll_div->k = K;
 775
 776         return 0;
 777 }
 778
 779 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
 780                           int source, unsigned int freq_in,
 781                           unsigned int freq_out)
 782 {
 783         int ret;
 784         struct snd_soc_codec *codec;
 785         struct pll_div pll_div;
 786
 787         codec = dai->codec;
 788         if (freq_in && freq_out) {
 789                 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
 790                 if (ret)
 791                         return ret;
 792         }
 793
 794         /* disable the PLL before reprogramming it */
 795         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 796                             WM8985_PLLEN_MASK, 0);
 797
 798         if (!freq_in || !freq_out)
 799                 return 0;
 800
 801         /* set PLLN and PRESCALE */
 802         snd_soc_write(codec, WM8985_PLL_N,
 803                       (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
 804                       | pll_div.n);
 805         /* set PLLK */
 806         snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
 807         snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
 808         snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
 809         /* set the source of the clock to be the PLL */
 810         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 811                             WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 812         /* enable the PLL */
 813         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 814                             WM8985_PLLEN_MASK, WM8985_PLLEN);
 815         return 0;
 816 }
 817
 818 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
 819                              int clk_id, unsigned int freq, int dir)
 820 {
 821         struct snd_soc_codec *codec;
 822         struct wm8985_priv *wm8985;
 823
 824         codec = dai->codec;
 825         wm8985 = snd_soc_codec_get_drvdata(codec);
 826
 827         switch (clk_id) {
 828         case WM8985_CLKSRC_MCLK:
 829                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 830                                     WM8985_CLKSEL_MASK, 0);
 831                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 832                                     WM8985_PLLEN_MASK, 0);
 833                 break;
 834         case WM8985_CLKSRC_PLL:
 835                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 836                                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 837                 break;
 838         default:
 839                 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
 840                 return -EINVAL;
 841         }
 842
 843         wm8985->sysclk = freq;
 844         return 0;
 845 }
 846
 847 static void wm8985_sync_cache(struct snd_soc_codec *codec)
 848 {
 849         short i;
 850         u16 *cache;
 851
 852         if (!codec->cache_sync)
 853                 return;
 854         codec->cache_only = 0;
 855         /* restore cache */
 856         cache = codec->reg_cache;
 857         for (i = 0; i < codec->driver->reg_cache_size; i++) {
 858                 if (i == WM8985_SOFTWARE_RESET
 859                                 || cache[i] == wm8985_reg_defs[i])
 860                         continue;
 861                 snd_soc_write(codec, i, cache[i]);
 862         }
 863         codec->cache_sync = 0;
 864 }
 865
 866 static int wm8985_set_bias_level(struct snd_soc_codec *codec,
 867                                  enum snd_soc_bias_level level)
 868 {
 869         int ret;
 870         struct wm8985_priv *wm8985;
 871
 872         wm8985 = snd_soc_codec_get_drvdata(codec);
 873         switch (level) {
 874         case SND_SOC_BIAS_ON:
 875         case SND_SOC_BIAS_PREPARE:
 876                 /* VMID at 75k */
 877                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 878                                     WM8985_VMIDSEL_MASK,
 879                                     1 << WM8985_VMIDSEL_SHIFT);
 880                 break;
 881         case SND_SOC_BIAS_STANDBY:
 882                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 883                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
 884                                                     wm8985->supplies);
 885                         if (ret) {
 886                                 dev_err(codec->dev,
 887                                         "Failed to enable supplies: %d\n",
 888                                         ret);
 889                                 return ret;
 890                         }
 891
 892                         wm8985_sync_cache(codec);
 893
 894                         /* enable anti-pop features */
 895                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 896                                             WM8985_POBCTRL_MASK,
 897                                             WM8985_POBCTRL);
 898                         /* enable thermal shutdown */
 899                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 900                                             WM8985_TSDEN_MASK, WM8985_TSDEN);
 901                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 902                                             WM8985_TSOPCTRL_MASK,
 903                                             WM8985_TSOPCTRL);
 904                         /* enable BIASEN */
 905                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 906                                             WM8985_BIASEN_MASK, WM8985_BIASEN);
 907                         /* VMID at 75k */
 908                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 909                                             WM8985_VMIDSEL_MASK,
 910                                             1 << WM8985_VMIDSEL_SHIFT);
 911                         msleep(500);
 912                         /* disable anti-pop features */
 913                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 914                                             WM8985_POBCTRL_MASK, 0);
 915                 }
 916                 /* VMID at 300k */
 917                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 918                                     WM8985_VMIDSEL_MASK,
 919                                     2 << WM8985_VMIDSEL_SHIFT);
 920                 break;
 921         case SND_SOC_BIAS_OFF:
 922                 /* disable thermal shutdown */
 923                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 924                                     WM8985_TSOPCTRL_MASK, 0);
 925                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 926                                     WM8985_TSDEN_MASK, 0);
 927                 /* disable VMIDSEL and BIASEN */
 928                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 929                                     WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
 930                                     0);
 931                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
 932                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
 933                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
 934
 935                 codec->cache_sync = 1;
 936
 937                 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
 938                                        wm8985->supplies);
 939                 break;
 940         }
 941
 942         codec->dapm.bias_level = level;
 943         return 0;
 944 }
 945
 946 #ifdef CONFIG_PM
 947 static int wm8985_suspend(struct snd_soc_codec *codec, pm_message_t state)
 948 {
 949         wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
 950         return 0;
 951 }
 952
 953 static int wm8985_resume(struct snd_soc_codec *codec)
 954 {
 955         wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 956         return 0;
 957 }
 958 #else
 959 #define wm8985_suspend NULL
 960 #define wm8985_resume NULL
 961 #endif
 962
 963 static int wm8985_remove(struct snd_soc_codec *codec)
 964 {
 965         struct wm8985_priv *wm8985;
 966
 967         wm8985 = snd_soc_codec_get_drvdata(codec);
 968         wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
 969         regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
 970         return 0;
 971 }
 972
 973 static int wm8985_probe(struct snd_soc_codec *codec)
 974 {
 975         size_t i;
 976         struct wm8985_priv *wm8985;
 977         int ret;
 978         u16 *cache;
 979
 980         wm8985 = snd_soc_codec_get_drvdata(codec);
 981
 982         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8985->control_type);
 983         if (ret < 0) {
 984                 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
 985                 return ret;
 986         }
 987
 988         for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
 989                 wm8985->supplies[i].supply = wm8985_supply_names[i];
 990
 991         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
 992                                  wm8985->supplies);
 993         if (ret) {
 994                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 995                 return ret;
 996         }
 997
 998         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
 999                                     wm8985->supplies);
1000         if (ret) {
1001                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1002                 goto err_reg_get;
1003         }
1004
1005         ret = wm8985_reset(codec);
1006         if (ret < 0) {
1007                 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1008                 goto err_reg_enable;
1009         }
1010
1011         cache = codec->reg_cache;
1012         /* latch volume update bits */
1013         for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
1014                 cache[volume_update_regs[i]] |= 0x100;
1015         /* enable BIASCUT */
1016         cache[WM8985_BIAS_CTRL] |= WM8985_BIASCUT;
1017         codec->cache_sync = 1;
1018
1019         snd_soc_add_controls(codec, wm8985_snd_controls,
1020                              ARRAY_SIZE(wm8985_snd_controls));
1021         wm8985_add_widgets(codec);
1022
1023         wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1024         return 0;
1025
1026 err_reg_enable:
1027         regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1028 err_reg_get:
1029         regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1030         return ret;
1031 }
1032
1033 static struct snd_soc_dai_ops wm8985_dai_ops = {
1034         .digital_mute = wm8985_dac_mute,
1035         .hw_params = wm8985_hw_params,
1036         .set_fmt = wm8985_set_fmt,
1037         .set_sysclk = wm8985_set_sysclk,
1038         .set_pll = wm8985_set_pll
1039 };
1040
1041 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1042                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1043
1044 static struct snd_soc_dai_driver wm8985_dai = {
1045         .name = "wm8985-hifi",
1046         .playback = {
1047                 .stream_name = "Playback",
1048                 .channels_min = 2,
1049                 .channels_max = 2,
1050                 .rates = SNDRV_PCM_RATE_8000_48000,
1051                 .formats = WM8985_FORMATS,
1052         },
1053         .capture = {
1054                 .stream_name = "Capture",
1055                 .channels_min = 2,
1056                 .channels_max = 2,
1057                 .rates = SNDRV_PCM_RATE_8000_48000,
1058                 .formats = WM8985_FORMATS,
1059         },
1060         .ops = &wm8985_dai_ops,
1061         .symmetric_rates = 1
1062 };
1063
1064 static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1065         .probe = wm8985_probe,
1066         .remove = wm8985_remove,
1067         .suspend = wm8985_suspend,
1068         .resume = wm8985_resume,
1069         .set_bias_level = wm8985_set_bias_level,
1070         .reg_cache_size = ARRAY_SIZE(wm8985_reg_defs),
1071         .reg_word_size = sizeof(u16),
1072         .reg_cache_default = wm8985_reg_defs
1073 };
1074
1075 #if defined(CONFIG_SPI_MASTER)
1076 static int __devinit wm8985_spi_probe(struct spi_device *spi)
1077 {
1078         struct wm8985_priv *wm8985;
1079         int ret;
1080
1081         wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
1082         if (!wm8985)
1083                 return -ENOMEM;
1084
1085         wm8985->control_type = SND_SOC_SPI;
1086         spi_set_drvdata(spi, wm8985);
1087
1088         ret = snd_soc_register_codec(&spi->dev,
1089                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1090         if (ret < 0)
1091                 kfree(wm8985);
1092         return ret;
1093 }
1094
1095 static int __devexit wm8985_spi_remove(struct spi_device *spi)
1096 {
1097         snd_soc_unregister_codec(&spi->dev);
1098         kfree(spi_get_drvdata(spi));
1099         return 0;
1100 }
1101
1102 static struct spi_driver wm8985_spi_driver = {
1103         .driver = {
1104                 .name = "wm8985",
1105                 .owner = THIS_MODULE,
1106         },
1107         .probe = wm8985_spi_probe,
1108         .remove = __devexit_p(wm8985_spi_remove)
1109 };
1110 #endif
1111
1112 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1113 static __devinit int wm8985_i2c_probe(struct i2c_client *i2c,
1114                                       const struct i2c_device_id *id)
1115 {
1116         struct wm8985_priv *wm8985;
1117         int ret;
1118
1119         wm8985 = kzalloc(sizeof *wm8985, GFP_KERNEL);
1120         if (!wm8985)
1121                 return -ENOMEM;
1122
1123         wm8985->control_type = SND_SOC_I2C;
1124         i2c_set_clientdata(i2c, wm8985);
1125
1126         ret = snd_soc_register_codec(&i2c->dev,
1127                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1128         if (ret < 0)
1129                 kfree(wm8985);
1130         return ret;
1131 }
1132
1133 static __devexit int wm8985_i2c_remove(struct i2c_client *client)
1134 {
1135         snd_soc_unregister_codec(&client->dev);
1136         kfree(i2c_get_clientdata(client));
1137         return 0;
1138 }
1139
1140 static const struct i2c_device_id wm8985_i2c_id[] = {
1141         { "wm8985", 0 },
1142         { }
1143 };
1144 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1145
1146 static struct i2c_driver wm8985_i2c_driver = {
1147         .driver = {
1148                 .name = "wm8985",
1149                 .owner = THIS_MODULE,
1150         },
1151         .probe = wm8985_i2c_probe,
1152         .remove = __devexit_p(wm8985_i2c_remove),
1153         .id_table = wm8985_i2c_id
1154 };
1155 #endif
1156
1157 static int __init wm8985_modinit(void)
1158 {
1159         int ret = 0;
1160
1161 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1162         ret = i2c_add_driver(&wm8985_i2c_driver);
1163         if (ret) {
1164                 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1165                        ret);
1166         }
1167 #endif
1168 #if defined(CONFIG_SPI_MASTER)
1169         ret = spi_register_driver(&wm8985_spi_driver);
1170         if (ret != 0) {
1171                 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1172                        ret);
1173         }
1174 #endif
1175         return ret;
1176 }
1177 module_init(wm8985_modinit);
1178
1179 static void __exit wm8985_exit(void)
1180 {
1181 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1182         i2c_del_driver(&wm8985_i2c_driver);
1183 #endif
1184 #if defined(CONFIG_SPI_MASTER)
1185         spi_unregister_driver(&wm8985_spi_driver);
1186 #endif
1187 }
1188 module_exit(wm8985_exit);
1189
1190 MODULE_DESCRIPTION("ASoC WM8985 driver");
1191 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1192 MODULE_LICENSE("GPL");