sound/soc/codecs/wm8961.c

   1 /*
   2  * wm8961.c  --  WM8961 ALSA SoC Audio driver
   3  *
   4  * Author: Mark Brown
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Currently unimplemented features:
  11  *  - ALC
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/initval.h>
  27 #include <sound/tlv.h>
  28
  29 #include "wm8961.h"
  30
  31 #define WM8961_MAX_REGISTER                     0xFC
  32
  33 static u16 wm8961_reg_defaults[] = {
  34         0x009F,     /* R0   - Left Input volume */
  35         0x009F,     /* R1   - Right Input volume */
  36         0x0000,     /* R2   - LOUT1 volume */
  37         0x0000,     /* R3   - ROUT1 volume */
  38         0x0020,     /* R4   - Clocking1 */
  39         0x0008,     /* R5   - ADC & DAC Control 1 */
  40         0x0000,     /* R6   - ADC & DAC Control 2 */
  41         0x000A,     /* R7   - Audio Interface 0 */
  42         0x01F4,     /* R8   - Clocking2 */
  43         0x0000,     /* R9   - Audio Interface 1 */
  44         0x00FF,     /* R10  - Left DAC volume */
  45         0x00FF,     /* R11  - Right DAC volume */
  46         0x0000,     /* R12 */
  47         0x0000,     /* R13 */
  48         0x0040,     /* R14  - Audio Interface 2 */
  49         0x0000,     /* R15  - Software Reset */
  50         0x0000,     /* R16 */
  51         0x007B,     /* R17  - ALC1 */
  52         0x0000,     /* R18  - ALC2 */
  53         0x0032,     /* R19  - ALC3 */
  54         0x0000,     /* R20  - Noise Gate */
  55         0x00C0,     /* R21  - Left ADC volume */
  56         0x00C0,     /* R22  - Right ADC volume */
  57         0x0120,     /* R23  - Additional control(1) */
  58         0x0000,     /* R24  - Additional control(2) */
  59         0x0000,     /* R25  - Pwr Mgmt (1) */
  60         0x0000,     /* R26  - Pwr Mgmt (2) */
  61         0x0000,     /* R27  - Additional Control (3) */
  62         0x0000,     /* R28  - Anti-pop */
  63         0x0000,     /* R29 */
  64         0x005F,     /* R30  - Clocking 3 */
  65         0x0000,     /* R31 */
  66         0x0000,     /* R32  - ADCL signal path */
  67         0x0000,     /* R33  - ADCR signal path */
  68         0x0000,     /* R34 */
  69         0x0000,     /* R35 */
  70         0x0000,     /* R36 */
  71         0x0000,     /* R37 */
  72         0x0000,     /* R38 */
  73         0x0000,     /* R39 */
  74         0x0000,     /* R40  - LOUT2 volume */
  75         0x0000,     /* R41  - ROUT2 volume */
  76         0x0000,     /* R42 */
  77         0x0000,     /* R43 */
  78         0x0000,     /* R44 */
  79         0x0000,     /* R45 */
  80         0x0000,     /* R46 */
  81         0x0000,     /* R47  - Pwr Mgmt (3) */
  82         0x0023,     /* R48  - Additional Control (4) */
  83         0x0000,     /* R49  - Class D Control 1 */
  84         0x0000,     /* R50 */
  85         0x0003,     /* R51  - Class D Control 2 */
  86         0x0000,     /* R52 */
  87         0x0000,     /* R53 */
  88         0x0000,     /* R54 */
  89         0x0000,     /* R55 */
  90         0x0106,     /* R56  - Clocking 4 */
  91         0x0000,     /* R57  - DSP Sidetone 0 */
  92         0x0000,     /* R58  - DSP Sidetone 1 */
  93         0x0000,     /* R59 */
  94         0x0000,     /* R60  - DC Servo 0 */
  95         0x0000,     /* R61  - DC Servo 1 */
  96         0x0000,     /* R62 */
  97         0x015E,     /* R63  - DC Servo 3 */
  98         0x0010,     /* R64 */
  99         0x0010,     /* R65  - DC Servo 5 */
 100         0x0000,     /* R66 */
 101         0x0001,     /* R67 */
 102         0x0003,     /* R68  - Analogue PGA Bias */
 103         0x0000,     /* R69  - Analogue HP 0 */
 104         0x0060,     /* R70 */
 105         0x01FB,     /* R71  - Analogue HP 2 */
 106         0x0000,     /* R72  - Charge Pump 1 */
 107         0x0065,     /* R73 */
 108         0x005F,     /* R74 */
 109         0x0059,     /* R75 */
 110         0x006B,     /* R76 */
 111         0x0038,     /* R77 */
 112         0x000C,     /* R78 */
 113         0x000A,     /* R79 */
 114         0x006B,     /* R80 */
 115         0x0000,     /* R81 */
 116         0x0000,     /* R82  - Charge Pump B */
 117         0x0087,     /* R83 */
 118         0x0000,     /* R84 */
 119         0x005C,     /* R85 */
 120         0x0000,     /* R86 */
 121         0x0000,     /* R87  - Write Sequencer 1 */
 122         0x0000,     /* R88  - Write Sequencer 2 */
 123         0x0000,     /* R89  - Write Sequencer 3 */
 124         0x0000,     /* R90  - Write Sequencer 4 */
 125         0x0000,     /* R91  - Write Sequencer 5 */
 126         0x0000,     /* R92  - Write Sequencer 6 */
 127         0x0000,     /* R93  - Write Sequencer 7 */
 128         0x0000,     /* R94 */
 129         0x0000,     /* R95 */
 130         0x0000,     /* R96 */
 131         0x0000,     /* R97 */
 132         0x0000,     /* R98 */
 133         0x0000,     /* R99 */
 134         0x0000,     /* R100 */
 135         0x0000,     /* R101 */
 136         0x0000,     /* R102 */
 137         0x0000,     /* R103 */
 138         0x0000,     /* R104 */
 139         0x0000,     /* R105 */
 140         0x0000,     /* R106 */
 141         0x0000,     /* R107 */
 142         0x0000,     /* R108 */
 143         0x0000,     /* R109 */
 144         0x0000,     /* R110 */
 145         0x0000,     /* R111 */
 146         0x0000,     /* R112 */
 147         0x0000,     /* R113 */
 148         0x0000,     /* R114 */
 149         0x0000,     /* R115 */
 150         0x0000,     /* R116 */
 151         0x0000,     /* R117 */
 152         0x0000,     /* R118 */
 153         0x0000,     /* R119 */
 154         0x0000,     /* R120 */
 155         0x0000,     /* R121 */
 156         0x0000,     /* R122 */
 157         0x0000,     /* R123 */
 158         0x0000,     /* R124 */
 159         0x0000,     /* R125 */
 160         0x0000,     /* R126 */
 161         0x0000,     /* R127 */
 162         0x0000,     /* R128 */
 163         0x0000,     /* R129 */
 164         0x0000,     /* R130 */
 165         0x0000,     /* R131 */
 166         0x0000,     /* R132 */
 167         0x0000,     /* R133 */
 168         0x0000,     /* R134 */
 169         0x0000,     /* R135 */
 170         0x0000,     /* R136 */
 171         0x0000,     /* R137 */
 172         0x0000,     /* R138 */
 173         0x0000,     /* R139 */
 174         0x0000,     /* R140 */
 175         0x0000,     /* R141 */
 176         0x0000,     /* R142 */
 177         0x0000,     /* R143 */
 178         0x0000,     /* R144 */
 179         0x0000,     /* R145 */
 180         0x0000,     /* R146 */
 181         0x0000,     /* R147 */
 182         0x0000,     /* R148 */
 183         0x0000,     /* R149 */
 184         0x0000,     /* R150 */
 185         0x0000,     /* R151 */
 186         0x0000,     /* R152 */
 187         0x0000,     /* R153 */
 188         0x0000,     /* R154 */
 189         0x0000,     /* R155 */
 190         0x0000,     /* R156 */
 191         0x0000,     /* R157 */
 192         0x0000,     /* R158 */
 193         0x0000,     /* R159 */
 194         0x0000,     /* R160 */
 195         0x0000,     /* R161 */
 196         0x0000,     /* R162 */
 197         0x0000,     /* R163 */
 198         0x0000,     /* R164 */
 199         0x0000,     /* R165 */
 200         0x0000,     /* R166 */
 201         0x0000,     /* R167 */
 202         0x0000,     /* R168 */
 203         0x0000,     /* R169 */
 204         0x0000,     /* R170 */
 205         0x0000,     /* R171 */
 206         0x0000,     /* R172 */
 207         0x0000,     /* R173 */
 208         0x0000,     /* R174 */
 209         0x0000,     /* R175 */
 210         0x0000,     /* R176 */
 211         0x0000,     /* R177 */
 212         0x0000,     /* R178 */
 213         0x0000,     /* R179 */
 214         0x0000,     /* R180 */
 215         0x0000,     /* R181 */
 216         0x0000,     /* R182 */
 217         0x0000,     /* R183 */
 218         0x0000,     /* R184 */
 219         0x0000,     /* R185 */
 220         0x0000,     /* R186 */
 221         0x0000,     /* R187 */
 222         0x0000,     /* R188 */
 223         0x0000,     /* R189 */
 224         0x0000,     /* R190 */
 225         0x0000,     /* R191 */
 226         0x0000,     /* R192 */
 227         0x0000,     /* R193 */
 228         0x0000,     /* R194 */
 229         0x0000,     /* R195 */
 230         0x0030,     /* R196 */
 231         0x0006,     /* R197 */
 232         0x0000,     /* R198 */
 233         0x0060,     /* R199 */
 234         0x0000,     /* R200 */
 235         0x003F,     /* R201 */
 236         0x0000,     /* R202 */
 237         0x0000,     /* R203 */
 238         0x0000,     /* R204 */
 239         0x0001,     /* R205 */
 240         0x0000,     /* R206 */
 241         0x0181,     /* R207 */
 242         0x0005,     /* R208 */
 243         0x0008,     /* R209 */
 244         0x0008,     /* R210 */
 245         0x0000,     /* R211 */
 246         0x013B,     /* R212 */
 247         0x0000,     /* R213 */
 248         0x0000,     /* R214 */
 249         0x0000,     /* R215 */
 250         0x0000,     /* R216 */
 251         0x0070,     /* R217 */
 252         0x0000,     /* R218 */
 253         0x0000,     /* R219 */
 254         0x0000,     /* R220 */
 255         0x0000,     /* R221 */
 256         0x0000,     /* R222 */
 257         0x0003,     /* R223 */
 258         0x0000,     /* R224 */
 259         0x0000,     /* R225 */
 260         0x0001,     /* R226 */
 261         0x0008,     /* R227 */
 262         0x0000,     /* R228 */
 263         0x0000,     /* R229 */
 264         0x0000,     /* R230 */
 265         0x0000,     /* R231 */
 266         0x0004,     /* R232 */
 267         0x0000,     /* R233 */
 268         0x0000,     /* R234 */
 269         0x0000,     /* R235 */
 270         0x0000,     /* R236 */
 271         0x0000,     /* R237 */
 272         0x0080,     /* R238 */
 273         0x0000,     /* R239 */
 274         0x0000,     /* R240 */
 275         0x0000,     /* R241 */
 276         0x0000,     /* R242 */
 277         0x0000,     /* R243 */
 278         0x0000,     /* R244 */
 279         0x0052,     /* R245 */
 280         0x0110,     /* R246 */
 281         0x0040,     /* R247 */
 282         0x0000,     /* R248 */
 283         0x0030,     /* R249 */
 284         0x0000,     /* R250 */
 285         0x0000,     /* R251 */
 286         0x0001,     /* R252 - General test 1 */
 287 };
 288
 289 struct wm8961_priv {
 290         enum snd_soc_control_type control_type;
 291         int sysclk;
 292 };
 293
 294 static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
 295 {
 296         switch (reg) {
 297         case WM8961_SOFTWARE_RESET:
 298         case WM8961_WRITE_SEQUENCER_7:
 299         case WM8961_DC_SERVO_1:
 300                 return 1;
 301
 302         default:
 303                 return 0;
 304         }
 305 }
 306
 307 static int wm8961_reset(struct snd_soc_codec *codec)
 308 {
 309         return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
 310 }
 311
 312 /*
 313  * The headphone output supports special anti-pop sequences giving
 314  * silent power up and power down.
 315  */
 316 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
 317                            struct snd_kcontrol *kcontrol, int event)
 318 {
 319         struct snd_soc_codec *codec = w->codec;
 320         u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
 321         u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
 322         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 323         u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 324         int timeout = 500;
 325
 326         if (event & SND_SOC_DAPM_POST_PMU) {
 327                 /* Make sure the output is shorted */
 328                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 329                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 330
 331                 /* Enable the charge pump */
 332                 cp_reg |= WM8961_CP_ENA;
 333                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
 334                 mdelay(5);
 335
 336                 /* Enable the PGA */
 337                 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
 338                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 339
 340                 /* Enable the amplifier */
 341                 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
 342                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 343
 344                 /* Second stage enable */
 345                 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
 346                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 347
 348                 /* Enable the DC servo & trigger startup */
 349                 dcs_reg |=
 350                         WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
 351                         WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
 352                 dev_dbg(codec->dev, "Enabling DC servo\n");
 353
 354                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 355                 do {
 356                         msleep(1);
 357                         dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 358                 } while (--timeout &&
 359                          dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 360                                 WM8961_DCS_TRIG_STARTUP_HPL));
 361                 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 362                                WM8961_DCS_TRIG_STARTUP_HPL))
 363                         dev_err(codec->dev, "DC servo timed out\n");
 364                 else
 365                         dev_dbg(codec->dev, "DC servo startup complete\n");
 366
 367                 /* Enable the output stage */
 368                 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
 369                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 370
 371                 /* Remove the short on the output stage */
 372                 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
 373                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 374         }
 375
 376         if (event & SND_SOC_DAPM_PRE_PMD) {
 377                 /* Short the output */
 378                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 379                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 380
 381                 /* Disable the output stage */
 382                 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
 383                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 384
 385                 /* Disable DC offset cancellation */
 386                 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
 387                              WM8961_DCS_ENA_CHAN_HPL);
 388                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 389
 390                 /* Finish up */
 391                 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
 392                             WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
 393                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 394
 395                 /* Disable the PGA */
 396                 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
 397                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 398
 399                 /* Disable the charge pump */
 400                 dev_dbg(codec->dev, "Disabling charge pump\n");
 401                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
 402                              cp_reg & ~WM8961_CP_ENA);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
 409                             struct snd_kcontrol *kcontrol, int event)
 410 {
 411         struct snd_soc_codec *codec = w->codec;
 412         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 413         u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
 414
 415         if (event & SND_SOC_DAPM_POST_PMU) {
 416                 /* Enable the PGA */
 417                 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
 418                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 419
 420                 /* Enable the amplifier */
 421                 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
 422                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 423         }
 424
 425         if (event & SND_SOC_DAPM_PRE_PMD) {
 426                 /* Enable the amplifier */
 427                 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
 428                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 429
 430                 /* Enable the PGA */
 431                 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
 432                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 433         }
 434
 435         return 0;
 436 }
 437
 438 static const char *adc_hpf_text[] = {
 439         "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
 440 };
 441
 442 static const struct soc_enum adc_hpf =
 443         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
 444
 445 static const char *dac_deemph_text[] = {
 446         "None", "32kHz", "44.1kHz", "48kHz",
 447 };
 448
 449 static const struct soc_enum dac_deemph =
 450         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
 451
 452 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 453 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
 454 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 455 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 456 static unsigned int boost_tlv[] = {
 457         TLV_DB_RANGE_HEAD(4),
 458         0, 0, TLV_DB_SCALE_ITEM(0,  0, 0),
 459         1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
 460         2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
 461         3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
 462 };
 463 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
 464
 465 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
 466 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 467                  0, 127, 0, out_tlv),
 468 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
 469                6, 3, 7, 0, hp_sec_tlv),
 470 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 471              7, 1, 0),
 472
 473 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 474                  0, 127, 0, out_tlv),
 475 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 476            7, 1, 0),
 477 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
 478
 479 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
 480 SOC_ENUM("DAC Deemphasis", dac_deemph),
 481 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
 482
 483 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
 484                  WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
 485
 486 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
 487 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 488
 489 SOC_DOUBLE_R_TLV("Capture Volume",
 490                  WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
 491                  1, 119, 0, adc_tlv),
 492 SOC_DOUBLE_R_TLV("Capture Boost Volume",
 493                  WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
 494                  4, 3, 0, boost_tlv),
 495 SOC_DOUBLE_R_TLV("Capture PGA Volume",
 496                  WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 497                  0, 62, 0, pga_tlv),
 498 SOC_DOUBLE_R("Capture PGA ZC Switch",
 499              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 500              6, 1, 1),
 501 SOC_DOUBLE_R("Capture PGA Switch",
 502              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 503              7, 1, 1),
 504 };
 505
 506 static const char *sidetone_text[] = {
 507         "None", "Left", "Right"
 508 };
 509
 510 static const struct soc_enum dacl_sidetone =
 511         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
 512
 513 static const struct soc_enum dacr_sidetone =
 514         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
 515
 516 static const struct snd_kcontrol_new dacl_mux =
 517         SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
 518
 519 static const struct snd_kcontrol_new dacr_mux =
 520         SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
 521
 522 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
 523 SND_SOC_DAPM_INPUT("LINPUT"),
 524 SND_SOC_DAPM_INPUT("RINPUT"),
 525
 526 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
 527
 528 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
 529 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
 530
 531 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
 532 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
 533
 534 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
 535
 536 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
 537 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
 538
 539 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
 540 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
 541
 542 /* Handle as a mono path for DCS */
 543 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
 544                    4, 0, NULL, 0, wm8961_hp_event,
 545                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 546 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
 547                    4, 0, NULL, 0, wm8961_spk_event,
 548                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 549
 550 SND_SOC_DAPM_OUTPUT("HP_L"),
 551 SND_SOC_DAPM_OUTPUT("HP_R"),
 552 SND_SOC_DAPM_OUTPUT("SPK_LN"),
 553 SND_SOC_DAPM_OUTPUT("SPK_LP"),
 554 SND_SOC_DAPM_OUTPUT("SPK_RN"),
 555 SND_SOC_DAPM_OUTPUT("SPK_RP"),
 556 };
 557
 558
 559 static const struct snd_soc_dapm_route audio_paths[] = {
 560         { "DACL", NULL, "CLK_DSP" },
 561         { "DACL", NULL, "DACL Sidetone" },
 562         { "DACR", NULL, "CLK_DSP" },
 563         { "DACR", NULL, "DACR Sidetone" },
 564
 565         { "DACL Sidetone", "Left", "ADCL" },
 566         { "DACL Sidetone", "Right", "ADCR" },
 567
 568         { "DACR Sidetone", "Left", "ADCL" },
 569         { "DACR Sidetone", "Right", "ADCR" },
 570
 571         { "HP_L", NULL, "Headphone Output" },
 572         { "HP_R", NULL, "Headphone Output" },
 573         { "Headphone Output", NULL, "DACL" },
 574         { "Headphone Output", NULL, "DACR" },
 575
 576         { "SPK_LN", NULL, "Speaker Output" },
 577         { "SPK_LP", NULL, "Speaker Output" },
 578         { "SPK_RN", NULL, "Speaker Output" },
 579         { "SPK_RP", NULL, "Speaker Output" },
 580
 581         { "Speaker Output", NULL, "DACL" },
 582         { "Speaker Output", NULL, "DACR" },
 583
 584         { "ADCL", NULL, "Left Input" },
 585         { "ADCL", NULL, "CLK_DSP" },
 586         { "ADCR", NULL, "Right Input" },
 587         { "ADCR", NULL, "CLK_DSP" },
 588
 589         { "Left Input", NULL, "LINPUT" },
 590         { "Right Input", NULL, "RINPUT" },
 591
 592 };
 593
 594 /* Values for CLK_SYS_RATE */
 595 static struct {
 596         int ratio;
 597         u16 val;
 598 } wm8961_clk_sys_ratio[] = {
 599         {  64,  0 },
 600         {  128, 1 },
 601         {  192, 2 },
 602         {  256, 3 },
 603         {  384, 4 },
 604         {  512, 5 },
 605         {  768, 6 },
 606         { 1024, 7 },
 607         { 1408, 8 },
 608         { 1536, 9 },
 609 };
 610
 611 /* Values for SAMPLE_RATE */
 612 static struct {
 613         int rate;
 614         u16 val;
 615 } wm8961_srate[] = {
 616         { 48000, 0 },
 617         { 44100, 0 },
 618         { 32000, 1 },
 619         { 22050, 2 },
 620         { 24000, 2 },
 621         { 16000, 3 },
 622         { 11250, 4 },
 623         { 12000, 4 },
 624         {  8000, 5 },
 625 };
 626
 627 static int wm8961_hw_params(struct snd_pcm_substream *substream,
 628                             struct snd_pcm_hw_params *params,
 629                             struct snd_soc_dai *dai)
 630 {
 631         struct snd_soc_codec *codec = dai->codec;
 632         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 633         int i, best, target, fs;
 634         u16 reg;
 635
 636         fs = params_rate(params);
 637
 638         if (!wm8961->sysclk) {
 639                 dev_err(codec->dev, "MCLK has not been specified\n");
 640                 return -EINVAL;
 641         }
 642
 643         /* Find the closest sample rate for the filters */
 644         best = 0;
 645         for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
 646                 if (abs(wm8961_srate[i].rate - fs) <
 647                     abs(wm8961_srate[best].rate - fs))
 648                         best = i;
 649         }
 650         reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
 651         reg &= ~WM8961_SAMPLE_RATE_MASK;
 652         reg |= wm8961_srate[best].val;
 653         snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
 654         dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
 655                 wm8961_srate[best].rate, fs);
 656
 657         /* Select a CLK_SYS/fs ratio equal to or higher than required */
 658         target = wm8961->sysclk / fs;
 659
 660         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
 661                 dev_err(codec->dev,
 662                         "SYSCLK must be at least 64*fs for DAC\n");
 663                 return -EINVAL;
 664         }
 665         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
 666                 dev_err(codec->dev,
 667                         "SYSCLK must be at least 256*fs for ADC\n");
 668                 return -EINVAL;
 669         }
 670
 671         for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
 672                 if (wm8961_clk_sys_ratio[i].ratio >= target)
 673                         break;
 674         }
 675         if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
 676                 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
 677                 return -EINVAL;
 678         }
 679         dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
 680                 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
 681                 wm8961->sysclk / fs);
 682
 683         reg = snd_soc_read(codec, WM8961_CLOCKING_4);
 684         reg &= ~WM8961_CLK_SYS_RATE_MASK;
 685         reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
 686         snd_soc_write(codec, WM8961_CLOCKING_4, reg);
 687
 688         reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 689         reg &= ~WM8961_WL_MASK;
 690         switch (params_format(params)) {
 691         case SNDRV_PCM_FORMAT_S16_LE:
 692                 break;
 693         case SNDRV_PCM_FORMAT_S20_3LE:
 694                 reg |= 1 << WM8961_WL_SHIFT;
 695                 break;
 696         case SNDRV_PCM_FORMAT_S24_LE:
 697                 reg |= 2 << WM8961_WL_SHIFT;
 698                 break;
 699         case SNDRV_PCM_FORMAT_S32_LE:
 700                 reg |= 3 << WM8961_WL_SHIFT;
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705         snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
 706
 707         /* Sloping stop-band filter is recommended for <= 24kHz */
 708         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
 709         if (fs <= 24000)
 710                 reg |= WM8961_DACSLOPE;
 711         else
 712                 reg &= ~WM8961_DACSLOPE;
 713         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 714
 715         return 0;
 716 }
 717
 718 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 719                              unsigned int freq,
 720                              int dir)
 721 {
 722         struct snd_soc_codec *codec = dai->codec;
 723         struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
 724         u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
 725
 726         if (freq > 33000000) {
 727                 dev_err(codec->dev, "MCLK must be <33MHz\n");
 728                 return -EINVAL;
 729         }
 730
 731         if (freq > 16500000) {
 732                 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
 733                 reg |= WM8961_MCLKDIV;
 734                 freq /= 2;
 735         } else {
 736                 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
 737                 reg &= ~WM8961_MCLKDIV;
 738         }
 739
 740         snd_soc_write(codec, WM8961_CLOCKING1, reg);
 741
 742         wm8961->sysclk = freq;
 743
 744         return 0;
 745 }
 746
 747 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 748 {
 749         struct snd_soc_codec *codec = dai->codec;
 750         u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 751
 752         aif &= ~(WM8961_BCLKINV | WM8961_LRP |
 753                  WM8961_MS | WM8961_FORMAT_MASK);
 754
 755         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 756         case SND_SOC_DAIFMT_CBM_CFM:
 757                 aif |= WM8961_MS;
 758                 break;
 759         case SND_SOC_DAIFMT_CBS_CFS:
 760                 break;
 761         default:
 762                 return -EINVAL;
 763         }
 764
 765         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 766         case SND_SOC_DAIFMT_RIGHT_J:
 767                 break;
 768
 769         case SND_SOC_DAIFMT_LEFT_J:
 770                 aif |= 1;
 771                 break;
 772
 773         case SND_SOC_DAIFMT_I2S:
 774                 aif |= 2;
 775                 break;
 776
 777         case SND_SOC_DAIFMT_DSP_B:
 778                 aif |= WM8961_LRP;
 779         case SND_SOC_DAIFMT_DSP_A:
 780                 aif |= 3;
 781                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 782                 case SND_SOC_DAIFMT_NB_NF:
 783                 case SND_SOC_DAIFMT_IB_NF:
 784                         break;
 785                 default:
 786                         return -EINVAL;
 787                 }
 788                 break;
 789
 790         default:
 791                 return -EINVAL;
 792         }
 793
 794         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 795         case SND_SOC_DAIFMT_NB_NF:
 796                 break;
 797         case SND_SOC_DAIFMT_NB_IF:
 798                 aif |= WM8961_LRP;
 799                 break;
 800         case SND_SOC_DAIFMT_IB_NF:
 801                 aif |= WM8961_BCLKINV;
 802                 break;
 803         case SND_SOC_DAIFMT_IB_IF:
 804                 aif |= WM8961_BCLKINV | WM8961_LRP;
 805                 break;
 806         default:
 807                 return -EINVAL;
 808         }
 809
 810         return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
 811 }
 812
 813 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
 814 {
 815         struct snd_soc_codec *codec = dai->codec;
 816         u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
 817
 818         if (tristate)
 819                 reg |= WM8961_TRIS;
 820         else
 821                 reg &= ~WM8961_TRIS;
 822
 823         return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
 824 }
 825
 826 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
 827 {
 828         struct snd_soc_codec *codec = dai->codec;
 829         u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
 830
 831         if (mute)
 832                 reg |= WM8961_DACMU;
 833         else
 834                 reg &= ~WM8961_DACMU;
 835
 836         msleep(17);
 837
 838         return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
 839 }
 840
 841 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
 842 {
 843         struct snd_soc_codec *codec = dai->codec;
 844         u16 reg;
 845
 846         switch (div_id) {
 847         case WM8961_BCLK:
 848                 reg = snd_soc_read(codec, WM8961_CLOCKING2);
 849                 reg &= ~WM8961_BCLKDIV_MASK;
 850                 reg |= div;
 851                 snd_soc_write(codec, WM8961_CLOCKING2, reg);
 852                 break;
 853
 854         case WM8961_LRCLK:
 855                 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
 856                 reg &= ~WM8961_LRCLK_RATE_MASK;
 857                 reg |= div;
 858                 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
 859                 break;
 860
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
 869                                  enum snd_soc_bias_level level)
 870 {
 871         u16 reg;
 872
 873         /* This is all slightly unusual since we have no bypass paths
 874          * and the output amplifier structure means we can just slam
 875          * the biases straight up rather than having to ramp them
 876          * slowly.
 877          */
 878         switch (level) {
 879         case SND_SOC_BIAS_ON:
 880                 break;
 881
 882         case SND_SOC_BIAS_PREPARE:
 883                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
 884                         /* Enable bias generation */
 885                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 886                         reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
 887                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 888
 889                         /* VMID=2*50k, VREF */
 890                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 891                         reg &= ~WM8961_VMIDSEL_MASK;
 892                         reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
 893                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 894                 }
 895                 break;
 896
 897         case SND_SOC_BIAS_STANDBY:
 898                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
 899                         /* VREF off */
 900                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 901                         reg &= ~WM8961_VREF;
 902                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 903
 904                         /* Bias generation off */
 905                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 906                         reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
 907                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 908
 909                         /* VMID off */
 910                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 911                         reg &= ~WM8961_VMIDSEL_MASK;
 912                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 913                 }
 914                 break;
 915
 916         case SND_SOC_BIAS_OFF:
 917                 break;
 918         }
 919
 920         codec->dapm.bias_level = level;
 921
 922         return 0;
 923 }
 924
 925
 926 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
 927
 928 #define WM8961_FORMATS \
 929         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 930         SNDRV_PCM_FMTBIT_S24_LE)
 931
 932 static struct snd_soc_dai_ops wm8961_dai_ops = {
 933         .hw_params = wm8961_hw_params,
 934         .set_sysclk = wm8961_set_sysclk,
 935         .set_fmt = wm8961_set_fmt,
 936         .digital_mute = wm8961_digital_mute,
 937         .set_tristate = wm8961_set_tristate,
 938         .set_clkdiv = wm8961_set_clkdiv,
 939 };
 940
 941 static struct snd_soc_dai_driver wm8961_dai = {
 942         .name = "wm8961-hifi",
 943         .playback = {
 944                 .stream_name = "HiFi Playback",
 945                 .channels_min = 1,
 946                 .channels_max = 2,
 947                 .rates = WM8961_RATES,
 948                 .formats = WM8961_FORMATS,},
 949         .capture = {
 950                 .stream_name = "HiFi Capture",
 951                 .channels_min = 1,
 952                 .channels_max = 2,
 953                 .rates = WM8961_RATES,
 954                 .formats = WM8961_FORMATS,},
 955         .ops = &wm8961_dai_ops,
 956 };
 957
 958 static int wm8961_probe(struct snd_soc_codec *codec)
 959 {
 960         struct snd_soc_dapm_context *dapm = &codec->dapm;
 961         int ret = 0;
 962         u16 reg;
 963
 964         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
 965         if (ret != 0) {
 966                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 967                 return ret;
 968         }
 969
 970         reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
 971         if (reg != 0x1801) {
 972                 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
 973                 return -EINVAL;
 974         }
 975
 976         /* This isn't volatile - readback doesn't correspond to write */
 977         codec->cache_bypass = 1;
 978         reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
 979         codec->cache_bypass = 0;
 980         dev_info(codec->dev, "WM8961 family %d revision %c\n",
 981                  (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
 982                  ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
 983                  + 'A');
 984
 985         ret = wm8961_reset(codec);
 986         if (ret < 0) {
 987                 dev_err(codec->dev, "Failed to issue reset\n");
 988                 return ret;
 989         }
 990
 991         /* Enable class W */
 992         reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
 993         reg |= WM8961_CP_DYN_PWR_MASK;
 994         snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
 995
 996         /* Latch volume update bits (right channel only, we always
 997          * write both out) and default ZC on. */
 998         reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
 999         snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1000                      reg | WM8961_LO1ZC | WM8961_OUT1VU);
1001         snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1002         reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1003         snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1004                      reg | WM8961_SPKRZC | WM8961_SPKVU);
1005         snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1006
1007         reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1008         snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1009         reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1010         snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1011
1012         /* Use soft mute by default */
1013         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1014         reg |= WM8961_DACSMM;
1015         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1016
1017         /* Use automatic clocking mode by default; for now this is all
1018          * we support.
1019          */
1020         reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1021         reg &= ~WM8961_MANUAL_MODE;
1022         snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1023
1024         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1025
1026         snd_soc_add_controls(codec, wm8961_snd_controls,
1027                                 ARRAY_SIZE(wm8961_snd_controls));
1028         snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
1029                                   ARRAY_SIZE(wm8961_dapm_widgets));
1030         snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
1031
1032         return 0;
1033 }
1034
1035 static int wm8961_remove(struct snd_soc_codec *codec)
1036 {
1037         wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1038         return 0;
1039 }
1040
1041 #ifdef CONFIG_PM
1042 static int wm8961_suspend(struct snd_soc_codec *codec, pm_message_t state)
1043 {
1044         wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1045
1046         return 0;
1047 }
1048
1049 static int wm8961_resume(struct snd_soc_codec *codec)
1050 {
1051         u16 *reg_cache = codec->reg_cache;
1052         int i;
1053
1054         for (i = 0; i < codec->driver->reg_cache_size; i++) {
1055                 if (reg_cache[i] == wm8961_reg_defaults[i])
1056                         continue;
1057
1058                 if (i == WM8961_SOFTWARE_RESET)
1059                         continue;
1060
1061                 snd_soc_write(codec, i, reg_cache[i]);
1062         }
1063
1064         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1065
1066         return 0;
1067 }
1068 #else
1069 #define wm8961_suspend NULL
1070 #define wm8961_resume NULL
1071 #endif
1072
1073 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1074         .probe =        wm8961_probe,
1075         .remove =       wm8961_remove,
1076         .suspend =      wm8961_suspend,
1077         .resume =       wm8961_resume,
1078         .set_bias_level = wm8961_set_bias_level,
1079         .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
1080         .reg_word_size = sizeof(u16),
1081         .reg_cache_default = wm8961_reg_defaults,
1082         .volatile_register = wm8961_volatile_register,
1083 };
1084
1085 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1086 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1087                                       const struct i2c_device_id *id)
1088 {
1089         struct wm8961_priv *wm8961;
1090         int ret;
1091
1092         wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1093         if (wm8961 == NULL)
1094                 return -ENOMEM;
1095
1096         i2c_set_clientdata(i2c, wm8961);
1097
1098         ret = snd_soc_register_codec(&i2c->dev,
1099                         &soc_codec_dev_wm8961, &wm8961_dai, 1);
1100         if (ret < 0)
1101                 kfree(wm8961);
1102         return ret;
1103 }
1104
1105 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1106 {
1107         snd_soc_unregister_codec(&client->dev);
1108         kfree(i2c_get_clientdata(client));
1109         return 0;
1110 }
1111
1112 static const struct i2c_device_id wm8961_i2c_id[] = {
1113         { "wm8961", 0 },
1114         { }
1115 };
1116 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1117
1118 static struct i2c_driver wm8961_i2c_driver = {
1119         .driver = {
1120                 .name = "wm8961-codec",
1121                 .owner = THIS_MODULE,
1122         },
1123         .probe =    wm8961_i2c_probe,
1124         .remove =   __devexit_p(wm8961_i2c_remove),
1125         .id_table = wm8961_i2c_id,
1126 };
1127 #endif
1128
1129 static int __init wm8961_modinit(void)
1130 {
1131         int ret = 0;
1132 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1133         ret = i2c_add_driver(&wm8961_i2c_driver);
1134         if (ret != 0) {
1135                 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
1136                        ret);
1137         }
1138 #endif
1139         return ret;
1140 }
1141 module_init(wm8961_modinit);
1142
1143 static void __exit wm8961_exit(void)
1144 {
1145 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1146         i2c_del_driver(&wm8961_i2c_driver);
1147 #endif
1148 }
1149 module_exit(wm8961_exit);
1150
1151 MODULE_DESCRIPTION("ASoC WM8961 driver");
1152 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1153 MODULE_LICENSE("GPL");