sound/soc/codecs/wm8961.c

   1 /*
   2  * wm8961.c  --  WM8961 ALSA SoC Audio driver
   3  *
   4  * Author: Mark Brown
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Currently unimplemented features:
  11  *  - ALC
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27 #include <sound/tlv.h>
  28
  29 #include "wm8961.h"
  30
  31 #define WM8961_MAX_REGISTER                     0xFC
  32
  33 static u16 wm8961_reg_defaults[] = {
  34         0x009F,     /* R0   - Left Input volume */
  35         0x009F,     /* R1   - Right Input volume */
  36         0x0000,     /* R2   - LOUT1 volume */
  37         0x0000,     /* R3   - ROUT1 volume */
  38         0x0020,     /* R4   - Clocking1 */
  39         0x0008,     /* R5   - ADC & DAC Control 1 */
  40         0x0000,     /* R6   - ADC & DAC Control 2 */
  41         0x000A,     /* R7   - Audio Interface 0 */
  42         0x01F4,     /* R8   - Clocking2 */
  43         0x0000,     /* R9   - Audio Interface 1 */
  44         0x00FF,     /* R10  - Left DAC volume */
  45         0x00FF,     /* R11  - Right DAC volume */
  46         0x0000,     /* R12 */
  47         0x0000,     /* R13 */
  48         0x0040,     /* R14  - Audio Interface 2 */
  49         0x0000,     /* R15  - Software Reset */
  50         0x0000,     /* R16 */
  51         0x007B,     /* R17  - ALC1 */
  52         0x0000,     /* R18  - ALC2 */
  53         0x0032,     /* R19  - ALC3 */
  54         0x0000,     /* R20  - Noise Gate */
  55         0x00C0,     /* R21  - Left ADC volume */
  56         0x00C0,     /* R22  - Right ADC volume */
  57         0x0120,     /* R23  - Additional control(1) */
  58         0x0000,     /* R24  - Additional control(2) */
  59         0x0000,     /* R25  - Pwr Mgmt (1) */
  60         0x0000,     /* R26  - Pwr Mgmt (2) */
  61         0x0000,     /* R27  - Additional Control (3) */
  62         0x0000,     /* R28  - Anti-pop */
  63         0x0000,     /* R29 */
  64         0x005F,     /* R30  - Clocking 3 */
  65         0x0000,     /* R31 */
  66         0x0000,     /* R32  - ADCL signal path */
  67         0x0000,     /* R33  - ADCR signal path */
  68         0x0000,     /* R34 */
  69         0x0000,     /* R35 */
  70         0x0000,     /* R36 */
  71         0x0000,     /* R37 */
  72         0x0000,     /* R38 */
  73         0x0000,     /* R39 */
  74         0x0000,     /* R40  - LOUT2 volume */
  75         0x0000,     /* R41  - ROUT2 volume */
  76         0x0000,     /* R42 */
  77         0x0000,     /* R43 */
  78         0x0000,     /* R44 */
  79         0x0000,     /* R45 */
  80         0x0000,     /* R46 */
  81         0x0000,     /* R47  - Pwr Mgmt (3) */
  82         0x0023,     /* R48  - Additional Control (4) */
  83         0x0000,     /* R49  - Class D Control 1 */
  84         0x0000,     /* R50 */
  85         0x0003,     /* R51  - Class D Control 2 */
  86         0x0000,     /* R52 */
  87         0x0000,     /* R53 */
  88         0x0000,     /* R54 */
  89         0x0000,     /* R55 */
  90         0x0106,     /* R56  - Clocking 4 */
  91         0x0000,     /* R57  - DSP Sidetone 0 */
  92         0x0000,     /* R58  - DSP Sidetone 1 */
  93         0x0000,     /* R59 */
  94         0x0000,     /* R60  - DC Servo 0 */
  95         0x0000,     /* R61  - DC Servo 1 */
  96         0x0000,     /* R62 */
  97         0x015E,     /* R63  - DC Servo 3 */
  98         0x0010,     /* R64 */
  99         0x0010,     /* R65  - DC Servo 5 */
 100         0x0000,     /* R66 */
 101         0x0001,     /* R67 */
 102         0x0003,     /* R68  - Analogue PGA Bias */
 103         0x0000,     /* R69  - Analogue HP 0 */
 104         0x0060,     /* R70 */
 105         0x01FB,     /* R71  - Analogue HP 2 */
 106         0x0000,     /* R72  - Charge Pump 1 */
 107         0x0065,     /* R73 */
 108         0x005F,     /* R74 */
 109         0x0059,     /* R75 */
 110         0x006B,     /* R76 */
 111         0x0038,     /* R77 */
 112         0x000C,     /* R78 */
 113         0x000A,     /* R79 */
 114         0x006B,     /* R80 */
 115         0x0000,     /* R81 */
 116         0x0000,     /* R82  - Charge Pump B */
 117         0x0087,     /* R83 */
 118         0x0000,     /* R84 */
 119         0x005C,     /* R85 */
 120         0x0000,     /* R86 */
 121         0x0000,     /* R87  - Write Sequencer 1 */
 122         0x0000,     /* R88  - Write Sequencer 2 */
 123         0x0000,     /* R89  - Write Sequencer 3 */
 124         0x0000,     /* R90  - Write Sequencer 4 */
 125         0x0000,     /* R91  - Write Sequencer 5 */
 126         0x0000,     /* R92  - Write Sequencer 6 */
 127         0x0000,     /* R93  - Write Sequencer 7 */
 128         0x0000,     /* R94 */
 129         0x0000,     /* R95 */
 130         0x0000,     /* R96 */
 131         0x0000,     /* R97 */
 132         0x0000,     /* R98 */
 133         0x0000,     /* R99 */
 134         0x0000,     /* R100 */
 135         0x0000,     /* R101 */
 136         0x0000,     /* R102 */
 137         0x0000,     /* R103 */
 138         0x0000,     /* R104 */
 139         0x0000,     /* R105 */
 140         0x0000,     /* R106 */
 141         0x0000,     /* R107 */
 142         0x0000,     /* R108 */
 143         0x0000,     /* R109 */
 144         0x0000,     /* R110 */
 145         0x0000,     /* R111 */
 146         0x0000,     /* R112 */
 147         0x0000,     /* R113 */
 148         0x0000,     /* R114 */
 149         0x0000,     /* R115 */
 150         0x0000,     /* R116 */
 151         0x0000,     /* R117 */
 152         0x0000,     /* R118 */
 153         0x0000,     /* R119 */
 154         0x0000,     /* R120 */
 155         0x0000,     /* R121 */
 156         0x0000,     /* R122 */
 157         0x0000,     /* R123 */
 158         0x0000,     /* R124 */
 159         0x0000,     /* R125 */
 160         0x0000,     /* R126 */
 161         0x0000,     /* R127 */
 162         0x0000,     /* R128 */
 163         0x0000,     /* R129 */
 164         0x0000,     /* R130 */
 165         0x0000,     /* R131 */
 166         0x0000,     /* R132 */
 167         0x0000,     /* R133 */
 168         0x0000,     /* R134 */
 169         0x0000,     /* R135 */
 170         0x0000,     /* R136 */
 171         0x0000,     /* R137 */
 172         0x0000,     /* R138 */
 173         0x0000,     /* R139 */
 174         0x0000,     /* R140 */
 175         0x0000,     /* R141 */
 176         0x0000,     /* R142 */
 177         0x0000,     /* R143 */
 178         0x0000,     /* R144 */
 179         0x0000,     /* R145 */
 180         0x0000,     /* R146 */
 181         0x0000,     /* R147 */
 182         0x0000,     /* R148 */
 183         0x0000,     /* R149 */
 184         0x0000,     /* R150 */
 185         0x0000,     /* R151 */
 186         0x0000,     /* R152 */
 187         0x0000,     /* R153 */
 188         0x0000,     /* R154 */
 189         0x0000,     /* R155 */
 190         0x0000,     /* R156 */
 191         0x0000,     /* R157 */
 192         0x0000,     /* R158 */
 193         0x0000,     /* R159 */
 194         0x0000,     /* R160 */
 195         0x0000,     /* R161 */
 196         0x0000,     /* R162 */
 197         0x0000,     /* R163 */
 198         0x0000,     /* R164 */
 199         0x0000,     /* R165 */
 200         0x0000,     /* R166 */
 201         0x0000,     /* R167 */
 202         0x0000,     /* R168 */
 203         0x0000,     /* R169 */
 204         0x0000,     /* R170 */
 205         0x0000,     /* R171 */
 206         0x0000,     /* R172 */
 207         0x0000,     /* R173 */
 208         0x0000,     /* R174 */
 209         0x0000,     /* R175 */
 210         0x0000,     /* R176 */
 211         0x0000,     /* R177 */
 212         0x0000,     /* R178 */
 213         0x0000,     /* R179 */
 214         0x0000,     /* R180 */
 215         0x0000,     /* R181 */
 216         0x0000,     /* R182 */
 217         0x0000,     /* R183 */
 218         0x0000,     /* R184 */
 219         0x0000,     /* R185 */
 220         0x0000,     /* R186 */
 221         0x0000,     /* R187 */
 222         0x0000,     /* R188 */
 223         0x0000,     /* R189 */
 224         0x0000,     /* R190 */
 225         0x0000,     /* R191 */
 226         0x0000,     /* R192 */
 227         0x0000,     /* R193 */
 228         0x0000,     /* R194 */
 229         0x0000,     /* R195 */
 230         0x0030,     /* R196 */
 231         0x0006,     /* R197 */
 232         0x0000,     /* R198 */
 233         0x0060,     /* R199 */
 234         0x0000,     /* R200 */
 235         0x003F,     /* R201 */
 236         0x0000,     /* R202 */
 237         0x0000,     /* R203 */
 238         0x0000,     /* R204 */
 239         0x0001,     /* R205 */
 240         0x0000,     /* R206 */
 241         0x0181,     /* R207 */
 242         0x0005,     /* R208 */
 243         0x0008,     /* R209 */
 244         0x0008,     /* R210 */
 245         0x0000,     /* R211 */
 246         0x013B,     /* R212 */
 247         0x0000,     /* R213 */
 248         0x0000,     /* R214 */
 249         0x0000,     /* R215 */
 250         0x0000,     /* R216 */
 251         0x0070,     /* R217 */
 252         0x0000,     /* R218 */
 253         0x0000,     /* R219 */
 254         0x0000,     /* R220 */
 255         0x0000,     /* R221 */
 256         0x0000,     /* R222 */
 257         0x0003,     /* R223 */
 258         0x0000,     /* R224 */
 259         0x0000,     /* R225 */
 260         0x0001,     /* R226 */
 261         0x0008,     /* R227 */
 262         0x0000,     /* R228 */
 263         0x0000,     /* R229 */
 264         0x0000,     /* R230 */
 265         0x0000,     /* R231 */
 266         0x0004,     /* R232 */
 267         0x0000,     /* R233 */
 268         0x0000,     /* R234 */
 269         0x0000,     /* R235 */
 270         0x0000,     /* R236 */
 271         0x0000,     /* R237 */
 272         0x0080,     /* R238 */
 273         0x0000,     /* R239 */
 274         0x0000,     /* R240 */
 275         0x0000,     /* R241 */
 276         0x0000,     /* R242 */
 277         0x0000,     /* R243 */
 278         0x0000,     /* R244 */
 279         0x0052,     /* R245 */
 280         0x0110,     /* R246 */
 281         0x0040,     /* R247 */
 282         0x0000,     /* R248 */
 283         0x0030,     /* R249 */
 284         0x0000,     /* R250 */
 285         0x0000,     /* R251 */
 286         0x0001,     /* R252 - General test 1 */
 287 };
 288
 289 struct wm8961_priv {
 290         struct snd_soc_codec codec;
 291         int sysclk;
 292         u16 reg_cache[WM8961_MAX_REGISTER];
 293 };
 294
 295 static int wm8961_volatile_register(unsigned int reg)
 296 {
 297         switch (reg) {
 298         case WM8961_SOFTWARE_RESET:
 299         case WM8961_WRITE_SEQUENCER_7:
 300         case WM8961_DC_SERVO_1:
 301                 return 1;
 302
 303         default:
 304                 return 0;
 305         }
 306 }
 307
 308 static int wm8961_reset(struct snd_soc_codec *codec)
 309 {
 310         return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
 311 }
 312
 313 /*
 314  * The headphone output supports special anti-pop sequences giving
 315  * silent power up and power down.
 316  */
 317 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
 318                            struct snd_kcontrol *kcontrol, int event)
 319 {
 320         struct snd_soc_codec *codec = w->codec;
 321         u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
 322         u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
 323         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 324         u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 325         int timeout = 500;
 326
 327         if (event & SND_SOC_DAPM_POST_PMU) {
 328                 /* Make sure the output is shorted */
 329                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 330                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 331
 332                 /* Enable the charge pump */
 333                 cp_reg |= WM8961_CP_ENA;
 334                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
 335                 mdelay(5);
 336
 337                 /* Enable the PGA */
 338                 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
 339                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 340
 341                 /* Enable the amplifier */
 342                 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
 343                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 344
 345                 /* Second stage enable */
 346                 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
 347                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 348
 349                 /* Enable the DC servo & trigger startup */
 350                 dcs_reg |=
 351                         WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
 352                         WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
 353                 dev_dbg(codec->dev, "Enabling DC servo\n");
 354
 355                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 356                 do {
 357                         msleep(1);
 358                         dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
 359                 } while (--timeout &&
 360                          dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 361                                 WM8961_DCS_TRIG_STARTUP_HPL));
 362                 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
 363                                WM8961_DCS_TRIG_STARTUP_HPL))
 364                         dev_err(codec->dev, "DC servo timed out\n");
 365                 else
 366                         dev_dbg(codec->dev, "DC servo startup complete\n");
 367
 368                 /* Enable the output stage */
 369                 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
 370                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 371
 372                 /* Remove the short on the output stage */
 373                 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
 374                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 375         }
 376
 377         if (event & SND_SOC_DAPM_PRE_PMD) {
 378                 /* Short the output */
 379                 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
 380                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 381
 382                 /* Disable the output stage */
 383                 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
 384                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 385
 386                 /* Disable DC offset cancellation */
 387                 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
 388                              WM8961_DCS_ENA_CHAN_HPL);
 389                 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
 390
 391                 /* Finish up */
 392                 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
 393                             WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
 394                 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
 395
 396                 /* Disable the PGA */
 397                 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
 398                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 399
 400                 /* Disable the charge pump */
 401                 dev_dbg(codec->dev, "Disabling charge pump\n");
 402                 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
 403                              cp_reg & ~WM8961_CP_ENA);
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
 410                             struct snd_kcontrol *kcontrol, int event)
 411 {
 412         struct snd_soc_codec *codec = w->codec;
 413         u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
 414         u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
 415
 416         if (event & SND_SOC_DAPM_POST_PMU) {
 417                 /* Enable the PGA */
 418                 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
 419                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 420
 421                 /* Enable the amplifier */
 422                 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
 423                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 424         }
 425
 426         if (event & SND_SOC_DAPM_PRE_PMD) {
 427                 /* Enable the amplifier */
 428                 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
 429                 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
 430
 431                 /* Enable the PGA */
 432                 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
 433                 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
 434         }
 435
 436         return 0;
 437 }
 438
 439 static const char *adc_hpf_text[] = {
 440         "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
 441 };
 442
 443 static const struct soc_enum adc_hpf =
 444         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
 445
 446 static const char *dac_deemph_text[] = {
 447         "None", "32kHz", "44.1kHz", "48kHz",
 448 };
 449
 450 static const struct soc_enum dac_deemph =
 451         SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
 452
 453 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 454 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
 455 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 456 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 457 static unsigned int boost_tlv[] = {
 458         TLV_DB_RANGE_HEAD(4),
 459         0, 0, TLV_DB_SCALE_ITEM(0,  0, 0),
 460         1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
 461         2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
 462         3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
 463 };
 464 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
 465
 466 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
 467 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 468                  0, 127, 0, out_tlv),
 469 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
 470                6, 3, 7, 0, hp_sec_tlv),
 471 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
 472              7, 1, 0),
 473
 474 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 475                  0, 127, 0, out_tlv),
 476 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
 477            7, 1, 0),
 478 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
 479
 480 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
 481 SOC_ENUM("DAC Deemphasis", dac_deemph),
 482 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
 483
 484 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
 485                  WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
 486
 487 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
 488 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 489
 490 SOC_DOUBLE_R_TLV("Capture Volume",
 491                  WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
 492                  1, 119, 0, adc_tlv),
 493 SOC_DOUBLE_R_TLV("Capture Boost Volume",
 494                  WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
 495                  4, 3, 0, boost_tlv),
 496 SOC_DOUBLE_R_TLV("Capture PGA Volume",
 497                  WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 498                  0, 62, 0, pga_tlv),
 499 SOC_DOUBLE_R("Capture PGA ZC Switch",
 500              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 501              6, 1, 1),
 502 SOC_DOUBLE_R("Capture PGA Switch",
 503              WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
 504              7, 1, 1),
 505 };
 506
 507 static const char *sidetone_text[] = {
 508         "None", "Left", "Right"
 509 };
 510
 511 static const struct soc_enum dacl_sidetone =
 512         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
 513
 514 static const struct soc_enum dacr_sidetone =
 515         SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
 516
 517 static const struct snd_kcontrol_new dacl_mux =
 518         SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
 519
 520 static const struct snd_kcontrol_new dacr_mux =
 521         SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
 522
 523 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
 524 SND_SOC_DAPM_INPUT("LINPUT"),
 525 SND_SOC_DAPM_INPUT("RINPUT"),
 526
 527 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
 528
 529 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
 530 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
 531
 532 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
 533 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
 534
 535 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
 536
 537 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
 538 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
 539
 540 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
 541 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
 542
 543 /* Handle as a mono path for DCS */
 544 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
 545                    4, 0, NULL, 0, wm8961_hp_event,
 546                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 547 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
 548                    4, 0, NULL, 0, wm8961_spk_event,
 549                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 550
 551 SND_SOC_DAPM_OUTPUT("HP_L"),
 552 SND_SOC_DAPM_OUTPUT("HP_R"),
 553 SND_SOC_DAPM_OUTPUT("SPK_LN"),
 554 SND_SOC_DAPM_OUTPUT("SPK_LP"),
 555 SND_SOC_DAPM_OUTPUT("SPK_RN"),
 556 SND_SOC_DAPM_OUTPUT("SPK_RP"),
 557 };
 558
 559
 560 static const struct snd_soc_dapm_route audio_paths[] = {
 561         { "DACL", NULL, "CLK_DSP" },
 562         { "DACL", NULL, "DACL Sidetone" },
 563         { "DACR", NULL, "CLK_DSP" },
 564         { "DACR", NULL, "DACR Sidetone" },
 565
 566         { "DACL Sidetone", "Left", "ADCL" },
 567         { "DACL Sidetone", "Right", "ADCR" },
 568
 569         { "DACR Sidetone", "Left", "ADCL" },
 570         { "DACR Sidetone", "Right", "ADCR" },
 571
 572         { "HP_L", NULL, "Headphone Output" },
 573         { "HP_R", NULL, "Headphone Output" },
 574         { "Headphone Output", NULL, "DACL" },
 575         { "Headphone Output", NULL, "DACR" },
 576
 577         { "SPK_LN", NULL, "Speaker Output" },
 578         { "SPK_LP", NULL, "Speaker Output" },
 579         { "SPK_RN", NULL, "Speaker Output" },
 580         { "SPK_RP", NULL, "Speaker Output" },
 581
 582         { "Speaker Output", NULL, "DACL" },
 583         { "Speaker Output", NULL, "DACR" },
 584
 585         { "ADCL", NULL, "Left Input" },
 586         { "ADCL", NULL, "CLK_DSP" },
 587         { "ADCR", NULL, "Right Input" },
 588         { "ADCR", NULL, "CLK_DSP" },
 589
 590         { "Left Input", NULL, "LINPUT" },
 591         { "Right Input", NULL, "RINPUT" },
 592
 593 };
 594
 595 /* Values for CLK_SYS_RATE */
 596 static struct {
 597         int ratio;
 598         u16 val;
 599 } wm8961_clk_sys_ratio[] = {
 600         {  64,  0 },
 601         {  128, 1 },
 602         {  192, 2 },
 603         {  256, 3 },
 604         {  384, 4 },
 605         {  512, 5 },
 606         {  768, 6 },
 607         { 1024, 7 },
 608         { 1408, 8 },
 609         { 1536, 9 },
 610 };
 611
 612 /* Values for SAMPLE_RATE */
 613 static struct {
 614         int rate;
 615         u16 val;
 616 } wm8961_srate[] = {
 617         { 48000, 0 },
 618         { 44100, 0 },
 619         { 32000, 1 },
 620         { 22050, 2 },
 621         { 24000, 2 },
 622         { 16000, 3 },
 623         { 11250, 4 },
 624         { 12000, 4 },
 625         {  8000, 5 },
 626 };
 627
 628 static int wm8961_hw_params(struct snd_pcm_substream *substream,
 629                             struct snd_pcm_hw_params *params,
 630                             struct snd_soc_dai *dai)
 631 {
 632         struct snd_soc_codec *codec = dai->codec;
 633         struct wm8961_priv *wm8961 = codec->private_data;
 634         int i, best, target, fs;
 635         u16 reg;
 636
 637         fs = params_rate(params);
 638
 639         if (!wm8961->sysclk) {
 640                 dev_err(codec->dev, "MCLK has not been specified\n");
 641                 return -EINVAL;
 642         }
 643
 644         /* Find the closest sample rate for the filters */
 645         best = 0;
 646         for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
 647                 if (abs(wm8961_srate[i].rate - fs) <
 648                     abs(wm8961_srate[best].rate - fs))
 649                         best = i;
 650         }
 651         reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
 652         reg &= ~WM8961_SAMPLE_RATE_MASK;
 653         reg |= wm8961_srate[best].val;
 654         snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
 655         dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
 656                 wm8961_srate[best].rate, fs);
 657
 658         /* Select a CLK_SYS/fs ratio equal to or higher than required */
 659         target = wm8961->sysclk / fs;
 660
 661         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
 662                 dev_err(codec->dev,
 663                         "SYSCLK must be at least 64*fs for DAC\n");
 664                 return -EINVAL;
 665         }
 666         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
 667                 dev_err(codec->dev,
 668                         "SYSCLK must be at least 256*fs for ADC\n");
 669                 return -EINVAL;
 670         }
 671
 672         for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
 673                 if (wm8961_clk_sys_ratio[i].ratio >= target)
 674                         break;
 675         }
 676         if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
 677                 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
 678                 return -EINVAL;
 679         }
 680         dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
 681                 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
 682                 wm8961->sysclk / fs);
 683
 684         reg = snd_soc_read(codec, WM8961_CLOCKING_4);
 685         reg &= ~WM8961_CLK_SYS_RATE_MASK;
 686         reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
 687         snd_soc_write(codec, WM8961_CLOCKING_4, reg);
 688
 689         reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 690         reg &= ~WM8961_WL_MASK;
 691         switch (params_format(params)) {
 692         case SNDRV_PCM_FORMAT_S16_LE:
 693                 break;
 694         case SNDRV_PCM_FORMAT_S20_3LE:
 695                 reg |= 1 << WM8961_WL_SHIFT;
 696                 break;
 697         case SNDRV_PCM_FORMAT_S24_LE:
 698                 reg |= 2 << WM8961_WL_SHIFT;
 699                 break;
 700         case SNDRV_PCM_FORMAT_S32_LE:
 701                 reg |= 3 << WM8961_WL_SHIFT;
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706         snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
 707
 708         /* Sloping stop-band filter is recommended for <= 24kHz */
 709         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
 710         if (fs <= 24000)
 711                 reg |= WM8961_DACSLOPE;
 712         else
 713                 reg &= WM8961_DACSLOPE;
 714         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
 715
 716         return 0;
 717 }
 718
 719 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 720                              unsigned int freq,
 721                              int dir)
 722 {
 723         struct snd_soc_codec *codec = dai->codec;
 724         struct wm8961_priv *wm8961 = codec->private_data;
 725         u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
 726
 727         if (freq > 33000000) {
 728                 dev_err(codec->dev, "MCLK must be <33MHz\n");
 729                 return -EINVAL;
 730         }
 731
 732         if (freq > 16500000) {
 733                 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
 734                 reg |= WM8961_MCLKDIV;
 735                 freq /= 2;
 736         } else {
 737                 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
 738                 reg &= WM8961_MCLKDIV;
 739         }
 740
 741         snd_soc_write(codec, WM8961_CLOCKING1, reg);
 742
 743         wm8961->sysclk = freq;
 744
 745         return 0;
 746 }
 747
 748 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 749 {
 750         struct snd_soc_codec *codec = dai->codec;
 751         u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
 752
 753         aif &= ~(WM8961_BCLKINV | WM8961_LRP |
 754                  WM8961_MS | WM8961_FORMAT_MASK);
 755
 756         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 757         case SND_SOC_DAIFMT_CBM_CFM:
 758                 aif |= WM8961_MS;
 759                 break;
 760         case SND_SOC_DAIFMT_CBS_CFS:
 761                 break;
 762         default:
 763                 return -EINVAL;
 764         }
 765
 766         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 767         case SND_SOC_DAIFMT_RIGHT_J:
 768                 break;
 769
 770         case SND_SOC_DAIFMT_LEFT_J:
 771                 aif |= 1;
 772                 break;
 773
 774         case SND_SOC_DAIFMT_I2S:
 775                 aif |= 2;
 776                 break;
 777
 778         case SND_SOC_DAIFMT_DSP_B:
 779                 aif |= WM8961_LRP;
 780         case SND_SOC_DAIFMT_DSP_A:
 781                 aif |= 3;
 782                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 783                 case SND_SOC_DAIFMT_NB_NF:
 784                 case SND_SOC_DAIFMT_IB_NF:
 785                         break;
 786                 default:
 787                         return -EINVAL;
 788                 }
 789                 break;
 790
 791         default:
 792                 return -EINVAL;
 793         }
 794
 795         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 796         case SND_SOC_DAIFMT_NB_NF:
 797                 break;
 798         case SND_SOC_DAIFMT_NB_IF:
 799                 aif |= WM8961_LRP;
 800                 break;
 801         case SND_SOC_DAIFMT_IB_NF:
 802                 aif |= WM8961_BCLKINV;
 803                 break;
 804         case SND_SOC_DAIFMT_IB_IF:
 805                 aif |= WM8961_BCLKINV | WM8961_LRP;
 806                 break;
 807         default:
 808                 return -EINVAL;
 809         }
 810
 811         return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
 812 }
 813
 814 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
 815 {
 816         struct snd_soc_codec *codec = dai->codec;
 817         u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
 818
 819         if (tristate)
 820                 reg |= WM8961_TRIS;
 821         else
 822                 reg &= ~WM8961_TRIS;
 823
 824         return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
 825 }
 826
 827 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
 828 {
 829         struct snd_soc_codec *codec = dai->codec;
 830         u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
 831
 832         if (mute)
 833                 reg |= WM8961_DACMU;
 834         else
 835                 reg &= ~WM8961_DACMU;
 836
 837         msleep(17);
 838
 839         return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
 840 }
 841
 842 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
 843 {
 844         struct snd_soc_codec *codec = dai->codec;
 845         u16 reg;
 846
 847         switch (div_id) {
 848         case WM8961_BCLK:
 849                 reg = snd_soc_read(codec, WM8961_CLOCKING2);
 850                 reg &= ~WM8961_BCLKDIV_MASK;
 851                 reg |= div;
 852                 snd_soc_write(codec, WM8961_CLOCKING2, reg);
 853                 break;
 854
 855         case WM8961_LRCLK:
 856                 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
 857                 reg &= ~WM8961_LRCLK_RATE_MASK;
 858                 reg |= div;
 859                 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
 860                 break;
 861
 862         default:
 863                 return -EINVAL;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
 870                                  enum snd_soc_bias_level level)
 871 {
 872         u16 reg;
 873
 874         /* This is all slightly unusual since we have no bypass paths
 875          * and the output amplifier structure means we can just slam
 876          * the biases straight up rather than having to ramp them
 877          * slowly.
 878          */
 879         switch (level) {
 880         case SND_SOC_BIAS_ON:
 881                 break;
 882
 883         case SND_SOC_BIAS_PREPARE:
 884                 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
 885                         /* Enable bias generation */
 886                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 887                         reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
 888                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 889
 890                         /* VMID=2*50k, VREF */
 891                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 892                         reg &= ~WM8961_VMIDSEL_MASK;
 893                         reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
 894                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 895                 }
 896                 break;
 897
 898         case SND_SOC_BIAS_STANDBY:
 899                 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
 900                         /* VREF off */
 901                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 902                         reg &= ~WM8961_VREF;
 903                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 904
 905                         /* Bias generation off */
 906                         reg = snd_soc_read(codec, WM8961_ANTI_POP);
 907                         reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
 908                         snd_soc_write(codec, WM8961_ANTI_POP, reg);
 909
 910                         /* VMID off */
 911                         reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
 912                         reg &= ~WM8961_VMIDSEL_MASK;
 913                         snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
 914                 }
 915                 break;
 916
 917         case SND_SOC_BIAS_OFF:
 918                 break;
 919         }
 920
 921         codec->bias_level = level;
 922
 923         return 0;
 924 }
 925
 926
 927 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
 928
 929 #define WM8961_FORMATS \
 930         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 931         SNDRV_PCM_FMTBIT_S24_LE)
 932
 933 static struct snd_soc_dai_ops wm8961_dai_ops = {
 934         .hw_params = wm8961_hw_params,
 935         .set_sysclk = wm8961_set_sysclk,
 936         .set_fmt = wm8961_set_fmt,
 937         .digital_mute = wm8961_digital_mute,
 938         .set_tristate = wm8961_set_tristate,
 939         .set_clkdiv = wm8961_set_clkdiv,
 940 };
 941
 942 struct snd_soc_dai wm8961_dai = {
 943         .name = "WM8961",
 944         .playback = {
 945                 .stream_name = "HiFi Playback",
 946                 .channels_min = 1,
 947                 .channels_max = 2,
 948                 .rates = WM8961_RATES,
 949                 .formats = WM8961_FORMATS,},
 950         .capture = {
 951                 .stream_name = "HiFi Capture",
 952                 .channels_min = 1,
 953                 .channels_max = 2,
 954                 .rates = WM8961_RATES,
 955                 .formats = WM8961_FORMATS,},
 956         .ops = &wm8961_dai_ops,
 957 };
 958 EXPORT_SYMBOL_GPL(wm8961_dai);
 959
 960
 961 static struct snd_soc_codec *wm8961_codec;
 962
 963 static int wm8961_probe(struct platform_device *pdev)
 964 {
 965         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 966         struct snd_soc_codec *codec;
 967         int ret = 0;
 968
 969         if (wm8961_codec == NULL) {
 970                 dev_err(&pdev->dev, "Codec device not registered\n");
 971                 return -ENODEV;
 972         }
 973
 974         socdev->card->codec = wm8961_codec;
 975         codec = wm8961_codec;
 976
 977         /* register pcms */
 978         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 979         if (ret < 0) {
 980                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 981                 goto pcm_err;
 982         }
 983
 984         snd_soc_add_controls(codec, wm8961_snd_controls,
 985                                 ARRAY_SIZE(wm8961_snd_controls));
 986         snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets,
 987                                   ARRAY_SIZE(wm8961_dapm_widgets));
 988         snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
 989         snd_soc_dapm_new_widgets(codec);
 990
 991         ret = snd_soc_init_card(socdev);
 992         if (ret < 0) {
 993                 dev_err(codec->dev, "failed to register card: %d\n", ret);
 994                 goto card_err;
 995         }
 996
 997         return ret;
 998
 999 card_err:
1000         snd_soc_free_pcms(socdev);
1001         snd_soc_dapm_free(socdev);
1002 pcm_err:
1003         return ret;
1004 }
1005
1006 static int wm8961_remove(struct platform_device *pdev)
1007 {
1008         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1009
1010         snd_soc_free_pcms(socdev);
1011         snd_soc_dapm_free(socdev);
1012
1013         return 0;
1014 }
1015
1016 #ifdef CONFIG_PM
1017 static int wm8961_suspend(struct platform_device *pdev, pm_message_t state)
1018 {
1019         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1020         struct snd_soc_codec *codec = socdev->card->codec;
1021
1022         wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1023
1024         return 0;
1025 }
1026
1027 static int wm8961_resume(struct platform_device *pdev)
1028 {
1029         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1030         struct snd_soc_codec *codec = socdev->card->codec;
1031         u16 *reg_cache = codec->reg_cache;
1032         int i;
1033
1034         for (i = 0; i < codec->reg_cache_size; i++) {
1035                 if (i == WM8961_SOFTWARE_RESET)
1036                         continue;
1037
1038                 snd_soc_write(codec, i, reg_cache[i]);
1039         }
1040
1041         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1042
1043         return 0;
1044 }
1045 #else
1046 #define wm8961_suspend NULL
1047 #define wm8961_resume NULL
1048 #endif
1049
1050 struct snd_soc_codec_device soc_codec_dev_wm8961 = {
1051         .probe =        wm8961_probe,
1052         .remove =       wm8961_remove,
1053         .suspend =      wm8961_suspend,
1054         .resume =       wm8961_resume,
1055 };
1056 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8961);
1057
1058 static int wm8961_register(struct wm8961_priv *wm8961)
1059 {
1060         struct snd_soc_codec *codec = &wm8961->codec;
1061         int ret;
1062         u16 reg;
1063
1064         if (wm8961_codec) {
1065                 dev_err(codec->dev, "Another WM8961 is registered\n");
1066                 ret = -EINVAL;
1067                 goto err;
1068         }
1069
1070         mutex_init(&codec->mutex);
1071         INIT_LIST_HEAD(&codec->dapm_widgets);
1072         INIT_LIST_HEAD(&codec->dapm_paths);
1073
1074         codec->private_data = wm8961;
1075         codec->name = "WM8961";
1076         codec->owner = THIS_MODULE;
1077         codec->dai = &wm8961_dai;
1078         codec->num_dai = 1;
1079         codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache);
1080         codec->reg_cache = &wm8961->reg_cache;
1081         codec->bias_level = SND_SOC_BIAS_OFF;
1082         codec->set_bias_level = wm8961_set_bias_level;
1083         codec->volatile_register = wm8961_volatile_register;
1084
1085         memcpy(codec->reg_cache, wm8961_reg_defaults,
1086                sizeof(wm8961_reg_defaults));
1087
1088         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1089         if (ret != 0) {
1090                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1091                 goto err;
1092         }
1093
1094         reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
1095         if (reg != 0x1801) {
1096                 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
1097                 ret = -EINVAL;
1098                 goto err;
1099         }
1100
1101         /* This isn't volatile - readback doesn't correspond to write */
1102         reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1103         dev_info(codec->dev, "WM8961 family %d revision %c\n",
1104                  (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
1105                  ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
1106                  + 'A');
1107
1108         ret = wm8961_reset(codec);
1109         if (ret < 0) {
1110                 dev_err(codec->dev, "Failed to issue reset\n");
1111                 return ret;
1112         }
1113
1114         /* Enable class W */
1115         reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
1116         reg |= WM8961_CP_DYN_PWR_MASK;
1117         snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
1118
1119         /* Latch volume update bits (right channel only, we always
1120          * write both out) and default ZC on. */
1121         reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1122         snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1123                      reg | WM8961_LO1ZC | WM8961_OUT1VU);
1124         snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1125         reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1126         snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1127                      reg | WM8961_SPKRZC | WM8961_SPKVU);
1128         snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1129
1130         reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1131         snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1132         reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1133         snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1134
1135         /* Use soft mute by default */
1136         reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1137         reg |= WM8961_DACSMM;
1138         snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1139
1140         /* Use automatic clocking mode by default; for now this is all
1141          * we support.
1142          */
1143         reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1144         reg &= ~WM8961_MANUAL_MODE;
1145         snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1146
1147         wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1148
1149         wm8961_dai.dev = codec->dev;
1150
1151         wm8961_codec = codec;
1152
1153         ret = snd_soc_register_codec(codec);
1154         if (ret != 0) {
1155                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1156                 return ret;
1157         }
1158
1159         ret = snd_soc_register_dai(&wm8961_dai);
1160         if (ret != 0) {
1161                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1162                 snd_soc_unregister_codec(codec);
1163                 return ret;
1164         }
1165
1166         return 0;
1167
1168 err:
1169         kfree(wm8961);
1170         return ret;
1171 }
1172
1173 static void wm8961_unregister(struct wm8961_priv *wm8961)
1174 {
1175         wm8961_set_bias_level(&wm8961->codec, SND_SOC_BIAS_OFF);
1176         snd_soc_unregister_dai(&wm8961_dai);
1177         snd_soc_unregister_codec(&wm8961->codec);
1178         kfree(wm8961);
1179         wm8961_codec = NULL;
1180 }
1181
1182 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1183                                       const struct i2c_device_id *id)
1184 {
1185         struct wm8961_priv *wm8961;
1186         struct snd_soc_codec *codec;
1187
1188         wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1189         if (wm8961 == NULL)
1190                 return -ENOMEM;
1191
1192         codec = &wm8961->codec;
1193
1194         i2c_set_clientdata(i2c, wm8961);
1195         codec->control_data = i2c;
1196
1197         codec->dev = &i2c->dev;
1198
1199         return wm8961_register(wm8961);
1200 }
1201
1202 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1203 {
1204         struct wm8961_priv *wm8961 = i2c_get_clientdata(client);
1205         wm8961_unregister(wm8961);
1206         return 0;
1207 }
1208
1209 #ifdef CONFIG_PM
1210 static int wm8961_i2c_suspend(struct i2c_client *client, pm_message_t state)
1211 {
1212         return snd_soc_suspend_device(&client->dev);
1213 }
1214
1215 static int wm8961_i2c_resume(struct i2c_client *client)
1216 {
1217         return snd_soc_resume_device(&client->dev);
1218 }
1219 #else
1220 #define wm8961_i2c_suspend NULL
1221 #define wm8961_i2c_resume NULL
1222 #endif
1223
1224 static const struct i2c_device_id wm8961_i2c_id[] = {
1225         { "wm8961", 0 },
1226         { }
1227 };
1228 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1229
1230 static struct i2c_driver wm8961_i2c_driver = {
1231         .driver = {
1232                 .name = "wm8961",
1233                 .owner = THIS_MODULE,
1234         },
1235         .probe =    wm8961_i2c_probe,
1236         .remove =   __devexit_p(wm8961_i2c_remove),
1237         .suspend =  wm8961_i2c_suspend,
1238         .resume =   wm8961_i2c_resume,
1239         .id_table = wm8961_i2c_id,
1240 };
1241
1242 static int __init wm8961_modinit(void)
1243 {
1244         int ret;
1245
1246         ret = i2c_add_driver(&wm8961_i2c_driver);
1247         if (ret != 0) {
1248                 printk(KERN_ERR "Failed to register WM8961 I2C driver: %d\n",
1249                        ret);
1250         }
1251
1252         return ret;
1253 }
1254 module_init(wm8961_modinit);
1255
1256 static void __exit wm8961_exit(void)
1257 {
1258         i2c_del_driver(&wm8961_i2c_driver);
1259 }
1260 module_exit(wm8961_exit);
1261
1262
1263 MODULE_DESCRIPTION("ASoC WM8961 driver");
1264 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1265 MODULE_LICENSE("GPL");