sound/soc/codecs/wm8900.c

   1 /*
   2  * wm8900.c  --  WM8900 ALSA Soc Audio driver
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * TODO:
  13  *  - Tristating.
  14  *  - TDM.
  15  *  - Jack detect.
  16  *  - FLL source configuration, currently only MCLK is supported.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/soc-dapm.h>
  32 #include <sound/initval.h>
  33 #include <sound/tlv.h>
  34
  35 #include "wm8900.h"
  36
  37 /* WM8900 register space */
  38 #define WM8900_REG_RESET        0x0
  39 #define WM8900_REG_ID           0x0
  40 #define WM8900_REG_POWER1       0x1
  41 #define WM8900_REG_POWER2       0x2
  42 #define WM8900_REG_POWER3       0x3
  43 #define WM8900_REG_AUDIO1       0x4
  44 #define WM8900_REG_AUDIO2       0x5
  45 #define WM8900_REG_CLOCKING1    0x6
  46 #define WM8900_REG_CLOCKING2    0x7
  47 #define WM8900_REG_AUDIO3       0x8
  48 #define WM8900_REG_AUDIO4       0x9
  49 #define WM8900_REG_DACCTRL      0xa
  50 #define WM8900_REG_LDAC_DV      0xb
  51 #define WM8900_REG_RDAC_DV      0xc
  52 #define WM8900_REG_SIDETONE     0xd
  53 #define WM8900_REG_ADCCTRL      0xe
  54 #define WM8900_REG_LADC_DV      0xf
  55 #define WM8900_REG_RADC_DV      0x10
  56 #define WM8900_REG_GPIO         0x12
  57 #define WM8900_REG_INCTL        0x15
  58 #define WM8900_REG_LINVOL       0x16
  59 #define WM8900_REG_RINVOL       0x17
  60 #define WM8900_REG_INBOOSTMIX1  0x18
  61 #define WM8900_REG_INBOOSTMIX2  0x19
  62 #define WM8900_REG_ADCPATH      0x1a
  63 #define WM8900_REG_AUXBOOST     0x1b
  64 #define WM8900_REG_ADDCTL       0x1e
  65 #define WM8900_REG_FLLCTL1      0x24
  66 #define WM8900_REG_FLLCTL2      0x25
  67 #define WM8900_REG_FLLCTL3      0x26
  68 #define WM8900_REG_FLLCTL4      0x27
  69 #define WM8900_REG_FLLCTL5      0x28
  70 #define WM8900_REG_FLLCTL6      0x29
  71 #define WM8900_REG_LOUTMIXCTL1  0x2c
  72 #define WM8900_REG_ROUTMIXCTL1  0x2d
  73 #define WM8900_REG_BYPASS1      0x2e
  74 #define WM8900_REG_BYPASS2      0x2f
  75 #define WM8900_REG_AUXOUT_CTL   0x30
  76 #define WM8900_REG_LOUT1CTL     0x33
  77 #define WM8900_REG_ROUT1CTL     0x34
  78 #define WM8900_REG_LOUT2CTL     0x35
  79 #define WM8900_REG_ROUT2CTL     0x36
  80 #define WM8900_REG_HPCTL1       0x3a
  81 #define WM8900_REG_OUTBIASCTL   0x73
  82
  83 #define WM8900_MAXREG           0x80
  84
  85 #define WM8900_REG_ADDCTL_OUT1_DIS    0x80
  86 #define WM8900_REG_ADDCTL_OUT2_DIS    0x40
  87 #define WM8900_REG_ADDCTL_VMID_DIS    0x20
  88 #define WM8900_REG_ADDCTL_BIAS_SRC    0x10
  89 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
  90 #define WM8900_REG_ADDCTL_TEMP_SD     0x02
  91
  92 #define WM8900_REG_GPIO_TEMP_ENA   0x2
  93
  94 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
  95 #define WM8900_REG_POWER1_BIAS_ENA         0x0008
  96 #define WM8900_REG_POWER1_VMID_BUF_ENA     0x0004
  97 #define WM8900_REG_POWER1_FLL_ENA          0x0040
  98
  99 #define WM8900_REG_POWER2_SYSCLK_ENA  0x8000
 100 #define WM8900_REG_POWER2_ADCL_ENA    0x0002
 101 #define WM8900_REG_POWER2_ADCR_ENA    0x0001
 102
 103 #define WM8900_REG_POWER3_DACL_ENA    0x0002
 104 #define WM8900_REG_POWER3_DACR_ENA    0x0001
 105
 106 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
 107 #define WM8900_REG_AUDIO1_LRCLK_INV    0x0080
 108 #define WM8900_REG_AUDIO1_BCLK_INV     0x0100
 109
 110 #define WM8900_REG_CLOCKING1_BCLK_DIR   0x1
 111 #define WM8900_REG_CLOCKING1_MCLK_SRC   0x100
 112 #define WM8900_REG_CLOCKING1_BCLK_MASK  (~0x01e)
 113 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
 114
 115 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
 116 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
 117
 118 #define WM8900_REG_DACCTRL_MUTE          0x004
 119 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
 120
 121 #define WM8900_REG_AUDIO3_ADCLRC_DIR    0x0800
 122
 123 #define WM8900_REG_AUDIO4_DACLRC_DIR    0x0800
 124
 125 #define WM8900_REG_FLLCTL1_OSC_ENA    0x100
 126
 127 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
 128
 129 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
 130 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
 131 #define WM8900_REG_HPCTL1_HP_CLAMP_IP    0x20
 132 #define WM8900_REG_HPCTL1_HP_CLAMP_OP    0x10
 133 #define WM8900_REG_HPCTL1_HP_SHORT       0x08
 134 #define WM8900_REG_HPCTL1_HP_SHORT2      0x04
 135
 136 #define WM8900_LRC_MASK 0xfc00
 137
 138 struct snd_soc_codec_device soc_codec_dev_wm8900;
 139
 140 struct wm8900_priv {
 141         struct snd_soc_codec codec;
 142
 143         u16 reg_cache[WM8900_MAXREG];
 144
 145         u32 fll_in; /* FLL input frequency */
 146         u32 fll_out; /* FLL output frequency */
 147 };
 148
 149 /*
 150  * wm8900 register cache.  We can't read the entire register space and we
 151  * have slow control buses so we cache the registers.
 152  */
 153 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
 154         0x8900, 0x0000,
 155         0xc000, 0x0000,
 156         0x4050, 0x4000,
 157         0x0008, 0x0000,
 158         0x0040, 0x0040,
 159         0x1004, 0x00c0,
 160         0x00c0, 0x0000,
 161         0x0100, 0x00c0,
 162         0x00c0, 0x0000,
 163         0xb001, 0x0000,
 164         0x0000, 0x0044,
 165         0x004c, 0x004c,
 166         0x0044, 0x0044,
 167         0x0000, 0x0044,
 168         0x0000, 0x0000,
 169         0x0002, 0x0000,
 170         0x0000, 0x0000,
 171         0x0000, 0x0000,
 172         0x0008, 0x0000,
 173         0x0000, 0x0008,
 174         0x0097, 0x0100,
 175         0x0000, 0x0000,
 176         0x0050, 0x0050,
 177         0x0055, 0x0055,
 178         0x0055, 0x0000,
 179         0x0000, 0x0079,
 180         0x0079, 0x0079,
 181         0x0079, 0x0000,
 182         /* Remaining registers all zero */
 183 };
 184
 185 /*
 186  * read wm8900 register cache
 187  */
 188 static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec,
 189         unsigned int reg)
 190 {
 191         u16 *cache = codec->reg_cache;
 192
 193         BUG_ON(reg >= WM8900_MAXREG);
 194
 195         if (reg == WM8900_REG_ID)
 196                 return 0;
 197
 198         return cache[reg];
 199 }
 200
 201 /*
 202  * write wm8900 register cache
 203  */
 204 static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec,
 205         u16 reg, unsigned int value)
 206 {
 207         u16 *cache = codec->reg_cache;
 208
 209         BUG_ON(reg >= WM8900_MAXREG);
 210
 211         cache[reg] = value;
 212 }
 213
 214 /*
 215  * write to the WM8900 register space
 216  */
 217 static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg,
 218                         unsigned int value)
 219 {
 220         u8 data[3];
 221
 222         if (value == wm8900_read_reg_cache(codec, reg))
 223                 return 0;
 224
 225         /* data is
 226          *   D15..D9 WM8900 register offset
 227          *   D8...D0 register data
 228          */
 229         data[0] = reg;
 230         data[1] = value >> 8;
 231         data[2] = value & 0x00ff;
 232
 233         wm8900_write_reg_cache(codec, reg, value);
 234         if (codec->hw_write(codec->control_data, data, 3) == 3)
 235                 return 0;
 236         else
 237                 return -EIO;
 238 }
 239
 240 /*
 241  * Read from the wm8900.
 242  */
 243 static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg)
 244 {
 245         struct i2c_msg xfer[2];
 246         u16 data;
 247         int ret;
 248         struct i2c_client *client = codec->control_data;
 249
 250         BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1);
 251
 252         /* Write register */
 253         xfer[0].addr = client->addr;
 254         xfer[0].flags = 0;
 255         xfer[0].len = 1;
 256         xfer[0].buf = &reg;
 257
 258         /* Read data */
 259         xfer[1].addr = client->addr;
 260         xfer[1].flags = I2C_M_RD;
 261         xfer[1].len = 2;
 262         xfer[1].buf = (u8 *)&data;
 263
 264         ret = i2c_transfer(client->adapter, xfer, 2);
 265         if (ret != 2) {
 266                 printk(KERN_CRIT "i2c_transfer returned %d\n", ret);
 267                 return 0;
 268         }
 269
 270         return (data >> 8) | ((data & 0xff) << 8);
 271 }
 272
 273 /*
 274  * Read from the WM8900 register space.  Most registers can't be read
 275  * and are therefore supplied from cache.
 276  */
 277 static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg)
 278 {
 279         switch (reg) {
 280         case WM8900_REG_ID:
 281                 return wm8900_chip_read(codec, reg);
 282         default:
 283                 return wm8900_read_reg_cache(codec, reg);
 284         }
 285 }
 286
 287 static void wm8900_reset(struct snd_soc_codec *codec)
 288 {
 289         wm8900_write(codec, WM8900_REG_RESET, 0);
 290
 291         memcpy(codec->reg_cache, wm8900_reg_defaults,
 292                sizeof(codec->reg_cache));
 293 }
 294
 295 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
 296                            struct snd_kcontrol *kcontrol, int event)
 297 {
 298         struct snd_soc_codec *codec = w->codec;
 299         u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1);
 300
 301         switch (event) {
 302         case SND_SOC_DAPM_PRE_PMU:
 303                 /* Clamp headphone outputs */
 304                 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
 305                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
 306                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 307                 break;
 308
 309         case SND_SOC_DAPM_POST_PMU:
 310                 /* Enable the input stage */
 311                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
 312                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
 313                         WM8900_REG_HPCTL1_HP_SHORT2 |
 314                         WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
 315                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 316
 317                 msleep(400);
 318
 319                 /* Enable the output stage */
 320                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
 321                 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
 322                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 323
 324                 /* Remove the shorts */
 325                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
 326                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 327                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
 328                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 329                 break;
 330
 331         case SND_SOC_DAPM_PRE_PMD:
 332                 /* Short the output */
 333                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
 334                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 335
 336                 /* Disable the output stage */
 337                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
 338                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 339
 340                 /* Clamp the outputs and power down input */
 341                 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
 342                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
 343                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
 344                 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
 345                 break;
 346
 347         case SND_SOC_DAPM_POST_PMD:
 348                 /* Disable everything */
 349                 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
 350                 break;
 351
 352         default:
 353                 BUG();
 354         }
 355
 356         return 0;
 357 }
 358
 359 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
 360
 361 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
 362
 363 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
 364
 365 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
 366
 367 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
 368
 369 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
 370
 371 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
 372
 373 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 374
 375 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
 376
 377 static const struct soc_enum mic_bias_level =
 378 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
 379
 380 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
 381
 382 static const struct soc_enum dac_mute_rate =
 383 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
 384
 385 static const char *dac_deemphasis_txt[] = {
 386         "Disabled", "32kHz", "44.1kHz", "48kHz"
 387 };
 388
 389 static const struct soc_enum dac_deemphasis =
 390 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
 391
 392 static const char *adc_hpf_cut_txt[] = {
 393         "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
 394 };
 395
 396 static const struct soc_enum adc_hpf_cut =
 397 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
 398
 399 static const char *lr_txt[] = {
 400         "Left", "Right"
 401 };
 402
 403 static const struct soc_enum aifl_src =
 404 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
 405
 406 static const struct soc_enum aifr_src =
 407 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
 408
 409 static const struct soc_enum dacl_src =
 410 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
 411
 412 static const struct soc_enum dacr_src =
 413 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
 414
 415 static const char *sidetone_txt[] = {
 416         "Disabled", "Left ADC", "Right ADC"
 417 };
 418
 419 static const struct soc_enum dacl_sidetone =
 420 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
 421
 422 static const struct soc_enum dacr_sidetone =
 423 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
 424
 425 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
 426 SOC_ENUM("Mic Bias Level", mic_bias_level),
 427
 428 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
 429                in_pga_tlv),
 430 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
 431 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
 432
 433 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
 434                in_pga_tlv),
 435 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
 436 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
 437
 438 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
 439 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
 440 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
 441 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
 442 SOC_SINGLE("DAC Sloping Stopband Filter Switch", WM8900_REG_DACCTRL, 8, 1, 0),
 443 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
 444            12, 1, 0),
 445
 446 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
 447 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
 448 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
 449 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
 450                adc_svol_tlv),
 451 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
 452                adc_svol_tlv),
 453 SOC_ENUM("Left Digital Audio Source", aifl_src),
 454 SOC_ENUM("Right Digital Audio Source", aifr_src),
 455
 456 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
 457                dac_boost_tlv),
 458 SOC_ENUM("Left DAC Source", dacl_src),
 459 SOC_ENUM("Right DAC Source", dacr_src),
 460 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
 461 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
 462 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
 463
 464 SOC_DOUBLE_R_TLV("Digital Playback Volume",
 465                  WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
 466                  1, 96, 0, dac_tlv),
 467 SOC_DOUBLE_R_TLV("Digital Capture Volume",
 468                  WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
 469
 470 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
 471                out_mix_tlv),
 472 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
 473                out_mix_tlv),
 474 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
 475                out_mix_tlv),
 476 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
 477                out_mix_tlv),
 478
 479 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
 480                out_mix_tlv),
 481 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
 482                out_mix_tlv),
 483 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
 484                out_mix_tlv),
 485 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
 486                out_mix_tlv),
 487
 488 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
 489                in_boost_tlv),
 490 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
 491                in_boost_tlv),
 492 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
 493                in_boost_tlv),
 494 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
 495                in_boost_tlv),
 496 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
 497                in_boost_tlv),
 498 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
 499                in_boost_tlv),
 500
 501 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 502                0, 63, 0, out_pga_tlv),
 503 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 504              6, 1, 1),
 505 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 506              7, 1, 0),
 507
 508 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
 509                  WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
 510                  0, 63, 0, out_pga_tlv),
 511 SOC_DOUBLE_R("LINEOUT2 Switch",
 512              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
 513 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
 514              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
 515 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
 516            0, 1, 1),
 517
 518 };
 519
 520 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
 521 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
 522
 523 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
 524 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
 525
 526 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
 527 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
 528 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
 529 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
 530 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
 531 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
 532 };
 533
 534 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
 535 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
 536 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
 537 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
 538 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
 539 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
 540 };
 541
 542 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
 543 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
 544 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
 545 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
 546 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
 547 };
 548
 549 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
 550 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
 551 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
 552 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
 553 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
 554 };
 555
 556 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
 557 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
 558 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
 559 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
 560 };
 561
 562 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
 563 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
 564 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
 565 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
 566 };
 567
 568 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
 569
 570 static const struct soc_enum wm8900_lineout2_lp_mux =
 571 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
 572
 573 static const struct snd_kcontrol_new wm8900_lineout2_lp =
 574 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
 575
 576 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
 577
 578 /* Externally visible pins */
 579 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
 580 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
 581 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
 582 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
 583 SND_SOC_DAPM_OUTPUT("HP_L"),
 584 SND_SOC_DAPM_OUTPUT("HP_R"),
 585
 586 SND_SOC_DAPM_INPUT("RINPUT1"),
 587 SND_SOC_DAPM_INPUT("LINPUT1"),
 588 SND_SOC_DAPM_INPUT("RINPUT2"),
 589 SND_SOC_DAPM_INPUT("LINPUT2"),
 590 SND_SOC_DAPM_INPUT("RINPUT3"),
 591 SND_SOC_DAPM_INPUT("LINPUT3"),
 592 SND_SOC_DAPM_INPUT("AUX"),
 593
 594 SND_SOC_DAPM_VMID("VMID"),
 595
 596 /* Input */
 597 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
 598                    wm8900_linpga_controls,
 599                    ARRAY_SIZE(wm8900_linpga_controls)),
 600 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
 601                    wm8900_rinpga_controls,
 602                    ARRAY_SIZE(wm8900_rinpga_controls)),
 603
 604 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
 605                    wm8900_linmix_controls,
 606                    ARRAY_SIZE(wm8900_linmix_controls)),
 607 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
 608                    wm8900_rinmix_controls,
 609                    ARRAY_SIZE(wm8900_rinmix_controls)),
 610
 611 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
 612
 613 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
 614 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
 615
 616 /* Output */
 617 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
 618 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
 619
 620 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
 621                    wm8900_hp_event,
 622                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 623                    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 624
 625 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
 626 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
 627
 628 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
 629 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
 630 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
 631
 632 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
 633                    wm8900_loutmix_controls,
 634                    ARRAY_SIZE(wm8900_loutmix_controls)),
 635 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
 636                    wm8900_routmix_controls,
 637                    ARRAY_SIZE(wm8900_routmix_controls)),
 638 };
 639
 640 /* Target, Path, Source */
 641 static const struct snd_soc_dapm_route audio_map[] = {
 642 /* Inputs */
 643 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
 644 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
 645 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
 646
 647 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
 648 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
 649 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
 650
 651 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
 652 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
 653 {"Left Input Mixer", "AUX Switch", "AUX"},
 654 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
 655
 656 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
 657 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
 658 {"Right Input Mixer", "AUX Switch", "AUX"},
 659 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
 660
 661 {"ADCL", NULL, "Left Input Mixer"},
 662 {"ADCR", NULL, "Right Input Mixer"},
 663
 664 /* Outputs */
 665 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
 666 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
 667 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
 668 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
 669
 670 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
 671 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
 672 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
 673 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
 674
 675 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
 676 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
 677 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
 678 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
 679
 680 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
 681 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
 682 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
 683 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
 684 {"Left Output Mixer", "DACL Switch", "DACL"},
 685
 686 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
 687 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
 688 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
 689 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
 690 {"Right Output Mixer", "DACR Switch", "DACR"},
 691
 692 /* Note that the headphone output stage needs to be connected
 693  * externally to LINEOUT2 via DC blocking capacitors.  Other
 694  * configurations are not supported.
 695  *
 696  * Note also that left and right headphone paths are treated as a
 697  * mono path.
 698  */
 699 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
 700 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
 701 {"HP_L", NULL, "Headphone Amplifier"},
 702 {"HP_R", NULL, "Headphone Amplifier"},
 703 };
 704
 705 static int wm8900_add_widgets(struct snd_soc_codec *codec)
 706 {
 707         snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
 708                                   ARRAY_SIZE(wm8900_dapm_widgets));
 709
 710         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 711
 712         snd_soc_dapm_new_widgets(codec);
 713
 714         return 0;
 715 }
 716
 717 static int wm8900_hw_params(struct snd_pcm_substream *substream,
 718         struct snd_pcm_hw_params *params,
 719         struct snd_soc_dai *dai)
 720 {
 721         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 722         struct snd_soc_device *socdev = rtd->socdev;
 723         struct snd_soc_codec *codec = socdev->card->codec;
 724         u16 reg;
 725
 726         reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60;
 727
 728         switch (params_format(params)) {
 729         case SNDRV_PCM_FORMAT_S16_LE:
 730                 break;
 731         case SNDRV_PCM_FORMAT_S20_3LE:
 732                 reg |= 0x20;
 733                 break;
 734         case SNDRV_PCM_FORMAT_S24_LE:
 735                 reg |= 0x40;
 736                 break;
 737         case SNDRV_PCM_FORMAT_S32_LE:
 738                 reg |= 0x60;
 739                 break;
 740         default:
 741                 return -EINVAL;
 742         }
 743
 744         wm8900_write(codec, WM8900_REG_AUDIO1, reg);
 745
 746         return 0;
 747 }
 748
 749 /* FLL divisors */
 750 struct _fll_div {
 751         u16 fll_ratio;
 752         u16 fllclk_div;
 753         u16 fll_slow_lock_ref;
 754         u16 n;
 755         u16 k;
 756 };
 757
 758 /* The size in bits of the FLL divide multiplied by 10
 759  * to allow rounding later */
 760 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 761
 762 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 763                        unsigned int Fout)
 764 {
 765         u64 Kpart;
 766         unsigned int K, Ndiv, Nmod, target;
 767         unsigned int div;
 768
 769         BUG_ON(!Fout);
 770
 771         /* The FLL must run at 90-100MHz which is then scaled down to
 772          * the output value by FLLCLK_DIV. */
 773         target = Fout;
 774         div = 1;
 775         while (target < 90000000) {
 776                 div *= 2;
 777                 target *= 2;
 778         }
 779
 780         if (target > 100000000)
 781                 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
 782                        " Fout=%u\n", target, Fref, Fout);
 783         if (div > 32) {
 784                 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
 785                        "Fref=%u, Fout=%u, target=%u\n",
 786                        div, Fref, Fout, target);
 787                 return -EINVAL;
 788         }
 789
 790         fll_div->fllclk_div = div >> 2;
 791
 792         if (Fref < 48000)
 793                 fll_div->fll_slow_lock_ref = 1;
 794         else
 795                 fll_div->fll_slow_lock_ref = 0;
 796
 797         Ndiv = target / Fref;
 798
 799         if (Fref < 1000000)
 800                 fll_div->fll_ratio = 8;
 801         else
 802                 fll_div->fll_ratio = 1;
 803
 804         fll_div->n = Ndiv / fll_div->fll_ratio;
 805         Nmod = (target / fll_div->fll_ratio) % Fref;
 806
 807         /* Calculate fractional part - scale up so we can round. */
 808         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
 809
 810         do_div(Kpart, Fref);
 811
 812         K = Kpart & 0xFFFFFFFF;
 813
 814         if ((K % 10) >= 5)
 815                 K += 5;
 816
 817         /* Move down to proper range now rounding is done */
 818         fll_div->k = K / 10;
 819
 820         BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
 821         BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
 822
 823         return 0;
 824 }
 825
 826 static int wm8900_set_fll(struct snd_soc_codec *codec,
 827         int fll_id, unsigned int freq_in, unsigned int freq_out)
 828 {
 829         struct wm8900_priv *wm8900 = codec->private_data;
 830         struct _fll_div fll_div;
 831         unsigned int reg;
 832
 833         if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
 834                 return 0;
 835
 836         /* The digital side should be disabled during any change. */
 837         reg = wm8900_read(codec, WM8900_REG_POWER1);
 838         wm8900_write(codec, WM8900_REG_POWER1,
 839                      reg & (~WM8900_REG_POWER1_FLL_ENA));
 840
 841         /* Disable the FLL? */
 842         if (!freq_in || !freq_out) {
 843                 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
 844                 wm8900_write(codec, WM8900_REG_CLOCKING1,
 845                              reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
 846
 847                 reg = wm8900_read(codec, WM8900_REG_FLLCTL1);
 848                 wm8900_write(codec, WM8900_REG_FLLCTL1,
 849                              reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
 850
 851                 wm8900->fll_in = freq_in;
 852                 wm8900->fll_out = freq_out;
 853
 854                 return 0;
 855         }
 856
 857         if (fll_factors(&fll_div, freq_in, freq_out) != 0)
 858                 goto reenable;
 859
 860         wm8900->fll_in = freq_in;
 861         wm8900->fll_out = freq_out;
 862
 863         /* The osclilator *MUST* be enabled before we enable the
 864          * digital circuit. */
 865         wm8900_write(codec, WM8900_REG_FLLCTL1,
 866                      fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
 867
 868         wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
 869         wm8900_write(codec, WM8900_REG_FLLCTL5,
 870                      (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
 871
 872         if (fll_div.k) {
 873                 wm8900_write(codec, WM8900_REG_FLLCTL2,
 874                              (fll_div.k >> 8) | 0x100);
 875                 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
 876         } else
 877                 wm8900_write(codec, WM8900_REG_FLLCTL2, 0);
 878
 879         if (fll_div.fll_slow_lock_ref)
 880                 wm8900_write(codec, WM8900_REG_FLLCTL6,
 881                              WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
 882         else
 883                 wm8900_write(codec, WM8900_REG_FLLCTL6, 0);
 884
 885         reg = wm8900_read(codec, WM8900_REG_POWER1);
 886         wm8900_write(codec, WM8900_REG_POWER1,
 887                      reg | WM8900_REG_POWER1_FLL_ENA);
 888
 889 reenable:
 890         reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
 891         wm8900_write(codec, WM8900_REG_CLOCKING1,
 892                      reg | WM8900_REG_CLOCKING1_MCLK_SRC);
 893
 894         return 0;
 895 }
 896
 897 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai,
 898                 int pll_id, unsigned int freq_in, unsigned int freq_out)
 899 {
 900         return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
 901 }
 902
 903 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 904                                  int div_id, int div)
 905 {
 906         struct snd_soc_codec *codec = codec_dai->codec;
 907         unsigned int reg;
 908
 909         switch (div_id) {
 910         case WM8900_BCLK_DIV:
 911                 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
 912                 wm8900_write(codec, WM8900_REG_CLOCKING1,
 913                              div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
 914                 break;
 915         case WM8900_OPCLK_DIV:
 916                 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
 917                 wm8900_write(codec, WM8900_REG_CLOCKING1,
 918                              div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
 919                 break;
 920         case WM8900_DAC_LRCLK:
 921                 reg = wm8900_read(codec, WM8900_REG_AUDIO4);
 922                 wm8900_write(codec, WM8900_REG_AUDIO4,
 923                              div | (reg & WM8900_LRC_MASK));
 924                 break;
 925         case WM8900_ADC_LRCLK:
 926                 reg = wm8900_read(codec, WM8900_REG_AUDIO3);
 927                 wm8900_write(codec, WM8900_REG_AUDIO3,
 928                              div | (reg & WM8900_LRC_MASK));
 929                 break;
 930         case WM8900_DAC_CLKDIV:
 931                 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
 932                 wm8900_write(codec, WM8900_REG_CLOCKING2,
 933                              div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
 934                 break;
 935         case WM8900_ADC_CLKDIV:
 936                 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
 937                 wm8900_write(codec, WM8900_REG_CLOCKING2,
 938                              div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
 939                 break;
 940         case WM8900_LRCLK_MODE:
 941                 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
 942                 wm8900_write(codec, WM8900_REG_DACCTRL,
 943                              div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
 944                 break;
 945         default:
 946                 return -EINVAL;
 947         }
 948
 949         return 0;
 950 }
 951
 952
 953 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
 954                               unsigned int fmt)
 955 {
 956         struct snd_soc_codec *codec = codec_dai->codec;
 957         unsigned int clocking1, aif1, aif3, aif4;
 958
 959         clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1);
 960         aif1 = wm8900_read(codec, WM8900_REG_AUDIO1);
 961         aif3 = wm8900_read(codec, WM8900_REG_AUDIO3);
 962         aif4 = wm8900_read(codec, WM8900_REG_AUDIO4);
 963
 964         /* set master/slave audio interface */
 965         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 966         case SND_SOC_DAIFMT_CBS_CFS:
 967                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
 968                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
 969                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
 970                 break;
 971         case SND_SOC_DAIFMT_CBS_CFM:
 972                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
 973                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
 974                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
 975                 break;
 976         case SND_SOC_DAIFMT_CBM_CFM:
 977                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
 978                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
 979                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
 980                 break;
 981         case SND_SOC_DAIFMT_CBM_CFS:
 982                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
 983                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
 984                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
 985                 break;
 986         default:
 987                 return -EINVAL;
 988         }
 989
 990         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 991         case SND_SOC_DAIFMT_DSP_A:
 992                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
 993                 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
 994                 break;
 995         case SND_SOC_DAIFMT_DSP_B:
 996                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
 997                 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
 998                 break;
 999         case SND_SOC_DAIFMT_I2S:
1000                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1001                 aif1 |= 0x10;
1002                 break;
1003         case SND_SOC_DAIFMT_RIGHT_J:
1004                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1005                 break;
1006         case SND_SOC_DAIFMT_LEFT_J:
1007                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1008                 aif1 |= 0x8;
1009                 break;
1010         default:
1011                 return -EINVAL;
1012         }
1013
1014         /* Clock inversion */
1015         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1016         case SND_SOC_DAIFMT_DSP_A:
1017         case SND_SOC_DAIFMT_DSP_B:
1018                 /* frame inversion not valid for DSP modes */
1019                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1020                 case SND_SOC_DAIFMT_NB_NF:
1021                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1022                         break;
1023                 case SND_SOC_DAIFMT_IB_NF:
1024                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1025                         break;
1026                 default:
1027                         return -EINVAL;
1028                 }
1029                 break;
1030         case SND_SOC_DAIFMT_I2S:
1031         case SND_SOC_DAIFMT_RIGHT_J:
1032         case SND_SOC_DAIFMT_LEFT_J:
1033                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1034                 case SND_SOC_DAIFMT_NB_NF:
1035                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1036                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1037                         break;
1038                 case SND_SOC_DAIFMT_IB_IF:
1039                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1040                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1041                         break;
1042                 case SND_SOC_DAIFMT_IB_NF:
1043                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1044                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1045                         break;
1046                 case SND_SOC_DAIFMT_NB_IF:
1047                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1048                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1049                         break;
1050                 default:
1051                         return -EINVAL;
1052                 }
1053                 break;
1054         default:
1055                 return -EINVAL;
1056         }
1057
1058         wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1);
1059         wm8900_write(codec, WM8900_REG_AUDIO1, aif1);
1060         wm8900_write(codec, WM8900_REG_AUDIO3, aif3);
1061         wm8900_write(codec, WM8900_REG_AUDIO4, aif4);
1062
1063         return 0;
1064 }
1065
1066 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1067 {
1068         struct snd_soc_codec *codec = codec_dai->codec;
1069         u16 reg;
1070
1071         reg = wm8900_read(codec, WM8900_REG_DACCTRL);
1072
1073         if (mute)
1074                 reg |= WM8900_REG_DACCTRL_MUTE;
1075         else
1076                 reg &= ~WM8900_REG_DACCTRL_MUTE;
1077
1078         wm8900_write(codec, WM8900_REG_DACCTRL, reg);
1079
1080         return 0;
1081 }
1082
1083 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1084                       SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1085                       SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1086
1087 #define WM8900_PCM_FORMATS \
1088         (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1089          SNDRV_PCM_FORMAT_S24_LE)
1090
1091 static struct snd_soc_dai_ops wm8900_dai_ops = {
1092         .hw_params      = wm8900_hw_params,
1093         .set_clkdiv     = wm8900_set_dai_clkdiv,
1094         .set_pll        = wm8900_set_dai_pll,
1095         .set_fmt        = wm8900_set_dai_fmt,
1096         .digital_mute   = wm8900_digital_mute,
1097 };
1098
1099 struct snd_soc_dai wm8900_dai = {
1100         .name = "WM8900 HiFi",
1101         .playback = {
1102                 .stream_name = "HiFi Playback",
1103                 .channels_min = 1,
1104                 .channels_max = 2,
1105                 .rates = WM8900_RATES,
1106                 .formats = WM8900_PCM_FORMATS,
1107         },
1108         .capture = {
1109                 .stream_name = "HiFi Capture",
1110                 .channels_min = 1,
1111                 .channels_max = 2,
1112                 .rates = WM8900_RATES,
1113                 .formats = WM8900_PCM_FORMATS,
1114          },
1115         .ops = &wm8900_dai_ops,
1116 };
1117 EXPORT_SYMBOL_GPL(wm8900_dai);
1118
1119 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1120                                  enum snd_soc_bias_level level)
1121 {
1122         u16 reg;
1123
1124         switch (level) {
1125         case SND_SOC_BIAS_ON:
1126                 /* Enable thermal shutdown */
1127                 reg = wm8900_read(codec, WM8900_REG_GPIO);
1128                 wm8900_write(codec, WM8900_REG_GPIO,
1129                              reg | WM8900_REG_GPIO_TEMP_ENA);
1130                 reg = wm8900_read(codec, WM8900_REG_ADDCTL);
1131                 wm8900_write(codec, WM8900_REG_ADDCTL,
1132                              reg | WM8900_REG_ADDCTL_TEMP_SD);
1133                 break;
1134
1135         case SND_SOC_BIAS_PREPARE:
1136                 break;
1137
1138         case SND_SOC_BIAS_STANDBY:
1139                 /* Charge capacitors if initial power up */
1140                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1141                         /* STARTUP_BIAS_ENA on */
1142                         wm8900_write(codec, WM8900_REG_POWER1,
1143                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1144
1145                         /* Startup bias mode */
1146                         wm8900_write(codec, WM8900_REG_ADDCTL,
1147                                      WM8900_REG_ADDCTL_BIAS_SRC |
1148                                      WM8900_REG_ADDCTL_VMID_SOFTST);
1149
1150                         /* VMID 2x50k */
1151                         wm8900_write(codec, WM8900_REG_POWER1,
1152                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1153
1154                         /* Allow capacitors to charge */
1155                         schedule_timeout_interruptible(msecs_to_jiffies(400));
1156
1157                         /* Enable bias */
1158                         wm8900_write(codec, WM8900_REG_POWER1,
1159                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1160                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1161
1162                         wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1163
1164                         wm8900_write(codec, WM8900_REG_POWER1,
1165                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1166                 }
1167
1168                 reg = wm8900_read(codec, WM8900_REG_POWER1);
1169                 wm8900_write(codec, WM8900_REG_POWER1,
1170                              (reg & WM8900_REG_POWER1_FLL_ENA) |
1171                              WM8900_REG_POWER1_BIAS_ENA | 0x1);
1172                 wm8900_write(codec, WM8900_REG_POWER2,
1173                              WM8900_REG_POWER2_SYSCLK_ENA);
1174                 wm8900_write(codec, WM8900_REG_POWER3, 0);
1175                 break;
1176
1177         case SND_SOC_BIAS_OFF:
1178                 /* Startup bias enable */
1179                 reg = wm8900_read(codec, WM8900_REG_POWER1);
1180                 wm8900_write(codec, WM8900_REG_POWER1,
1181                              reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1182                 wm8900_write(codec, WM8900_REG_ADDCTL,
1183                              WM8900_REG_ADDCTL_BIAS_SRC |
1184                              WM8900_REG_ADDCTL_VMID_SOFTST);
1185
1186                 /* Discharge caps */
1187                 wm8900_write(codec, WM8900_REG_POWER1,
1188                              WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1189                 schedule_timeout_interruptible(msecs_to_jiffies(500));
1190
1191                 /* Remove clamp */
1192                 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
1193
1194                 /* Power down */
1195                 wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1196                 wm8900_write(codec, WM8900_REG_POWER1, 0);
1197                 wm8900_write(codec, WM8900_REG_POWER2, 0);
1198                 wm8900_write(codec, WM8900_REG_POWER3, 0);
1199
1200                 /* Need to let things settle before stopping the clock
1201                  * to ensure that restart works, see "Stopping the
1202                  * master clock" in the datasheet. */
1203                 schedule_timeout_interruptible(msecs_to_jiffies(1));
1204                 wm8900_write(codec, WM8900_REG_POWER2,
1205                              WM8900_REG_POWER2_SYSCLK_ENA);
1206                 break;
1207         }
1208         codec->bias_level = level;
1209         return 0;
1210 }
1211
1212 static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1213 {
1214         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1215         struct snd_soc_codec *codec = socdev->card->codec;
1216         struct wm8900_priv *wm8900 = codec->private_data;
1217         int fll_out = wm8900->fll_out;
1218         int fll_in  = wm8900->fll_in;
1219         int ret;
1220
1221         /* Stop the FLL in an orderly fashion */
1222         ret = wm8900_set_fll(codec, 0, 0, 0);
1223         if (ret != 0) {
1224                 dev_err(&pdev->dev, "Failed to stop FLL\n");
1225                 return ret;
1226         }
1227
1228         wm8900->fll_out = fll_out;
1229         wm8900->fll_in = fll_in;
1230
1231         wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1232
1233         return 0;
1234 }
1235
1236 static int wm8900_resume(struct platform_device *pdev)
1237 {
1238         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1239         struct snd_soc_codec *codec = socdev->card->codec;
1240         struct wm8900_priv *wm8900 = codec->private_data;
1241         u16 *cache;
1242         int i, ret;
1243
1244         cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1245                         GFP_KERNEL);
1246
1247         wm8900_reset(codec);
1248         wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1249
1250         /* Restart the FLL? */
1251         if (wm8900->fll_out) {
1252                 int fll_out = wm8900->fll_out;
1253                 int fll_in  = wm8900->fll_in;
1254
1255                 wm8900->fll_in = 0;
1256                 wm8900->fll_out = 0;
1257
1258                 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1259                 if (ret != 0) {
1260                         dev_err(&pdev->dev, "Failed to restart FLL\n");
1261                         return ret;
1262                 }
1263         }
1264
1265         if (cache) {
1266                 for (i = 0; i < WM8900_MAXREG; i++)
1267                         wm8900_write(codec, i, cache[i]);
1268                 kfree(cache);
1269         } else
1270                 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1271
1272         return 0;
1273 }
1274
1275 static struct snd_soc_codec *wm8900_codec;
1276
1277 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1278                                       const struct i2c_device_id *id)
1279 {
1280         struct wm8900_priv *wm8900;
1281         struct snd_soc_codec *codec;
1282         unsigned int reg;
1283         int ret;
1284
1285         wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1286         if (wm8900 == NULL)
1287                 return -ENOMEM;
1288
1289         codec = &wm8900->codec;
1290         codec->private_data = wm8900;
1291         codec->reg_cache = &wm8900->reg_cache[0];
1292         codec->reg_cache_size = WM8900_MAXREG;
1293
1294         mutex_init(&codec->mutex);
1295         INIT_LIST_HEAD(&codec->dapm_widgets);
1296         INIT_LIST_HEAD(&codec->dapm_paths);
1297
1298         codec->name = "WM8900";
1299         codec->owner = THIS_MODULE;
1300         codec->read = wm8900_read;
1301         codec->write = wm8900_write;
1302         codec->dai = &wm8900_dai;
1303         codec->num_dai = 1;
1304         codec->hw_write = (hw_write_t)i2c_master_send;
1305         codec->control_data = i2c;
1306         codec->set_bias_level = wm8900_set_bias_level;
1307         codec->dev = &i2c->dev;
1308
1309         reg = wm8900_read(codec, WM8900_REG_ID);
1310         if (reg != 0x8900) {
1311                 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1312                 ret = -ENODEV;
1313                 goto err;
1314         }
1315
1316         /* Read back from the chip */
1317         reg = wm8900_chip_read(codec, WM8900_REG_POWER1);
1318         reg = (reg >> 12) & 0xf;
1319         dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
1320
1321         wm8900_reset(codec);
1322
1323         /* Turn the chip on */
1324         wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1325
1326         /* Latch the volume update bits */
1327         wm8900_write(codec, WM8900_REG_LINVOL,
1328                      wm8900_read(codec, WM8900_REG_LINVOL) | 0x100);
1329         wm8900_write(codec, WM8900_REG_RINVOL,
1330                      wm8900_read(codec, WM8900_REG_RINVOL) | 0x100);
1331         wm8900_write(codec, WM8900_REG_LOUT1CTL,
1332                      wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1333         wm8900_write(codec, WM8900_REG_ROUT1CTL,
1334                      wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1335         wm8900_write(codec, WM8900_REG_LOUT2CTL,
1336                      wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1337         wm8900_write(codec, WM8900_REG_ROUT2CTL,
1338                      wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1339         wm8900_write(codec, WM8900_REG_LDAC_DV,
1340                      wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1341         wm8900_write(codec, WM8900_REG_RDAC_DV,
1342                      wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1343         wm8900_write(codec, WM8900_REG_LADC_DV,
1344                      wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100);
1345         wm8900_write(codec, WM8900_REG_RADC_DV,
1346                      wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100);
1347
1348         /* Set the DAC and mixer output bias */
1349         wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1350
1351         wm8900_dai.dev = &i2c->dev;
1352
1353         wm8900_codec = codec;
1354
1355         ret = snd_soc_register_codec(codec);
1356         if (ret != 0) {
1357                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1358                 goto err;
1359         }
1360
1361         ret = snd_soc_register_dai(&wm8900_dai);
1362         if (ret != 0) {
1363                 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1364                 goto err_codec;
1365         }
1366
1367         return ret;
1368
1369 err_codec:
1370         snd_soc_unregister_codec(codec);
1371 err:
1372         kfree(wm8900);
1373         wm8900_codec = NULL;
1374         return ret;
1375 }
1376
1377 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1378 {
1379         snd_soc_unregister_dai(&wm8900_dai);
1380         snd_soc_unregister_codec(wm8900_codec);
1381
1382         wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
1383
1384         wm8900_dai.dev = NULL;
1385         kfree(wm8900_codec->private_data);
1386         wm8900_codec = NULL;
1387
1388         return 0;
1389 }
1390
1391 static const struct i2c_device_id wm8900_i2c_id[] = {
1392         { "wm8900", 0 },
1393         { }
1394 };
1395 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1396
1397 static struct i2c_driver wm8900_i2c_driver = {
1398         .driver = {
1399                 .name = "WM8900",
1400                 .owner = THIS_MODULE,
1401         },
1402         .probe = wm8900_i2c_probe,
1403         .remove = __devexit_p(wm8900_i2c_remove),
1404         .id_table = wm8900_i2c_id,
1405 };
1406
1407 static int wm8900_probe(struct platform_device *pdev)
1408 {
1409         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1410         struct snd_soc_codec *codec;
1411         int ret = 0;
1412
1413         if (!wm8900_codec) {
1414                 dev_err(&pdev->dev, "I2C client not yet instantiated\n");
1415                 return -ENODEV;
1416         }
1417
1418         codec = wm8900_codec;
1419         socdev->card->codec = codec;
1420
1421         /* Register pcms */
1422         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1423         if (ret < 0) {
1424                 dev_err(&pdev->dev, "Failed to register new PCMs\n");
1425                 goto pcm_err;
1426         }
1427
1428         snd_soc_add_controls(codec, wm8900_snd_controls,
1429                                 ARRAY_SIZE(wm8900_snd_controls));
1430         wm8900_add_widgets(codec);
1431
1432         ret = snd_soc_init_card(socdev);
1433         if (ret < 0) {
1434                 dev_err(&pdev->dev, "Failed to register card\n");
1435                 goto card_err;
1436         }
1437
1438         return ret;
1439
1440 card_err:
1441         snd_soc_free_pcms(socdev);
1442         snd_soc_dapm_free(socdev);
1443 pcm_err:
1444         return ret;
1445 }
1446
1447 /* power down chip */
1448 static int wm8900_remove(struct platform_device *pdev)
1449 {
1450         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1451
1452         snd_soc_free_pcms(socdev);
1453         snd_soc_dapm_free(socdev);
1454
1455         return 0;
1456 }
1457
1458 struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1459         .probe =        wm8900_probe,
1460         .remove =       wm8900_remove,
1461         .suspend =      wm8900_suspend,
1462         .resume =       wm8900_resume,
1463 };
1464 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1465
1466 static int __init wm8900_modinit(void)
1467 {
1468         return i2c_add_driver(&wm8900_i2c_driver);
1469 }
1470 module_init(wm8900_modinit);
1471
1472 static void __exit wm8900_exit(void)
1473 {
1474         i2c_del_driver(&wm8900_i2c_driver);
1475 }
1476 module_exit(wm8900_exit);
1477
1478 MODULE_DESCRIPTION("ASoC WM8900 driver");
1479 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1480 MODULE_LICENSE("GPL");