sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/initval.h>
  40 #include <sound/tlv.h>
  41
  42 #include <sound/tlv320dac33-plat.h>
  43 #include "tlv320dac33.h"
  44
  45 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  46                                                  * 6144 stereo */
  47 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  48
  49 #define NSAMPLE_MAX             5700
  50
  51 #define MODE7_LTHR              10
  52 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  53
  54 #define BURST_BASEFREQ_HZ       49152000
  55
  56 #define SAMPLES_TO_US(rate, samples) \
  57         (1000000000 / ((rate * 1000) / samples))
  58
  59 #define US_TO_SAMPLES(rate, us) \
  60         (rate / (1000000 / (us < 1000000 ? us : 1000000)))
  61
  62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  63         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  64
  65 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  66 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  67
  68 enum dac33_state {
  69         DAC33_IDLE = 0,
  70         DAC33_PREFILL,
  71         DAC33_PLAYBACK,
  72         DAC33_FLUSH,
  73 };
  74
  75 enum dac33_fifo_modes {
  76         DAC33_FIFO_BYPASS = 0,
  77         DAC33_FIFO_MODE1,
  78         DAC33_FIFO_MODE7,
  79         DAC33_FIFO_LAST_MODE,
  80 };
  81
  82 #define DAC33_NUM_SUPPLIES 3
  83 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  84         "AVDD",
  85         "DVDD",
  86         "IOVDD",
  87 };
  88
  89 struct tlv320dac33_priv {
  90         struct mutex mutex;
  91         struct workqueue_struct *dac33_wq;
  92         struct work_struct work;
  93         struct snd_soc_codec *codec;
  94         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  95         struct snd_pcm_substream *substream;
  96         int power_gpio;
  97         int chip_power;
  98         int irq;
  99         unsigned int refclk;
 100
 101         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 102         unsigned int nsample_min;       /* nsample should not be lower than
 103                                          * this */
 104         unsigned int nsample_max;       /* nsample should not be higher than
 105                                          * this */
 106         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 107         unsigned int nsample;           /* burst read amount from host */
 108         int mode1_latency;              /* latency caused by the i2c writes in
 109                                          * us */
 110         int auto_fifo_config;           /* Configure the FIFO based on the
 111                                          * period size */
 112         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 113         unsigned int burst_rate;        /* Interface speed in Burst modes */
 114
 115         int keep_bclk;                  /* Keep the BCLK continuously running
 116                                          * in FIFO modes */
 117         spinlock_t lock;
 118         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 119         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 120
 121         unsigned int mode1_us_burst;    /* Time to burst read n number of
 122                                          * samples */
 123         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 124
 125         unsigned int uthr;
 126
 127         enum dac33_state state;
 128         enum snd_soc_control_type control_type;
 129         void *control_data;
 130 };
 131
 132 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 133 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 134 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 136 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 137 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 138 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 140 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 141 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 142 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 143 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 144 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 145 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 146 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 147 0x00, 0x00,             /* 0x38 - 0x39 */
 148 /* Registers 0x3a - 0x3f are reserved  */
 149             0x00, 0x00, /* 0x3a - 0x3b */
 150 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 151
 152 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 153 0x00, 0x80,             /* 0x44 - 0x45 */
 154 /* Registers 0x46 - 0x47 are reserved  */
 155             0x80, 0x80, /* 0x46 - 0x47 */
 156
 157 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 158 /* Registers 0x4b - 0x7c are reserved  */
 159                   0x00, /* 0x4b        */
 160 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 161 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 162 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 164 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 165 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 166 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 168 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 169 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 170 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 171 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 172 0x00,                   /* 0x7c        */
 173
 174       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 175 };
 176
 177 /* Register read and write */
 178 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 179                                                 unsigned reg)
 180 {
 181         u8 *cache = codec->reg_cache;
 182         if (reg >= DAC33_CACHEREGNUM)
 183                 return 0;
 184
 185         return cache[reg];
 186 }
 187
 188 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 189                                          u8 reg, u8 value)
 190 {
 191         u8 *cache = codec->reg_cache;
 192         if (reg >= DAC33_CACHEREGNUM)
 193                 return;
 194
 195         cache[reg] = value;
 196 }
 197
 198 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 199                       u8 *value)
 200 {
 201         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 202         int val, ret = 0;
 203
 204         *value = reg & 0xff;
 205
 206         /* If powered off, return the cached value */
 207         if (dac33->chip_power) {
 208                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 209                 if (val < 0) {
 210                         dev_err(codec->dev, "Read failed (%d)\n", val);
 211                         value[0] = dac33_read_reg_cache(codec, reg);
 212                         ret = val;
 213                 } else {
 214                         value[0] = val;
 215                         dac33_write_reg_cache(codec, reg, val);
 216                 }
 217         } else {
 218                 value[0] = dac33_read_reg_cache(codec, reg);
 219         }
 220
 221         return ret;
 222 }
 223
 224 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 225                        unsigned int value)
 226 {
 227         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 228         u8 data[2];
 229         int ret = 0;
 230
 231         /*
 232          * data is
 233          *   D15..D8 dac33 register offset
 234          *   D7...D0 register data
 235          */
 236         data[0] = reg & 0xff;
 237         data[1] = value & 0xff;
 238
 239         dac33_write_reg_cache(codec, data[0], data[1]);
 240         if (dac33->chip_power) {
 241                 ret = codec->hw_write(codec->control_data, data, 2);
 242                 if (ret != 2)
 243                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 244                 else
 245                         ret = 0;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 252                        unsigned int value)
 253 {
 254         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 255         int ret;
 256
 257         mutex_lock(&dac33->mutex);
 258         ret = dac33_write(codec, reg, value);
 259         mutex_unlock(&dac33->mutex);
 260
 261         return ret;
 262 }
 263
 264 #define DAC33_I2C_ADDR_AUTOINC  0x80
 265 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 266                        unsigned int value)
 267 {
 268         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 269         u8 data[3];
 270         int ret = 0;
 271
 272         /*
 273          * data is
 274          *   D23..D16 dac33 register offset
 275          *   D15..D8  register data MSB
 276          *   D7...D0  register data LSB
 277          */
 278         data[0] = reg & 0xff;
 279         data[1] = (value >> 8) & 0xff;
 280         data[2] = value & 0xff;
 281
 282         dac33_write_reg_cache(codec, data[0], data[1]);
 283         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 284
 285         if (dac33->chip_power) {
 286                 /* We need to set autoincrement mode for 16 bit writes */
 287                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 288                 ret = codec->hw_write(codec->control_data, data, 3);
 289                 if (ret != 3)
 290                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 291                 else
 292                         ret = 0;
 293         }
 294
 295         return ret;
 296 }
 297
 298 static void dac33_init_chip(struct snd_soc_codec *codec)
 299 {
 300         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 301
 302         if (unlikely(!dac33->chip_power))
 303                 return;
 304
 305         /* 44-46: DAC Control Registers */
 306         /* A : DAC sample rate Fsref/1.5 */
 307         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 308         /* B : DAC src=normal, not muted */
 309         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 310                                              DAC33_DACSRCL_LEFT);
 311         /* C : (defaults) */
 312         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 313
 314         /* 73 : volume soft stepping control,
 315          clock source = internal osc (?) */
 316         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 317
 318         /* Restore only selected registers (gains mostly) */
 319         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 320                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 321         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 322                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 323
 324         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 325                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 326         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 327                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 328 }
 329
 330 static inline int dac33_read_id(struct snd_soc_codec *codec)
 331 {
 332         int i, ret = 0;
 333         u8 reg;
 334
 335         for (i = 0; i < 3; i++) {
 336                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 337                 if (ret < 0)
 338                         break;
 339         }
 340
 341         return ret;
 342 }
 343
 344 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 345 {
 346         u8 reg;
 347
 348         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 349         if (power)
 350                 reg |= DAC33_PDNALLB;
 351         else
 352                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 353                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 354         dac33_write(codec, DAC33_PWR_CTRL, reg);
 355 }
 356
 357 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
 358 {
 359         u8 reg;
 360
 361         /* Stop the DAI clock */
 362         reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 363         reg &= ~DAC33_BCLKON;
 364         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
 365
 366         /* Power down the Oscillator, and DACs */
 367         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 368         reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
 369         dac33_write(codec, DAC33_PWR_CTRL, reg);
 370 }
 371
 372 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 373 {
 374         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 375         int ret = 0;
 376
 377         mutex_lock(&dac33->mutex);
 378
 379         /* Safety check */
 380         if (unlikely(power == dac33->chip_power)) {
 381                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 382                         power ? "ON" : "OFF");
 383                 goto exit;
 384         }
 385
 386         if (power) {
 387                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 388                                           dac33->supplies);
 389                 if (ret != 0) {
 390                         dev_err(codec->dev,
 391                                 "Failed to enable supplies: %d\n", ret);
 392                                 goto exit;
 393                 }
 394
 395                 if (dac33->power_gpio >= 0)
 396                         gpio_set_value(dac33->power_gpio, 1);
 397
 398                 dac33->chip_power = 1;
 399         } else {
 400                 dac33_soft_power(codec, 0);
 401                 if (dac33->power_gpio >= 0)
 402                         gpio_set_value(dac33->power_gpio, 0);
 403
 404                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 405                                              dac33->supplies);
 406                 if (ret != 0) {
 407                         dev_err(codec->dev,
 408                                 "Failed to disable supplies: %d\n", ret);
 409                         goto exit;
 410                 }
 411
 412                 dac33->chip_power = 0;
 413         }
 414
 415 exit:
 416         mutex_unlock(&dac33->mutex);
 417         return ret;
 418 }
 419
 420 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
 421                 struct snd_kcontrol *kcontrol, int event)
 422 {
 423         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 424
 425         switch (event) {
 426         case SND_SOC_DAPM_PRE_PMU:
 427                 if (likely(dac33->substream)) {
 428                         dac33_calculate_times(dac33->substream);
 429                         dac33_prepare_chip(dac33->substream);
 430                 }
 431                 break;
 432         case SND_SOC_DAPM_POST_PMD:
 433                 dac33_disable_digital(w->codec);
 434                 break;
 435         }
 436         return 0;
 437 }
 438
 439 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 440                          struct snd_ctl_elem_value *ucontrol)
 441 {
 442         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 443         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 444
 445         ucontrol->value.integer.value[0] = dac33->nsample;
 446
 447         return 0;
 448 }
 449
 450 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 451                          struct snd_ctl_elem_value *ucontrol)
 452 {
 453         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 454         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 455         int ret = 0;
 456
 457         if (dac33->nsample == ucontrol->value.integer.value[0])
 458                 return 0;
 459
 460         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 461             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 462                 ret = -EINVAL;
 463         } else {
 464                 dac33->nsample = ucontrol->value.integer.value[0];
 465                 /* Re calculate the burst time */
 466                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 467                                                       dac33->nsample);
 468         }
 469
 470         return ret;
 471 }
 472
 473 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
 474                          struct snd_ctl_elem_value *ucontrol)
 475 {
 476         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 477         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 478
 479         ucontrol->value.integer.value[0] = dac33->uthr;
 480
 481         return 0;
 482 }
 483
 484 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
 485                          struct snd_ctl_elem_value *ucontrol)
 486 {
 487         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 488         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 489         int ret = 0;
 490
 491         if (dac33->substream)
 492                 return -EBUSY;
 493
 494         if (dac33->uthr == ucontrol->value.integer.value[0])
 495                 return 0;
 496
 497         if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
 498             ucontrol->value.integer.value[0] > MODE7_UTHR)
 499                 ret = -EINVAL;
 500         else
 501                 dac33->uthr = ucontrol->value.integer.value[0];
 502
 503         return ret;
 504 }
 505
 506 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 507                          struct snd_ctl_elem_value *ucontrol)
 508 {
 509         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 510         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 511
 512         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 513
 514         return 0;
 515 }
 516
 517 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 518                          struct snd_ctl_elem_value *ucontrol)
 519 {
 520         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 521         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 522         int ret = 0;
 523
 524         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 525                 return 0;
 526         /* Do not allow changes while stream is running*/
 527         if (codec->active)
 528                 return -EPERM;
 529
 530         if (ucontrol->value.integer.value[0] < 0 ||
 531             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 532                 ret = -EINVAL;
 533         else
 534                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 535
 536         return ret;
 537 }
 538
 539 /* Codec operation modes */
 540 static const char *dac33_fifo_mode_texts[] = {
 541         "Bypass", "Mode 1", "Mode 7"
 542 };
 543
 544 static const struct soc_enum dac33_fifo_mode_enum =
 545         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 546                             dac33_fifo_mode_texts);
 547
 548 /* L/R Line Output Gain */
 549 static const char *lr_lineout_gain_texts[] = {
 550         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 551         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 552 };
 553
 554 static const struct soc_enum l_lineout_gain_enum =
 555         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 556                         ARRAY_SIZE(lr_lineout_gain_texts),
 557                         lr_lineout_gain_texts);
 558
 559 static const struct soc_enum r_lineout_gain_enum =
 560         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 561                         ARRAY_SIZE(lr_lineout_gain_texts),
 562                         lr_lineout_gain_texts);
 563
 564 /*
 565  * DACL/R digital volume control:
 566  * from 0 dB to -63.5 in 0.5 dB steps
 567  * Need to be inverted later on:
 568  * 0x00 == 0 dB
 569  * 0x7f == -63.5 dB
 570  */
 571 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 572
 573 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 574         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 575                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 576                 0, 0x7f, 1, dac_digivol_tlv),
 577         SOC_DOUBLE_R("DAC Digital Playback Switch",
 578                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 579         SOC_DOUBLE_R("Line to Line Out Volume",
 580                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 581         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 582         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 583 };
 584
 585 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 586         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 587                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 588 };
 589
 590 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
 591         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 592                 dac33_get_nsample, dac33_set_nsample),
 593         SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
 594                  dac33_get_uthr, dac33_set_uthr),
 595 };
 596
 597 /* Analog bypass */
 598 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 599         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 600
 601 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 602         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 603
 604 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 605         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 606         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 607
 608         SND_SOC_DAPM_INPUT("LINEL"),
 609         SND_SOC_DAPM_INPUT("LINER"),
 610
 611         SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
 612         SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 613
 614         /* Analog bypass */
 615         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 616                                 &dac33_dapm_abypassl_control),
 617         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 618                                 &dac33_dapm_abypassr_control),
 619
 620         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
 621                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 622         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
 623                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 624
 625         SND_SOC_DAPM_SUPPLY("Left DAC Power",
 626                             DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
 627         SND_SOC_DAPM_SUPPLY("Right DAC Power",
 628                             DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
 629
 630         SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
 631         SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 632 };
 633
 634 static const struct snd_soc_dapm_route audio_map[] = {
 635         /* Analog bypass */
 636         {"Analog Left Bypass", "Switch", "LINEL"},
 637         {"Analog Right Bypass", "Switch", "LINER"},
 638
 639         {"Output Left Amplifier", NULL, "DACL"},
 640         {"Output Right Amplifier", NULL, "DACR"},
 641
 642         {"Output Left Amplifier", NULL, "Analog Left Bypass"},
 643         {"Output Right Amplifier", NULL, "Analog Right Bypass"},
 644
 645         {"Output Left Amplifier", NULL, "Left DAC Power"},
 646         {"Output Right Amplifier", NULL, "Right DAC Power"},
 647
 648         /* output */
 649         {"LEFT_LO", NULL, "Output Left Amplifier"},
 650         {"RIGHT_LO", NULL, "Output Right Amplifier"},
 651 };
 652
 653 static int dac33_add_widgets(struct snd_soc_codec *codec)
 654 {
 655         struct snd_soc_dapm_context *dapm = &codec->dapm;
 656
 657         snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
 658                                   ARRAY_SIZE(dac33_dapm_widgets));
 659         /* set up audio path interconnects */
 660         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 661
 662         return 0;
 663 }
 664
 665 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 666                                 enum snd_soc_bias_level level)
 667 {
 668         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 669         int ret;
 670
 671         switch (level) {
 672         case SND_SOC_BIAS_ON:
 673                 if (!dac33->substream)
 674                         dac33_soft_power(codec, 1);
 675                 break;
 676         case SND_SOC_BIAS_PREPARE:
 677                 break;
 678         case SND_SOC_BIAS_STANDBY:
 679                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 680                         /* Coming from OFF, switch on the codec */
 681                         ret = dac33_hard_power(codec, 1);
 682                         if (ret != 0)
 683                                 return ret;
 684
 685                         dac33_init_chip(codec);
 686                 }
 687                 break;
 688         case SND_SOC_BIAS_OFF:
 689                 /* Do not power off, when the codec is already off */
 690                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 691                         return 0;
 692                 ret = dac33_hard_power(codec, 0);
 693                 if (ret != 0)
 694                         return ret;
 695                 break;
 696         }
 697         codec->dapm.bias_level = level;
 698
 699         return 0;
 700 }
 701
 702 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 703 {
 704         struct snd_soc_codec *codec = dac33->codec;
 705         unsigned int delay;
 706
 707         switch (dac33->fifo_mode) {
 708         case DAC33_FIFO_MODE1:
 709                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 710                         DAC33_THRREG(dac33->nsample));
 711
 712                 /* Take the timestamps */
 713                 spin_lock_irq(&dac33->lock);
 714                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 715                 dac33->t_stamp1 = dac33->t_stamp2;
 716                 spin_unlock_irq(&dac33->lock);
 717
 718                 dac33_write16(codec, DAC33_PREFILL_MSB,
 719                                 DAC33_THRREG(dac33->alarm_threshold));
 720                 /* Enable Alarm Threshold IRQ with a delay */
 721                 delay = SAMPLES_TO_US(dac33->burst_rate,
 722                                      dac33->alarm_threshold) + 1000;
 723                 usleep_range(delay, delay + 500);
 724                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 725                 break;
 726         case DAC33_FIFO_MODE7:
 727                 /* Take the timestamp */
 728                 spin_lock_irq(&dac33->lock);
 729                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 730                 /* Move back the timestamp with drain time */
 731                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 732                 spin_unlock_irq(&dac33->lock);
 733
 734                 dac33_write16(codec, DAC33_PREFILL_MSB,
 735                                 DAC33_THRREG(MODE7_LTHR));
 736
 737                 /* Enable Upper Threshold IRQ */
 738                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 739                 break;
 740         default:
 741                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 742                                                         dac33->fifo_mode);
 743                 break;
 744         }
 745 }
 746
 747 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 748 {
 749         struct snd_soc_codec *codec = dac33->codec;
 750
 751         switch (dac33->fifo_mode) {
 752         case DAC33_FIFO_MODE1:
 753                 /* Take the timestamp */
 754                 spin_lock_irq(&dac33->lock);
 755                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 756                 spin_unlock_irq(&dac33->lock);
 757
 758                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 759                                 DAC33_THRREG(dac33->nsample));
 760                 break;
 761         case DAC33_FIFO_MODE7:
 762                 /* At the moment we are not using interrupts in mode7 */
 763                 break;
 764         default:
 765                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 766                                                         dac33->fifo_mode);
 767                 break;
 768         }
 769 }
 770
 771 static void dac33_work(struct work_struct *work)
 772 {
 773         struct snd_soc_codec *codec;
 774         struct tlv320dac33_priv *dac33;
 775         u8 reg;
 776
 777         dac33 = container_of(work, struct tlv320dac33_priv, work);
 778         codec = dac33->codec;
 779
 780         mutex_lock(&dac33->mutex);
 781         switch (dac33->state) {
 782         case DAC33_PREFILL:
 783                 dac33->state = DAC33_PLAYBACK;
 784                 dac33_prefill_handler(dac33);
 785                 break;
 786         case DAC33_PLAYBACK:
 787                 dac33_playback_handler(dac33);
 788                 break;
 789         case DAC33_IDLE:
 790                 break;
 791         case DAC33_FLUSH:
 792                 dac33->state = DAC33_IDLE;
 793                 /* Mask all interrupts from dac33 */
 794                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 795
 796                 /* flush fifo */
 797                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 798                 reg |= DAC33_FIFOFLUSH;
 799                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 800                 break;
 801         }
 802         mutex_unlock(&dac33->mutex);
 803 }
 804
 805 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 806 {
 807         struct snd_soc_codec *codec = dev;
 808         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 809
 810         spin_lock(&dac33->lock);
 811         dac33->t_stamp1 = ktime_to_us(ktime_get());
 812         spin_unlock(&dac33->lock);
 813
 814         /* Do not schedule the workqueue in Mode7 */
 815         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 816                 queue_work(dac33->dac33_wq, &dac33->work);
 817
 818         return IRQ_HANDLED;
 819 }
 820
 821 static void dac33_oscwait(struct snd_soc_codec *codec)
 822 {
 823         int timeout = 60;
 824         u8 reg;
 825
 826         do {
 827                 usleep_range(1000, 2000);
 828                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 829         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 830         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 831                 dev_err(codec->dev,
 832                         "internal oscillator calibration failed\n");
 833 }
 834
 835 static int dac33_startup(struct snd_pcm_substream *substream,
 836                            struct snd_soc_dai *dai)
 837 {
 838         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 839         struct snd_soc_codec *codec = rtd->codec;
 840         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 841
 842         /* Stream started, save the substream pointer */
 843         dac33->substream = substream;
 844
 845         return 0;
 846 }
 847
 848 static void dac33_shutdown(struct snd_pcm_substream *substream,
 849                              struct snd_soc_dai *dai)
 850 {
 851         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 852         struct snd_soc_codec *codec = rtd->codec;
 853         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 854
 855         dac33->substream = NULL;
 856
 857         /* Reset the nSample restrictions */
 858         dac33->nsample_min = 0;
 859         dac33->nsample_max = NSAMPLE_MAX;
 860 }
 861
 862 static int dac33_hw_params(struct snd_pcm_substream *substream,
 863                            struct snd_pcm_hw_params *params,
 864                            struct snd_soc_dai *dai)
 865 {
 866         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 867         struct snd_soc_codec *codec = rtd->codec;
 868
 869         /* Check parameters for validity */
 870         switch (params_rate(params)) {
 871         case 44100:
 872         case 48000:
 873                 break;
 874         default:
 875                 dev_err(codec->dev, "unsupported rate %d\n",
 876                         params_rate(params));
 877                 return -EINVAL;
 878         }
 879
 880         switch (params_format(params)) {
 881         case SNDRV_PCM_FORMAT_S16_LE:
 882                 break;
 883         default:
 884                 dev_err(codec->dev, "unsupported format %d\n",
 885                         params_format(params));
 886                 return -EINVAL;
 887         }
 888
 889         return 0;
 890 }
 891
 892 #define CALC_OSCSET(rate, refclk) ( \
 893         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 894 #define CALC_RATIOSET(rate, refclk) ( \
 895         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 896
 897 /*
 898  * tlv320dac33 is strict on the sequence of the register writes, if the register
 899  * writes happens in different order, than dac33 might end up in unknown state.
 900  * Use the known, working sequence of register writes to initialize the dac33.
 901  */
 902 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 903 {
 904         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 905         struct snd_soc_codec *codec = rtd->codec;
 906         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 907         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 908         u8 aictrl_a, aictrl_b, fifoctrl_a;
 909
 910         switch (substream->runtime->rate) {
 911         case 44100:
 912         case 48000:
 913                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 914                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 915                                          dac33->refclk);
 916                 break;
 917         default:
 918                 dev_err(codec->dev, "unsupported rate %d\n",
 919                         substream->runtime->rate);
 920                 return -EINVAL;
 921         }
 922
 923
 924         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 925         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 926         /* Read FIFO control A, and clear FIFO flush bit */
 927         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 928         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 929
 930         fifoctrl_a &= ~DAC33_WIDTH;
 931         switch (substream->runtime->format) {
 932         case SNDRV_PCM_FORMAT_S16_LE:
 933                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 934                 fifoctrl_a |= DAC33_WIDTH;
 935                 break;
 936         default:
 937                 dev_err(codec->dev, "unsupported format %d\n",
 938                         substream->runtime->format);
 939                 return -EINVAL;
 940         }
 941
 942         mutex_lock(&dac33->mutex);
 943
 944         if (!dac33->chip_power) {
 945                 /*
 946                  * Chip is not powered yet.
 947                  * Do the init in the dac33_set_bias_level later.
 948                  */
 949                 mutex_unlock(&dac33->mutex);
 950                 return 0;
 951         }
 952
 953         dac33_soft_power(codec, 0);
 954         dac33_soft_power(codec, 1);
 955
 956         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 957         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 958
 959         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 960         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 961
 962         /* calib time: 128 is a nice number ;) */
 963         dac33_write(codec, DAC33_CALIB_TIME, 128);
 964
 965         /* adjustment treshold & step */
 966         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 967                                                  DAC33_ADJSTEP(1));
 968
 969         /* div=4 / gain=1 / div */
 970         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 971
 972         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 973         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 974         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 975
 976         dac33_oscwait(codec);
 977
 978         if (dac33->fifo_mode) {
 979                 /* Generic for all FIFO modes */
 980                 /* 50-51 : ASRC Control registers */
 981                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 982                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 983
 984                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 985                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 986
 987                 /* Set interrupts to high active */
 988                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 989         } else {
 990                 /* FIFO bypass mode */
 991                 /* 50-51 : ASRC Control registers */
 992                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 993                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 994         }
 995
 996         /* Interrupt behaviour configuration */
 997         switch (dac33->fifo_mode) {
 998         case DAC33_FIFO_MODE1:
 999                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
1000                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
1001                 break;
1002         case DAC33_FIFO_MODE7:
1003                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
1004                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
1005                 break;
1006         default:
1007                 /* in FIFO bypass mode, the interrupts are not used */
1008                 break;
1009         }
1010
1011         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1012
1013         switch (dac33->fifo_mode) {
1014         case DAC33_FIFO_MODE1:
1015                 /*
1016                  * For mode1:
1017                  * Disable the FIFO bypass (Enable the use of FIFO)
1018                  * Select nSample mode
1019                  * BCLK is only running when data is needed by DAC33
1020                  */
1021                 fifoctrl_a &= ~DAC33_FBYPAS;
1022                 fifoctrl_a &= ~DAC33_FAUTO;
1023                 if (dac33->keep_bclk)
1024                         aictrl_b |= DAC33_BCLKON;
1025                 else
1026                         aictrl_b &= ~DAC33_BCLKON;
1027                 break;
1028         case DAC33_FIFO_MODE7:
1029                 /*
1030                  * For mode1:
1031                  * Disable the FIFO bypass (Enable the use of FIFO)
1032                  * Select Threshold mode
1033                  * BCLK is only running when data is needed by DAC33
1034                  */
1035                 fifoctrl_a &= ~DAC33_FBYPAS;
1036                 fifoctrl_a |= DAC33_FAUTO;
1037                 if (dac33->keep_bclk)
1038                         aictrl_b |= DAC33_BCLKON;
1039                 else
1040                         aictrl_b &= ~DAC33_BCLKON;
1041                 break;
1042         default:
1043                 /*
1044                  * For FIFO bypass mode:
1045                  * Enable the FIFO bypass (Disable the FIFO use)
1046                  * Set the BCLK as continous
1047                  */
1048                 fifoctrl_a |= DAC33_FBYPAS;
1049                 aictrl_b |= DAC33_BCLKON;
1050                 break;
1051         }
1052
1053         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1054         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1055         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1056
1057         /*
1058          * BCLK divide ratio
1059          * 0: 1.5
1060          * 1: 1
1061          * 2: 2
1062          * ...
1063          * 254: 254
1064          * 255: 255
1065          */
1066         if (dac33->fifo_mode)
1067                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1068                                                         dac33->burst_bclkdiv);
1069         else
1070                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1071
1072         switch (dac33->fifo_mode) {
1073         case DAC33_FIFO_MODE1:
1074                 dac33_write16(codec, DAC33_ATHR_MSB,
1075                               DAC33_THRREG(dac33->alarm_threshold));
1076                 break;
1077         case DAC33_FIFO_MODE7:
1078                 /*
1079                  * Configure the threshold levels, and leave 10 sample space
1080                  * at the bottom, and also at the top of the FIFO
1081                  */
1082                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1083                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1084                 break;
1085         default:
1086                 break;
1087         }
1088
1089         mutex_unlock(&dac33->mutex);
1090
1091         return 0;
1092 }
1093
1094 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1095 {
1096         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1097         struct snd_soc_codec *codec = rtd->codec;
1098         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1099         unsigned int period_size = substream->runtime->period_size;
1100         unsigned int rate = substream->runtime->rate;
1101         unsigned int nsample_limit;
1102
1103         /* In bypass mode we don't need to calculate */
1104         if (!dac33->fifo_mode)
1105                 return;
1106
1107         switch (dac33->fifo_mode) {
1108         case DAC33_FIFO_MODE1:
1109                 /* Number of samples under i2c latency */
1110                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1111                                                 dac33->mode1_latency);
1112                 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1113                                 dac33->alarm_threshold;
1114
1115                 if (dac33->auto_fifo_config) {
1116                         if (period_size <= dac33->alarm_threshold)
1117                                 /*
1118                                  * Configure nSamaple to number of periods,
1119                                  * which covers the latency requironment.
1120                                  */
1121                                 dac33->nsample = period_size *
1122                                        ((dac33->alarm_threshold / period_size) +
1123                                        (dac33->alarm_threshold % period_size ?
1124                                        1 : 0));
1125                         else if (period_size > nsample_limit)
1126                                 dac33->nsample = nsample_limit;
1127                         else
1128                                 dac33->nsample = period_size;
1129                 } else {
1130                         /* nSample time shall not be shorter than i2c latency */
1131                         dac33->nsample_min = dac33->alarm_threshold;
1132                         /*
1133                          * nSample should not be bigger than alsa buffer minus
1134                          * size of one period to avoid overruns
1135                          */
1136                         dac33->nsample_max = substream->runtime->buffer_size -
1137                                                 period_size;
1138
1139                         if (dac33->nsample_max > nsample_limit)
1140                                 dac33->nsample_max = nsample_limit;
1141
1142                         /* Correct the nSample if it is outside of the ranges */
1143                         if (dac33->nsample < dac33->nsample_min)
1144                                 dac33->nsample = dac33->nsample_min;
1145                         if (dac33->nsample > dac33->nsample_max)
1146                                 dac33->nsample = dac33->nsample_max;
1147                 }
1148
1149                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1150                                                       dac33->nsample);
1151                 dac33->t_stamp1 = 0;
1152                 dac33->t_stamp2 = 0;
1153                 break;
1154         case DAC33_FIFO_MODE7:
1155                 if (dac33->auto_fifo_config) {
1156                         dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1157                                         period_size,
1158                                         rate,
1159                                         dac33->burst_rate) + 9;
1160                         if (dac33->uthr > MODE7_UTHR)
1161                                 dac33->uthr = MODE7_UTHR;
1162                         if (dac33->uthr < (MODE7_LTHR + 10))
1163                                 dac33->uthr = (MODE7_LTHR + 10);
1164                 }
1165                 dac33->mode7_us_to_lthr =
1166                                 SAMPLES_TO_US(substream->runtime->rate,
1167                                         dac33->uthr - MODE7_LTHR + 1);
1168                 dac33->t_stamp1 = 0;
1169                 break;
1170         default:
1171                 break;
1172         }
1173
1174 }
1175
1176 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1177                              struct snd_soc_dai *dai)
1178 {
1179         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1180         struct snd_soc_codec *codec = rtd->codec;
1181         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1182         int ret = 0;
1183
1184         switch (cmd) {
1185         case SNDRV_PCM_TRIGGER_START:
1186         case SNDRV_PCM_TRIGGER_RESUME:
1187         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1188                 if (dac33->fifo_mode) {
1189                         dac33->state = DAC33_PREFILL;
1190                         queue_work(dac33->dac33_wq, &dac33->work);
1191                 }
1192                 break;
1193         case SNDRV_PCM_TRIGGER_STOP:
1194         case SNDRV_PCM_TRIGGER_SUSPEND:
1195         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1196                 if (dac33->fifo_mode) {
1197                         dac33->state = DAC33_FLUSH;
1198                         queue_work(dac33->dac33_wq, &dac33->work);
1199                 }
1200                 break;
1201         default:
1202                 ret = -EINVAL;
1203         }
1204
1205         return ret;
1206 }
1207
1208 static snd_pcm_sframes_t dac33_dai_delay(
1209                         struct snd_pcm_substream *substream,
1210                         struct snd_soc_dai *dai)
1211 {
1212         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1213         struct snd_soc_codec *codec = rtd->codec;
1214         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1215         unsigned long long t0, t1, t_now;
1216         unsigned int time_delta, uthr;
1217         int samples_out, samples_in, samples;
1218         snd_pcm_sframes_t delay = 0;
1219
1220         switch (dac33->fifo_mode) {
1221         case DAC33_FIFO_BYPASS:
1222                 break;
1223         case DAC33_FIFO_MODE1:
1224                 spin_lock(&dac33->lock);
1225                 t0 = dac33->t_stamp1;
1226                 t1 = dac33->t_stamp2;
1227                 spin_unlock(&dac33->lock);
1228                 t_now = ktime_to_us(ktime_get());
1229
1230                 /* We have not started to fill the FIFO yet, delay is 0 */
1231                 if (!t1)
1232                         goto out;
1233
1234                 if (t0 > t1) {
1235                         /*
1236                          * Phase 1:
1237                          * After Alarm threshold, and before nSample write
1238                          */
1239                         time_delta = t_now - t0;
1240                         samples_out = time_delta ? US_TO_SAMPLES(
1241                                                 substream->runtime->rate,
1242                                                 time_delta) : 0;
1243
1244                         if (likely(dac33->alarm_threshold > samples_out))
1245                                 delay = dac33->alarm_threshold - samples_out;
1246                         else
1247                                 delay = 0;
1248                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1249                         /*
1250                          * Phase 2:
1251                          * After nSample write (during burst operation)
1252                          */
1253                         time_delta = t_now - t0;
1254                         samples_out = time_delta ? US_TO_SAMPLES(
1255                                                 substream->runtime->rate,
1256                                                 time_delta) : 0;
1257
1258                         time_delta = t_now - t1;
1259                         samples_in = time_delta ? US_TO_SAMPLES(
1260                                                 dac33->burst_rate,
1261                                                 time_delta) : 0;
1262
1263                         samples = dac33->alarm_threshold;
1264                         samples += (samples_in - samples_out);
1265
1266                         if (likely(samples > 0))
1267                                 delay = samples;
1268                         else
1269                                 delay = 0;
1270                 } else {
1271                         /*
1272                          * Phase 3:
1273                          * After burst operation, before next alarm threshold
1274                          */
1275                         time_delta = t_now - t0;
1276                         samples_out = time_delta ? US_TO_SAMPLES(
1277                                                 substream->runtime->rate,
1278                                                 time_delta) : 0;
1279
1280                         samples_in = dac33->nsample;
1281                         samples = dac33->alarm_threshold;
1282                         samples += (samples_in - samples_out);
1283
1284                         if (likely(samples > 0))
1285                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1286                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1287                         else
1288                                 delay = 0;
1289                 }
1290                 break;
1291         case DAC33_FIFO_MODE7:
1292                 spin_lock(&dac33->lock);
1293                 t0 = dac33->t_stamp1;
1294                 uthr = dac33->uthr;
1295                 spin_unlock(&dac33->lock);
1296                 t_now = ktime_to_us(ktime_get());
1297
1298                 /* We have not started to fill the FIFO yet, delay is 0 */
1299                 if (!t0)
1300                         goto out;
1301
1302                 if (t_now <= t0) {
1303                         /*
1304                          * Either the timestamps are messed or equal. Report
1305                          * maximum delay
1306                          */
1307                         delay = uthr;
1308                         goto out;
1309                 }
1310
1311                 time_delta = t_now - t0;
1312                 if (time_delta <= dac33->mode7_us_to_lthr) {
1313                         /*
1314                         * Phase 1:
1315                         * After burst (draining phase)
1316                         */
1317                         samples_out = US_TO_SAMPLES(
1318                                         substream->runtime->rate,
1319                                         time_delta);
1320
1321                         if (likely(uthr > samples_out))
1322                                 delay = uthr - samples_out;
1323                         else
1324                                 delay = 0;
1325                 } else {
1326                         /*
1327                         * Phase 2:
1328                         * During burst operation
1329                         */
1330                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1331
1332                         samples_out = US_TO_SAMPLES(
1333                                         substream->runtime->rate,
1334                                         time_delta);
1335                         samples_in = US_TO_SAMPLES(
1336                                         dac33->burst_rate,
1337                                         time_delta);
1338                         delay = MODE7_LTHR + samples_in - samples_out;
1339
1340                         if (unlikely(delay > uthr))
1341                                 delay = uthr;
1342                 }
1343                 break;
1344         default:
1345                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1346                                                         dac33->fifo_mode);
1347                 break;
1348         }
1349 out:
1350         return delay;
1351 }
1352
1353 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1354                 int clk_id, unsigned int freq, int dir)
1355 {
1356         struct snd_soc_codec *codec = codec_dai->codec;
1357         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1358         u8 ioc_reg, asrcb_reg;
1359
1360         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1361         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1362         switch (clk_id) {
1363         case TLV320DAC33_MCLK:
1364                 ioc_reg |= DAC33_REFSEL;
1365                 asrcb_reg |= DAC33_SRCREFSEL;
1366                 break;
1367         case TLV320DAC33_SLEEPCLK:
1368                 ioc_reg &= ~DAC33_REFSEL;
1369                 asrcb_reg &= ~DAC33_SRCREFSEL;
1370                 break;
1371         default:
1372                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1373                 break;
1374         }
1375         dac33->refclk = freq;
1376
1377         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1378         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1379
1380         return 0;
1381 }
1382
1383 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1384                              unsigned int fmt)
1385 {
1386         struct snd_soc_codec *codec = codec_dai->codec;
1387         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1388         u8 aictrl_a, aictrl_b;
1389
1390         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1391         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1392         /* set master/slave audio interface */
1393         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1394         case SND_SOC_DAIFMT_CBM_CFM:
1395                 /* Codec Master */
1396                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1397                 break;
1398         case SND_SOC_DAIFMT_CBS_CFS:
1399                 /* Codec Slave */
1400                 if (dac33->fifo_mode) {
1401                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1402                         return -EINVAL;
1403                 } else
1404                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1405                 break;
1406         default:
1407                 return -EINVAL;
1408         }
1409
1410         aictrl_a &= ~DAC33_AFMT_MASK;
1411         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1412         case SND_SOC_DAIFMT_I2S:
1413                 aictrl_a |= DAC33_AFMT_I2S;
1414                 break;
1415         case SND_SOC_DAIFMT_DSP_A:
1416                 aictrl_a |= DAC33_AFMT_DSP;
1417                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1418                 aictrl_b |= DAC33_DATA_DELAY(0);
1419                 break;
1420         case SND_SOC_DAIFMT_RIGHT_J:
1421                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1422                 break;
1423         case SND_SOC_DAIFMT_LEFT_J:
1424                 aictrl_a |= DAC33_AFMT_LEFT_J;
1425                 break;
1426         default:
1427                 dev_err(codec->dev, "Unsupported format (%u)\n",
1428                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1429                 return -EINVAL;
1430         }
1431
1432         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1433         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1434
1435         return 0;
1436 }
1437
1438 static int dac33_soc_probe(struct snd_soc_codec *codec)
1439 {
1440         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1441         int ret = 0;
1442
1443         codec->control_data = dac33->control_data;
1444         codec->hw_write = (hw_write_t) i2c_master_send;
1445         codec->dapm.idle_bias_off = 1;
1446         dac33->codec = codec;
1447
1448         /* Read the tlv320dac33 ID registers */
1449         ret = dac33_hard_power(codec, 1);
1450         if (ret != 0) {
1451                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1452                 goto err_power;
1453         }
1454         ret = dac33_read_id(codec);
1455         dac33_hard_power(codec, 0);
1456
1457         if (ret < 0) {
1458                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1459                 ret = -ENODEV;
1460                 goto err_power;
1461         }
1462
1463         /* Check if the IRQ number is valid and request it */
1464         if (dac33->irq >= 0) {
1465                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1466                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1467                                   codec->name, codec);
1468                 if (ret < 0) {
1469                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1470                                                 dac33->irq, ret);
1471                         dac33->irq = -1;
1472                 }
1473                 if (dac33->irq != -1) {
1474                         /* Setup work queue */
1475                         dac33->dac33_wq =
1476                                 create_singlethread_workqueue("tlv320dac33");
1477                         if (dac33->dac33_wq == NULL) {
1478                                 free_irq(dac33->irq, codec);
1479                                 return -ENOMEM;
1480                         }
1481
1482                         INIT_WORK(&dac33->work, dac33_work);
1483                 }
1484         }
1485
1486         snd_soc_add_controls(codec, dac33_snd_controls,
1487                              ARRAY_SIZE(dac33_snd_controls));
1488         /* Only add the FIFO controls, if we have valid IRQ number */
1489         if (dac33->irq >= 0) {
1490                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1491                                      ARRAY_SIZE(dac33_mode_snd_controls));
1492                 /* FIFO usage controls only, if autoio config is not selected */
1493                 if (!dac33->auto_fifo_config)
1494                         snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1495                                         ARRAY_SIZE(dac33_fifo_snd_controls));
1496         }
1497         dac33_add_widgets(codec);
1498
1499 err_power:
1500         return ret;
1501 }
1502
1503 static int dac33_soc_remove(struct snd_soc_codec *codec)
1504 {
1505         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1506
1507         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1508
1509         if (dac33->irq >= 0) {
1510                 free_irq(dac33->irq, dac33->codec);
1511                 destroy_workqueue(dac33->dac33_wq);
1512         }
1513         return 0;
1514 }
1515
1516 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1517 {
1518         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1519
1520         return 0;
1521 }
1522
1523 static int dac33_soc_resume(struct snd_soc_codec *codec)
1524 {
1525         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1526
1527         return 0;
1528 }
1529
1530 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1531         .read = dac33_read_reg_cache,
1532         .write = dac33_write_locked,
1533         .set_bias_level = dac33_set_bias_level,
1534         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1535         .reg_word_size = sizeof(u8),
1536         .reg_cache_default = dac33_reg,
1537         .probe = dac33_soc_probe,
1538         .remove = dac33_soc_remove,
1539         .suspend = dac33_soc_suspend,
1540         .resume = dac33_soc_resume,
1541 };
1542
1543 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1544                          SNDRV_PCM_RATE_48000)
1545 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1546
1547 static struct snd_soc_dai_ops dac33_dai_ops = {
1548         .startup        = dac33_startup,
1549         .shutdown       = dac33_shutdown,
1550         .hw_params      = dac33_hw_params,
1551         .trigger        = dac33_pcm_trigger,
1552         .delay          = dac33_dai_delay,
1553         .set_sysclk     = dac33_set_dai_sysclk,
1554         .set_fmt        = dac33_set_dai_fmt,
1555 };
1556
1557 static struct snd_soc_dai_driver dac33_dai = {
1558         .name = "tlv320dac33-hifi",
1559         .playback = {
1560                 .stream_name = "Playback",
1561                 .channels_min = 2,
1562                 .channels_max = 2,
1563                 .rates = DAC33_RATES,
1564                 .formats = DAC33_FORMATS,},
1565         .ops = &dac33_dai_ops,
1566 };
1567
1568 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1569                                      const struct i2c_device_id *id)
1570 {
1571         struct tlv320dac33_platform_data *pdata;
1572         struct tlv320dac33_priv *dac33;
1573         int ret, i;
1574
1575         if (client->dev.platform_data == NULL) {
1576                 dev_err(&client->dev, "Platform data not set\n");
1577                 return -ENODEV;
1578         }
1579         pdata = client->dev.platform_data;
1580
1581         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1582         if (dac33 == NULL)
1583                 return -ENOMEM;
1584
1585         dac33->control_data = client;
1586         mutex_init(&dac33->mutex);
1587         spin_lock_init(&dac33->lock);
1588
1589         i2c_set_clientdata(client, dac33);
1590
1591         dac33->power_gpio = pdata->power_gpio;
1592         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1593         /* Pre calculate the burst rate */
1594         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1595         dac33->keep_bclk = pdata->keep_bclk;
1596         dac33->auto_fifo_config = pdata->auto_fifo_config;
1597         dac33->mode1_latency = pdata->mode1_latency;
1598         if (!dac33->mode1_latency)
1599                 dac33->mode1_latency = 10000; /* 10ms */
1600         dac33->irq = client->irq;
1601         dac33->nsample = NSAMPLE_MAX;
1602         dac33->nsample_max = NSAMPLE_MAX;
1603         dac33->uthr = MODE7_UTHR;
1604         /* Disable FIFO use by default */
1605         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1606
1607         /* Check if the reset GPIO number is valid and request it */
1608         if (dac33->power_gpio >= 0) {
1609                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1610                 if (ret < 0) {
1611                         dev_err(&client->dev,
1612                                 "Failed to request reset GPIO (%d)\n",
1613                                 dac33->power_gpio);
1614                         goto err_gpio;
1615                 }
1616                 gpio_direction_output(dac33->power_gpio, 0);
1617         }
1618
1619         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1620                 dac33->supplies[i].supply = dac33_supply_names[i];
1621
1622         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1623                                  dac33->supplies);
1624
1625         if (ret != 0) {
1626                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1627                 goto err_get;
1628         }
1629
1630         ret = snd_soc_register_codec(&client->dev,
1631                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1632         if (ret < 0)
1633                 goto err_register;
1634
1635         return ret;
1636 err_register:
1637         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1638 err_get:
1639         if (dac33->power_gpio >= 0)
1640                 gpio_free(dac33->power_gpio);
1641 err_gpio:
1642         kfree(dac33);
1643         return ret;
1644 }
1645
1646 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1647 {
1648         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1649
1650         if (unlikely(dac33->chip_power))
1651                 dac33_hard_power(dac33->codec, 0);
1652
1653         if (dac33->power_gpio >= 0)
1654                 gpio_free(dac33->power_gpio);
1655
1656         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1657
1658         snd_soc_unregister_codec(&client->dev);
1659         kfree(dac33);
1660
1661         return 0;
1662 }
1663
1664 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1665         {
1666                 .name = "tlv320dac33",
1667                 .driver_data = 0,
1668         },
1669         { },
1670 };
1671
1672 static struct i2c_driver tlv320dac33_i2c_driver = {
1673         .driver = {
1674                 .name = "tlv320dac33-codec",
1675                 .owner = THIS_MODULE,
1676         },
1677         .probe          = dac33_i2c_probe,
1678         .remove         = __devexit_p(dac33_i2c_remove),
1679         .id_table       = tlv320dac33_i2c_id,
1680 };
1681
1682 static int __init dac33_module_init(void)
1683 {
1684         int r;
1685         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1686         if (r < 0) {
1687                 printk(KERN_ERR "DAC33: driver registration failed\n");
1688                 return r;
1689         }
1690         return 0;
1691 }
1692 module_init(dac33_module_init);
1693
1694 static void __exit dac33_module_exit(void)
1695 {
1696         i2c_del_driver(&tlv320dac33_i2c_driver);
1697 }
1698 module_exit(dac33_module_exit);
1699
1700
1701 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1702 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1703 MODULE_LICENSE("GPL");