sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/initval.h>
  40 #include <sound/tlv.h>
  41
  42 #include <sound/tlv320dac33-plat.h>
  43 #include "tlv320dac33.h"
  44
  45 /*
  46  * The internal FIFO is 24576 bytes long
  47  * It can be configured to hold 16bit or 24bit samples
  48  * In 16bit configuration the FIFO can hold 6144 stereo samples
  49  * In 24bit configuration the FIFO can hold 4096 stereo samples
  50  */
  51 #define DAC33_FIFO_SIZE_16BIT   6144
  52 #define DAC33_FIFO_SIZE_24BIT   4096
  53 #define DAC33_MODE7_MARGIN      10      /* Safety margin for FIFO in Mode7 */
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / (((rate) * 1000) / (samples)))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 104         unsigned int fifo_size;         /* Size of the FIFO in samples */
 105         unsigned int nsample;           /* burst read amount from host */
 106         int mode1_latency;              /* latency caused by the i2c writes in
 107                                          * us */
 108         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 109         unsigned int burst_rate;        /* Interface speed in Burst modes */
 110
 111         int keep_bclk;                  /* Keep the BCLK continuously running
 112                                          * in FIFO modes */
 113         spinlock_t lock;
 114         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 115         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 116
 117         unsigned int mode1_us_burst;    /* Time to burst read n number of
 118                                          * samples */
 119         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 120
 121         unsigned int uthr;
 122
 123         enum dac33_state state;
 124         enum snd_soc_control_type control_type;
 125         void *control_data;
 126 };
 127
 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 143 0x00, 0x00,             /* 0x38 - 0x39 */
 144 /* Registers 0x3a - 0x3f are reserved  */
 145             0x00, 0x00, /* 0x3a - 0x3b */
 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 147
 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 149 0x00, 0x80,             /* 0x44 - 0x45 */
 150 /* Registers 0x46 - 0x47 are reserved  */
 151             0x80, 0x80, /* 0x46 - 0x47 */
 152
 153 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 154 /* Registers 0x4b - 0x7c are reserved  */
 155                   0x00, /* 0x4b        */
 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 168 0x00,                   /* 0x7c        */
 169
 170       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 171 };
 172
 173 /* Register read and write */
 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 175                                                 unsigned reg)
 176 {
 177         u8 *cache = codec->reg_cache;
 178         if (reg >= DAC33_CACHEREGNUM)
 179                 return 0;
 180
 181         return cache[reg];
 182 }
 183
 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 185                                          u8 reg, u8 value)
 186 {
 187         u8 *cache = codec->reg_cache;
 188         if (reg >= DAC33_CACHEREGNUM)
 189                 return;
 190
 191         cache[reg] = value;
 192 }
 193
 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 195                       u8 *value)
 196 {
 197         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 198         int val, ret = 0;
 199
 200         *value = reg & 0xff;
 201
 202         /* If powered off, return the cached value */
 203         if (dac33->chip_power) {
 204                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 205                 if (val < 0) {
 206                         dev_err(codec->dev, "Read failed (%d)\n", val);
 207                         value[0] = dac33_read_reg_cache(codec, reg);
 208                         ret = val;
 209                 } else {
 210                         value[0] = val;
 211                         dac33_write_reg_cache(codec, reg, val);
 212                 }
 213         } else {
 214                 value[0] = dac33_read_reg_cache(codec, reg);
 215         }
 216
 217         return ret;
 218 }
 219
 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 221                        unsigned int value)
 222 {
 223         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 224         u8 data[2];
 225         int ret = 0;
 226
 227         /*
 228          * data is
 229          *   D15..D8 dac33 register offset
 230          *   D7...D0 register data
 231          */
 232         data[0] = reg & 0xff;
 233         data[1] = value & 0xff;
 234
 235         dac33_write_reg_cache(codec, data[0], data[1]);
 236         if (dac33->chip_power) {
 237                 ret = codec->hw_write(codec->control_data, data, 2);
 238                 if (ret != 2)
 239                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 240                 else
 241                         ret = 0;
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 248                        unsigned int value)
 249 {
 250         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 251         int ret;
 252
 253         mutex_lock(&dac33->mutex);
 254         ret = dac33_write(codec, reg, value);
 255         mutex_unlock(&dac33->mutex);
 256
 257         return ret;
 258 }
 259
 260 #define DAC33_I2C_ADDR_AUTOINC  0x80
 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 262                        unsigned int value)
 263 {
 264         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 265         u8 data[3];
 266         int ret = 0;
 267
 268         /*
 269          * data is
 270          *   D23..D16 dac33 register offset
 271          *   D15..D8  register data MSB
 272          *   D7...D0  register data LSB
 273          */
 274         data[0] = reg & 0xff;
 275         data[1] = (value >> 8) & 0xff;
 276         data[2] = value & 0xff;
 277
 278         dac33_write_reg_cache(codec, data[0], data[1]);
 279         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 280
 281         if (dac33->chip_power) {
 282                 /* We need to set autoincrement mode for 16 bit writes */
 283                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 284                 ret = codec->hw_write(codec->control_data, data, 3);
 285                 if (ret != 3)
 286                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 287                 else
 288                         ret = 0;
 289         }
 290
 291         return ret;
 292 }
 293
 294 static void dac33_init_chip(struct snd_soc_codec *codec)
 295 {
 296         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 297
 298         if (unlikely(!dac33->chip_power))
 299                 return;
 300
 301         /* A : DAC sample rate Fsref/1.5 */
 302         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 303         /* B : DAC src=normal, not muted */
 304         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 305                                              DAC33_DACSRCL_LEFT);
 306         /* C : (defaults) */
 307         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 308
 309         /* 73 : volume soft stepping control,
 310          clock source = internal osc (?) */
 311         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 312
 313         /* Restore only selected registers (gains mostly) */
 314         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 315                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 316         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 317                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 318
 319         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 320                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 321         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 322                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 323
 324         dac33_write(codec, DAC33_OUT_AMP_CTRL,
 325                     dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
 326
 327         dac33_write(codec, DAC33_LDAC_PWR_CTRL,
 328                     dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
 329         dac33_write(codec, DAC33_RDAC_PWR_CTRL,
 330                     dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
 331 }
 332
 333 static inline int dac33_read_id(struct snd_soc_codec *codec)
 334 {
 335         int i, ret = 0;
 336         u8 reg;
 337
 338         for (i = 0; i < 3; i++) {
 339                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 340                 if (ret < 0)
 341                         break;
 342         }
 343
 344         return ret;
 345 }
 346
 347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 348 {
 349         u8 reg;
 350
 351         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 352         if (power)
 353                 reg |= DAC33_PDNALLB;
 354         else
 355                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 356                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 357         dac33_write(codec, DAC33_PWR_CTRL, reg);
 358 }
 359
 360 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
 361 {
 362         u8 reg;
 363
 364         /* Stop the DAI clock */
 365         reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 366         reg &= ~DAC33_BCLKON;
 367         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
 368
 369         /* Power down the Oscillator, and DACs */
 370         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 371         reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
 372         dac33_write(codec, DAC33_PWR_CTRL, reg);
 373 }
 374
 375 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 376 {
 377         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 378         int ret = 0;
 379
 380         mutex_lock(&dac33->mutex);
 381
 382         /* Safety check */
 383         if (unlikely(power == dac33->chip_power)) {
 384                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 385                         power ? "ON" : "OFF");
 386                 goto exit;
 387         }
 388
 389         if (power) {
 390                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 391                                           dac33->supplies);
 392                 if (ret != 0) {
 393                         dev_err(codec->dev,
 394                                 "Failed to enable supplies: %d\n", ret);
 395                                 goto exit;
 396                 }
 397
 398                 if (dac33->power_gpio >= 0)
 399                         gpio_set_value(dac33->power_gpio, 1);
 400
 401                 dac33->chip_power = 1;
 402         } else {
 403                 dac33_soft_power(codec, 0);
 404                 if (dac33->power_gpio >= 0)
 405                         gpio_set_value(dac33->power_gpio, 0);
 406
 407                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 408                                              dac33->supplies);
 409                 if (ret != 0) {
 410                         dev_err(codec->dev,
 411                                 "Failed to disable supplies: %d\n", ret);
 412                         goto exit;
 413                 }
 414
 415                 dac33->chip_power = 0;
 416         }
 417
 418 exit:
 419         mutex_unlock(&dac33->mutex);
 420         return ret;
 421 }
 422
 423 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
 424                 struct snd_kcontrol *kcontrol, int event)
 425 {
 426         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 427
 428         switch (event) {
 429         case SND_SOC_DAPM_PRE_PMU:
 430                 if (likely(dac33->substream)) {
 431                         dac33_calculate_times(dac33->substream);
 432                         dac33_prepare_chip(dac33->substream);
 433                 }
 434                 break;
 435         case SND_SOC_DAPM_POST_PMD:
 436                 dac33_disable_digital(w->codec);
 437                 break;
 438         }
 439         return 0;
 440 }
 441
 442 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 443                          struct snd_ctl_elem_value *ucontrol)
 444 {
 445         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 446         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 447
 448         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 449
 450         return 0;
 451 }
 452
 453 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 454                          struct snd_ctl_elem_value *ucontrol)
 455 {
 456         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 457         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 458         int ret = 0;
 459
 460         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 461                 return 0;
 462         /* Do not allow changes while stream is running*/
 463         if (codec->active)
 464                 return -EPERM;
 465
 466         if (ucontrol->value.integer.value[0] < 0 ||
 467             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 468                 ret = -EINVAL;
 469         else
 470                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 471
 472         return ret;
 473 }
 474
 475 /* Codec operation modes */
 476 static const char *dac33_fifo_mode_texts[] = {
 477         "Bypass", "Mode 1", "Mode 7"
 478 };
 479
 480 static const struct soc_enum dac33_fifo_mode_enum =
 481         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 482                             dac33_fifo_mode_texts);
 483
 484 /* L/R Line Output Gain */
 485 static const char *lr_lineout_gain_texts[] = {
 486         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 487         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 488 };
 489
 490 static const struct soc_enum l_lineout_gain_enum =
 491         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 492                         ARRAY_SIZE(lr_lineout_gain_texts),
 493                         lr_lineout_gain_texts);
 494
 495 static const struct soc_enum r_lineout_gain_enum =
 496         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 497                         ARRAY_SIZE(lr_lineout_gain_texts),
 498                         lr_lineout_gain_texts);
 499
 500 /*
 501  * DACL/R digital volume control:
 502  * from 0 dB to -63.5 in 0.5 dB steps
 503  * Need to be inverted later on:
 504  * 0x00 == 0 dB
 505  * 0x7f == -63.5 dB
 506  */
 507 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 508
 509 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 510         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 511                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 512                 0, 0x7f, 1, dac_digivol_tlv),
 513         SOC_DOUBLE_R("DAC Digital Playback Switch",
 514                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 515         SOC_DOUBLE_R("Line to Line Out Volume",
 516                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 517         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 518         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 519 };
 520
 521 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 522         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 523                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 524 };
 525
 526 /* Analog bypass */
 527 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 528         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 529
 530 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 531         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 532
 533 /* LOP L/R invert selection */
 534 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
 535
 536 static const struct soc_enum dac33_left_lom_enum =
 537         SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
 538                         ARRAY_SIZE(dac33_lr_lom_texts),
 539                         dac33_lr_lom_texts);
 540
 541 static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
 542 SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
 543
 544 static const struct soc_enum dac33_right_lom_enum =
 545         SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
 546                         ARRAY_SIZE(dac33_lr_lom_texts),
 547                         dac33_lr_lom_texts);
 548
 549 static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
 550 SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
 551
 552 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 553         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 554         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 555
 556         SND_SOC_DAPM_INPUT("LINEL"),
 557         SND_SOC_DAPM_INPUT("LINER"),
 558
 559         SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
 560         SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 561
 562         /* Analog bypass */
 563         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 564                                 &dac33_dapm_abypassl_control),
 565         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 566                                 &dac33_dapm_abypassr_control),
 567
 568         SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
 569                 &dac33_dapm_left_lom_control),
 570         SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
 571                 &dac33_dapm_right_lom_control),
 572         /*
 573          * For DAPM path, when only the anlog bypass path is enabled, and the
 574          * LOP inverted from the corresponding DAC side.
 575          * This is needed, so we can attach the DAC power supply in this case.
 576          */
 577         SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 578         SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 579
 580         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
 581                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 582         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
 583                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 584
 585         SND_SOC_DAPM_SUPPLY("Left DAC Power",
 586                             DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
 587         SND_SOC_DAPM_SUPPLY("Right DAC Power",
 588                             DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
 589
 590         SND_SOC_DAPM_SUPPLY("Codec Power",
 591                             DAC33_PWR_CTRL, 4, 0, NULL, 0),
 592
 593         SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
 594         SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 595 };
 596
 597 static const struct snd_soc_dapm_route audio_map[] = {
 598         /* Analog bypass */
 599         {"Analog Left Bypass", "Switch", "LINEL"},
 600         {"Analog Right Bypass", "Switch", "LINER"},
 601
 602         {"Output Left Amplifier", NULL, "DACL"},
 603         {"Output Right Amplifier", NULL, "DACR"},
 604
 605         {"Left Bypass PGA", NULL, "Analog Left Bypass"},
 606         {"Right Bypass PGA", NULL, "Analog Right Bypass"},
 607
 608         {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
 609         {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
 610         {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
 611         {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
 612
 613         {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
 614         {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
 615
 616         {"DACL", NULL, "Left DAC Power"},
 617         {"DACR", NULL, "Right DAC Power"},
 618
 619         {"Left Bypass PGA", NULL, "Left DAC Power"},
 620         {"Right Bypass PGA", NULL, "Right DAC Power"},
 621
 622         /* output */
 623         {"LEFT_LO", NULL, "Output Left Amplifier"},
 624         {"RIGHT_LO", NULL, "Output Right Amplifier"},
 625
 626         {"LEFT_LO", NULL, "Codec Power"},
 627         {"RIGHT_LO", NULL, "Codec Power"},
 628 };
 629
 630 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 631                                 enum snd_soc_bias_level level)
 632 {
 633         int ret;
 634
 635         switch (level) {
 636         case SND_SOC_BIAS_ON:
 637                 break;
 638         case SND_SOC_BIAS_PREPARE:
 639                 break;
 640         case SND_SOC_BIAS_STANDBY:
 641                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 642                         /* Coming from OFF, switch on the codec */
 643                         ret = dac33_hard_power(codec, 1);
 644                         if (ret != 0)
 645                                 return ret;
 646
 647                         dac33_init_chip(codec);
 648                 }
 649                 break;
 650         case SND_SOC_BIAS_OFF:
 651                 /* Do not power off, when the codec is already off */
 652                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 653                         return 0;
 654                 ret = dac33_hard_power(codec, 0);
 655                 if (ret != 0)
 656                         return ret;
 657                 break;
 658         }
 659         codec->dapm.bias_level = level;
 660
 661         return 0;
 662 }
 663
 664 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 665 {
 666         struct snd_soc_codec *codec = dac33->codec;
 667         unsigned int delay;
 668         unsigned long flags;
 669
 670         switch (dac33->fifo_mode) {
 671         case DAC33_FIFO_MODE1:
 672                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 673                         DAC33_THRREG(dac33->nsample));
 674
 675                 /* Take the timestamps */
 676                 spin_lock_irqsave(&dac33->lock, flags);
 677                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 678                 dac33->t_stamp1 = dac33->t_stamp2;
 679                 spin_unlock_irqrestore(&dac33->lock, flags);
 680
 681                 dac33_write16(codec, DAC33_PREFILL_MSB,
 682                                 DAC33_THRREG(dac33->alarm_threshold));
 683                 /* Enable Alarm Threshold IRQ with a delay */
 684                 delay = SAMPLES_TO_US(dac33->burst_rate,
 685                                      dac33->alarm_threshold) + 1000;
 686                 usleep_range(delay, delay + 500);
 687                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 688                 break;
 689         case DAC33_FIFO_MODE7:
 690                 /* Take the timestamp */
 691                 spin_lock_irqsave(&dac33->lock, flags);
 692                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 693                 /* Move back the timestamp with drain time */
 694                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 695                 spin_unlock_irqrestore(&dac33->lock, flags);
 696
 697                 dac33_write16(codec, DAC33_PREFILL_MSB,
 698                                 DAC33_THRREG(DAC33_MODE7_MARGIN));
 699
 700                 /* Enable Upper Threshold IRQ */
 701                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 702                 break;
 703         default:
 704                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 705                                                         dac33->fifo_mode);
 706                 break;
 707         }
 708 }
 709
 710 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 711 {
 712         struct snd_soc_codec *codec = dac33->codec;
 713         unsigned long flags;
 714
 715         switch (dac33->fifo_mode) {
 716         case DAC33_FIFO_MODE1:
 717                 /* Take the timestamp */
 718                 spin_lock_irqsave(&dac33->lock, flags);
 719                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 720                 spin_unlock_irqrestore(&dac33->lock, flags);
 721
 722                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 723                                 DAC33_THRREG(dac33->nsample));
 724                 break;
 725         case DAC33_FIFO_MODE7:
 726                 /* At the moment we are not using interrupts in mode7 */
 727                 break;
 728         default:
 729                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 730                                                         dac33->fifo_mode);
 731                 break;
 732         }
 733 }
 734
 735 static void dac33_work(struct work_struct *work)
 736 {
 737         struct snd_soc_codec *codec;
 738         struct tlv320dac33_priv *dac33;
 739         u8 reg;
 740
 741         dac33 = container_of(work, struct tlv320dac33_priv, work);
 742         codec = dac33->codec;
 743
 744         mutex_lock(&dac33->mutex);
 745         switch (dac33->state) {
 746         case DAC33_PREFILL:
 747                 dac33->state = DAC33_PLAYBACK;
 748                 dac33_prefill_handler(dac33);
 749                 break;
 750         case DAC33_PLAYBACK:
 751                 dac33_playback_handler(dac33);
 752                 break;
 753         case DAC33_IDLE:
 754                 break;
 755         case DAC33_FLUSH:
 756                 dac33->state = DAC33_IDLE;
 757                 /* Mask all interrupts from dac33 */
 758                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 759
 760                 /* flush fifo */
 761                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 762                 reg |= DAC33_FIFOFLUSH;
 763                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 764                 break;
 765         }
 766         mutex_unlock(&dac33->mutex);
 767 }
 768
 769 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 770 {
 771         struct snd_soc_codec *codec = dev;
 772         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 773         unsigned long flags;
 774
 775         spin_lock_irqsave(&dac33->lock, flags);
 776         dac33->t_stamp1 = ktime_to_us(ktime_get());
 777         spin_unlock_irqrestore(&dac33->lock, flags);
 778
 779         /* Do not schedule the workqueue in Mode7 */
 780         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 781                 queue_work(dac33->dac33_wq, &dac33->work);
 782
 783         return IRQ_HANDLED;
 784 }
 785
 786 static void dac33_oscwait(struct snd_soc_codec *codec)
 787 {
 788         int timeout = 60;
 789         u8 reg;
 790
 791         do {
 792                 usleep_range(1000, 2000);
 793                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 794         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 795         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 796                 dev_err(codec->dev,
 797                         "internal oscillator calibration failed\n");
 798 }
 799
 800 static int dac33_startup(struct snd_pcm_substream *substream,
 801                            struct snd_soc_dai *dai)
 802 {
 803         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 804         struct snd_soc_codec *codec = rtd->codec;
 805         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 806
 807         /* Stream started, save the substream pointer */
 808         dac33->substream = substream;
 809
 810         snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
 811
 812         return 0;
 813 }
 814
 815 static void dac33_shutdown(struct snd_pcm_substream *substream,
 816                              struct snd_soc_dai *dai)
 817 {
 818         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 819         struct snd_soc_codec *codec = rtd->codec;
 820         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 821
 822         dac33->substream = NULL;
 823 }
 824
 825 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
 826         (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
 827 static int dac33_hw_params(struct snd_pcm_substream *substream,
 828                            struct snd_pcm_hw_params *params,
 829                            struct snd_soc_dai *dai)
 830 {
 831         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 832         struct snd_soc_codec *codec = rtd->codec;
 833         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 834
 835         /* Check parameters for validity */
 836         switch (params_rate(params)) {
 837         case 44100:
 838         case 48000:
 839                 break;
 840         default:
 841                 dev_err(codec->dev, "unsupported rate %d\n",
 842                         params_rate(params));
 843                 return -EINVAL;
 844         }
 845
 846         switch (params_format(params)) {
 847         case SNDRV_PCM_FORMAT_S16_LE:
 848                 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
 849                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
 850                 break;
 851         case SNDRV_PCM_FORMAT_S32_LE:
 852                 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
 853                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
 854                 break;
 855         default:
 856                 dev_err(codec->dev, "unsupported format %d\n",
 857                         params_format(params));
 858                 return -EINVAL;
 859         }
 860
 861         return 0;
 862 }
 863
 864 #define CALC_OSCSET(rate, refclk) ( \
 865         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 866 #define CALC_RATIOSET(rate, refclk) ( \
 867         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 868
 869 /*
 870  * tlv320dac33 is strict on the sequence of the register writes, if the register
 871  * writes happens in different order, than dac33 might end up in unknown state.
 872  * Use the known, working sequence of register writes to initialize the dac33.
 873  */
 874 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 875 {
 876         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 877         struct snd_soc_codec *codec = rtd->codec;
 878         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 879         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 880         u8 aictrl_a, aictrl_b, fifoctrl_a;
 881
 882         switch (substream->runtime->rate) {
 883         case 44100:
 884         case 48000:
 885                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 886                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 887                                          dac33->refclk);
 888                 break;
 889         default:
 890                 dev_err(codec->dev, "unsupported rate %d\n",
 891                         substream->runtime->rate);
 892                 return -EINVAL;
 893         }
 894
 895
 896         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 897         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 898         /* Read FIFO control A, and clear FIFO flush bit */
 899         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 900         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 901
 902         fifoctrl_a &= ~DAC33_WIDTH;
 903         switch (substream->runtime->format) {
 904         case SNDRV_PCM_FORMAT_S16_LE:
 905                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 906                 fifoctrl_a |= DAC33_WIDTH;
 907                 break;
 908         case SNDRV_PCM_FORMAT_S32_LE:
 909                 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
 910                 break;
 911         default:
 912                 dev_err(codec->dev, "unsupported format %d\n",
 913                         substream->runtime->format);
 914                 return -EINVAL;
 915         }
 916
 917         mutex_lock(&dac33->mutex);
 918
 919         if (!dac33->chip_power) {
 920                 /*
 921                  * Chip is not powered yet.
 922                  * Do the init in the dac33_set_bias_level later.
 923                  */
 924                 mutex_unlock(&dac33->mutex);
 925                 return 0;
 926         }
 927
 928         dac33_soft_power(codec, 0);
 929         dac33_soft_power(codec, 1);
 930
 931         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 932         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 933
 934         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 935         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 936
 937         /* OSC calibration time */
 938         dac33_write(codec, DAC33_CALIB_TIME, 96);
 939
 940         /* adjustment treshold & step */
 941         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 942                                                  DAC33_ADJSTEP(1));
 943
 944         /* div=4 / gain=1 / div */
 945         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 946
 947         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 948         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 949         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 950
 951         dac33_oscwait(codec);
 952
 953         if (dac33->fifo_mode) {
 954                 /* Generic for all FIFO modes */
 955                 /* 50-51 : ASRC Control registers */
 956                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 957                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 958
 959                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 960                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 961
 962                 /* Set interrupts to high active */
 963                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 964         } else {
 965                 /* FIFO bypass mode */
 966                 /* 50-51 : ASRC Control registers */
 967                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 968                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 969         }
 970
 971         /* Interrupt behaviour configuration */
 972         switch (dac33->fifo_mode) {
 973         case DAC33_FIFO_MODE1:
 974                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 975                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 976                 break;
 977         case DAC33_FIFO_MODE7:
 978                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 979                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 980                 break;
 981         default:
 982                 /* in FIFO bypass mode, the interrupts are not used */
 983                 break;
 984         }
 985
 986         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 987
 988         switch (dac33->fifo_mode) {
 989         case DAC33_FIFO_MODE1:
 990                 /*
 991                  * For mode1:
 992                  * Disable the FIFO bypass (Enable the use of FIFO)
 993                  * Select nSample mode
 994                  * BCLK is only running when data is needed by DAC33
 995                  */
 996                 fifoctrl_a &= ~DAC33_FBYPAS;
 997                 fifoctrl_a &= ~DAC33_FAUTO;
 998                 if (dac33->keep_bclk)
 999                         aictrl_b |= DAC33_BCLKON;
1000                 else
1001                         aictrl_b &= ~DAC33_BCLKON;
1002                 break;
1003         case DAC33_FIFO_MODE7:
1004                 /*
1005                  * For mode1:
1006                  * Disable the FIFO bypass (Enable the use of FIFO)
1007                  * Select Threshold mode
1008                  * BCLK is only running when data is needed by DAC33
1009                  */
1010                 fifoctrl_a &= ~DAC33_FBYPAS;
1011                 fifoctrl_a |= DAC33_FAUTO;
1012                 if (dac33->keep_bclk)
1013                         aictrl_b |= DAC33_BCLKON;
1014                 else
1015                         aictrl_b &= ~DAC33_BCLKON;
1016                 break;
1017         default:
1018                 /*
1019                  * For FIFO bypass mode:
1020                  * Enable the FIFO bypass (Disable the FIFO use)
1021                  * Set the BCLK as continuous
1022                  */
1023                 fifoctrl_a |= DAC33_FBYPAS;
1024                 aictrl_b |= DAC33_BCLKON;
1025                 break;
1026         }
1027
1028         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1029         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1030         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1031
1032         /*
1033          * BCLK divide ratio
1034          * 0: 1.5
1035          * 1: 1
1036          * 2: 2
1037          * ...
1038          * 254: 254
1039          * 255: 255
1040          */
1041         if (dac33->fifo_mode)
1042                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1043                                                         dac33->burst_bclkdiv);
1044         else
1045                 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1046                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1047                 else
1048                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
1049
1050         switch (dac33->fifo_mode) {
1051         case DAC33_FIFO_MODE1:
1052                 dac33_write16(codec, DAC33_ATHR_MSB,
1053                               DAC33_THRREG(dac33->alarm_threshold));
1054                 break;
1055         case DAC33_FIFO_MODE7:
1056                 /*
1057                  * Configure the threshold levels, and leave 10 sample space
1058                  * at the bottom, and also at the top of the FIFO
1059                  */
1060                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1061                 dac33_write16(codec, DAC33_LTHR_MSB,
1062                               DAC33_THRREG(DAC33_MODE7_MARGIN));
1063                 break;
1064         default:
1065                 break;
1066         }
1067
1068         mutex_unlock(&dac33->mutex);
1069
1070         return 0;
1071 }
1072
1073 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1074 {
1075         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1076         struct snd_soc_codec *codec = rtd->codec;
1077         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1078         unsigned int period_size = substream->runtime->period_size;
1079         unsigned int rate = substream->runtime->rate;
1080         unsigned int nsample_limit;
1081
1082         /* In bypass mode we don't need to calculate */
1083         if (!dac33->fifo_mode)
1084                 return;
1085
1086         switch (dac33->fifo_mode) {
1087         case DAC33_FIFO_MODE1:
1088                 /* Number of samples under i2c latency */
1089                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1090                                                 dac33->mode1_latency);
1091                 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1092
1093                 if (period_size <= dac33->alarm_threshold)
1094                         /*
1095                          * Configure nSamaple to number of periods,
1096                          * which covers the latency requironment.
1097                          */
1098                         dac33->nsample = period_size *
1099                                 ((dac33->alarm_threshold / period_size) +
1100                                 (dac33->alarm_threshold % period_size ?
1101                                 1 : 0));
1102                 else if (period_size > nsample_limit)
1103                         dac33->nsample = nsample_limit;
1104                 else
1105                         dac33->nsample = period_size;
1106
1107                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1108                                                       dac33->nsample);
1109                 dac33->t_stamp1 = 0;
1110                 dac33->t_stamp2 = 0;
1111                 break;
1112         case DAC33_FIFO_MODE7:
1113                 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1114                                                     dac33->burst_rate) + 9;
1115                 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1116                         dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1117                 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1118                         dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1119
1120                 dac33->mode7_us_to_lthr =
1121                                 SAMPLES_TO_US(substream->runtime->rate,
1122                                         dac33->uthr - DAC33_MODE7_MARGIN + 1);
1123                 dac33->t_stamp1 = 0;
1124                 break;
1125         default:
1126                 break;
1127         }
1128
1129 }
1130
1131 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1132                              struct snd_soc_dai *dai)
1133 {
1134         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1135         struct snd_soc_codec *codec = rtd->codec;
1136         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1137         int ret = 0;
1138
1139         switch (cmd) {
1140         case SNDRV_PCM_TRIGGER_START:
1141         case SNDRV_PCM_TRIGGER_RESUME:
1142         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1143                 if (dac33->fifo_mode) {
1144                         dac33->state = DAC33_PREFILL;
1145                         queue_work(dac33->dac33_wq, &dac33->work);
1146                 }
1147                 break;
1148         case SNDRV_PCM_TRIGGER_STOP:
1149         case SNDRV_PCM_TRIGGER_SUSPEND:
1150         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1151                 if (dac33->fifo_mode) {
1152                         dac33->state = DAC33_FLUSH;
1153                         queue_work(dac33->dac33_wq, &dac33->work);
1154                 }
1155                 break;
1156         default:
1157                 ret = -EINVAL;
1158         }
1159
1160         return ret;
1161 }
1162
1163 static snd_pcm_sframes_t dac33_dai_delay(
1164                         struct snd_pcm_substream *substream,
1165                         struct snd_soc_dai *dai)
1166 {
1167         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1168         struct snd_soc_codec *codec = rtd->codec;
1169         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1170         unsigned long long t0, t1, t_now;
1171         unsigned int time_delta, uthr;
1172         int samples_out, samples_in, samples;
1173         snd_pcm_sframes_t delay = 0;
1174         unsigned long flags;
1175
1176         switch (dac33->fifo_mode) {
1177         case DAC33_FIFO_BYPASS:
1178                 break;
1179         case DAC33_FIFO_MODE1:
1180                 spin_lock_irqsave(&dac33->lock, flags);
1181                 t0 = dac33->t_stamp1;
1182                 t1 = dac33->t_stamp2;
1183                 spin_unlock_irqrestore(&dac33->lock, flags);
1184                 t_now = ktime_to_us(ktime_get());
1185
1186                 /* We have not started to fill the FIFO yet, delay is 0 */
1187                 if (!t1)
1188                         goto out;
1189
1190                 if (t0 > t1) {
1191                         /*
1192                          * Phase 1:
1193                          * After Alarm threshold, and before nSample write
1194                          */
1195                         time_delta = t_now - t0;
1196                         samples_out = time_delta ? US_TO_SAMPLES(
1197                                                 substream->runtime->rate,
1198                                                 time_delta) : 0;
1199
1200                         if (likely(dac33->alarm_threshold > samples_out))
1201                                 delay = dac33->alarm_threshold - samples_out;
1202                         else
1203                                 delay = 0;
1204                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1205                         /*
1206                          * Phase 2:
1207                          * After nSample write (during burst operation)
1208                          */
1209                         time_delta = t_now - t0;
1210                         samples_out = time_delta ? US_TO_SAMPLES(
1211                                                 substream->runtime->rate,
1212                                                 time_delta) : 0;
1213
1214                         time_delta = t_now - t1;
1215                         samples_in = time_delta ? US_TO_SAMPLES(
1216                                                 dac33->burst_rate,
1217                                                 time_delta) : 0;
1218
1219                         samples = dac33->alarm_threshold;
1220                         samples += (samples_in - samples_out);
1221
1222                         if (likely(samples > 0))
1223                                 delay = samples;
1224                         else
1225                                 delay = 0;
1226                 } else {
1227                         /*
1228                          * Phase 3:
1229                          * After burst operation, before next alarm threshold
1230                          */
1231                         time_delta = t_now - t0;
1232                         samples_out = time_delta ? US_TO_SAMPLES(
1233                                                 substream->runtime->rate,
1234                                                 time_delta) : 0;
1235
1236                         samples_in = dac33->nsample;
1237                         samples = dac33->alarm_threshold;
1238                         samples += (samples_in - samples_out);
1239
1240                         if (likely(samples > 0))
1241                                 delay = samples > dac33->fifo_size ?
1242                                         dac33->fifo_size : samples;
1243                         else
1244                                 delay = 0;
1245                 }
1246                 break;
1247         case DAC33_FIFO_MODE7:
1248                 spin_lock_irqsave(&dac33->lock, flags);
1249                 t0 = dac33->t_stamp1;
1250                 uthr = dac33->uthr;
1251                 spin_unlock_irqrestore(&dac33->lock, flags);
1252                 t_now = ktime_to_us(ktime_get());
1253
1254                 /* We have not started to fill the FIFO yet, delay is 0 */
1255                 if (!t0)
1256                         goto out;
1257
1258                 if (t_now <= t0) {
1259                         /*
1260                          * Either the timestamps are messed or equal. Report
1261                          * maximum delay
1262                          */
1263                         delay = uthr;
1264                         goto out;
1265                 }
1266
1267                 time_delta = t_now - t0;
1268                 if (time_delta <= dac33->mode7_us_to_lthr) {
1269                         /*
1270                         * Phase 1:
1271                         * After burst (draining phase)
1272                         */
1273                         samples_out = US_TO_SAMPLES(
1274                                         substream->runtime->rate,
1275                                         time_delta);
1276
1277                         if (likely(uthr > samples_out))
1278                                 delay = uthr - samples_out;
1279                         else
1280                                 delay = 0;
1281                 } else {
1282                         /*
1283                         * Phase 2:
1284                         * During burst operation
1285                         */
1286                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1287
1288                         samples_out = US_TO_SAMPLES(
1289                                         substream->runtime->rate,
1290                                         time_delta);
1291                         samples_in = US_TO_SAMPLES(
1292                                         dac33->burst_rate,
1293                                         time_delta);
1294                         delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1295
1296                         if (unlikely(delay > uthr))
1297                                 delay = uthr;
1298                 }
1299                 break;
1300         default:
1301                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1302                                                         dac33->fifo_mode);
1303                 break;
1304         }
1305 out:
1306         return delay;
1307 }
1308
1309 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1310                 int clk_id, unsigned int freq, int dir)
1311 {
1312         struct snd_soc_codec *codec = codec_dai->codec;
1313         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1314         u8 ioc_reg, asrcb_reg;
1315
1316         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1317         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1318         switch (clk_id) {
1319         case TLV320DAC33_MCLK:
1320                 ioc_reg |= DAC33_REFSEL;
1321                 asrcb_reg |= DAC33_SRCREFSEL;
1322                 break;
1323         case TLV320DAC33_SLEEPCLK:
1324                 ioc_reg &= ~DAC33_REFSEL;
1325                 asrcb_reg &= ~DAC33_SRCREFSEL;
1326                 break;
1327         default:
1328                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1329                 break;
1330         }
1331         dac33->refclk = freq;
1332
1333         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1334         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1335
1336         return 0;
1337 }
1338
1339 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1340                              unsigned int fmt)
1341 {
1342         struct snd_soc_codec *codec = codec_dai->codec;
1343         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1344         u8 aictrl_a, aictrl_b;
1345
1346         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1347         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1348         /* set master/slave audio interface */
1349         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1350         case SND_SOC_DAIFMT_CBM_CFM:
1351                 /* Codec Master */
1352                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1353                 break;
1354         case SND_SOC_DAIFMT_CBS_CFS:
1355                 /* Codec Slave */
1356                 if (dac33->fifo_mode) {
1357                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1358                         return -EINVAL;
1359                 } else
1360                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1361                 break;
1362         default:
1363                 return -EINVAL;
1364         }
1365
1366         aictrl_a &= ~DAC33_AFMT_MASK;
1367         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1368         case SND_SOC_DAIFMT_I2S:
1369                 aictrl_a |= DAC33_AFMT_I2S;
1370                 break;
1371         case SND_SOC_DAIFMT_DSP_A:
1372                 aictrl_a |= DAC33_AFMT_DSP;
1373                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1374                 aictrl_b |= DAC33_DATA_DELAY(0);
1375                 break;
1376         case SND_SOC_DAIFMT_RIGHT_J:
1377                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1378                 break;
1379         case SND_SOC_DAIFMT_LEFT_J:
1380                 aictrl_a |= DAC33_AFMT_LEFT_J;
1381                 break;
1382         default:
1383                 dev_err(codec->dev, "Unsupported format (%u)\n",
1384                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1385                 return -EINVAL;
1386         }
1387
1388         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1389         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1390
1391         return 0;
1392 }
1393
1394 static int dac33_soc_probe(struct snd_soc_codec *codec)
1395 {
1396         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1397         int ret = 0;
1398
1399         codec->control_data = dac33->control_data;
1400         codec->hw_write = (hw_write_t) i2c_master_send;
1401         codec->dapm.idle_bias_off = 1;
1402         dac33->codec = codec;
1403
1404         /* Read the tlv320dac33 ID registers */
1405         ret = dac33_hard_power(codec, 1);
1406         if (ret != 0) {
1407                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1408                 goto err_power;
1409         }
1410         ret = dac33_read_id(codec);
1411         dac33_hard_power(codec, 0);
1412
1413         if (ret < 0) {
1414                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1415                 ret = -ENODEV;
1416                 goto err_power;
1417         }
1418
1419         /* Check if the IRQ number is valid and request it */
1420         if (dac33->irq >= 0) {
1421                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1422                                   IRQF_TRIGGER_RISING,
1423                                   codec->name, codec);
1424                 if (ret < 0) {
1425                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1426                                                 dac33->irq, ret);
1427                         dac33->irq = -1;
1428                 }
1429                 if (dac33->irq != -1) {
1430                         /* Setup work queue */
1431                         dac33->dac33_wq =
1432                                 create_singlethread_workqueue("tlv320dac33");
1433                         if (dac33->dac33_wq == NULL) {
1434                                 free_irq(dac33->irq, codec);
1435                                 return -ENOMEM;
1436                         }
1437
1438                         INIT_WORK(&dac33->work, dac33_work);
1439                 }
1440         }
1441
1442         /* Only add the FIFO controls, if we have valid IRQ number */
1443         if (dac33->irq >= 0)
1444                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1445                                      ARRAY_SIZE(dac33_mode_snd_controls));
1446
1447 err_power:
1448         return ret;
1449 }
1450
1451 static int dac33_soc_remove(struct snd_soc_codec *codec)
1452 {
1453         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1454
1455         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1456
1457         if (dac33->irq >= 0) {
1458                 free_irq(dac33->irq, dac33->codec);
1459                 destroy_workqueue(dac33->dac33_wq);
1460         }
1461         return 0;
1462 }
1463
1464 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1465 {
1466         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1467
1468         return 0;
1469 }
1470
1471 static int dac33_soc_resume(struct snd_soc_codec *codec)
1472 {
1473         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1474
1475         return 0;
1476 }
1477
1478 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1479         .read = dac33_read_reg_cache,
1480         .write = dac33_write_locked,
1481         .set_bias_level = dac33_set_bias_level,
1482         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1483         .reg_word_size = sizeof(u8),
1484         .reg_cache_default = dac33_reg,
1485         .probe = dac33_soc_probe,
1486         .remove = dac33_soc_remove,
1487         .suspend = dac33_soc_suspend,
1488         .resume = dac33_soc_resume,
1489
1490         .controls = dac33_snd_controls,
1491         .num_controls = ARRAY_SIZE(dac33_snd_controls),
1492         .dapm_widgets = dac33_dapm_widgets,
1493         .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets),
1494         .dapm_routes = audio_map,
1495         .num_dapm_routes = ARRAY_SIZE(audio_map),
1496 };
1497
1498 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1499                          SNDRV_PCM_RATE_48000)
1500 #define DAC33_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1501
1502 static struct snd_soc_dai_ops dac33_dai_ops = {
1503         .startup        = dac33_startup,
1504         .shutdown       = dac33_shutdown,
1505         .hw_params      = dac33_hw_params,
1506         .trigger        = dac33_pcm_trigger,
1507         .delay          = dac33_dai_delay,
1508         .set_sysclk     = dac33_set_dai_sysclk,
1509         .set_fmt        = dac33_set_dai_fmt,
1510 };
1511
1512 static struct snd_soc_dai_driver dac33_dai = {
1513         .name = "tlv320dac33-hifi",
1514         .playback = {
1515                 .stream_name = "Playback",
1516                 .channels_min = 2,
1517                 .channels_max = 2,
1518                 .rates = DAC33_RATES,
1519                 .formats = DAC33_FORMATS,},
1520         .ops = &dac33_dai_ops,
1521 };
1522
1523 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1524                                      const struct i2c_device_id *id)
1525 {
1526         struct tlv320dac33_platform_data *pdata;
1527         struct tlv320dac33_priv *dac33;
1528         int ret, i;
1529
1530         if (client->dev.platform_data == NULL) {
1531                 dev_err(&client->dev, "Platform data not set\n");
1532                 return -ENODEV;
1533         }
1534         pdata = client->dev.platform_data;
1535
1536         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1537         if (dac33 == NULL)
1538                 return -ENOMEM;
1539
1540         dac33->control_data = client;
1541         mutex_init(&dac33->mutex);
1542         spin_lock_init(&dac33->lock);
1543
1544         i2c_set_clientdata(client, dac33);
1545
1546         dac33->power_gpio = pdata->power_gpio;
1547         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1548         dac33->keep_bclk = pdata->keep_bclk;
1549         dac33->mode1_latency = pdata->mode1_latency;
1550         if (!dac33->mode1_latency)
1551                 dac33->mode1_latency = 10000; /* 10ms */
1552         dac33->irq = client->irq;
1553         /* Disable FIFO use by default */
1554         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1555
1556         /* Check if the reset GPIO number is valid and request it */
1557         if (dac33->power_gpio >= 0) {
1558                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1559                 if (ret < 0) {
1560                         dev_err(&client->dev,
1561                                 "Failed to request reset GPIO (%d)\n",
1562                                 dac33->power_gpio);
1563                         goto err_gpio;
1564                 }
1565                 gpio_direction_output(dac33->power_gpio, 0);
1566         }
1567
1568         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1569                 dac33->supplies[i].supply = dac33_supply_names[i];
1570
1571         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1572                                  dac33->supplies);
1573
1574         if (ret != 0) {
1575                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1576                 goto err_get;
1577         }
1578
1579         ret = snd_soc_register_codec(&client->dev,
1580                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1581         if (ret < 0)
1582                 goto err_register;
1583
1584         return ret;
1585 err_register:
1586         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1587 err_get:
1588         if (dac33->power_gpio >= 0)
1589                 gpio_free(dac33->power_gpio);
1590 err_gpio:
1591         kfree(dac33);
1592         return ret;
1593 }
1594
1595 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1596 {
1597         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1598
1599         if (unlikely(dac33->chip_power))
1600                 dac33_hard_power(dac33->codec, 0);
1601
1602         if (dac33->power_gpio >= 0)
1603                 gpio_free(dac33->power_gpio);
1604
1605         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1606
1607         snd_soc_unregister_codec(&client->dev);
1608         kfree(dac33);
1609
1610         return 0;
1611 }
1612
1613 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1614         {
1615                 .name = "tlv320dac33",
1616                 .driver_data = 0,
1617         },
1618         { },
1619 };
1620 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
1621
1622 static struct i2c_driver tlv320dac33_i2c_driver = {
1623         .driver = {
1624                 .name = "tlv320dac33-codec",
1625                 .owner = THIS_MODULE,
1626         },
1627         .probe          = dac33_i2c_probe,
1628         .remove         = __devexit_p(dac33_i2c_remove),
1629         .id_table       = tlv320dac33_i2c_id,
1630 };
1631
1632 static int __init dac33_module_init(void)
1633 {
1634         int r;
1635         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1636         if (r < 0) {
1637                 printk(KERN_ERR "DAC33: driver registration failed\n");
1638                 return r;
1639         }
1640         return 0;
1641 }
1642 module_init(dac33_module_init);
1643
1644 static void __exit dac33_module_exit(void)
1645 {
1646         i2c_del_driver(&tlv320dac33_i2c_driver);
1647 }
1648 module_exit(dac33_module_exit);
1649
1650
1651 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1652 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1653 MODULE_LICENSE("GPL");