sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/initval.h>
  40 #include <sound/tlv.h>
  41
  42 #include <sound/tlv320dac33-plat.h>
  43 #include "tlv320dac33.h"
  44
  45 /*
  46  * The internal FIFO is 24576 bytes long
  47  * It can be configured to hold 16bit or 24bit samples
  48  * In 16bit configuration the FIFO can hold 6144 stereo samples
  49  * In 24bit configuration the FIFO can hold 4096 stereo samples
  50  */
  51 #define DAC33_FIFO_SIZE_16BIT   6144
  52 #define DAC33_FIFO_SIZE_24BIT   4096
  53 #define DAC33_MODE7_MARGIN      10      /* Safety margin for FIFO in Mode7 */
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / (us < 1000000 ? us : 1000000)))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 104         unsigned int fifo_size;         /* Size of the FIFO in samples */
 105         unsigned int nsample;           /* burst read amount from host */
 106         int mode1_latency;              /* latency caused by the i2c writes in
 107                                          * us */
 108         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 109         unsigned int burst_rate;        /* Interface speed in Burst modes */
 110
 111         int keep_bclk;                  /* Keep the BCLK continuously running
 112                                          * in FIFO modes */
 113         spinlock_t lock;
 114         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 115         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 116
 117         unsigned int mode1_us_burst;    /* Time to burst read n number of
 118                                          * samples */
 119         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 120
 121         unsigned int uthr;
 122
 123         enum dac33_state state;
 124         enum snd_soc_control_type control_type;
 125         void *control_data;
 126 };
 127
 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 143 0x00, 0x00,             /* 0x38 - 0x39 */
 144 /* Registers 0x3a - 0x3f are reserved  */
 145             0x00, 0x00, /* 0x3a - 0x3b */
 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 147
 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 149 0x00, 0x80,             /* 0x44 - 0x45 */
 150 /* Registers 0x46 - 0x47 are reserved  */
 151             0x80, 0x80, /* 0x46 - 0x47 */
 152
 153 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 154 /* Registers 0x4b - 0x7c are reserved  */
 155                   0x00, /* 0x4b        */
 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 168 0x00,                   /* 0x7c        */
 169
 170       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 171 };
 172
 173 /* Register read and write */
 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 175                                                 unsigned reg)
 176 {
 177         u8 *cache = codec->reg_cache;
 178         if (reg >= DAC33_CACHEREGNUM)
 179                 return 0;
 180
 181         return cache[reg];
 182 }
 183
 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 185                                          u8 reg, u8 value)
 186 {
 187         u8 *cache = codec->reg_cache;
 188         if (reg >= DAC33_CACHEREGNUM)
 189                 return;
 190
 191         cache[reg] = value;
 192 }
 193
 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 195                       u8 *value)
 196 {
 197         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 198         int val, ret = 0;
 199
 200         *value = reg & 0xff;
 201
 202         /* If powered off, return the cached value */
 203         if (dac33->chip_power) {
 204                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 205                 if (val < 0) {
 206                         dev_err(codec->dev, "Read failed (%d)\n", val);
 207                         value[0] = dac33_read_reg_cache(codec, reg);
 208                         ret = val;
 209                 } else {
 210                         value[0] = val;
 211                         dac33_write_reg_cache(codec, reg, val);
 212                 }
 213         } else {
 214                 value[0] = dac33_read_reg_cache(codec, reg);
 215         }
 216
 217         return ret;
 218 }
 219
 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 221                        unsigned int value)
 222 {
 223         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 224         u8 data[2];
 225         int ret = 0;
 226
 227         /*
 228          * data is
 229          *   D15..D8 dac33 register offset
 230          *   D7...D0 register data
 231          */
 232         data[0] = reg & 0xff;
 233         data[1] = value & 0xff;
 234
 235         dac33_write_reg_cache(codec, data[0], data[1]);
 236         if (dac33->chip_power) {
 237                 ret = codec->hw_write(codec->control_data, data, 2);
 238                 if (ret != 2)
 239                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 240                 else
 241                         ret = 0;
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 248                        unsigned int value)
 249 {
 250         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 251         int ret;
 252
 253         mutex_lock(&dac33->mutex);
 254         ret = dac33_write(codec, reg, value);
 255         mutex_unlock(&dac33->mutex);
 256
 257         return ret;
 258 }
 259
 260 #define DAC33_I2C_ADDR_AUTOINC  0x80
 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 262                        unsigned int value)
 263 {
 264         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 265         u8 data[3];
 266         int ret = 0;
 267
 268         /*
 269          * data is
 270          *   D23..D16 dac33 register offset
 271          *   D15..D8  register data MSB
 272          *   D7...D0  register data LSB
 273          */
 274         data[0] = reg & 0xff;
 275         data[1] = (value >> 8) & 0xff;
 276         data[2] = value & 0xff;
 277
 278         dac33_write_reg_cache(codec, data[0], data[1]);
 279         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 280
 281         if (dac33->chip_power) {
 282                 /* We need to set autoincrement mode for 16 bit writes */
 283                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 284                 ret = codec->hw_write(codec->control_data, data, 3);
 285                 if (ret != 3)
 286                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 287                 else
 288                         ret = 0;
 289         }
 290
 291         return ret;
 292 }
 293
 294 static void dac33_init_chip(struct snd_soc_codec *codec)
 295 {
 296         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 297
 298         if (unlikely(!dac33->chip_power))
 299                 return;
 300
 301         /* A : DAC sample rate Fsref/1.5 */
 302         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 303         /* B : DAC src=normal, not muted */
 304         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 305                                              DAC33_DACSRCL_LEFT);
 306         /* C : (defaults) */
 307         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 308
 309         /* 73 : volume soft stepping control,
 310          clock source = internal osc (?) */
 311         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 312
 313         /* Restore only selected registers (gains mostly) */
 314         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 315                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 316         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 317                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 318
 319         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 320                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 321         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 322                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 323
 324         dac33_write(codec, DAC33_OUT_AMP_CTRL,
 325                     dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
 326
 327 }
 328
 329 static inline int dac33_read_id(struct snd_soc_codec *codec)
 330 {
 331         int i, ret = 0;
 332         u8 reg;
 333
 334         for (i = 0; i < 3; i++) {
 335                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 336                 if (ret < 0)
 337                         break;
 338         }
 339
 340         return ret;
 341 }
 342
 343 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 344 {
 345         u8 reg;
 346
 347         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 348         if (power)
 349                 reg |= DAC33_PDNALLB;
 350         else
 351                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 352                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 353         dac33_write(codec, DAC33_PWR_CTRL, reg);
 354 }
 355
 356 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
 357 {
 358         u8 reg;
 359
 360         /* Stop the DAI clock */
 361         reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 362         reg &= ~DAC33_BCLKON;
 363         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
 364
 365         /* Power down the Oscillator, and DACs */
 366         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 367         reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
 368         dac33_write(codec, DAC33_PWR_CTRL, reg);
 369 }
 370
 371 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 372 {
 373         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 374         int ret = 0;
 375
 376         mutex_lock(&dac33->mutex);
 377
 378         /* Safety check */
 379         if (unlikely(power == dac33->chip_power)) {
 380                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 381                         power ? "ON" : "OFF");
 382                 goto exit;
 383         }
 384
 385         if (power) {
 386                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 387                                           dac33->supplies);
 388                 if (ret != 0) {
 389                         dev_err(codec->dev,
 390                                 "Failed to enable supplies: %d\n", ret);
 391                                 goto exit;
 392                 }
 393
 394                 if (dac33->power_gpio >= 0)
 395                         gpio_set_value(dac33->power_gpio, 1);
 396
 397                 dac33->chip_power = 1;
 398         } else {
 399                 dac33_soft_power(codec, 0);
 400                 if (dac33->power_gpio >= 0)
 401                         gpio_set_value(dac33->power_gpio, 0);
 402
 403                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 404                                              dac33->supplies);
 405                 if (ret != 0) {
 406                         dev_err(codec->dev,
 407                                 "Failed to disable supplies: %d\n", ret);
 408                         goto exit;
 409                 }
 410
 411                 dac33->chip_power = 0;
 412         }
 413
 414 exit:
 415         mutex_unlock(&dac33->mutex);
 416         return ret;
 417 }
 418
 419 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
 420                 struct snd_kcontrol *kcontrol, int event)
 421 {
 422         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 423
 424         switch (event) {
 425         case SND_SOC_DAPM_PRE_PMU:
 426                 if (likely(dac33->substream)) {
 427                         dac33_calculate_times(dac33->substream);
 428                         dac33_prepare_chip(dac33->substream);
 429                 }
 430                 break;
 431         case SND_SOC_DAPM_POST_PMD:
 432                 dac33_disable_digital(w->codec);
 433                 break;
 434         }
 435         return 0;
 436 }
 437
 438 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 439                          struct snd_ctl_elem_value *ucontrol)
 440 {
 441         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 442         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 443
 444         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 445
 446         return 0;
 447 }
 448
 449 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 450                          struct snd_ctl_elem_value *ucontrol)
 451 {
 452         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 453         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 454         int ret = 0;
 455
 456         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 457                 return 0;
 458         /* Do not allow changes while stream is running*/
 459         if (codec->active)
 460                 return -EPERM;
 461
 462         if (ucontrol->value.integer.value[0] < 0 ||
 463             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 464                 ret = -EINVAL;
 465         else
 466                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 467
 468         return ret;
 469 }
 470
 471 /* Codec operation modes */
 472 static const char *dac33_fifo_mode_texts[] = {
 473         "Bypass", "Mode 1", "Mode 7"
 474 };
 475
 476 static const struct soc_enum dac33_fifo_mode_enum =
 477         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 478                             dac33_fifo_mode_texts);
 479
 480 /* L/R Line Output Gain */
 481 static const char *lr_lineout_gain_texts[] = {
 482         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 483         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 484 };
 485
 486 static const struct soc_enum l_lineout_gain_enum =
 487         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 488                         ARRAY_SIZE(lr_lineout_gain_texts),
 489                         lr_lineout_gain_texts);
 490
 491 static const struct soc_enum r_lineout_gain_enum =
 492         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 493                         ARRAY_SIZE(lr_lineout_gain_texts),
 494                         lr_lineout_gain_texts);
 495
 496 /*
 497  * DACL/R digital volume control:
 498  * from 0 dB to -63.5 in 0.5 dB steps
 499  * Need to be inverted later on:
 500  * 0x00 == 0 dB
 501  * 0x7f == -63.5 dB
 502  */
 503 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 504
 505 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 506         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 507                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 508                 0, 0x7f, 1, dac_digivol_tlv),
 509         SOC_DOUBLE_R("DAC Digital Playback Switch",
 510                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 511         SOC_DOUBLE_R("Line to Line Out Volume",
 512                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 513         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 514         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 515 };
 516
 517 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 518         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 519                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 520 };
 521
 522 /* Analog bypass */
 523 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 524         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 525
 526 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 527         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 528
 529 /* LOP L/R invert selection */
 530 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
 531
 532 static const struct soc_enum dac33_left_lom_enum =
 533         SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
 534                         ARRAY_SIZE(dac33_lr_lom_texts),
 535                         dac33_lr_lom_texts);
 536
 537 static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
 538 SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
 539
 540 static const struct soc_enum dac33_right_lom_enum =
 541         SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
 542                         ARRAY_SIZE(dac33_lr_lom_texts),
 543                         dac33_lr_lom_texts);
 544
 545 static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
 546 SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
 547
 548 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 549         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 550         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 551
 552         SND_SOC_DAPM_INPUT("LINEL"),
 553         SND_SOC_DAPM_INPUT("LINER"),
 554
 555         SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
 556         SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 557
 558         /* Analog bypass */
 559         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 560                                 &dac33_dapm_abypassl_control),
 561         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 562                                 &dac33_dapm_abypassr_control),
 563
 564         SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
 565                 &dac33_dapm_left_lom_control),
 566         SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
 567                 &dac33_dapm_right_lom_control),
 568         /*
 569          * For DAPM path, when only the anlog bypass path is enabled, and the
 570          * LOP inverted from the corresponding DAC side.
 571          * This is needed, so we can attach the DAC power supply in this case.
 572          */
 573         SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 574         SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 575
 576         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
 577                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 578         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
 579                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 580
 581         SND_SOC_DAPM_SUPPLY("Left DAC Power",
 582                             DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
 583         SND_SOC_DAPM_SUPPLY("Right DAC Power",
 584                             DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
 585
 586         SND_SOC_DAPM_SUPPLY("Codec Power",
 587                             DAC33_PWR_CTRL, 4, 0, NULL, 0),
 588
 589         SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
 590         SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 591 };
 592
 593 static const struct snd_soc_dapm_route audio_map[] = {
 594         /* Analog bypass */
 595         {"Analog Left Bypass", "Switch", "LINEL"},
 596         {"Analog Right Bypass", "Switch", "LINER"},
 597
 598         {"Output Left Amplifier", NULL, "DACL"},
 599         {"Output Right Amplifier", NULL, "DACR"},
 600
 601         {"Left Bypass PGA", NULL, "Analog Left Bypass"},
 602         {"Right Bypass PGA", NULL, "Analog Right Bypass"},
 603
 604         {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
 605         {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
 606         {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
 607         {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
 608
 609         {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
 610         {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
 611
 612         {"DACL", NULL, "Left DAC Power"},
 613         {"DACR", NULL, "Right DAC Power"},
 614
 615         {"Left Bypass PGA", NULL, "Left DAC Power"},
 616         {"Right Bypass PGA", NULL, "Right DAC Power"},
 617
 618         /* output */
 619         {"LEFT_LO", NULL, "Output Left Amplifier"},
 620         {"RIGHT_LO", NULL, "Output Right Amplifier"},
 621
 622         {"LEFT_LO", NULL, "Codec Power"},
 623         {"RIGHT_LO", NULL, "Codec Power"},
 624 };
 625
 626 static int dac33_add_widgets(struct snd_soc_codec *codec)
 627 {
 628         struct snd_soc_dapm_context *dapm = &codec->dapm;
 629
 630         snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
 631                                   ARRAY_SIZE(dac33_dapm_widgets));
 632         /* set up audio path interconnects */
 633         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 634
 635         return 0;
 636 }
 637
 638 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 639                                 enum snd_soc_bias_level level)
 640 {
 641         int ret;
 642
 643         switch (level) {
 644         case SND_SOC_BIAS_ON:
 645                 break;
 646         case SND_SOC_BIAS_PREPARE:
 647                 break;
 648         case SND_SOC_BIAS_STANDBY:
 649                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 650                         /* Coming from OFF, switch on the codec */
 651                         ret = dac33_hard_power(codec, 1);
 652                         if (ret != 0)
 653                                 return ret;
 654
 655                         dac33_init_chip(codec);
 656                 }
 657                 break;
 658         case SND_SOC_BIAS_OFF:
 659                 /* Do not power off, when the codec is already off */
 660                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 661                         return 0;
 662                 ret = dac33_hard_power(codec, 0);
 663                 if (ret != 0)
 664                         return ret;
 665                 break;
 666         }
 667         codec->dapm.bias_level = level;
 668
 669         return 0;
 670 }
 671
 672 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 673 {
 674         struct snd_soc_codec *codec = dac33->codec;
 675         unsigned int delay;
 676
 677         switch (dac33->fifo_mode) {
 678         case DAC33_FIFO_MODE1:
 679                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 680                         DAC33_THRREG(dac33->nsample));
 681
 682                 /* Take the timestamps */
 683                 spin_lock_irq(&dac33->lock);
 684                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 685                 dac33->t_stamp1 = dac33->t_stamp2;
 686                 spin_unlock_irq(&dac33->lock);
 687
 688                 dac33_write16(codec, DAC33_PREFILL_MSB,
 689                                 DAC33_THRREG(dac33->alarm_threshold));
 690                 /* Enable Alarm Threshold IRQ with a delay */
 691                 delay = SAMPLES_TO_US(dac33->burst_rate,
 692                                      dac33->alarm_threshold) + 1000;
 693                 usleep_range(delay, delay + 500);
 694                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 695                 break;
 696         case DAC33_FIFO_MODE7:
 697                 /* Take the timestamp */
 698                 spin_lock_irq(&dac33->lock);
 699                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 700                 /* Move back the timestamp with drain time */
 701                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 702                 spin_unlock_irq(&dac33->lock);
 703
 704                 dac33_write16(codec, DAC33_PREFILL_MSB,
 705                                 DAC33_THRREG(DAC33_MODE7_MARGIN));
 706
 707                 /* Enable Upper Threshold IRQ */
 708                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 709                 break;
 710         default:
 711                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 712                                                         dac33->fifo_mode);
 713                 break;
 714         }
 715 }
 716
 717 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 718 {
 719         struct snd_soc_codec *codec = dac33->codec;
 720
 721         switch (dac33->fifo_mode) {
 722         case DAC33_FIFO_MODE1:
 723                 /* Take the timestamp */
 724                 spin_lock_irq(&dac33->lock);
 725                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 726                 spin_unlock_irq(&dac33->lock);
 727
 728                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 729                                 DAC33_THRREG(dac33->nsample));
 730                 break;
 731         case DAC33_FIFO_MODE7:
 732                 /* At the moment we are not using interrupts in mode7 */
 733                 break;
 734         default:
 735                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 736                                                         dac33->fifo_mode);
 737                 break;
 738         }
 739 }
 740
 741 static void dac33_work(struct work_struct *work)
 742 {
 743         struct snd_soc_codec *codec;
 744         struct tlv320dac33_priv *dac33;
 745         u8 reg;
 746
 747         dac33 = container_of(work, struct tlv320dac33_priv, work);
 748         codec = dac33->codec;
 749
 750         mutex_lock(&dac33->mutex);
 751         switch (dac33->state) {
 752         case DAC33_PREFILL:
 753                 dac33->state = DAC33_PLAYBACK;
 754                 dac33_prefill_handler(dac33);
 755                 break;
 756         case DAC33_PLAYBACK:
 757                 dac33_playback_handler(dac33);
 758                 break;
 759         case DAC33_IDLE:
 760                 break;
 761         case DAC33_FLUSH:
 762                 dac33->state = DAC33_IDLE;
 763                 /* Mask all interrupts from dac33 */
 764                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 765
 766                 /* flush fifo */
 767                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 768                 reg |= DAC33_FIFOFLUSH;
 769                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 770                 break;
 771         }
 772         mutex_unlock(&dac33->mutex);
 773 }
 774
 775 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 776 {
 777         struct snd_soc_codec *codec = dev;
 778         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 779
 780         spin_lock(&dac33->lock);
 781         dac33->t_stamp1 = ktime_to_us(ktime_get());
 782         spin_unlock(&dac33->lock);
 783
 784         /* Do not schedule the workqueue in Mode7 */
 785         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 786                 queue_work(dac33->dac33_wq, &dac33->work);
 787
 788         return IRQ_HANDLED;
 789 }
 790
 791 static void dac33_oscwait(struct snd_soc_codec *codec)
 792 {
 793         int timeout = 60;
 794         u8 reg;
 795
 796         do {
 797                 usleep_range(1000, 2000);
 798                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 799         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 800         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 801                 dev_err(codec->dev,
 802                         "internal oscillator calibration failed\n");
 803 }
 804
 805 static int dac33_startup(struct snd_pcm_substream *substream,
 806                            struct snd_soc_dai *dai)
 807 {
 808         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 809         struct snd_soc_codec *codec = rtd->codec;
 810         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 811
 812         /* Stream started, save the substream pointer */
 813         dac33->substream = substream;
 814
 815         snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
 816
 817         return 0;
 818 }
 819
 820 static void dac33_shutdown(struct snd_pcm_substream *substream,
 821                              struct snd_soc_dai *dai)
 822 {
 823         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 824         struct snd_soc_codec *codec = rtd->codec;
 825         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 826
 827         dac33->substream = NULL;
 828 }
 829
 830 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
 831         (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
 832 static int dac33_hw_params(struct snd_pcm_substream *substream,
 833                            struct snd_pcm_hw_params *params,
 834                            struct snd_soc_dai *dai)
 835 {
 836         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 837         struct snd_soc_codec *codec = rtd->codec;
 838         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 839
 840         /* Check parameters for validity */
 841         switch (params_rate(params)) {
 842         case 44100:
 843         case 48000:
 844                 break;
 845         default:
 846                 dev_err(codec->dev, "unsupported rate %d\n",
 847                         params_rate(params));
 848                 return -EINVAL;
 849         }
 850
 851         switch (params_format(params)) {
 852         case SNDRV_PCM_FORMAT_S16_LE:
 853                 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
 854                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
 855                 break;
 856         case SNDRV_PCM_FORMAT_S32_LE:
 857                 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
 858                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
 859                 break;
 860         default:
 861                 dev_err(codec->dev, "unsupported format %d\n",
 862                         params_format(params));
 863                 return -EINVAL;
 864         }
 865
 866         return 0;
 867 }
 868
 869 #define CALC_OSCSET(rate, refclk) ( \
 870         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 871 #define CALC_RATIOSET(rate, refclk) ( \
 872         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 873
 874 /*
 875  * tlv320dac33 is strict on the sequence of the register writes, if the register
 876  * writes happens in different order, than dac33 might end up in unknown state.
 877  * Use the known, working sequence of register writes to initialize the dac33.
 878  */
 879 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 880 {
 881         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 882         struct snd_soc_codec *codec = rtd->codec;
 883         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 884         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 885         u8 aictrl_a, aictrl_b, fifoctrl_a;
 886
 887         switch (substream->runtime->rate) {
 888         case 44100:
 889         case 48000:
 890                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 891                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 892                                          dac33->refclk);
 893                 break;
 894         default:
 895                 dev_err(codec->dev, "unsupported rate %d\n",
 896                         substream->runtime->rate);
 897                 return -EINVAL;
 898         }
 899
 900
 901         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 902         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 903         /* Read FIFO control A, and clear FIFO flush bit */
 904         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 905         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 906
 907         fifoctrl_a &= ~DAC33_WIDTH;
 908         switch (substream->runtime->format) {
 909         case SNDRV_PCM_FORMAT_S16_LE:
 910                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 911                 fifoctrl_a |= DAC33_WIDTH;
 912                 break;
 913         case SNDRV_PCM_FORMAT_S32_LE:
 914                 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
 915                 break;
 916         default:
 917                 dev_err(codec->dev, "unsupported format %d\n",
 918                         substream->runtime->format);
 919                 return -EINVAL;
 920         }
 921
 922         mutex_lock(&dac33->mutex);
 923
 924         if (!dac33->chip_power) {
 925                 /*
 926                  * Chip is not powered yet.
 927                  * Do the init in the dac33_set_bias_level later.
 928                  */
 929                 mutex_unlock(&dac33->mutex);
 930                 return 0;
 931         }
 932
 933         dac33_soft_power(codec, 0);
 934         dac33_soft_power(codec, 1);
 935
 936         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 937         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 938
 939         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 940         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 941
 942         /* OSC calibration time */
 943         dac33_write(codec, DAC33_CALIB_TIME, 96);
 944
 945         /* adjustment treshold & step */
 946         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 947                                                  DAC33_ADJSTEP(1));
 948
 949         /* div=4 / gain=1 / div */
 950         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 951
 952         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 953         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 954         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 955
 956         dac33_oscwait(codec);
 957
 958         if (dac33->fifo_mode) {
 959                 /* Generic for all FIFO modes */
 960                 /* 50-51 : ASRC Control registers */
 961                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 962                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 963
 964                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 965                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 966
 967                 /* Set interrupts to high active */
 968                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 969         } else {
 970                 /* FIFO bypass mode */
 971                 /* 50-51 : ASRC Control registers */
 972                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 973                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 974         }
 975
 976         /* Interrupt behaviour configuration */
 977         switch (dac33->fifo_mode) {
 978         case DAC33_FIFO_MODE1:
 979                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 980                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 981                 break;
 982         case DAC33_FIFO_MODE7:
 983                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 984                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 985                 break;
 986         default:
 987                 /* in FIFO bypass mode, the interrupts are not used */
 988                 break;
 989         }
 990
 991         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 992
 993         switch (dac33->fifo_mode) {
 994         case DAC33_FIFO_MODE1:
 995                 /*
 996                  * For mode1:
 997                  * Disable the FIFO bypass (Enable the use of FIFO)
 998                  * Select nSample mode
 999                  * BCLK is only running when data is needed by DAC33
1000                  */
1001                 fifoctrl_a &= ~DAC33_FBYPAS;
1002                 fifoctrl_a &= ~DAC33_FAUTO;
1003                 if (dac33->keep_bclk)
1004                         aictrl_b |= DAC33_BCLKON;
1005                 else
1006                         aictrl_b &= ~DAC33_BCLKON;
1007                 break;
1008         case DAC33_FIFO_MODE7:
1009                 /*
1010                  * For mode1:
1011                  * Disable the FIFO bypass (Enable the use of FIFO)
1012                  * Select Threshold mode
1013                  * BCLK is only running when data is needed by DAC33
1014                  */
1015                 fifoctrl_a &= ~DAC33_FBYPAS;
1016                 fifoctrl_a |= DAC33_FAUTO;
1017                 if (dac33->keep_bclk)
1018                         aictrl_b |= DAC33_BCLKON;
1019                 else
1020                         aictrl_b &= ~DAC33_BCLKON;
1021                 break;
1022         default:
1023                 /*
1024                  * For FIFO bypass mode:
1025                  * Enable the FIFO bypass (Disable the FIFO use)
1026                  * Set the BCLK as continous
1027                  */
1028                 fifoctrl_a |= DAC33_FBYPAS;
1029                 aictrl_b |= DAC33_BCLKON;
1030                 break;
1031         }
1032
1033         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1034         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1035         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1036
1037         /*
1038          * BCLK divide ratio
1039          * 0: 1.5
1040          * 1: 1
1041          * 2: 2
1042          * ...
1043          * 254: 254
1044          * 255: 255
1045          */
1046         if (dac33->fifo_mode)
1047                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1048                                                         dac33->burst_bclkdiv);
1049         else
1050                 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1051                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1052                 else
1053                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
1054
1055         switch (dac33->fifo_mode) {
1056         case DAC33_FIFO_MODE1:
1057                 dac33_write16(codec, DAC33_ATHR_MSB,
1058                               DAC33_THRREG(dac33->alarm_threshold));
1059                 break;
1060         case DAC33_FIFO_MODE7:
1061                 /*
1062                  * Configure the threshold levels, and leave 10 sample space
1063                  * at the bottom, and also at the top of the FIFO
1064                  */
1065                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1066                 dac33_write16(codec, DAC33_LTHR_MSB,
1067                               DAC33_THRREG(DAC33_MODE7_MARGIN));
1068                 break;
1069         default:
1070                 break;
1071         }
1072
1073         mutex_unlock(&dac33->mutex);
1074
1075         return 0;
1076 }
1077
1078 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1079 {
1080         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1081         struct snd_soc_codec *codec = rtd->codec;
1082         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1083         unsigned int period_size = substream->runtime->period_size;
1084         unsigned int rate = substream->runtime->rate;
1085         unsigned int nsample_limit;
1086
1087         /* In bypass mode we don't need to calculate */
1088         if (!dac33->fifo_mode)
1089                 return;
1090
1091         switch (dac33->fifo_mode) {
1092         case DAC33_FIFO_MODE1:
1093                 /* Number of samples under i2c latency */
1094                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1095                                                 dac33->mode1_latency);
1096                 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1097
1098                 if (period_size <= dac33->alarm_threshold)
1099                         /*
1100                          * Configure nSamaple to number of periods,
1101                          * which covers the latency requironment.
1102                          */
1103                         dac33->nsample = period_size *
1104                                 ((dac33->alarm_threshold / period_size) +
1105                                 (dac33->alarm_threshold % period_size ?
1106                                 1 : 0));
1107                 else if (period_size > nsample_limit)
1108                         dac33->nsample = nsample_limit;
1109                 else
1110                         dac33->nsample = period_size;
1111
1112                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1113                                                       dac33->nsample);
1114                 dac33->t_stamp1 = 0;
1115                 dac33->t_stamp2 = 0;
1116                 break;
1117         case DAC33_FIFO_MODE7:
1118                 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1119                                                     dac33->burst_rate) + 9;
1120                 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1121                         dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1122                 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1123                         dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1124
1125                 dac33->mode7_us_to_lthr =
1126                                 SAMPLES_TO_US(substream->runtime->rate,
1127                                         dac33->uthr - DAC33_MODE7_MARGIN + 1);
1128                 dac33->t_stamp1 = 0;
1129                 break;
1130         default:
1131                 break;
1132         }
1133
1134 }
1135
1136 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1137                              struct snd_soc_dai *dai)
1138 {
1139         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1140         struct snd_soc_codec *codec = rtd->codec;
1141         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1142         int ret = 0;
1143
1144         switch (cmd) {
1145         case SNDRV_PCM_TRIGGER_START:
1146         case SNDRV_PCM_TRIGGER_RESUME:
1147         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1148                 if (dac33->fifo_mode) {
1149                         dac33->state = DAC33_PREFILL;
1150                         queue_work(dac33->dac33_wq, &dac33->work);
1151                 }
1152                 break;
1153         case SNDRV_PCM_TRIGGER_STOP:
1154         case SNDRV_PCM_TRIGGER_SUSPEND:
1155         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1156                 if (dac33->fifo_mode) {
1157                         dac33->state = DAC33_FLUSH;
1158                         queue_work(dac33->dac33_wq, &dac33->work);
1159                 }
1160                 break;
1161         default:
1162                 ret = -EINVAL;
1163         }
1164
1165         return ret;
1166 }
1167
1168 static snd_pcm_sframes_t dac33_dai_delay(
1169                         struct snd_pcm_substream *substream,
1170                         struct snd_soc_dai *dai)
1171 {
1172         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1173         struct snd_soc_codec *codec = rtd->codec;
1174         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1175         unsigned long long t0, t1, t_now;
1176         unsigned int time_delta, uthr;
1177         int samples_out, samples_in, samples;
1178         snd_pcm_sframes_t delay = 0;
1179
1180         switch (dac33->fifo_mode) {
1181         case DAC33_FIFO_BYPASS:
1182                 break;
1183         case DAC33_FIFO_MODE1:
1184                 spin_lock(&dac33->lock);
1185                 t0 = dac33->t_stamp1;
1186                 t1 = dac33->t_stamp2;
1187                 spin_unlock(&dac33->lock);
1188                 t_now = ktime_to_us(ktime_get());
1189
1190                 /* We have not started to fill the FIFO yet, delay is 0 */
1191                 if (!t1)
1192                         goto out;
1193
1194                 if (t0 > t1) {
1195                         /*
1196                          * Phase 1:
1197                          * After Alarm threshold, and before nSample write
1198                          */
1199                         time_delta = t_now - t0;
1200                         samples_out = time_delta ? US_TO_SAMPLES(
1201                                                 substream->runtime->rate,
1202                                                 time_delta) : 0;
1203
1204                         if (likely(dac33->alarm_threshold > samples_out))
1205                                 delay = dac33->alarm_threshold - samples_out;
1206                         else
1207                                 delay = 0;
1208                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1209                         /*
1210                          * Phase 2:
1211                          * After nSample write (during burst operation)
1212                          */
1213                         time_delta = t_now - t0;
1214                         samples_out = time_delta ? US_TO_SAMPLES(
1215                                                 substream->runtime->rate,
1216                                                 time_delta) : 0;
1217
1218                         time_delta = t_now - t1;
1219                         samples_in = time_delta ? US_TO_SAMPLES(
1220                                                 dac33->burst_rate,
1221                                                 time_delta) : 0;
1222
1223                         samples = dac33->alarm_threshold;
1224                         samples += (samples_in - samples_out);
1225
1226                         if (likely(samples > 0))
1227                                 delay = samples;
1228                         else
1229                                 delay = 0;
1230                 } else {
1231                         /*
1232                          * Phase 3:
1233                          * After burst operation, before next alarm threshold
1234                          */
1235                         time_delta = t_now - t0;
1236                         samples_out = time_delta ? US_TO_SAMPLES(
1237                                                 substream->runtime->rate,
1238                                                 time_delta) : 0;
1239
1240                         samples_in = dac33->nsample;
1241                         samples = dac33->alarm_threshold;
1242                         samples += (samples_in - samples_out);
1243
1244                         if (likely(samples > 0))
1245                                 delay = samples > dac33->fifo_size ?
1246                                         dac33->fifo_size : samples;
1247                         else
1248                                 delay = 0;
1249                 }
1250                 break;
1251         case DAC33_FIFO_MODE7:
1252                 spin_lock(&dac33->lock);
1253                 t0 = dac33->t_stamp1;
1254                 uthr = dac33->uthr;
1255                 spin_unlock(&dac33->lock);
1256                 t_now = ktime_to_us(ktime_get());
1257
1258                 /* We have not started to fill the FIFO yet, delay is 0 */
1259                 if (!t0)
1260                         goto out;
1261
1262                 if (t_now <= t0) {
1263                         /*
1264                          * Either the timestamps are messed or equal. Report
1265                          * maximum delay
1266                          */
1267                         delay = uthr;
1268                         goto out;
1269                 }
1270
1271                 time_delta = t_now - t0;
1272                 if (time_delta <= dac33->mode7_us_to_lthr) {
1273                         /*
1274                         * Phase 1:
1275                         * After burst (draining phase)
1276                         */
1277                         samples_out = US_TO_SAMPLES(
1278                                         substream->runtime->rate,
1279                                         time_delta);
1280
1281                         if (likely(uthr > samples_out))
1282                                 delay = uthr - samples_out;
1283                         else
1284                                 delay = 0;
1285                 } else {
1286                         /*
1287                         * Phase 2:
1288                         * During burst operation
1289                         */
1290                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1291
1292                         samples_out = US_TO_SAMPLES(
1293                                         substream->runtime->rate,
1294                                         time_delta);
1295                         samples_in = US_TO_SAMPLES(
1296                                         dac33->burst_rate,
1297                                         time_delta);
1298                         delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1299
1300                         if (unlikely(delay > uthr))
1301                                 delay = uthr;
1302                 }
1303                 break;
1304         default:
1305                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1306                                                         dac33->fifo_mode);
1307                 break;
1308         }
1309 out:
1310         return delay;
1311 }
1312
1313 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1314                 int clk_id, unsigned int freq, int dir)
1315 {
1316         struct snd_soc_codec *codec = codec_dai->codec;
1317         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1318         u8 ioc_reg, asrcb_reg;
1319
1320         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1321         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1322         switch (clk_id) {
1323         case TLV320DAC33_MCLK:
1324                 ioc_reg |= DAC33_REFSEL;
1325                 asrcb_reg |= DAC33_SRCREFSEL;
1326                 break;
1327         case TLV320DAC33_SLEEPCLK:
1328                 ioc_reg &= ~DAC33_REFSEL;
1329                 asrcb_reg &= ~DAC33_SRCREFSEL;
1330                 break;
1331         default:
1332                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1333                 break;
1334         }
1335         dac33->refclk = freq;
1336
1337         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1338         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1339
1340         return 0;
1341 }
1342
1343 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1344                              unsigned int fmt)
1345 {
1346         struct snd_soc_codec *codec = codec_dai->codec;
1347         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1348         u8 aictrl_a, aictrl_b;
1349
1350         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1351         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1352         /* set master/slave audio interface */
1353         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1354         case SND_SOC_DAIFMT_CBM_CFM:
1355                 /* Codec Master */
1356                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1357                 break;
1358         case SND_SOC_DAIFMT_CBS_CFS:
1359                 /* Codec Slave */
1360                 if (dac33->fifo_mode) {
1361                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1362                         return -EINVAL;
1363                 } else
1364                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1365                 break;
1366         default:
1367                 return -EINVAL;
1368         }
1369
1370         aictrl_a &= ~DAC33_AFMT_MASK;
1371         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1372         case SND_SOC_DAIFMT_I2S:
1373                 aictrl_a |= DAC33_AFMT_I2S;
1374                 break;
1375         case SND_SOC_DAIFMT_DSP_A:
1376                 aictrl_a |= DAC33_AFMT_DSP;
1377                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1378                 aictrl_b |= DAC33_DATA_DELAY(0);
1379                 break;
1380         case SND_SOC_DAIFMT_RIGHT_J:
1381                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1382                 break;
1383         case SND_SOC_DAIFMT_LEFT_J:
1384                 aictrl_a |= DAC33_AFMT_LEFT_J;
1385                 break;
1386         default:
1387                 dev_err(codec->dev, "Unsupported format (%u)\n",
1388                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1389                 return -EINVAL;
1390         }
1391
1392         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1393         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1394
1395         return 0;
1396 }
1397
1398 static int dac33_soc_probe(struct snd_soc_codec *codec)
1399 {
1400         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1401         int ret = 0;
1402
1403         codec->control_data = dac33->control_data;
1404         codec->hw_write = (hw_write_t) i2c_master_send;
1405         codec->dapm.idle_bias_off = 1;
1406         dac33->codec = codec;
1407
1408         /* Read the tlv320dac33 ID registers */
1409         ret = dac33_hard_power(codec, 1);
1410         if (ret != 0) {
1411                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1412                 goto err_power;
1413         }
1414         ret = dac33_read_id(codec);
1415         dac33_hard_power(codec, 0);
1416
1417         if (ret < 0) {
1418                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1419                 ret = -ENODEV;
1420                 goto err_power;
1421         }
1422
1423         /* Check if the IRQ number is valid and request it */
1424         if (dac33->irq >= 0) {
1425                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1426                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1427                                   codec->name, codec);
1428                 if (ret < 0) {
1429                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1430                                                 dac33->irq, ret);
1431                         dac33->irq = -1;
1432                 }
1433                 if (dac33->irq != -1) {
1434                         /* Setup work queue */
1435                         dac33->dac33_wq =
1436                                 create_singlethread_workqueue("tlv320dac33");
1437                         if (dac33->dac33_wq == NULL) {
1438                                 free_irq(dac33->irq, codec);
1439                                 return -ENOMEM;
1440                         }
1441
1442                         INIT_WORK(&dac33->work, dac33_work);
1443                 }
1444         }
1445
1446         snd_soc_add_controls(codec, dac33_snd_controls,
1447                              ARRAY_SIZE(dac33_snd_controls));
1448         /* Only add the FIFO controls, if we have valid IRQ number */
1449         if (dac33->irq >= 0)
1450                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1451                                      ARRAY_SIZE(dac33_mode_snd_controls));
1452
1453         dac33_add_widgets(codec);
1454
1455 err_power:
1456         return ret;
1457 }
1458
1459 static int dac33_soc_remove(struct snd_soc_codec *codec)
1460 {
1461         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1462
1463         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1464
1465         if (dac33->irq >= 0) {
1466                 free_irq(dac33->irq, dac33->codec);
1467                 destroy_workqueue(dac33->dac33_wq);
1468         }
1469         return 0;
1470 }
1471
1472 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1473 {
1474         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1475
1476         return 0;
1477 }
1478
1479 static int dac33_soc_resume(struct snd_soc_codec *codec)
1480 {
1481         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1482
1483         return 0;
1484 }
1485
1486 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1487         .read = dac33_read_reg_cache,
1488         .write = dac33_write_locked,
1489         .set_bias_level = dac33_set_bias_level,
1490         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1491         .reg_word_size = sizeof(u8),
1492         .reg_cache_default = dac33_reg,
1493         .probe = dac33_soc_probe,
1494         .remove = dac33_soc_remove,
1495         .suspend = dac33_soc_suspend,
1496         .resume = dac33_soc_resume,
1497 };
1498
1499 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1500                          SNDRV_PCM_RATE_48000)
1501 #define DAC33_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1502
1503 static struct snd_soc_dai_ops dac33_dai_ops = {
1504         .startup        = dac33_startup,
1505         .shutdown       = dac33_shutdown,
1506         .hw_params      = dac33_hw_params,
1507         .trigger        = dac33_pcm_trigger,
1508         .delay          = dac33_dai_delay,
1509         .set_sysclk     = dac33_set_dai_sysclk,
1510         .set_fmt        = dac33_set_dai_fmt,
1511 };
1512
1513 static struct snd_soc_dai_driver dac33_dai = {
1514         .name = "tlv320dac33-hifi",
1515         .playback = {
1516                 .stream_name = "Playback",
1517                 .channels_min = 2,
1518                 .channels_max = 2,
1519                 .rates = DAC33_RATES,
1520                 .formats = DAC33_FORMATS,},
1521         .ops = &dac33_dai_ops,
1522 };
1523
1524 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1525                                      const struct i2c_device_id *id)
1526 {
1527         struct tlv320dac33_platform_data *pdata;
1528         struct tlv320dac33_priv *dac33;
1529         int ret, i;
1530
1531         if (client->dev.platform_data == NULL) {
1532                 dev_err(&client->dev, "Platform data not set\n");
1533                 return -ENODEV;
1534         }
1535         pdata = client->dev.platform_data;
1536
1537         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1538         if (dac33 == NULL)
1539                 return -ENOMEM;
1540
1541         dac33->control_data = client;
1542         mutex_init(&dac33->mutex);
1543         spin_lock_init(&dac33->lock);
1544
1545         i2c_set_clientdata(client, dac33);
1546
1547         dac33->power_gpio = pdata->power_gpio;
1548         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1549         dac33->keep_bclk = pdata->keep_bclk;
1550         dac33->mode1_latency = pdata->mode1_latency;
1551         if (!dac33->mode1_latency)
1552                 dac33->mode1_latency = 10000; /* 10ms */
1553         dac33->irq = client->irq;
1554         /* Disable FIFO use by default */
1555         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1556
1557         /* Check if the reset GPIO number is valid and request it */
1558         if (dac33->power_gpio >= 0) {
1559                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1560                 if (ret < 0) {
1561                         dev_err(&client->dev,
1562                                 "Failed to request reset GPIO (%d)\n",
1563                                 dac33->power_gpio);
1564                         goto err_gpio;
1565                 }
1566                 gpio_direction_output(dac33->power_gpio, 0);
1567         }
1568
1569         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1570                 dac33->supplies[i].supply = dac33_supply_names[i];
1571
1572         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1573                                  dac33->supplies);
1574
1575         if (ret != 0) {
1576                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1577                 goto err_get;
1578         }
1579
1580         ret = snd_soc_register_codec(&client->dev,
1581                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1582         if (ret < 0)
1583                 goto err_register;
1584
1585         return ret;
1586 err_register:
1587         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1588 err_get:
1589         if (dac33->power_gpio >= 0)
1590                 gpio_free(dac33->power_gpio);
1591 err_gpio:
1592         kfree(dac33);
1593         return ret;
1594 }
1595
1596 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1597 {
1598         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1599
1600         if (unlikely(dac33->chip_power))
1601                 dac33_hard_power(dac33->codec, 0);
1602
1603         if (dac33->power_gpio >= 0)
1604                 gpio_free(dac33->power_gpio);
1605
1606         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1607
1608         snd_soc_unregister_codec(&client->dev);
1609         kfree(dac33);
1610
1611         return 0;
1612 }
1613
1614 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1615         {
1616                 .name = "tlv320dac33",
1617                 .driver_data = 0,
1618         },
1619         { },
1620 };
1621 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
1622
1623 static struct i2c_driver tlv320dac33_i2c_driver = {
1624         .driver = {
1625                 .name = "tlv320dac33-codec",
1626                 .owner = THIS_MODULE,
1627         },
1628         .probe          = dac33_i2c_probe,
1629         .remove         = __devexit_p(dac33_i2c_remove),
1630         .id_table       = tlv320dac33_i2c_id,
1631 };
1632
1633 static int __init dac33_module_init(void)
1634 {
1635         int r;
1636         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1637         if (r < 0) {
1638                 printk(KERN_ERR "DAC33: driver registration failed\n");
1639                 return r;
1640         }
1641         return 0;
1642 }
1643 module_init(dac33_module_init);
1644
1645 static void __exit dac33_module_exit(void)
1646 {
1647         i2c_del_driver(&tlv320dac33_i2c_driver);
1648 }
1649 module_exit(dac33_module_exit);
1650
1651
1652 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1653 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1654 MODULE_LICENSE("GPL");