2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
509 #define AES32_CHANNELS 16
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 /* revisions >= 230 indicate AES32 card */
524 #define HDSPM_MADI_ANCIENT_REV 204
525 #define HDSPM_MADI_OLD_REV 207
526 #define HDSPM_MADI_REV 210
527 #define HDSPM_RAYDAT_REV 211
528 #define HDSPM_AIO_REV 212
529 #define HDSPM_MADIFACE_REV 213
530 #define HDSPM_AES_REV 240
531 #define HDSPM_AES32_REV 234
532 #define HDSPM_AES32_OLD_REV 233
534 /* speed factor modes */
535 #define HDSPM_SPEED_SINGLE 0
536 #define HDSPM_SPEED_DOUBLE 1
537 #define HDSPM_SPEED_QUAD 2
539 /* names for speed modes */
540 static char *hdspm_speed_names[] = { "single", "double", "quad" };
542 static char *texts_autosync_aes_tco[] = { "Word Clock",
543 "AES1", "AES2", "AES3", "AES4",
544 "AES5", "AES6", "AES7", "AES8",
546 static char *texts_autosync_aes[] = { "Word Clock",
547 "AES1", "AES2", "AES3", "AES4",
548 "AES5", "AES6", "AES7", "AES8" };
549 static char *texts_autosync_madi_tco[] = { "Word Clock",
550 "MADI", "TCO", "Sync In" };
551 static char *texts_autosync_madi[] = { "Word Clock",
554 static char *texts_autosync_raydat_tco[] = {
556 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
557 "AES", "SPDIF", "TCO", "Sync In"
559 static char *texts_autosync_raydat[] = {
561 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
562 "AES", "SPDIF", "Sync In"
564 static char *texts_autosync_aio_tco[] = {
566 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
568 static char *texts_autosync_aio[] = { "Word Clock",
569 "ADAT", "AES", "SPDIF", "Sync In" };
571 static char *texts_freq[] = {
584 static char *texts_ports_madi[] = {
585 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
586 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
587 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
588 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
589 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
590 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
591 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
592 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
593 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
594 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
595 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
599 static char *texts_ports_raydat_ss[] = {
600 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
601 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
602 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
603 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
604 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
605 "ADAT4.7", "ADAT4.8",
610 static char *texts_ports_raydat_ds[] = {
611 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
612 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
613 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
614 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
619 static char *texts_ports_raydat_qs[] = {
620 "ADAT1.1", "ADAT1.2",
621 "ADAT2.1", "ADAT2.2",
622 "ADAT3.1", "ADAT3.2",
623 "ADAT4.1", "ADAT4.2",
629 static char *texts_ports_aio_in_ss[] = {
630 "Analogue.L", "Analogue.R",
632 "SPDIF.L", "SPDIF.R",
633 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
637 static char *texts_ports_aio_out_ss[] = {
638 "Analogue.L", "Analogue.R",
640 "SPDIF.L", "SPDIF.R",
641 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
646 static char *texts_ports_aio_in_ds[] = {
647 "Analogue.L", "Analogue.R",
649 "SPDIF.L", "SPDIF.R",
650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
653 static char *texts_ports_aio_out_ds[] = {
654 "Analogue.L", "Analogue.R",
656 "SPDIF.L", "SPDIF.R",
657 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
661 static char *texts_ports_aio_in_qs[] = {
662 "Analogue.L", "Analogue.R",
664 "SPDIF.L", "SPDIF.R",
665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
668 static char *texts_ports_aio_out_qs[] = {
669 "Analogue.L", "Analogue.R",
671 "SPDIF.L", "SPDIF.R",
672 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
676 static char *texts_ports_aes32[] = {
677 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
678 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
682 /* These tables map the ALSA channels 1..N to the channels that we
683 need to use in order to find the relevant channel buffer. RME
684 refers to this kind of mapping as between "the ADAT channel and
685 the DMA channel." We index it using the logical audio channel,
686 and the value is the DMA channel (i.e. channel buffer number)
687 where the data for that channel can be read/written from/to.
690 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
691 0, 1, 2, 3, 4, 5, 6, 7,
692 8, 9, 10, 11, 12, 13, 14, 15,
693 16, 17, 18, 19, 20, 21, 22, 23,
694 24, 25, 26, 27, 28, 29, 30, 31,
695 32, 33, 34, 35, 36, 37, 38, 39,
696 40, 41, 42, 43, 44, 45, 46, 47,
697 48, 49, 50, 51, 52, 53, 54, 55,
698 56, 57, 58, 59, 60, 61, 62, 63
701 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
702 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
703 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
704 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
705 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
709 -1, -1, -1, -1, -1, -1, -1, -1,
710 -1, -1, -1, -1, -1, -1, -1, -1,
711 -1, -1, -1, -1, -1, -1, -1, -1,
714 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
715 4, 5, 6, 7, /* ADAT 1 */
716 8, 9, 10, 11, /* ADAT 2 */
717 12, 13, 14, 15, /* ADAT 3 */
718 16, 17, 18, 19, /* ADAT 4 */
722 -1, -1, -1, -1, -1, -1, -1, -1,
723 -1, -1, -1, -1, -1, -1, -1, -1,
724 -1, -1, -1, -1, -1, -1, -1, -1,
725 -1, -1, -1, -1, -1, -1, -1, -1,
726 -1, -1, -1, -1, -1, -1, -1, -1,
729 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
737 -1, -1, -1, -1, -1, -1, -1, -1,
738 -1, -1, -1, -1, -1, -1, -1, -1,
739 -1, -1, -1, -1, -1, -1, -1, -1,
740 -1, -1, -1, -1, -1, -1, -1, -1,
741 -1, -1, -1, -1, -1, -1, -1, -1,
742 -1, -1, -1, -1, -1, -1, -1, -1,
745 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
748 10, 11, /* spdif in */
749 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
751 -1, -1, -1, -1, -1, -1, -1, -1,
752 -1, -1, -1, -1, -1, -1, -1, -1,
753 -1, -1, -1, -1, -1, -1, -1, -1,
754 -1, -1, -1, -1, -1, -1, -1, -1,
755 -1, -1, -1, -1, -1, -1, -1, -1,
756 -1, -1, -1, -1, -1, -1, -1, -1,
759 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
762 10, 11, /* spdif out */
763 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
764 6, 7, /* phone out */
765 -1, -1, -1, -1, -1, -1, -1, -1,
766 -1, -1, -1, -1, -1, -1, -1, -1,
767 -1, -1, -1, -1, -1, -1, -1, -1,
768 -1, -1, -1, -1, -1, -1, -1, -1,
769 -1, -1, -1, -1, -1, -1, -1, -1,
770 -1, -1, -1, -1, -1, -1, -1, -1,
773 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
776 10, 11, /* spdif in */
777 12, 14, 16, 18, /* adat in */
778 -1, -1, -1, -1, -1, -1,
779 -1, -1, -1, -1, -1, -1, -1, -1,
780 -1, -1, -1, -1, -1, -1, -1, -1,
781 -1, -1, -1, -1, -1, -1, -1, -1,
782 -1, -1, -1, -1, -1, -1, -1, -1,
783 -1, -1, -1, -1, -1, -1, -1, -1,
784 -1, -1, -1, -1, -1, -1, -1, -1
787 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
790 10, 11, /* spdif out */
791 12, 14, 16, 18, /* adat out */
792 6, 7, /* phone out */
794 -1, -1, -1, -1, -1, -1, -1, -1,
795 -1, -1, -1, -1, -1, -1, -1, -1,
796 -1, -1, -1, -1, -1, -1, -1, -1,
797 -1, -1, -1, -1, -1, -1, -1, -1,
798 -1, -1, -1, -1, -1, -1, -1, -1,
799 -1, -1, -1, -1, -1, -1, -1, -1
802 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
805 10, 11, /* spdif in */
806 12, 16, /* adat in */
807 -1, -1, -1, -1, -1, -1, -1, -1,
808 -1, -1, -1, -1, -1, -1, -1, -1,
809 -1, -1, -1, -1, -1, -1, -1, -1,
810 -1, -1, -1, -1, -1, -1, -1, -1,
811 -1, -1, -1, -1, -1, -1, -1, -1,
812 -1, -1, -1, -1, -1, -1, -1, -1,
813 -1, -1, -1, -1, -1, -1, -1, -1
816 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
819 10, 11, /* spdif out */
820 12, 16, /* adat out */
821 6, 7, /* phone out */
822 -1, -1, -1, -1, -1, -1,
823 -1, -1, -1, -1, -1, -1, -1, -1,
824 -1, -1, -1, -1, -1, -1, -1, -1,
825 -1, -1, -1, -1, -1, -1, -1, -1,
826 -1, -1, -1, -1, -1, -1, -1, -1,
827 -1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1
831 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
832 0, 1, 2, 3, 4, 5, 6, 7,
833 8, 9, 10, 11, 12, 13, 14, 15,
834 -1, -1, -1, -1, -1, -1, -1, -1,
835 -1, -1, -1, -1, -1, -1, -1, -1,
836 -1, -1, -1, -1, -1, -1, -1, -1,
837 -1, -1, -1, -1, -1, -1, -1, -1,
838 -1, -1, -1, -1, -1, -1, -1, -1,
839 -1, -1, -1, -1, -1, -1, -1, -1
845 struct snd_rawmidi *rmidi;
846 struct snd_rawmidi_substream *input;
847 struct snd_rawmidi_substream *output;
848 char istimer; /* timer in use */
849 struct timer_list timer;
866 int term; /* 0 = off, 1 = on */
871 /* only one playback and/or capture stream */
872 struct snd_pcm_substream *capture_substream;
873 struct snd_pcm_substream *playback_substream;
875 char *card_name; /* for procinfo */
876 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
880 int monitor_outs; /* set up monitoring outs init flag */
882 u32 control_register; /* cached value */
883 u32 control2_register; /* cached value */
884 u32 settings_register;
886 struct hdspm_midi midi[4];
887 struct tasklet_struct midi_tasklet;
890 unsigned char ss_in_channels;
891 unsigned char ds_in_channels;
892 unsigned char qs_in_channels;
893 unsigned char ss_out_channels;
894 unsigned char ds_out_channels;
895 unsigned char qs_out_channels;
897 unsigned char max_channels_in;
898 unsigned char max_channels_out;
900 signed char *channel_map_in;
901 signed char *channel_map_out;
903 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
904 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
906 char **port_names_in;
907 char **port_names_out;
909 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
910 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
912 unsigned char *playback_buffer; /* suitably aligned address */
913 unsigned char *capture_buffer; /* suitably aligned address */
915 pid_t capture_pid; /* process id which uses capture */
916 pid_t playback_pid; /* process id which uses capture */
917 int running; /* running status */
919 int last_external_sample_rate; /* samplerate mystic ... */
920 int last_internal_sample_rate;
921 int system_sample_rate;
923 int dev; /* Hardware vars... */
926 void __iomem *iobase;
928 int irq_count; /* for debug */
931 struct snd_card *card; /* one card */
932 struct snd_pcm *pcm; /* has one pcm */
933 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
934 struct pci_dev *pci; /* and an pci info */
937 /* fast alsa mixer */
938 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
939 /* but input to much, so not used */
940 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
941 /* full mixer accessible over mixer ioctl or hwdep-device */
942 struct hdspm_mixer *mixer;
944 struct hdspm_tco *tco; /* NULL if no TCO detected */
946 char **texts_autosync;
947 int texts_autosync_items;
949 cycles_t last_interrupt;
951 struct hdspm_peak_rms peak_rms;
955 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
957 .vendor = PCI_VENDOR_ID_XILINX,
958 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
959 .subvendor = PCI_ANY_ID,
960 .subdevice = PCI_ANY_ID,
967 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
970 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
971 struct hdspm * hdspm);
972 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
973 struct hdspm * hdspm);
975 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
976 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
977 static int hdspm_autosync_ref(struct hdspm *hdspm);
978 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
979 static void hdspm_set_sgbuf(struct hdspm *hdspm,
980 struct snd_pcm_substream *substream,
981 unsigned int reg, int channels);
983 static inline int HDSPM_bit2freq(int n)
985 static const int bit2freq_tab[] = {
986 0, 32000, 44100, 48000, 64000, 88200,
987 96000, 128000, 176400, 192000 };
990 return bit2freq_tab[n];
993 /* Write/read to/from HDSPM with Adresses in Bytes
994 not words but only 32Bit writes are allowed */
996 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
999 writel(val, hdspm->iobase + reg);
1002 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1004 return readl(hdspm->iobase + reg);
1007 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1008 mixer is write only on hardware so we have to cache him for read
1009 each fader is a u32, but uses only the first 16 bit */
1011 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1014 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1017 return hdspm->mixer->ch[chan].in[in];
1020 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1023 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1025 return hdspm->mixer->ch[chan].pb[pb];
1028 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1029 unsigned int in, unsigned short data)
1031 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1035 HDSPM_MADI_mixerBase +
1036 ((in + 128 * chan) * sizeof(u32)),
1037 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1041 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1042 unsigned int pb, unsigned short data)
1044 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1048 HDSPM_MADI_mixerBase +
1049 ((64 + pb + 128 * chan) * sizeof(u32)),
1050 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1055 /* enable DMA for specific channels, now available for DSP-MADI */
1056 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1058 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1061 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1063 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1066 /* check if same process is writing and reading */
1067 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1069 unsigned long flags;
1072 spin_lock_irqsave(&hdspm->lock, flags);
1073 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1074 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1077 spin_unlock_irqrestore(&hdspm->lock, flags);
1081 /* check for external sample rate */
1082 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1084 unsigned int status, status2, timecode;
1085 int syncref, rate = 0, rate_bits;
1087 switch (hdspm->io_type) {
1089 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1090 status = hdspm_read(hdspm, HDSPM_statusRegister);
1091 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1093 syncref = hdspm_autosync_ref(hdspm);
1095 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1096 status & HDSPM_AES32_wcLock)
1097 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1099 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1100 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1101 status2 & (HDSPM_LockAES >>
1102 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1103 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1108 status = hdspm_read(hdspm, HDSPM_statusRegister);
1110 if (!(status & HDSPM_madiLock)) {
1111 rate = 0; /* no lock */
1113 switch (status & (HDSPM_status1_freqMask)) {
1114 case HDSPM_status1_F_0*1:
1115 rate = 32000; break;
1116 case HDSPM_status1_F_0*2:
1117 rate = 44100; break;
1118 case HDSPM_status1_F_0*3:
1119 rate = 48000; break;
1120 case HDSPM_status1_F_0*4:
1121 rate = 64000; break;
1122 case HDSPM_status1_F_0*5:
1123 rate = 88200; break;
1124 case HDSPM_status1_F_0*6:
1125 rate = 96000; break;
1126 case HDSPM_status1_F_0*7:
1127 rate = 128000; break;
1128 case HDSPM_status1_F_0*8:
1129 rate = 176400; break;
1130 case HDSPM_status1_F_0*9:
1131 rate = 192000; break;
1142 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1143 status = hdspm_read(hdspm, HDSPM_statusRegister);
1146 /* if wordclock has synced freq and wordclock is valid */
1147 if ((status2 & HDSPM_wcLock) != 0 &&
1148 (status2 & HDSPM_SelSyncRef0) == 0) {
1150 rate_bits = status2 & HDSPM_wcFreqMask;
1153 switch (rate_bits) {
1154 case HDSPM_wcFreq32:
1157 case HDSPM_wcFreq44_1:
1160 case HDSPM_wcFreq48:
1163 case HDSPM_wcFreq64:
1166 case HDSPM_wcFreq88_2:
1169 case HDSPM_wcFreq96:
1178 /* if rate detected and Syncref is Word than have it,
1179 * word has priority to MADI
1182 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1185 /* maybe a madi input (which is taken if sel sync is madi) */
1186 if (status & HDSPM_madiLock) {
1187 rate_bits = status & HDSPM_madiFreqMask;
1189 switch (rate_bits) {
1190 case HDSPM_madiFreq32:
1193 case HDSPM_madiFreq44_1:
1196 case HDSPM_madiFreq48:
1199 case HDSPM_madiFreq64:
1202 case HDSPM_madiFreq88_2:
1205 case HDSPM_madiFreq96:
1208 case HDSPM_madiFreq128:
1211 case HDSPM_madiFreq176_4:
1214 case HDSPM_madiFreq192:
1222 /* QS and DS rates normally can not be detected
1223 * automatically by the card. Only exception is MADI
1224 * in 96k frame mode.
1226 * So if we read SS values (32 .. 48k), check for
1227 * user-provided DS/QS bits in the control register
1228 * and multiply the base frequency accordingly.
1230 if (rate <= 48000) {
1231 if (hdspm->control_register & HDSPM_QuadSpeed)
1233 else if (hdspm->control_register &
1244 /* Latency function */
1245 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1247 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1251 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1255 position = hdspm_read(hdspm, HDSPM_statusRegister);
1257 switch (hdspm->io_type) {
1260 position &= HDSPM_BufferPositionMask;
1261 position /= 4; /* Bytes per sample */
1264 position = (position & HDSPM_BufferID) ?
1265 (hdspm->period_bytes / 4) : 0;
1272 static inline void hdspm_start_audio(struct hdspm * s)
1274 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1275 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1278 static inline void hdspm_stop_audio(struct hdspm * s)
1280 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1281 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1284 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1285 static void hdspm_silence_playback(struct hdspm *hdspm)
1288 int n = hdspm->period_bytes;
1289 void *buf = hdspm->playback_buffer;
1294 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1296 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1300 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1304 spin_lock_irq(&s->lock);
1312 s->control_register &= ~HDSPM_LatencyMask;
1313 s->control_register |= hdspm_encode_latency(n);
1315 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1317 hdspm_compute_period_size(s);
1319 spin_unlock_irq(&s->lock);
1324 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1331 switch (hdspm->io_type) {
1334 freq_const = 110069313433624ULL;
1338 freq_const = 104857600000000ULL;
1341 freq_const = 131072000000000ULL;
1344 return div_u64(freq_const, period);
1348 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1354 else if (rate >= 56000)
1357 switch (hdspm->io_type) {
1359 n = 131072000000000ULL; /* 125 MHz */
1363 n = 110069313433624ULL; /* 105 MHz */
1367 n = 104857600000000ULL; /* 100 MHz */
1371 n = div_u64(n, rate);
1372 /* n should be less than 2^32 for being written to FREQ register */
1373 snd_BUG_ON(n >> 32);
1374 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1377 /* dummy set rate lets see what happens */
1378 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1383 int current_speed, target_speed;
1385 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1386 it (e.g. during module initialization).
1389 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1392 if (called_internally) {
1394 /* request from ctl or card initialization
1395 just make a warning an remember setting
1396 for future master mode switching */
1398 snd_printk(KERN_WARNING "HDSPM: "
1399 "Warning: device is not running "
1400 "as a clock master.\n");
1404 /* hw_param request while in AutoSync mode */
1406 hdspm_external_sample_rate(hdspm);
1408 if (hdspm_autosync_ref(hdspm) ==
1409 HDSPM_AUTOSYNC_FROM_NONE) {
1411 snd_printk(KERN_WARNING "HDSPM: "
1412 "Detected no Externel Sync \n");
1415 } else if (rate != external_freq) {
1417 snd_printk(KERN_WARNING "HDSPM: "
1418 "Warning: No AutoSync source for "
1419 "requested rate\n");
1425 current_rate = hdspm->system_sample_rate;
1427 /* Changing between Singe, Double and Quad speed is not
1428 allowed if any substreams are open. This is because such a change
1429 causes a shift in the location of the DMA buffers and a reduction
1430 in the number of available buffers.
1432 Note that a similar but essentially insoluble problem exists for
1433 externally-driven rate changes. All we can do is to flag rate
1434 changes in the read/write routines.
1437 if (current_rate <= 48000)
1438 current_speed = HDSPM_SPEED_SINGLE;
1439 else if (current_rate <= 96000)
1440 current_speed = HDSPM_SPEED_DOUBLE;
1442 current_speed = HDSPM_SPEED_QUAD;
1445 target_speed = HDSPM_SPEED_SINGLE;
1446 else if (rate <= 96000)
1447 target_speed = HDSPM_SPEED_DOUBLE;
1449 target_speed = HDSPM_SPEED_QUAD;
1453 rate_bits = HDSPM_Frequency32KHz;
1456 rate_bits = HDSPM_Frequency44_1KHz;
1459 rate_bits = HDSPM_Frequency48KHz;
1462 rate_bits = HDSPM_Frequency64KHz;
1465 rate_bits = HDSPM_Frequency88_2KHz;
1468 rate_bits = HDSPM_Frequency96KHz;
1471 rate_bits = HDSPM_Frequency128KHz;
1474 rate_bits = HDSPM_Frequency176_4KHz;
1477 rate_bits = HDSPM_Frequency192KHz;
1483 if (current_speed != target_speed
1484 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1487 "cannot change from %s speed to %s speed mode "
1488 "(capture PID = %d, playback PID = %d)\n",
1489 hdspm_speed_names[current_speed],
1490 hdspm_speed_names[target_speed],
1491 hdspm->capture_pid, hdspm->playback_pid);
1495 hdspm->control_register &= ~HDSPM_FrequencyMask;
1496 hdspm->control_register |= rate_bits;
1497 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1499 /* For AES32, need to set DDS value in FREQ register
1500 For MADI, also apparently */
1501 hdspm_set_dds_value(hdspm, rate);
1503 if (AES32 == hdspm->io_type && rate != current_rate)
1504 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1506 hdspm->system_sample_rate = rate;
1508 if (rate <= 48000) {
1509 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1510 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1511 hdspm->max_channels_in = hdspm->ss_in_channels;
1512 hdspm->max_channels_out = hdspm->ss_out_channels;
1513 hdspm->port_names_in = hdspm->port_names_in_ss;
1514 hdspm->port_names_out = hdspm->port_names_out_ss;
1515 } else if (rate <= 96000) {
1516 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1517 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1518 hdspm->max_channels_in = hdspm->ds_in_channels;
1519 hdspm->max_channels_out = hdspm->ds_out_channels;
1520 hdspm->port_names_in = hdspm->port_names_in_ds;
1521 hdspm->port_names_out = hdspm->port_names_out_ds;
1523 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1524 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1525 hdspm->max_channels_in = hdspm->qs_in_channels;
1526 hdspm->max_channels_out = hdspm->qs_out_channels;
1527 hdspm->port_names_in = hdspm->port_names_in_qs;
1528 hdspm->port_names_out = hdspm->port_names_out_qs;
1537 /* mainly for init to 0 on load */
1538 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1543 if (sgain > UNITY_GAIN)
1550 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1551 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1552 hdspm_write_in_gain(hdspm, i, j, gain);
1553 hdspm_write_pb_gain(hdspm, i, j, gain);
1557 /*----------------------------------------------------------------------------
1559 ----------------------------------------------------------------------------*/
1561 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1564 /* the hardware already does the relevant bit-mask with 0xff */
1565 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1568 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1571 /* the hardware already does the relevant bit-mask with 0xff */
1572 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1575 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1577 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1580 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1582 int fifo_bytes_used;
1584 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1586 if (fifo_bytes_used < 128)
1587 return 128 - fifo_bytes_used;
1592 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1594 while (snd_hdspm_midi_input_available (hdspm, id))
1595 snd_hdspm_midi_read_byte (hdspm, id);
1598 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1600 unsigned long flags;
1604 unsigned char buf[128];
1606 /* Output is not interrupt driven */
1608 spin_lock_irqsave (&hmidi->lock, flags);
1609 if (hmidi->output &&
1610 !snd_rawmidi_transmit_empty (hmidi->output)) {
1611 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1613 if (n_pending > 0) {
1614 if (n_pending > (int)sizeof (buf))
1615 n_pending = sizeof (buf);
1617 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1620 for (i = 0; i < to_write; ++i)
1621 snd_hdspm_midi_write_byte (hmidi->hdspm,
1627 spin_unlock_irqrestore (&hmidi->lock, flags);
1631 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1633 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1636 unsigned long flags;
1640 spin_lock_irqsave (&hmidi->lock, flags);
1641 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1642 if (n_pending > 0) {
1644 if (n_pending > (int)sizeof (buf))
1645 n_pending = sizeof (buf);
1646 for (i = 0; i < n_pending; ++i)
1647 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1650 snd_rawmidi_receive (hmidi->input, buf,
1653 /* flush the MIDI input FIFO */
1655 snd_hdspm_midi_read_byte (hmidi->hdspm,
1660 spin_unlock_irqrestore(&hmidi->lock, flags);
1662 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1663 hmidi->hdspm->control_register |= hmidi->ie;
1664 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1665 hmidi->hdspm->control_register);
1666 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1668 return snd_hdspm_midi_output_write (hmidi);
1672 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1674 struct hdspm *hdspm;
1675 struct hdspm_midi *hmidi;
1676 unsigned long flags;
1678 hmidi = substream->rmidi->private_data;
1679 hdspm = hmidi->hdspm;
1681 spin_lock_irqsave (&hdspm->lock, flags);
1683 if (!(hdspm->control_register & hmidi->ie)) {
1684 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1685 hdspm->control_register |= hmidi->ie;
1688 hdspm->control_register &= ~hmidi->ie;
1691 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1692 spin_unlock_irqrestore (&hdspm->lock, flags);
1695 static void snd_hdspm_midi_output_timer(unsigned long data)
1697 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1698 unsigned long flags;
1700 snd_hdspm_midi_output_write(hmidi);
1701 spin_lock_irqsave (&hmidi->lock, flags);
1703 /* this does not bump hmidi->istimer, because the
1704 kernel automatically removed the timer when it
1705 expired, and we are now adding it back, thus
1706 leaving istimer wherever it was set before.
1709 if (hmidi->istimer) {
1710 hmidi->timer.expires = 1 + jiffies;
1711 add_timer(&hmidi->timer);
1714 spin_unlock_irqrestore (&hmidi->lock, flags);
1718 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1720 struct hdspm_midi *hmidi;
1721 unsigned long flags;
1723 hmidi = substream->rmidi->private_data;
1724 spin_lock_irqsave (&hmidi->lock, flags);
1726 if (!hmidi->istimer) {
1727 init_timer(&hmidi->timer);
1728 hmidi->timer.function = snd_hdspm_midi_output_timer;
1729 hmidi->timer.data = (unsigned long) hmidi;
1730 hmidi->timer.expires = 1 + jiffies;
1731 add_timer(&hmidi->timer);
1735 if (hmidi->istimer && --hmidi->istimer <= 0)
1736 del_timer (&hmidi->timer);
1738 spin_unlock_irqrestore (&hmidi->lock, flags);
1740 snd_hdspm_midi_output_write(hmidi);
1743 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1745 struct hdspm_midi *hmidi;
1747 hmidi = substream->rmidi->private_data;
1748 spin_lock_irq (&hmidi->lock);
1749 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1750 hmidi->input = substream;
1751 spin_unlock_irq (&hmidi->lock);
1756 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1758 struct hdspm_midi *hmidi;
1760 hmidi = substream->rmidi->private_data;
1761 spin_lock_irq (&hmidi->lock);
1762 hmidi->output = substream;
1763 spin_unlock_irq (&hmidi->lock);
1768 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1770 struct hdspm_midi *hmidi;
1772 snd_hdspm_midi_input_trigger (substream, 0);
1774 hmidi = substream->rmidi->private_data;
1775 spin_lock_irq (&hmidi->lock);
1776 hmidi->input = NULL;
1777 spin_unlock_irq (&hmidi->lock);
1782 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1784 struct hdspm_midi *hmidi;
1786 snd_hdspm_midi_output_trigger (substream, 0);
1788 hmidi = substream->rmidi->private_data;
1789 spin_lock_irq (&hmidi->lock);
1790 hmidi->output = NULL;
1791 spin_unlock_irq (&hmidi->lock);
1796 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1798 .open = snd_hdspm_midi_output_open,
1799 .close = snd_hdspm_midi_output_close,
1800 .trigger = snd_hdspm_midi_output_trigger,
1803 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1805 .open = snd_hdspm_midi_input_open,
1806 .close = snd_hdspm_midi_input_close,
1807 .trigger = snd_hdspm_midi_input_trigger,
1810 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1811 struct hdspm *hdspm, int id)
1816 hdspm->midi[id].id = id;
1817 hdspm->midi[id].hdspm = hdspm;
1818 spin_lock_init (&hdspm->midi[id].lock);
1821 if (MADIface == hdspm->io_type) {
1822 /* MIDI-over-MADI on HDSPe MADIface */
1823 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1824 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1825 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1826 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1827 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1828 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1830 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1831 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1832 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1833 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1834 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1835 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1837 } else if (1 == id) {
1838 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1839 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1840 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1841 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1842 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1843 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1844 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1845 /* MIDI-over-MADI on HDSPe MADI */
1846 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1847 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1848 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1849 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1850 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1851 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1852 } else if (2 == id) {
1853 /* TCO MTC, read only */
1854 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1855 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1856 hdspm->midi[2].dataOut = -1;
1857 hdspm->midi[2].statusOut = -1;
1858 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1859 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1860 } else if (3 == id) {
1861 /* TCO MTC on HDSPe MADI */
1862 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1863 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1864 hdspm->midi[3].dataOut = -1;
1865 hdspm->midi[3].statusOut = -1;
1866 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1867 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1870 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1871 (MADIface == hdspm->io_type)))) {
1872 if ((id == 0) && (MADIface == hdspm->io_type)) {
1873 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1874 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1875 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1877 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1879 err = snd_rawmidi_new(card, buf, id, 1, 1,
1880 &hdspm->midi[id].rmidi);
1884 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1886 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1888 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1889 SNDRV_RAWMIDI_STREAM_OUTPUT,
1890 &snd_hdspm_midi_output);
1891 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1892 SNDRV_RAWMIDI_STREAM_INPUT,
1893 &snd_hdspm_midi_input);
1895 hdspm->midi[id].rmidi->info_flags |=
1896 SNDRV_RAWMIDI_INFO_OUTPUT |
1897 SNDRV_RAWMIDI_INFO_INPUT |
1898 SNDRV_RAWMIDI_INFO_DUPLEX;
1900 /* TCO MTC, read only */
1901 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1902 err = snd_rawmidi_new(card, buf, id, 1, 1,
1903 &hdspm->midi[id].rmidi);
1907 sprintf(hdspm->midi[id].rmidi->name,
1908 "%s MTC %d", card->id, id+1);
1909 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1911 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1912 SNDRV_RAWMIDI_STREAM_INPUT,
1913 &snd_hdspm_midi_input);
1915 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1922 static void hdspm_midi_tasklet(unsigned long arg)
1924 struct hdspm *hdspm = (struct hdspm *)arg;
1927 while (i < hdspm->midiPorts) {
1928 if (hdspm->midi[i].pending)
1929 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1936 /*-----------------------------------------------------------------------------
1938 ----------------------------------------------------------------------------*/
1940 /* get the system sample rate which is set */
1944 * Calculate the real sample rate from the
1945 * current DDS value.
1947 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1949 unsigned int period, rate;
1951 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1952 rate = hdspm_calc_dds_value(hdspm, period);
1958 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1959 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1962 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1963 .info = snd_hdspm_info_system_sample_rate, \
1964 .get = snd_hdspm_get_system_sample_rate \
1967 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1968 struct snd_ctl_elem_info *uinfo)
1970 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1972 uinfo->value.integer.min = 27000;
1973 uinfo->value.integer.max = 207000;
1974 uinfo->value.integer.step = 1;
1979 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *
1983 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1985 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1991 * Returns the WordClock sample rate class for the given card.
1993 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1997 switch (hdspm->io_type) {
2000 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2001 return (status >> 16) & 0xF;
2013 * Returns the TCO sample rate class for the given card.
2015 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2020 switch (hdspm->io_type) {
2023 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2024 return (status >> 20) & 0xF;
2036 * Returns the SYNC_IN sample rate class for the given card.
2038 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2043 switch (hdspm->io_type) {
2046 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2047 return (status >> 12) & 0xF;
2059 * Returns the sample rate class for input source <idx> for
2060 * 'new style' cards like the AIO and RayDAT.
2062 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2064 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2066 return (status >> (idx*4)) & 0xF;
2071 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2072 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2074 .private_value = xindex, \
2075 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2076 .info = snd_hdspm_info_autosync_sample_rate, \
2077 .get = snd_hdspm_get_autosync_sample_rate \
2081 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2082 struct snd_ctl_elem_info *uinfo)
2084 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2086 uinfo->value.enumerated.items = 10;
2088 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2089 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2090 strcpy(uinfo->value.enumerated.name,
2091 texts_freq[uinfo->value.enumerated.item]);
2096 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *
2100 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2102 switch (hdspm->io_type) {
2104 switch (kcontrol->private_value) {
2106 ucontrol->value.enumerated.item[0] =
2107 hdspm_get_wc_sample_rate(hdspm);
2110 ucontrol->value.enumerated.item[0] =
2111 hdspm_get_tco_sample_rate(hdspm);
2114 ucontrol->value.enumerated.item[0] =
2115 hdspm_get_sync_in_sample_rate(hdspm);
2118 ucontrol->value.enumerated.item[0] =
2119 hdspm_get_s1_sample_rate(hdspm,
2120 kcontrol->private_value-1);
2124 switch (kcontrol->private_value) {
2126 ucontrol->value.enumerated.item[0] =
2127 hdspm_get_wc_sample_rate(hdspm);
2130 ucontrol->value.enumerated.item[0] =
2131 hdspm_get_tco_sample_rate(hdspm);
2133 case 5: /* SYNC_IN */
2134 ucontrol->value.enumerated.item[0] =
2135 hdspm_get_sync_in_sample_rate(hdspm);
2138 ucontrol->value.enumerated.item[0] =
2139 hdspm_get_s1_sample_rate(hdspm,
2140 ucontrol->id.index-1);
2145 switch (kcontrol->private_value) {
2147 ucontrol->value.enumerated.item[0] =
2148 hdspm_get_wc_sample_rate(hdspm);
2151 ucontrol->value.enumerated.item[0] =
2152 hdspm_get_tco_sample_rate(hdspm);
2154 case 10: /* SYNC_IN */
2155 ucontrol->value.enumerated.item[0] =
2156 hdspm_get_sync_in_sample_rate(hdspm);
2158 default: /* AES1 to AES8 */
2159 ucontrol->value.enumerated.item[0] =
2160 hdspm_get_s1_sample_rate(hdspm,
2161 kcontrol->private_value-1);
2173 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2174 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2177 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2178 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2179 .info = snd_hdspm_info_system_clock_mode, \
2180 .get = snd_hdspm_get_system_clock_mode, \
2181 .put = snd_hdspm_put_system_clock_mode, \
2186 * Returns the system clock mode for the given card.
2187 * @returns 0 - master, 1 - slave
2189 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2191 switch (hdspm->io_type) {
2194 if (hdspm->settings_register & HDSPM_c0Master)
2199 if (hdspm->control_register & HDSPM_ClockModeMaster)
2208 * Sets the system clock mode.
2209 * @param mode 0 - master, 1 - slave
2211 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2213 switch (hdspm->io_type) {
2217 hdspm->settings_register |= HDSPM_c0Master;
2219 hdspm->settings_register &= ~HDSPM_c0Master;
2221 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2226 hdspm->control_register |= HDSPM_ClockModeMaster;
2228 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2230 hdspm_write(hdspm, HDSPM_controlRegister,
2231 hdspm->control_register);
2236 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2237 struct snd_ctl_elem_info *uinfo)
2239 static char *texts[] = { "Master", "AutoSync" };
2241 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2243 uinfo->value.enumerated.items = 2;
2244 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2245 uinfo->value.enumerated.item =
2246 uinfo->value.enumerated.items - 1;
2247 strcpy(uinfo->value.enumerated.name,
2248 texts[uinfo->value.enumerated.item]);
2252 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2253 struct snd_ctl_elem_value *ucontrol)
2255 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2257 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2261 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_value *ucontrol)
2264 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2267 if (!snd_hdspm_use_is_exclusive(hdspm))
2270 val = ucontrol->value.enumerated.item[0];
2276 hdspm_set_system_clock_mode(hdspm, val);
2282 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2283 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2286 .info = snd_hdspm_info_clock_source, \
2287 .get = snd_hdspm_get_clock_source, \
2288 .put = snd_hdspm_put_clock_source \
2292 static int hdspm_clock_source(struct hdspm * hdspm)
2294 switch (hdspm->system_sample_rate) {
2295 case 32000: return 0;
2296 case 44100: return 1;
2297 case 48000: return 2;
2298 case 64000: return 3;
2299 case 88200: return 4;
2300 case 96000: return 5;
2301 case 128000: return 6;
2302 case 176400: return 7;
2303 case 192000: return 8;
2309 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2314 rate = 32000; break;
2316 rate = 44100; break;
2318 rate = 48000; break;
2320 rate = 64000; break;
2322 rate = 88200; break;
2324 rate = 96000; break;
2326 rate = 128000; break;
2328 rate = 176400; break;
2330 rate = 192000; break;
2334 hdspm_set_rate(hdspm, rate, 1);
2338 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2339 struct snd_ctl_elem_info *uinfo)
2341 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2343 uinfo->value.enumerated.items = 9;
2345 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2346 uinfo->value.enumerated.item =
2347 uinfo->value.enumerated.items - 1;
2349 strcpy(uinfo->value.enumerated.name,
2350 texts_freq[uinfo->value.enumerated.item+1]);
2355 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2356 struct snd_ctl_elem_value *ucontrol)
2358 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2360 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2364 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2365 struct snd_ctl_elem_value *ucontrol)
2367 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2371 if (!snd_hdspm_use_is_exclusive(hdspm))
2373 val = ucontrol->value.enumerated.item[0];
2378 spin_lock_irq(&hdspm->lock);
2379 if (val != hdspm_clock_source(hdspm))
2380 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2383 spin_unlock_irq(&hdspm->lock);
2388 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2389 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2392 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2393 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2394 .info = snd_hdspm_info_pref_sync_ref, \
2395 .get = snd_hdspm_get_pref_sync_ref, \
2396 .put = snd_hdspm_put_pref_sync_ref \
2401 * Returns the current preferred sync reference setting.
2402 * The semantics of the return value are depending on the
2403 * card, please see the comments for clarification.
2405 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2407 switch (hdspm->io_type) {
2409 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2410 case 0: return 0; /* WC */
2411 case HDSPM_SyncRef0: return 1; /* AES 1 */
2412 case HDSPM_SyncRef1: return 2; /* AES 2 */
2413 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2414 case HDSPM_SyncRef2: return 4; /* AES 4 */
2415 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2416 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2417 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2418 return 7; /* AES 7 */
2419 case HDSPM_SyncRef3: return 8; /* AES 8 */
2420 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2427 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2428 case 0: return 0; /* WC */
2429 case HDSPM_SyncRef0: return 1; /* MADI */
2430 case HDSPM_SyncRef1: return 2; /* TCO */
2431 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2432 return 3; /* SYNC_IN */
2435 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2436 case 0: return 0; /* WC */
2437 case HDSPM_SyncRef0: return 1; /* MADI */
2438 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2439 return 2; /* SYNC_IN */
2446 switch ((hdspm->settings_register &
2447 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2448 case 0: return 0; /* WC */
2449 case 3: return 1; /* ADAT 1 */
2450 case 4: return 2; /* ADAT 2 */
2451 case 5: return 3; /* ADAT 3 */
2452 case 6: return 4; /* ADAT 4 */
2453 case 1: return 5; /* AES */
2454 case 2: return 6; /* SPDIF */
2455 case 9: return 7; /* TCO */
2456 case 10: return 8; /* SYNC_IN */
2459 switch ((hdspm->settings_register &
2460 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2461 case 0: return 0; /* WC */
2462 case 3: return 1; /* ADAT 1 */
2463 case 4: return 2; /* ADAT 2 */
2464 case 5: return 3; /* ADAT 3 */
2465 case 6: return 4; /* ADAT 4 */
2466 case 1: return 5; /* AES */
2467 case 2: return 6; /* SPDIF */
2468 case 10: return 7; /* SYNC_IN */
2476 switch ((hdspm->settings_register &
2477 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2478 case 0: return 0; /* WC */
2479 case 3: return 1; /* ADAT */
2480 case 1: return 2; /* AES */
2481 case 2: return 3; /* SPDIF */
2482 case 9: return 4; /* TCO */
2483 case 10: return 5; /* SYNC_IN */
2486 switch ((hdspm->settings_register &
2487 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2488 case 0: return 0; /* WC */
2489 case 3: return 1; /* ADAT */
2490 case 1: return 2; /* AES */
2491 case 2: return 3; /* SPDIF */
2492 case 10: return 4; /* SYNC_IN */
2504 * Set the preferred sync reference to <pref>. The semantics
2505 * of <pref> are depending on the card type, see the comments
2506 * for clarification.
2508 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2512 switch (hdspm->io_type) {
2514 hdspm->control_register &= ~HDSPM_SyncRefMask;
2519 hdspm->control_register |= HDSPM_SyncRef0;
2522 hdspm->control_register |= HDSPM_SyncRef1;
2525 hdspm->control_register |=
2526 HDSPM_SyncRef1+HDSPM_SyncRef0;
2529 hdspm->control_register |= HDSPM_SyncRef2;
2532 hdspm->control_register |=
2533 HDSPM_SyncRef2+HDSPM_SyncRef0;
2536 hdspm->control_register |=
2537 HDSPM_SyncRef2+HDSPM_SyncRef1;
2540 hdspm->control_register |=
2541 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2544 hdspm->control_register |= HDSPM_SyncRef3;
2547 hdspm->control_register |=
2548 HDSPM_SyncRef3+HDSPM_SyncRef0;
2558 hdspm->control_register &= ~HDSPM_SyncRefMask;
2564 hdspm->control_register |= HDSPM_SyncRef0;
2567 hdspm->control_register |= HDSPM_SyncRef1;
2569 case 3: /* SYNC_IN */
2570 hdspm->control_register |=
2571 HDSPM_SyncRef0+HDSPM_SyncRef1;
2581 hdspm->control_register |= HDSPM_SyncRef0;
2583 case 2: /* SYNC_IN */
2584 hdspm->control_register |=
2585 HDSPM_SyncRef0+HDSPM_SyncRef1;
2597 case 0: p = 0; break; /* WC */
2598 case 1: p = 3; break; /* ADAT 1 */
2599 case 2: p = 4; break; /* ADAT 2 */
2600 case 3: p = 5; break; /* ADAT 3 */
2601 case 4: p = 6; break; /* ADAT 4 */
2602 case 5: p = 1; break; /* AES */
2603 case 6: p = 2; break; /* SPDIF */
2604 case 7: p = 9; break; /* TCO */
2605 case 8: p = 10; break; /* SYNC_IN */
2610 case 0: p = 0; break; /* WC */
2611 case 1: p = 3; break; /* ADAT 1 */
2612 case 2: p = 4; break; /* ADAT 2 */
2613 case 3: p = 5; break; /* ADAT 3 */
2614 case 4: p = 6; break; /* ADAT 4 */
2615 case 5: p = 1; break; /* AES */
2616 case 6: p = 2; break; /* SPDIF */
2617 case 7: p = 10; break; /* SYNC_IN */
2626 case 0: p = 0; break; /* WC */
2627 case 1: p = 3; break; /* ADAT */
2628 case 2: p = 1; break; /* AES */
2629 case 3: p = 2; break; /* SPDIF */
2630 case 4: p = 9; break; /* TCO */
2631 case 5: p = 10; break; /* SYNC_IN */
2636 case 0: p = 0; break; /* WC */
2637 case 1: p = 3; break; /* ADAT */
2638 case 2: p = 1; break; /* AES */
2639 case 3: p = 2; break; /* SPDIF */
2640 case 4: p = 10; break; /* SYNC_IN */
2647 switch (hdspm->io_type) {
2650 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2651 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2652 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2658 hdspm_write(hdspm, HDSPM_controlRegister,
2659 hdspm->control_register);
2666 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2667 struct snd_ctl_elem_info *uinfo)
2669 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2671 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2673 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2675 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2676 uinfo->value.enumerated.item =
2677 uinfo->value.enumerated.items - 1;
2679 strcpy(uinfo->value.enumerated.name,
2680 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2685 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2686 struct snd_ctl_elem_value *ucontrol)
2688 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2689 int psf = hdspm_pref_sync_ref(hdspm);
2692 ucontrol->value.enumerated.item[0] = psf;
2699 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2700 struct snd_ctl_elem_value *ucontrol)
2702 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2703 int val, change = 0;
2705 if (!snd_hdspm_use_is_exclusive(hdspm))
2708 val = ucontrol->value.enumerated.item[0];
2712 else if (val >= hdspm->texts_autosync_items)
2713 val = hdspm->texts_autosync_items-1;
2715 spin_lock_irq(&hdspm->lock);
2716 if (val != hdspm_pref_sync_ref(hdspm))
2717 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2719 spin_unlock_irq(&hdspm->lock);
2724 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2725 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2728 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2729 .info = snd_hdspm_info_autosync_ref, \
2730 .get = snd_hdspm_get_autosync_ref, \
2733 static int hdspm_autosync_ref(struct hdspm *hdspm)
2735 if (AES32 == hdspm->io_type) {
2736 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2737 unsigned int syncref =
2738 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2740 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2743 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2744 } else if (MADI == hdspm->io_type) {
2745 /* This looks at the autosync selected sync reference */
2746 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2748 switch (status2 & HDSPM_SelSyncRefMask) {
2749 case HDSPM_SelSyncRef_WORD:
2750 return HDSPM_AUTOSYNC_FROM_WORD;
2751 case HDSPM_SelSyncRef_MADI:
2752 return HDSPM_AUTOSYNC_FROM_MADI;
2753 case HDSPM_SelSyncRef_TCO:
2754 return HDSPM_AUTOSYNC_FROM_TCO;
2755 case HDSPM_SelSyncRef_SyncIn:
2756 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2757 case HDSPM_SelSyncRef_NVALID:
2758 return HDSPM_AUTOSYNC_FROM_NONE;
2768 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2769 struct snd_ctl_elem_info *uinfo)
2771 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2773 if (AES32 == hdspm->io_type) {
2774 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2775 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2777 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2779 uinfo->value.enumerated.items = 10;
2780 if (uinfo->value.enumerated.item >=
2781 uinfo->value.enumerated.items)
2782 uinfo->value.enumerated.item =
2783 uinfo->value.enumerated.items - 1;
2784 strcpy(uinfo->value.enumerated.name,
2785 texts[uinfo->value.enumerated.item]);
2786 } else if (MADI == hdspm->io_type) {
2787 static char *texts[] = {"Word Clock", "MADI", "TCO",
2788 "Sync In", "None" };
2790 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2792 uinfo->value.enumerated.items = 5;
2793 if (uinfo->value.enumerated.item >=
2794 uinfo->value.enumerated.items)
2795 uinfo->value.enumerated.item =
2796 uinfo->value.enumerated.items - 1;
2797 strcpy(uinfo->value.enumerated.name,
2798 texts[uinfo->value.enumerated.item]);
2803 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2804 struct snd_ctl_elem_value *ucontrol)
2806 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2808 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2813 #define HDSPM_LINE_OUT(xname, xindex) \
2814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2817 .info = snd_hdspm_info_line_out, \
2818 .get = snd_hdspm_get_line_out, \
2819 .put = snd_hdspm_put_line_out \
2822 static int hdspm_line_out(struct hdspm * hdspm)
2824 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2828 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2831 hdspm->control_register |= HDSPM_LineOut;
2833 hdspm->control_register &= ~HDSPM_LineOut;
2834 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2839 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2841 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2842 struct snd_ctl_elem_value *ucontrol)
2844 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2846 spin_lock_irq(&hdspm->lock);
2847 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2848 spin_unlock_irq(&hdspm->lock);
2852 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2853 struct snd_ctl_elem_value *ucontrol)
2855 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2859 if (!snd_hdspm_use_is_exclusive(hdspm))
2861 val = ucontrol->value.integer.value[0] & 1;
2862 spin_lock_irq(&hdspm->lock);
2863 change = (int) val != hdspm_line_out(hdspm);
2864 hdspm_set_line_output(hdspm, val);
2865 spin_unlock_irq(&hdspm->lock);
2870 #define HDSPM_TX_64(xname, xindex) \
2871 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2874 .info = snd_hdspm_info_tx_64, \
2875 .get = snd_hdspm_get_tx_64, \
2876 .put = snd_hdspm_put_tx_64 \
2879 static int hdspm_tx_64(struct hdspm * hdspm)
2881 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2884 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2887 hdspm->control_register |= HDSPM_TX_64ch;
2889 hdspm->control_register &= ~HDSPM_TX_64ch;
2890 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2895 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2897 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2898 struct snd_ctl_elem_value *ucontrol)
2900 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2902 spin_lock_irq(&hdspm->lock);
2903 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2904 spin_unlock_irq(&hdspm->lock);
2908 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2909 struct snd_ctl_elem_value *ucontrol)
2911 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2915 if (!snd_hdspm_use_is_exclusive(hdspm))
2917 val = ucontrol->value.integer.value[0] & 1;
2918 spin_lock_irq(&hdspm->lock);
2919 change = (int) val != hdspm_tx_64(hdspm);
2920 hdspm_set_tx_64(hdspm, val);
2921 spin_unlock_irq(&hdspm->lock);
2926 #define HDSPM_C_TMS(xname, xindex) \
2927 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2930 .info = snd_hdspm_info_c_tms, \
2931 .get = snd_hdspm_get_c_tms, \
2932 .put = snd_hdspm_put_c_tms \
2935 static int hdspm_c_tms(struct hdspm * hdspm)
2937 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2940 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2943 hdspm->control_register |= HDSPM_clr_tms;
2945 hdspm->control_register &= ~HDSPM_clr_tms;
2946 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2951 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2953 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2954 struct snd_ctl_elem_value *ucontrol)
2956 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2958 spin_lock_irq(&hdspm->lock);
2959 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2960 spin_unlock_irq(&hdspm->lock);
2964 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2965 struct snd_ctl_elem_value *ucontrol)
2967 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2971 if (!snd_hdspm_use_is_exclusive(hdspm))
2973 val = ucontrol->value.integer.value[0] & 1;
2974 spin_lock_irq(&hdspm->lock);
2975 change = (int) val != hdspm_c_tms(hdspm);
2976 hdspm_set_c_tms(hdspm, val);
2977 spin_unlock_irq(&hdspm->lock);
2982 #define HDSPM_SAFE_MODE(xname, xindex) \
2983 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2986 .info = snd_hdspm_info_safe_mode, \
2987 .get = snd_hdspm_get_safe_mode, \
2988 .put = snd_hdspm_put_safe_mode \
2991 static int hdspm_safe_mode(struct hdspm * hdspm)
2993 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2996 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2999 hdspm->control_register |= HDSPM_AutoInp;
3001 hdspm->control_register &= ~HDSPM_AutoInp;
3002 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3007 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3009 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3010 struct snd_ctl_elem_value *ucontrol)
3012 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3014 spin_lock_irq(&hdspm->lock);
3015 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3016 spin_unlock_irq(&hdspm->lock);
3020 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3021 struct snd_ctl_elem_value *ucontrol)
3023 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3027 if (!snd_hdspm_use_is_exclusive(hdspm))
3029 val = ucontrol->value.integer.value[0] & 1;
3030 spin_lock_irq(&hdspm->lock);
3031 change = (int) val != hdspm_safe_mode(hdspm);
3032 hdspm_set_safe_mode(hdspm, val);
3033 spin_unlock_irq(&hdspm->lock);
3038 #define HDSPM_EMPHASIS(xname, xindex) \
3039 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3042 .info = snd_hdspm_info_emphasis, \
3043 .get = snd_hdspm_get_emphasis, \
3044 .put = snd_hdspm_put_emphasis \
3047 static int hdspm_emphasis(struct hdspm * hdspm)
3049 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3052 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3055 hdspm->control_register |= HDSPM_Emphasis;
3057 hdspm->control_register &= ~HDSPM_Emphasis;
3058 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3063 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3065 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3066 struct snd_ctl_elem_value *ucontrol)
3068 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3070 spin_lock_irq(&hdspm->lock);
3071 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3072 spin_unlock_irq(&hdspm->lock);
3076 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3077 struct snd_ctl_elem_value *ucontrol)
3079 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3083 if (!snd_hdspm_use_is_exclusive(hdspm))
3085 val = ucontrol->value.integer.value[0] & 1;
3086 spin_lock_irq(&hdspm->lock);
3087 change = (int) val != hdspm_emphasis(hdspm);
3088 hdspm_set_emphasis(hdspm, val);
3089 spin_unlock_irq(&hdspm->lock);
3094 #define HDSPM_DOLBY(xname, xindex) \
3095 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3098 .info = snd_hdspm_info_dolby, \
3099 .get = snd_hdspm_get_dolby, \
3100 .put = snd_hdspm_put_dolby \
3103 static int hdspm_dolby(struct hdspm * hdspm)
3105 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3108 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3111 hdspm->control_register |= HDSPM_Dolby;
3113 hdspm->control_register &= ~HDSPM_Dolby;
3114 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3119 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3121 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3122 struct snd_ctl_elem_value *ucontrol)
3124 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3126 spin_lock_irq(&hdspm->lock);
3127 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3128 spin_unlock_irq(&hdspm->lock);
3132 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3133 struct snd_ctl_elem_value *ucontrol)
3135 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3139 if (!snd_hdspm_use_is_exclusive(hdspm))
3141 val = ucontrol->value.integer.value[0] & 1;
3142 spin_lock_irq(&hdspm->lock);
3143 change = (int) val != hdspm_dolby(hdspm);
3144 hdspm_set_dolby(hdspm, val);
3145 spin_unlock_irq(&hdspm->lock);
3150 #define HDSPM_PROFESSIONAL(xname, xindex) \
3151 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3154 .info = snd_hdspm_info_professional, \
3155 .get = snd_hdspm_get_professional, \
3156 .put = snd_hdspm_put_professional \
3159 static int hdspm_professional(struct hdspm * hdspm)
3161 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3164 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3167 hdspm->control_register |= HDSPM_Professional;
3169 hdspm->control_register &= ~HDSPM_Professional;
3170 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3175 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3177 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3178 struct snd_ctl_elem_value *ucontrol)
3180 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3182 spin_lock_irq(&hdspm->lock);
3183 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3184 spin_unlock_irq(&hdspm->lock);
3188 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3189 struct snd_ctl_elem_value *ucontrol)
3191 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3195 if (!snd_hdspm_use_is_exclusive(hdspm))
3197 val = ucontrol->value.integer.value[0] & 1;
3198 spin_lock_irq(&hdspm->lock);
3199 change = (int) val != hdspm_professional(hdspm);
3200 hdspm_set_professional(hdspm, val);
3201 spin_unlock_irq(&hdspm->lock);
3205 #define HDSPM_INPUT_SELECT(xname, xindex) \
3206 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3209 .info = snd_hdspm_info_input_select, \
3210 .get = snd_hdspm_get_input_select, \
3211 .put = snd_hdspm_put_input_select \
3214 static int hdspm_input_select(struct hdspm * hdspm)
3216 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3219 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3222 hdspm->control_register |= HDSPM_InputSelect0;
3224 hdspm->control_register &= ~HDSPM_InputSelect0;
3225 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3230 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3231 struct snd_ctl_elem_info *uinfo)
3233 static char *texts[] = { "optical", "coaxial" };
3235 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3237 uinfo->value.enumerated.items = 2;
3239 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3240 uinfo->value.enumerated.item =
3241 uinfo->value.enumerated.items - 1;
3242 strcpy(uinfo->value.enumerated.name,
3243 texts[uinfo->value.enumerated.item]);
3248 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3249 struct snd_ctl_elem_value *ucontrol)
3251 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3253 spin_lock_irq(&hdspm->lock);
3254 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3255 spin_unlock_irq(&hdspm->lock);
3259 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3260 struct snd_ctl_elem_value *ucontrol)
3262 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3266 if (!snd_hdspm_use_is_exclusive(hdspm))
3268 val = ucontrol->value.integer.value[0] & 1;
3269 spin_lock_irq(&hdspm->lock);
3270 change = (int) val != hdspm_input_select(hdspm);
3271 hdspm_set_input_select(hdspm, val);
3272 spin_unlock_irq(&hdspm->lock);
3277 #define HDSPM_DS_WIRE(xname, xindex) \
3278 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3281 .info = snd_hdspm_info_ds_wire, \
3282 .get = snd_hdspm_get_ds_wire, \
3283 .put = snd_hdspm_put_ds_wire \
3286 static int hdspm_ds_wire(struct hdspm * hdspm)
3288 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3291 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3294 hdspm->control_register |= HDSPM_DS_DoubleWire;
3296 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3297 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3302 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3303 struct snd_ctl_elem_info *uinfo)
3305 static char *texts[] = { "Single", "Double" };
3307 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3309 uinfo->value.enumerated.items = 2;
3311 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3312 uinfo->value.enumerated.item =
3313 uinfo->value.enumerated.items - 1;
3314 strcpy(uinfo->value.enumerated.name,
3315 texts[uinfo->value.enumerated.item]);
3320 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3321 struct snd_ctl_elem_value *ucontrol)
3323 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3325 spin_lock_irq(&hdspm->lock);
3326 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3327 spin_unlock_irq(&hdspm->lock);
3331 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3332 struct snd_ctl_elem_value *ucontrol)
3334 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3338 if (!snd_hdspm_use_is_exclusive(hdspm))
3340 val = ucontrol->value.integer.value[0] & 1;
3341 spin_lock_irq(&hdspm->lock);
3342 change = (int) val != hdspm_ds_wire(hdspm);
3343 hdspm_set_ds_wire(hdspm, val);
3344 spin_unlock_irq(&hdspm->lock);
3349 #define HDSPM_QS_WIRE(xname, xindex) \
3350 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3353 .info = snd_hdspm_info_qs_wire, \
3354 .get = snd_hdspm_get_qs_wire, \
3355 .put = snd_hdspm_put_qs_wire \
3358 static int hdspm_qs_wire(struct hdspm * hdspm)
3360 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3362 if (hdspm->control_register & HDSPM_QS_QuadWire)
3367 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3369 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3374 hdspm->control_register |= HDSPM_QS_DoubleWire;
3377 hdspm->control_register |= HDSPM_QS_QuadWire;
3380 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3385 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3386 struct snd_ctl_elem_info *uinfo)
3388 static char *texts[] = { "Single", "Double", "Quad" };
3390 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3392 uinfo->value.enumerated.items = 3;
3394 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3395 uinfo->value.enumerated.item =
3396 uinfo->value.enumerated.items - 1;
3397 strcpy(uinfo->value.enumerated.name,
3398 texts[uinfo->value.enumerated.item]);
3403 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3404 struct snd_ctl_elem_value *ucontrol)
3406 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3408 spin_lock_irq(&hdspm->lock);
3409 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3410 spin_unlock_irq(&hdspm->lock);
3414 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3415 struct snd_ctl_elem_value *ucontrol)
3417 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3421 if (!snd_hdspm_use_is_exclusive(hdspm))
3423 val = ucontrol->value.integer.value[0];
3428 spin_lock_irq(&hdspm->lock);
3429 change = val != hdspm_qs_wire(hdspm);
3430 hdspm_set_qs_wire(hdspm, val);
3431 spin_unlock_irq(&hdspm->lock);
3435 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3436 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3439 .info = snd_hdspm_info_madi_speedmode, \
3440 .get = snd_hdspm_get_madi_speedmode, \
3441 .put = snd_hdspm_put_madi_speedmode \
3444 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3446 if (hdspm->control_register & HDSPM_QuadSpeed)
3448 if (hdspm->control_register & HDSPM_DoubleSpeed)
3453 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3455 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3460 hdspm->control_register |= HDSPM_DoubleSpeed;
3463 hdspm->control_register |= HDSPM_QuadSpeed;
3466 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3471 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3472 struct snd_ctl_elem_info *uinfo)
3474 static char *texts[] = { "Single", "Double", "Quad" };
3476 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3478 uinfo->value.enumerated.items = 3;
3480 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3481 uinfo->value.enumerated.item =
3482 uinfo->value.enumerated.items - 1;
3483 strcpy(uinfo->value.enumerated.name,
3484 texts[uinfo->value.enumerated.item]);
3489 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3490 struct snd_ctl_elem_value *ucontrol)
3492 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3494 spin_lock_irq(&hdspm->lock);
3495 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3496 spin_unlock_irq(&hdspm->lock);
3500 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3501 struct snd_ctl_elem_value *ucontrol)
3503 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3507 if (!snd_hdspm_use_is_exclusive(hdspm))
3509 val = ucontrol->value.integer.value[0];
3514 spin_lock_irq(&hdspm->lock);
3515 change = val != hdspm_madi_speedmode(hdspm);
3516 hdspm_set_madi_speedmode(hdspm, val);
3517 spin_unlock_irq(&hdspm->lock);
3521 #define HDSPM_MIXER(xname, xindex) \
3522 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3526 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3527 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3528 .info = snd_hdspm_info_mixer, \
3529 .get = snd_hdspm_get_mixer, \
3530 .put = snd_hdspm_put_mixer \
3533 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3534 struct snd_ctl_elem_info *uinfo)
3536 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3538 uinfo->value.integer.min = 0;
3539 uinfo->value.integer.max = 65535;
3540 uinfo->value.integer.step = 1;
3544 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3545 struct snd_ctl_elem_value *ucontrol)
3547 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3551 source = ucontrol->value.integer.value[0];
3554 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3555 source = 2 * HDSPM_MAX_CHANNELS - 1;
3557 destination = ucontrol->value.integer.value[1];
3558 if (destination < 0)
3560 else if (destination >= HDSPM_MAX_CHANNELS)
3561 destination = HDSPM_MAX_CHANNELS - 1;
3563 spin_lock_irq(&hdspm->lock);
3564 if (source >= HDSPM_MAX_CHANNELS)
3565 ucontrol->value.integer.value[2] =
3566 hdspm_read_pb_gain(hdspm, destination,
3567 source - HDSPM_MAX_CHANNELS);
3569 ucontrol->value.integer.value[2] =
3570 hdspm_read_in_gain(hdspm, destination, source);
3572 spin_unlock_irq(&hdspm->lock);
3577 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3578 struct snd_ctl_elem_value *ucontrol)
3580 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3586 if (!snd_hdspm_use_is_exclusive(hdspm))
3589 source = ucontrol->value.integer.value[0];
3590 destination = ucontrol->value.integer.value[1];
3592 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3594 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3597 gain = ucontrol->value.integer.value[2];
3599 spin_lock_irq(&hdspm->lock);
3601 if (source >= HDSPM_MAX_CHANNELS)
3602 change = gain != hdspm_read_pb_gain(hdspm, destination,
3604 HDSPM_MAX_CHANNELS);
3606 change = gain != hdspm_read_in_gain(hdspm, destination,
3610 if (source >= HDSPM_MAX_CHANNELS)
3611 hdspm_write_pb_gain(hdspm, destination,
3612 source - HDSPM_MAX_CHANNELS,
3615 hdspm_write_in_gain(hdspm, destination, source,
3618 spin_unlock_irq(&hdspm->lock);
3623 /* The simple mixer control(s) provide gain control for the
3624 basic 1:1 mappings of playback streams to output
3628 #define HDSPM_PLAYBACK_MIXER \
3629 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3630 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3631 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3632 .info = snd_hdspm_info_playback_mixer, \
3633 .get = snd_hdspm_get_playback_mixer, \
3634 .put = snd_hdspm_put_playback_mixer \
3637 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3638 struct snd_ctl_elem_info *uinfo)
3640 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3642 uinfo->value.integer.min = 0;
3643 uinfo->value.integer.max = 64;
3644 uinfo->value.integer.step = 1;
3648 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3649 struct snd_ctl_elem_value *ucontrol)
3651 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3654 channel = ucontrol->id.index - 1;
3656 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3659 spin_lock_irq(&hdspm->lock);
3660 ucontrol->value.integer.value[0] =
3661 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3662 spin_unlock_irq(&hdspm->lock);
3667 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3668 struct snd_ctl_elem_value *ucontrol)
3670 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3675 if (!snd_hdspm_use_is_exclusive(hdspm))
3678 channel = ucontrol->id.index - 1;
3680 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3683 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3685 spin_lock_irq(&hdspm->lock);
3687 gain != hdspm_read_pb_gain(hdspm, channel,
3690 hdspm_write_pb_gain(hdspm, channel, channel,
3692 spin_unlock_irq(&hdspm->lock);
3696 #define HDSPM_SYNC_CHECK(xname, xindex) \
3697 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3699 .private_value = xindex, \
3700 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3701 .info = snd_hdspm_info_sync_check, \
3702 .get = snd_hdspm_get_sync_check \
3706 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3707 struct snd_ctl_elem_info *uinfo)
3709 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3710 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3712 uinfo->value.enumerated.items = 4;
3713 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3714 uinfo->value.enumerated.item =
3715 uinfo->value.enumerated.items - 1;
3716 strcpy(uinfo->value.enumerated.name,
3717 texts[uinfo->value.enumerated.item]);
3721 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3723 int status, status2;
3725 switch (hdspm->io_type) {
3727 status = hdspm_read(hdspm, HDSPM_statusRegister);
3728 if (status & HDSPM_wcSync)
3730 else if (status & HDSPM_wcLock)
3736 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3737 if (status2 & HDSPM_wcLock) {
3738 if (status2 & HDSPM_wcSync)
3748 status = hdspm_read(hdspm, HDSPM_statusRegister);
3750 if (status & 0x2000000)
3752 else if (status & 0x1000000)
3767 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3769 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3770 if (status & HDSPM_madiLock) {
3771 if (status & HDSPM_madiSync)
3780 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3782 int status, lock, sync;
3784 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3786 lock = (status & (0x1<<idx)) ? 1 : 0;
3787 sync = (status & (0x100<<idx)) ? 1 : 0;
3797 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3799 int status, lock = 0, sync = 0;
3801 switch (hdspm->io_type) {
3804 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3805 lock = (status & 0x400) ? 1 : 0;
3806 sync = (status & 0x800) ? 1 : 0;
3811 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3812 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3813 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3828 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3830 int status2, lock, sync;
3831 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3833 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3834 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3844 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3849 switch (hdspm->io_type) {
3852 status = hdspm_read(hdspm, HDSPM_statusRegister);
3853 if (status & HDSPM_tcoLock) {
3854 if (status & HDSPM_tcoSync)
3865 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3867 if (status & 0x8000000)
3868 return 2; /* Sync */
3869 if (status & 0x4000000)
3870 return 1; /* Lock */
3871 return 0; /* No signal */
3883 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3884 struct snd_ctl_elem_value *ucontrol)
3886 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3889 switch (hdspm->io_type) {
3891 switch (kcontrol->private_value) {
3893 val = hdspm_wc_sync_check(hdspm); break;
3895 val = hdspm_tco_sync_check(hdspm); break;
3896 case 8: /* SYNC IN */
3897 val = hdspm_sync_in_sync_check(hdspm); break;
3899 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3903 switch (kcontrol->private_value) {
3905 val = hdspm_wc_sync_check(hdspm); break;
3907 val = hdspm_tco_sync_check(hdspm); break;
3908 case 5: /* SYNC IN */
3909 val = hdspm_sync_in_sync_check(hdspm); break;
3911 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3915 switch (kcontrol->private_value) {
3917 val = hdspm_wc_sync_check(hdspm); break;
3919 val = hdspm_madi_sync_check(hdspm); break;
3921 val = hdspm_tco_sync_check(hdspm); break;
3922 case 3: /* SYNC_IN */
3923 val = hdspm_sync_in_sync_check(hdspm); break;
3927 val = hdspm_madi_sync_check(hdspm); /* MADI */
3931 switch (kcontrol->private_value) {
3933 val = hdspm_wc_sync_check(hdspm); break;
3935 val = hdspm_tco_sync_check(hdspm); break;
3936 case 10 /* SYNC IN */:
3937 val = hdspm_sync_in_sync_check(hdspm); break;
3938 default: /* AES1 to AES8 */
3939 val = hdspm_aes_sync_check(hdspm,
3940 kcontrol->private_value-1);
3948 ucontrol->value.enumerated.item[0] = val;
3957 static void hdspm_tco_write(struct hdspm *hdspm)
3959 unsigned int tc[4] = { 0, 0, 0, 0};
3961 switch (hdspm->tco->input) {
3963 tc[2] |= HDSPM_TCO2_set_input_MSB;
3966 tc[2] |= HDSPM_TCO2_set_input_LSB;
3972 switch (hdspm->tco->framerate) {
3974 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3977 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3980 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3981 HDSPM_TCO1_set_drop_frame_flag;
3984 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3985 HDSPM_TCO1_LTC_Format_MSB;
3988 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3989 HDSPM_TCO1_LTC_Format_MSB +
3990 HDSPM_TCO1_set_drop_frame_flag;
3996 switch (hdspm->tco->wordclock) {
3998 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4001 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4007 switch (hdspm->tco->samplerate) {
4009 tc[2] |= HDSPM_TCO2_set_freq;
4012 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4018 switch (hdspm->tco->pull) {
4020 tc[2] |= HDSPM_TCO2_set_pull_up;
4023 tc[2] |= HDSPM_TCO2_set_pull_down;
4026 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4029 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4035 if (1 == hdspm->tco->term) {
4036 tc[2] |= HDSPM_TCO2_set_term_75R;
4039 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4040 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4041 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4042 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4046 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4047 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4050 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4051 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4052 .info = snd_hdspm_info_tco_sample_rate, \
4053 .get = snd_hdspm_get_tco_sample_rate, \
4054 .put = snd_hdspm_put_tco_sample_rate \
4057 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4058 struct snd_ctl_elem_info *uinfo)
4060 static char *texts[] = { "44.1 kHz", "48 kHz" };
4061 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4063 uinfo->value.enumerated.items = 2;
4065 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4066 uinfo->value.enumerated.item =
4067 uinfo->value.enumerated.items - 1;
4069 strcpy(uinfo->value.enumerated.name,
4070 texts[uinfo->value.enumerated.item]);
4075 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4076 struct snd_ctl_elem_value *ucontrol)
4078 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4080 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4085 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4086 struct snd_ctl_elem_value *ucontrol)
4088 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4090 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4091 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4093 hdspm_tco_write(hdspm);
4102 #define HDSPM_TCO_PULL(xname, xindex) \
4103 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4106 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4107 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4108 .info = snd_hdspm_info_tco_pull, \
4109 .get = snd_hdspm_get_tco_pull, \
4110 .put = snd_hdspm_put_tco_pull \
4113 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4114 struct snd_ctl_elem_info *uinfo)
4116 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4117 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4119 uinfo->value.enumerated.items = 5;
4121 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4122 uinfo->value.enumerated.item =
4123 uinfo->value.enumerated.items - 1;
4125 strcpy(uinfo->value.enumerated.name,
4126 texts[uinfo->value.enumerated.item]);
4131 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4132 struct snd_ctl_elem_value *ucontrol)
4134 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4136 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4141 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4142 struct snd_ctl_elem_value *ucontrol)
4144 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4146 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4147 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4149 hdspm_tco_write(hdspm);
4157 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4161 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4162 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4163 .info = snd_hdspm_info_tco_wck_conversion, \
4164 .get = snd_hdspm_get_tco_wck_conversion, \
4165 .put = snd_hdspm_put_tco_wck_conversion \
4168 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4169 struct snd_ctl_elem_info *uinfo)
4171 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4172 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4174 uinfo->value.enumerated.items = 3;
4176 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4177 uinfo->value.enumerated.item =
4178 uinfo->value.enumerated.items - 1;
4180 strcpy(uinfo->value.enumerated.name,
4181 texts[uinfo->value.enumerated.item]);
4186 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4187 struct snd_ctl_elem_value *ucontrol)
4189 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4191 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4196 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4197 struct snd_ctl_elem_value *ucontrol)
4199 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4201 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4202 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4204 hdspm_tco_write(hdspm);
4213 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4214 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4217 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4218 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4219 .info = snd_hdspm_info_tco_frame_rate, \
4220 .get = snd_hdspm_get_tco_frame_rate, \
4221 .put = snd_hdspm_put_tco_frame_rate \
4224 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4225 struct snd_ctl_elem_info *uinfo)
4227 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4228 "29.97 dfps", "30 fps", "30 dfps" };
4229 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4231 uinfo->value.enumerated.items = 6;
4233 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4234 uinfo->value.enumerated.item =
4235 uinfo->value.enumerated.items - 1;
4237 strcpy(uinfo->value.enumerated.name,
4238 texts[uinfo->value.enumerated.item]);
4243 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4244 struct snd_ctl_elem_value *ucontrol)
4246 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4248 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4253 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4254 struct snd_ctl_elem_value *ucontrol)
4256 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4258 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4259 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4261 hdspm_tco_write(hdspm);
4270 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4271 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4274 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4275 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4276 .info = snd_hdspm_info_tco_sync_source, \
4277 .get = snd_hdspm_get_tco_sync_source, \
4278 .put = snd_hdspm_put_tco_sync_source \
4281 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4282 struct snd_ctl_elem_info *uinfo)
4284 static char *texts[] = { "LTC", "Video", "WCK" };
4285 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4287 uinfo->value.enumerated.items = 3;
4289 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4290 uinfo->value.enumerated.item =
4291 uinfo->value.enumerated.items - 1;
4293 strcpy(uinfo->value.enumerated.name,
4294 texts[uinfo->value.enumerated.item]);
4299 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4300 struct snd_ctl_elem_value *ucontrol)
4302 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4304 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4309 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4310 struct snd_ctl_elem_value *ucontrol)
4312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4314 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4315 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4317 hdspm_tco_write(hdspm);
4326 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4327 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4330 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4331 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4332 .info = snd_hdspm_info_tco_word_term, \
4333 .get = snd_hdspm_get_tco_word_term, \
4334 .put = snd_hdspm_put_tco_word_term \
4337 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4338 struct snd_ctl_elem_info *uinfo)
4340 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4342 uinfo->value.integer.min = 0;
4343 uinfo->value.integer.max = 1;
4349 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4350 struct snd_ctl_elem_value *ucontrol)
4352 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4354 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4360 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4361 struct snd_ctl_elem_value *ucontrol)
4363 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4365 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4366 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4368 hdspm_tco_write(hdspm);
4379 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4380 HDSPM_MIXER("Mixer", 0),
4381 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4382 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4383 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4384 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4385 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4386 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4387 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4388 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4389 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4390 HDSPM_LINE_OUT("Line Out", 0),
4391 HDSPM_TX_64("TX 64 channels mode", 0),
4392 HDSPM_C_TMS("Clear Track Marker", 0),
4393 HDSPM_SAFE_MODE("Safe Mode", 0),
4394 HDSPM_INPUT_SELECT("Input Select", 0),
4395 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4399 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4400 HDSPM_MIXER("Mixer", 0),
4401 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4402 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4403 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4404 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4405 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4406 HDSPM_TX_64("TX 64 channels mode", 0),
4407 HDSPM_C_TMS("Clear Track Marker", 0),
4408 HDSPM_SAFE_MODE("Safe Mode", 0),
4409 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4412 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4413 HDSPM_MIXER("Mixer", 0),
4414 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4415 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4416 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4417 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4418 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4419 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4420 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4421 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4422 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4423 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4424 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4425 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4426 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4427 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4428 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4429 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4430 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4431 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4434 HDSPM_INPUT_SELECT("Input Select", 0),
4435 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4436 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4437 HDSPM_SPDIF_IN("SPDIF In", 0);
4438 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4439 HDSPM_INPUT_LEVEL("Input Level", 0);
4440 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4441 HDSPM_PHONES("Phones", 0);
4445 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4446 HDSPM_MIXER("Mixer", 0),
4447 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4448 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4449 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4450 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4451 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4452 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4453 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4454 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4455 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4456 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4457 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4458 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4459 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4460 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4461 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4462 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4463 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4464 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4465 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4466 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4467 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4468 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4471 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4472 HDSPM_MIXER("Mixer", 0),
4473 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4474 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4475 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4476 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4477 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4478 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4479 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4480 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4481 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4482 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4483 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4484 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4485 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4486 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4487 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4488 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4489 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4490 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4491 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4492 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4493 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4494 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4495 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4496 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4497 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4498 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4499 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4500 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4501 HDSPM_LINE_OUT("Line Out", 0),
4502 HDSPM_EMPHASIS("Emphasis", 0),
4503 HDSPM_DOLBY("Non Audio", 0),
4504 HDSPM_PROFESSIONAL("Professional", 0),
4505 HDSPM_C_TMS("Clear Track Marker", 0),
4506 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4507 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4512 /* Control elements for the optional TCO module */
4513 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4514 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4515 HDSPM_TCO_PULL("TCO Pull", 0),
4516 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4517 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4518 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4519 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4523 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4526 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4530 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4531 if (hdspm->system_sample_rate > 48000) {
4532 hdspm->playback_mixer_ctls[i]->vd[0].access =
4533 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4534 SNDRV_CTL_ELEM_ACCESS_READ |
4535 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4537 hdspm->playback_mixer_ctls[i]->vd[0].access =
4538 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4539 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4541 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4542 SNDRV_CTL_EVENT_MASK_INFO,
4543 &hdspm->playback_mixer_ctls[i]->id);
4550 static int snd_hdspm_create_controls(struct snd_card *card,
4551 struct hdspm *hdspm)
4553 unsigned int idx, limit;
4555 struct snd_kcontrol *kctl;
4556 struct snd_kcontrol_new *list = NULL;
4558 switch (hdspm->io_type) {
4560 list = snd_hdspm_controls_madi;
4561 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4564 list = snd_hdspm_controls_madiface;
4565 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4568 list = snd_hdspm_controls_aio;
4569 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4572 list = snd_hdspm_controls_raydat;
4573 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4576 list = snd_hdspm_controls_aes32;
4577 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4582 for (idx = 0; idx < limit; idx++) {
4583 err = snd_ctl_add(card,
4584 snd_ctl_new1(&list[idx], hdspm));
4591 /* create simple 1:1 playback mixer controls */
4592 snd_hdspm_playback_mixer.name = "Chn";
4593 if (hdspm->system_sample_rate >= 128000) {
4594 limit = hdspm->qs_out_channels;
4595 } else if (hdspm->system_sample_rate >= 64000) {
4596 limit = hdspm->ds_out_channels;
4598 limit = hdspm->ss_out_channels;
4600 for (idx = 0; idx < limit; ++idx) {
4601 snd_hdspm_playback_mixer.index = idx + 1;
4602 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4603 err = snd_ctl_add(card, kctl);
4606 hdspm->playback_mixer_ctls[idx] = kctl;
4611 /* add tco control elements */
4612 list = snd_hdspm_controls_tco;
4613 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4614 for (idx = 0; idx < limit; idx++) {
4615 err = snd_ctl_add(card,
4616 snd_ctl_new1(&list[idx], hdspm));
4625 /*------------------------------------------------------------
4627 ------------------------------------------------------------*/
4630 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4631 struct snd_info_buffer *buffer)
4633 struct hdspm *hdspm = entry->private_data;
4634 unsigned int status, status2, control, freq;
4636 char *pref_sync_ref;
4638 char *system_clock_mode;
4643 int a, ltc, frames, seconds, minutes, hours;
4644 unsigned int period;
4648 status = hdspm_read(hdspm, HDSPM_statusRegister);
4649 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4650 control = hdspm->control_register;
4651 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4653 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4654 hdspm->card_name, hdspm->card->number + 1,
4655 hdspm->firmware_rev,
4656 (status2 & HDSPM_version0) |
4657 (status2 & HDSPM_version1) | (status2 &
4660 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4661 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4662 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4664 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4665 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4667 snd_iprintf(buffer, "--- System ---\n");
4670 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4671 status & HDSPM_audioIRQPending,
4672 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4673 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4676 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4677 "estimated= %ld (bytes)\n",
4678 ((status & HDSPM_BufferID) ? 1 : 0),
4679 (status & HDSPM_BufferPositionMask),
4680 (status & HDSPM_BufferPositionMask) %
4681 (2 * (int)hdspm->period_bytes),
4682 ((status & HDSPM_BufferPositionMask) - 64) %
4683 (2 * (int)hdspm->period_bytes),
4684 (long) hdspm_hw_pointer(hdspm) * 4);
4687 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4688 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4689 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4690 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4691 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4693 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4694 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4695 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4697 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4699 hdspm->control_register, hdspm->control2_register,
4701 if (status & HDSPM_tco_detect) {
4702 snd_iprintf(buffer, "TCO module detected.\n");
4703 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4704 if (a & HDSPM_TCO1_LTC_Input_valid) {
4705 snd_iprintf(buffer, " LTC valid, ");
4706 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4707 HDSPM_TCO1_LTC_Format_MSB)) {
4709 snd_iprintf(buffer, "24 fps, ");
4711 case HDSPM_TCO1_LTC_Format_LSB:
4712 snd_iprintf(buffer, "25 fps, ");
4714 case HDSPM_TCO1_LTC_Format_MSB:
4715 snd_iprintf(buffer, "29.97 fps, ");
4718 snd_iprintf(buffer, "30 fps, ");
4721 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4722 snd_iprintf(buffer, "drop frame\n");
4724 snd_iprintf(buffer, "full frame\n");
4727 snd_iprintf(buffer, " no LTC\n");
4729 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4730 snd_iprintf(buffer, " Video: NTSC\n");
4731 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4732 snd_iprintf(buffer, " Video: PAL\n");
4734 snd_iprintf(buffer, " No video\n");
4736 if (a & HDSPM_TCO1_TCO_lock) {
4737 snd_iprintf(buffer, " Sync: lock\n");
4739 snd_iprintf(buffer, " Sync: no lock\n");
4742 switch (hdspm->io_type) {
4745 freq_const = 110069313433624ULL;
4749 freq_const = 104857600000000ULL;
4752 break; /* no TCO possible */
4755 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4756 snd_iprintf(buffer, " period: %u\n", period);
4759 /* rate = freq_const/period; */
4760 rate = div_u64(freq_const, period);
4762 if (control & HDSPM_QuadSpeed) {
4764 } else if (control & HDSPM_DoubleSpeed) {
4768 snd_iprintf(buffer, " Frequency: %u Hz\n",
4769 (unsigned int) rate);
4771 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4774 frames += (ltc & 0x3) * 10;
4776 seconds = ltc & 0xF;
4778 seconds += (ltc & 0x7) * 10;
4780 minutes = ltc & 0xF;
4782 minutes += (ltc & 0x7) * 10;
4786 hours += (ltc & 0x3) * 10;
4788 " LTC In: %02d:%02d:%02d:%02d\n",
4789 hours, minutes, seconds, frames);
4792 snd_iprintf(buffer, "No TCO module detected.\n");
4795 snd_iprintf(buffer, "--- Settings ---\n");
4797 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4798 HDSPM_LatencyMask));
4801 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4802 x, (unsigned long) hdspm->period_bytes);
4804 snd_iprintf(buffer, "Line out: %s\n",
4805 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4807 switch (hdspm->control_register & HDSPM_InputMask) {
4808 case HDSPM_InputOptical:
4811 case HDSPM_InputCoaxial:
4819 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4821 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4822 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4823 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4826 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4827 system_clock_mode = "AutoSync";
4829 system_clock_mode = "Master";
4830 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4832 switch (hdspm_pref_sync_ref(hdspm)) {
4833 case HDSPM_SYNC_FROM_WORD:
4834 pref_sync_ref = "Word Clock";
4836 case HDSPM_SYNC_FROM_MADI:
4837 pref_sync_ref = "MADI Sync";
4839 case HDSPM_SYNC_FROM_TCO:
4840 pref_sync_ref = "TCO";
4842 case HDSPM_SYNC_FROM_SYNC_IN:
4843 pref_sync_ref = "Sync In";
4846 pref_sync_ref = "XXXX Clock";
4849 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4852 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4853 hdspm->system_sample_rate);
4856 snd_iprintf(buffer, "--- Status:\n");
4858 x = status & HDSPM_madiSync;
4859 x2 = status2 & HDSPM_wcSync;
4861 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4862 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4864 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4867 switch (hdspm_autosync_ref(hdspm)) {
4868 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4869 autosync_ref = "Sync In";
4871 case HDSPM_AUTOSYNC_FROM_TCO:
4872 autosync_ref = "TCO";
4874 case HDSPM_AUTOSYNC_FROM_WORD:
4875 autosync_ref = "Word Clock";
4877 case HDSPM_AUTOSYNC_FROM_MADI:
4878 autosync_ref = "MADI Sync";
4880 case HDSPM_AUTOSYNC_FROM_NONE:
4881 autosync_ref = "Input not valid";
4884 autosync_ref = "---";
4888 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4889 autosync_ref, hdspm_external_sample_rate(hdspm),
4890 (status & HDSPM_madiFreqMask) >> 22,
4891 (status2 & HDSPM_wcFreqMask) >> 5);
4893 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4894 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4895 (status & HDSPM_RX_64ch) ? "64 channels" :
4898 snd_iprintf(buffer, "\n");
4902 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4903 struct snd_info_buffer *buffer)
4905 struct hdspm *hdspm = entry->private_data;
4906 unsigned int status;
4907 unsigned int status2;
4908 unsigned int timecode;
4913 status = hdspm_read(hdspm, HDSPM_statusRegister);
4914 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4915 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4917 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4918 hdspm->card_name, hdspm->card->number + 1,
4919 hdspm->firmware_rev);
4921 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4922 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4924 snd_iprintf(buffer, "--- System ---\n");
4927 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4928 status & HDSPM_audioIRQPending,
4929 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4930 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4933 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4934 "estimated= %ld (bytes)\n",
4935 ((status & HDSPM_BufferID) ? 1 : 0),
4936 (status & HDSPM_BufferPositionMask),
4937 (status & HDSPM_BufferPositionMask) %
4938 (2 * (int)hdspm->period_bytes),
4939 ((status & HDSPM_BufferPositionMask) - 64) %
4940 (2 * (int)hdspm->period_bytes),
4941 (long) hdspm_hw_pointer(hdspm) * 4);
4944 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4945 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4946 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4947 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4948 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4950 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4951 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4952 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4954 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4956 hdspm->control_register, hdspm->control2_register,
4959 snd_iprintf(buffer, "--- Settings ---\n");
4961 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4962 HDSPM_LatencyMask));
4965 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4966 x, (unsigned long) hdspm->period_bytes);
4968 snd_iprintf(buffer, "Line out: %s\n",
4970 control_register & HDSPM_LineOut) ? "on " : "off");
4973 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4975 control_register & HDSPM_clr_tms) ? "on" : "off",
4977 control_register & HDSPM_Emphasis) ? "on" : "off",
4979 control_register & HDSPM_Dolby) ? "on" : "off");
4982 pref_syncref = hdspm_pref_sync_ref(hdspm);
4983 if (pref_syncref == 0)
4984 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4986 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4989 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4990 hdspm->system_sample_rate);
4992 snd_iprintf(buffer, "Double speed: %s\n",
4993 hdspm->control_register & HDSPM_DS_DoubleWire?
4994 "Double wire" : "Single wire");
4995 snd_iprintf(buffer, "Quad speed: %s\n",
4996 hdspm->control_register & HDSPM_QS_DoubleWire?
4998 hdspm->control_register & HDSPM_QS_QuadWire?
4999 "Quad wire" : "Single wire");
5001 snd_iprintf(buffer, "--- Status:\n");
5003 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5004 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
5005 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5007 for (x = 0; x < 8; x++) {
5008 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5010 (status2 & (HDSPM_LockAES >> x)) ?
5011 "Sync " : "No Lock",
5012 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5015 switch (hdspm_autosync_ref(hdspm)) {
5016 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5017 autosync_ref = "None"; break;
5018 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5019 autosync_ref = "Word Clock"; break;
5020 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5021 autosync_ref = "AES1"; break;
5022 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5023 autosync_ref = "AES2"; break;
5024 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5025 autosync_ref = "AES3"; break;
5026 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5027 autosync_ref = "AES4"; break;
5028 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5029 autosync_ref = "AES5"; break;
5030 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5031 autosync_ref = "AES6"; break;
5032 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5033 autosync_ref = "AES7"; break;
5034 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5035 autosync_ref = "AES8"; break;
5037 autosync_ref = "---"; break;
5039 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5041 snd_iprintf(buffer, "\n");
5045 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5046 struct snd_info_buffer *buffer)
5048 struct hdspm *hdspm = entry->private_data;
5049 unsigned int status1, status2, status3, control, i;
5050 unsigned int lock, sync;
5052 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5053 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5054 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5056 control = hdspm->control_register;
5058 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5059 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5060 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5063 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5065 snd_iprintf(buffer, "Clock mode : %s\n",
5066 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5067 snd_iprintf(buffer, "System frequency: %d Hz\n",
5068 hdspm_get_system_sample_rate(hdspm));
5070 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5075 for (i = 0; i < 8; i++) {
5076 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5078 (status1 & lock) ? 1 : 0,
5079 (status1 & sync) ? 1 : 0,
5080 texts_freq[(status2 >> (i * 4)) & 0xF]);
5086 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5087 (status1 & 0x1000000) ? 1 : 0,
5088 (status1 & 0x2000000) ? 1 : 0,
5089 texts_freq[(status1 >> 16) & 0xF]);
5091 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5092 (status1 & 0x4000000) ? 1 : 0,
5093 (status1 & 0x8000000) ? 1 : 0,
5094 texts_freq[(status1 >> 20) & 0xF]);
5096 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5097 (status3 & 0x400) ? 1 : 0,
5098 (status3 & 0x800) ? 1 : 0,
5099 texts_freq[(status2 >> 12) & 0xF]);
5103 #ifdef CONFIG_SND_DEBUG
5105 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5106 struct snd_info_buffer *buffer)
5108 struct hdspm *hdspm = entry->private_data;
5112 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5113 snd_iprintf(buffer, "0x%08X: ", i);
5114 for (j = 0; j < 16; j += 4)
5115 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5116 snd_iprintf(buffer, "\n");
5122 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5123 struct snd_info_buffer *buffer)
5125 struct hdspm *hdspm = entry->private_data;
5128 snd_iprintf(buffer, "# generated by hdspm\n");
5130 for (i = 0; i < hdspm->max_channels_in; i++) {
5131 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5135 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5136 struct snd_info_buffer *buffer)
5138 struct hdspm *hdspm = entry->private_data;
5141 snd_iprintf(buffer, "# generated by hdspm\n");
5143 for (i = 0; i < hdspm->max_channels_out; i++) {
5144 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5149 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5151 struct snd_info_entry *entry;
5153 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5154 switch (hdspm->io_type) {
5156 snd_info_set_text_ops(entry, hdspm,
5157 snd_hdspm_proc_read_aes32);
5160 snd_info_set_text_ops(entry, hdspm,
5161 snd_hdspm_proc_read_madi);
5164 /* snd_info_set_text_ops(entry, hdspm,
5165 snd_hdspm_proc_read_madiface); */
5168 snd_info_set_text_ops(entry, hdspm,
5169 snd_hdspm_proc_read_raydat);
5176 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5177 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5180 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5181 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5184 #ifdef CONFIG_SND_DEBUG
5185 /* debug file to read all hdspm registers */
5186 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5187 snd_info_set_text_ops(entry, hdspm,
5188 snd_hdspm_proc_read_debug);
5192 /*------------------------------------------------------------
5194 ------------------------------------------------------------*/
5196 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5198 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5199 hold it (e.g. during module initialization).
5204 hdspm->settings_register = 0;
5206 switch (hdspm->io_type) {
5209 hdspm->control_register =
5210 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5215 hdspm->settings_register = 0x1 + 0x1000;
5216 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5218 hdspm->control_register =
5219 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5223 hdspm->control_register =
5224 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5225 hdspm_encode_latency(7) | /* latency max=8192samples */
5226 HDSPM_SyncRef0 | /* AES1 is syncclock */
5227 HDSPM_LineOut | /* Analog output in */
5228 HDSPM_Professional; /* Professional mode */
5232 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5234 if (AES32 == hdspm->io_type) {
5235 /* No control2 register for AES32 */
5236 #ifdef SNDRV_BIG_ENDIAN
5237 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5239 hdspm->control2_register = 0;
5242 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5244 hdspm_compute_period_size(hdspm);
5246 /* silence everything */
5248 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5250 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5251 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5254 /* set a default rate so that the channel map is set up. */
5255 hdspm_set_rate(hdspm, 48000, 1);
5261 /*------------------------------------------------------------
5263 ------------------------------------------------------------*/
5265 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5267 struct hdspm *hdspm = (struct hdspm *) dev_id;
5268 unsigned int status;
5269 int i, audio, midi, schedule = 0;
5272 status = hdspm_read(hdspm, HDSPM_statusRegister);
5274 audio = status & HDSPM_audioIRQPending;
5275 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5276 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5278 /* now = get_cycles(); */
5280 * LAT_2..LAT_0 period counter (win) counter (mac)
5281 * 6 4096 ~256053425 ~514672358
5282 * 5 2048 ~128024983 ~257373821
5283 * 4 1024 ~64023706 ~128718089
5284 * 3 512 ~32005945 ~64385999
5285 * 2 256 ~16003039 ~32260176
5286 * 1 128 ~7998738 ~16194507
5287 * 0 64 ~3998231 ~8191558
5290 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5291 now-hdspm->last_interrupt, status & 0xFFC0);
5292 hdspm->last_interrupt = now;
5295 if (!audio && !midi)
5298 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5303 if (hdspm->capture_substream)
5304 snd_pcm_period_elapsed(hdspm->capture_substream);
5306 if (hdspm->playback_substream)
5307 snd_pcm_period_elapsed(hdspm->playback_substream);
5312 while (i < hdspm->midiPorts) {
5313 if ((hdspm_read(hdspm,
5314 hdspm->midi[i].statusIn) & 0xff) &&
5315 (status & hdspm->midi[i].irq)) {
5316 /* we disable interrupts for this input until
5317 * processing is done
5319 hdspm->control_register &= ~hdspm->midi[i].ie;
5320 hdspm_write(hdspm, HDSPM_controlRegister,
5321 hdspm->control_register);
5322 hdspm->midi[i].pending = 1;
5330 tasklet_hi_schedule(&hdspm->midi_tasklet);
5336 /*------------------------------------------------------------
5338 ------------------------------------------------------------*/
5341 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5344 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5345 return hdspm_hw_pointer(hdspm);
5349 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5351 struct snd_pcm_runtime *runtime = substream->runtime;
5352 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5353 struct snd_pcm_substream *other;
5355 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5356 other = hdspm->capture_substream;
5358 other = hdspm->playback_substream;
5361 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5363 runtime->status->hw_ptr = 0;
5365 struct snd_pcm_substream *s;
5366 struct snd_pcm_runtime *oruntime = other->runtime;
5367 snd_pcm_group_for_each_entry(s, substream) {
5369 oruntime->status->hw_ptr =
5370 runtime->status->hw_ptr;
5378 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5379 struct snd_pcm_hw_params *params)
5381 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5387 spin_lock_irq(&hdspm->lock);
5389 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5390 this_pid = hdspm->playback_pid;
5391 other_pid = hdspm->capture_pid;
5393 this_pid = hdspm->capture_pid;
5394 other_pid = hdspm->playback_pid;
5397 if (other_pid > 0 && this_pid != other_pid) {
5399 /* The other stream is open, and not by the same
5400 task as this one. Make sure that the parameters
5401 that matter are the same.
5404 if (params_rate(params) != hdspm->system_sample_rate) {
5405 spin_unlock_irq(&hdspm->lock);
5406 _snd_pcm_hw_param_setempty(params,
5407 SNDRV_PCM_HW_PARAM_RATE);
5411 if (params_period_size(params) != hdspm->period_bytes / 4) {
5412 spin_unlock_irq(&hdspm->lock);
5413 _snd_pcm_hw_param_setempty(params,
5414 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5420 spin_unlock_irq(&hdspm->lock);
5422 /* how to make sure that the rate matches an externally-set one ? */
5424 spin_lock_irq(&hdspm->lock);
5425 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5427 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5428 spin_unlock_irq(&hdspm->lock);
5429 _snd_pcm_hw_param_setempty(params,
5430 SNDRV_PCM_HW_PARAM_RATE);
5433 spin_unlock_irq(&hdspm->lock);
5435 err = hdspm_set_interrupt_interval(hdspm,
5436 params_period_size(params));
5438 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5439 _snd_pcm_hw_param_setempty(params,
5440 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5444 /* Memory allocation, takashi's method, dont know if we should
5447 /* malloc all buffer even if not enabled to get sure */
5448 /* Update for MADI rev 204: we need to allocate for all channels,
5449 * otherwise it doesn't work at 96kHz */
5452 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5454 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5458 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5460 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5461 params_channels(params));
5463 for (i = 0; i < params_channels(params); ++i)
5464 snd_hdspm_enable_out(hdspm, i, 1);
5466 hdspm->playback_buffer =
5467 (unsigned char *) substream->runtime->dma_area;
5468 snd_printdd("Allocated sample buffer for playback at %p\n",
5469 hdspm->playback_buffer);
5471 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5472 params_channels(params));
5474 for (i = 0; i < params_channels(params); ++i)
5475 snd_hdspm_enable_in(hdspm, i, 1);
5477 hdspm->capture_buffer =
5478 (unsigned char *) substream->runtime->dma_area;
5479 snd_printdd("Allocated sample buffer for capture at %p\n",
5480 hdspm->capture_buffer);
5484 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5485 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5486 "playback" : "capture",
5487 snd_pcm_sgbuf_get_addr(substream, 0));
5490 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5491 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5492 "playback" : "capture",
5493 params_rate(params), params_channels(params),
5494 params_buffer_size(params));
5498 /* Switch to native float format if requested */
5499 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5500 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5501 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5503 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5504 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5505 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5506 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5508 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5510 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5515 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5518 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5520 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5522 /* params_channels(params) should be enough,
5523 but to get sure in case of error */
5524 for (i = 0; i < hdspm->max_channels_out; ++i)
5525 snd_hdspm_enable_out(hdspm, i, 0);
5527 hdspm->playback_buffer = NULL;
5529 for (i = 0; i < hdspm->max_channels_in; ++i)
5530 snd_hdspm_enable_in(hdspm, i, 0);
5532 hdspm->capture_buffer = NULL;
5536 snd_pcm_lib_free_pages(substream);
5542 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5543 struct snd_pcm_channel_info *info)
5545 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5547 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5548 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5549 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5553 if (hdspm->channel_map_out[info->channel] < 0) {
5554 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5558 info->offset = hdspm->channel_map_out[info->channel] *
5559 HDSPM_CHANNEL_BUFFER_BYTES;
5561 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5562 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5566 if (hdspm->channel_map_in[info->channel] < 0) {
5567 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5571 info->offset = hdspm->channel_map_in[info->channel] *
5572 HDSPM_CHANNEL_BUFFER_BYTES;
5581 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5582 unsigned int cmd, void *arg)
5585 case SNDRV_PCM_IOCTL1_RESET:
5586 return snd_hdspm_reset(substream);
5588 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5590 struct snd_pcm_channel_info *info = arg;
5591 return snd_hdspm_channel_info(substream, info);
5597 return snd_pcm_lib_ioctl(substream, cmd, arg);
5600 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5602 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5603 struct snd_pcm_substream *other;
5606 spin_lock(&hdspm->lock);
5607 running = hdspm->running;
5609 case SNDRV_PCM_TRIGGER_START:
5610 running |= 1 << substream->stream;
5612 case SNDRV_PCM_TRIGGER_STOP:
5613 running &= ~(1 << substream->stream);
5617 spin_unlock(&hdspm->lock);
5620 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5621 other = hdspm->capture_substream;
5623 other = hdspm->playback_substream;
5626 struct snd_pcm_substream *s;
5627 snd_pcm_group_for_each_entry(s, substream) {
5629 snd_pcm_trigger_done(s, substream);
5630 if (cmd == SNDRV_PCM_TRIGGER_START)
5631 running |= 1 << s->stream;
5633 running &= ~(1 << s->stream);
5637 if (cmd == SNDRV_PCM_TRIGGER_START) {
5638 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5639 && substream->stream ==
5640 SNDRV_PCM_STREAM_CAPTURE)
5641 hdspm_silence_playback(hdspm);
5644 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5645 hdspm_silence_playback(hdspm);
5648 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5649 hdspm_silence_playback(hdspm);
5652 snd_pcm_trigger_done(substream, substream);
5653 if (!hdspm->running && running)
5654 hdspm_start_audio(hdspm);
5655 else if (hdspm->running && !running)
5656 hdspm_stop_audio(hdspm);
5657 hdspm->running = running;
5658 spin_unlock(&hdspm->lock);
5663 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5668 static unsigned int period_sizes_old[] = {
5669 64, 128, 256, 512, 1024, 2048, 4096
5672 static unsigned int period_sizes_new[] = {
5673 32, 64, 128, 256, 512, 1024, 2048, 4096
5676 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5677 static unsigned int raydat_aio_buffer_sizes[] = {
5681 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5682 .info = (SNDRV_PCM_INFO_MMAP |
5683 SNDRV_PCM_INFO_MMAP_VALID |
5684 SNDRV_PCM_INFO_NONINTERLEAVED |
5685 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5686 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5687 .rates = (SNDRV_PCM_RATE_32000 |
5688 SNDRV_PCM_RATE_44100 |
5689 SNDRV_PCM_RATE_48000 |
5690 SNDRV_PCM_RATE_64000 |
5691 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5692 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5696 .channels_max = HDSPM_MAX_CHANNELS,
5698 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5699 .period_bytes_min = (64 * 4),
5700 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5706 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5707 .info = (SNDRV_PCM_INFO_MMAP |
5708 SNDRV_PCM_INFO_MMAP_VALID |
5709 SNDRV_PCM_INFO_NONINTERLEAVED |
5710 SNDRV_PCM_INFO_SYNC_START),
5711 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5712 .rates = (SNDRV_PCM_RATE_32000 |
5713 SNDRV_PCM_RATE_44100 |
5714 SNDRV_PCM_RATE_48000 |
5715 SNDRV_PCM_RATE_64000 |
5716 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5717 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5721 .channels_max = HDSPM_MAX_CHANNELS,
5723 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5724 .period_bytes_min = (64 * 4),
5725 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5731 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5732 .count = ARRAY_SIZE(period_sizes_old),
5733 .list = period_sizes_old,
5737 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5738 .count = ARRAY_SIZE(period_sizes_new),
5739 .list = period_sizes_new,
5743 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5744 .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5745 .list = raydat_aio_buffer_sizes,
5749 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5750 struct snd_pcm_hw_rule *rule)
5752 struct hdspm *hdspm = rule->private;
5753 struct snd_interval *c =
5754 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5755 struct snd_interval *r =
5756 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5758 if (r->min > 96000 && r->max <= 192000) {
5759 struct snd_interval t = {
5760 .min = hdspm->qs_in_channels,
5761 .max = hdspm->qs_in_channels,
5764 return snd_interval_refine(c, &t);
5765 } else if (r->min > 48000 && r->max <= 96000) {
5766 struct snd_interval t = {
5767 .min = hdspm->ds_in_channels,
5768 .max = hdspm->ds_in_channels,
5771 return snd_interval_refine(c, &t);
5772 } else if (r->max < 64000) {
5773 struct snd_interval t = {
5774 .min = hdspm->ss_in_channels,
5775 .max = hdspm->ss_in_channels,
5778 return snd_interval_refine(c, &t);
5784 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5785 struct snd_pcm_hw_rule * rule)
5787 struct hdspm *hdspm = rule->private;
5788 struct snd_interval *c =
5789 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5790 struct snd_interval *r =
5791 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5793 if (r->min > 96000 && r->max <= 192000) {
5794 struct snd_interval t = {
5795 .min = hdspm->qs_out_channels,
5796 .max = hdspm->qs_out_channels,
5799 return snd_interval_refine(c, &t);
5800 } else if (r->min > 48000 && r->max <= 96000) {
5801 struct snd_interval t = {
5802 .min = hdspm->ds_out_channels,
5803 .max = hdspm->ds_out_channels,
5806 return snd_interval_refine(c, &t);
5807 } else if (r->max < 64000) {
5808 struct snd_interval t = {
5809 .min = hdspm->ss_out_channels,
5810 .max = hdspm->ss_out_channels,
5813 return snd_interval_refine(c, &t);
5819 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5820 struct snd_pcm_hw_rule * rule)
5822 struct hdspm *hdspm = rule->private;
5823 struct snd_interval *c =
5824 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5825 struct snd_interval *r =
5826 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5828 if (c->min >= hdspm->ss_in_channels) {
5829 struct snd_interval t = {
5834 return snd_interval_refine(r, &t);
5835 } else if (c->max <= hdspm->qs_in_channels) {
5836 struct snd_interval t = {
5841 return snd_interval_refine(r, &t);
5842 } else if (c->max <= hdspm->ds_in_channels) {
5843 struct snd_interval t = {
5848 return snd_interval_refine(r, &t);
5853 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5854 struct snd_pcm_hw_rule *rule)
5856 struct hdspm *hdspm = rule->private;
5857 struct snd_interval *c =
5858 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5859 struct snd_interval *r =
5860 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5862 if (c->min >= hdspm->ss_out_channels) {
5863 struct snd_interval t = {
5868 return snd_interval_refine(r, &t);
5869 } else if (c->max <= hdspm->qs_out_channels) {
5870 struct snd_interval t = {
5875 return snd_interval_refine(r, &t);
5876 } else if (c->max <= hdspm->ds_out_channels) {
5877 struct snd_interval t = {
5882 return snd_interval_refine(r, &t);
5888 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5889 struct snd_pcm_hw_rule *rule)
5891 unsigned int list[3];
5892 struct hdspm *hdspm = rule->private;
5893 struct snd_interval *c = hw_param_interval(params,
5894 SNDRV_PCM_HW_PARAM_CHANNELS);
5896 list[0] = hdspm->qs_in_channels;
5897 list[1] = hdspm->ds_in_channels;
5898 list[2] = hdspm->ss_in_channels;
5899 return snd_interval_list(c, 3, list, 0);
5902 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5903 struct snd_pcm_hw_rule *rule)
5905 unsigned int list[3];
5906 struct hdspm *hdspm = rule->private;
5907 struct snd_interval *c = hw_param_interval(params,
5908 SNDRV_PCM_HW_PARAM_CHANNELS);
5910 list[0] = hdspm->qs_out_channels;
5911 list[1] = hdspm->ds_out_channels;
5912 list[2] = hdspm->ss_out_channels;
5913 return snd_interval_list(c, 3, list, 0);
5917 static unsigned int hdspm_aes32_sample_rates[] = {
5918 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5921 static struct snd_pcm_hw_constraint_list
5922 hdspm_hw_constraints_aes32_sample_rates = {
5923 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5924 .list = hdspm_aes32_sample_rates,
5928 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5930 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5931 struct snd_pcm_runtime *runtime = substream->runtime;
5933 spin_lock_irq(&hdspm->lock);
5935 snd_pcm_set_sync(substream);
5938 runtime->hw = snd_hdspm_playback_subinfo;
5940 if (hdspm->capture_substream == NULL)
5941 hdspm_stop_audio(hdspm);
5943 hdspm->playback_pid = current->pid;
5944 hdspm->playback_substream = substream;
5946 spin_unlock_irq(&hdspm->lock);
5948 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5950 switch (hdspm->io_type) {
5953 snd_pcm_hw_constraint_list(runtime, 0,
5954 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5955 &hw_constraints_period_sizes_new);
5956 snd_pcm_hw_constraint_list(runtime, 0,
5957 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5958 &hw_constraints_raydat_io_buffer);
5963 snd_pcm_hw_constraint_list(runtime, 0,
5964 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5965 &hw_constraints_period_sizes_old);
5968 if (AES32 == hdspm->io_type) {
5969 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5970 &hdspm_hw_constraints_aes32_sample_rates);
5972 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5973 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5974 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5977 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5978 snd_hdspm_hw_rule_out_channels, hdspm,
5979 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5981 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5982 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5983 SNDRV_PCM_HW_PARAM_RATE, -1);
5988 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5990 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5992 spin_lock_irq(&hdspm->lock);
5994 hdspm->playback_pid = -1;
5995 hdspm->playback_substream = NULL;
5997 spin_unlock_irq(&hdspm->lock);
6003 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6005 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6006 struct snd_pcm_runtime *runtime = substream->runtime;
6008 spin_lock_irq(&hdspm->lock);
6009 snd_pcm_set_sync(substream);
6010 runtime->hw = snd_hdspm_capture_subinfo;
6012 if (hdspm->playback_substream == NULL)
6013 hdspm_stop_audio(hdspm);
6015 hdspm->capture_pid = current->pid;
6016 hdspm->capture_substream = substream;
6018 spin_unlock_irq(&hdspm->lock);
6020 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6021 switch (hdspm->io_type) {
6024 snd_pcm_hw_constraint_list(runtime, 0,
6025 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6026 &hw_constraints_period_sizes_new);
6027 snd_pcm_hw_constraint_list(runtime, 0,
6028 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6029 &hw_constraints_raydat_io_buffer);
6033 snd_pcm_hw_constraint_list(runtime, 0,
6034 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6035 &hw_constraints_period_sizes_old);
6038 if (AES32 == hdspm->io_type) {
6039 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6040 &hdspm_hw_constraints_aes32_sample_rates);
6042 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6043 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6044 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6047 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6048 snd_hdspm_hw_rule_in_channels, hdspm,
6049 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6051 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6052 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6053 SNDRV_PCM_HW_PARAM_RATE, -1);
6058 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6060 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6062 spin_lock_irq(&hdspm->lock);
6064 hdspm->capture_pid = -1;
6065 hdspm->capture_substream = NULL;
6067 spin_unlock_irq(&hdspm->lock);
6071 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6073 /* we have nothing to initialize but the call is required */
6077 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6079 u32 val = readl(src);
6080 return copy_to_user(dest, &val, 4);
6083 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6084 unsigned int cmd, unsigned long __user arg)
6086 void __user *argp = (void __user *)arg;
6087 struct hdspm *hdspm = hw->private_data;
6088 struct hdspm_mixer_ioctl mixer;
6089 struct hdspm_config info;
6090 struct hdspm_status status;
6091 struct hdspm_version hdspm_version;
6092 struct hdspm_peak_rms *levels;
6093 struct hdspm_ltc ltc;
6094 unsigned int statusregister;
6095 long unsigned int s;
6100 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6101 levels = &hdspm->peak_rms;
6102 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6103 levels->input_peaks[i] =
6104 readl(hdspm->iobase +
6105 HDSPM_MADI_INPUT_PEAK + i*4);
6106 levels->playback_peaks[i] =
6107 readl(hdspm->iobase +
6108 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6109 levels->output_peaks[i] =
6110 readl(hdspm->iobase +
6111 HDSPM_MADI_OUTPUT_PEAK + i*4);
6113 levels->input_rms[i] =
6114 ((uint64_t) readl(hdspm->iobase +
6115 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6116 (uint64_t) readl(hdspm->iobase +
6117 HDSPM_MADI_INPUT_RMS_L + i*4);
6118 levels->playback_rms[i] =
6119 ((uint64_t)readl(hdspm->iobase +
6120 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6121 (uint64_t)readl(hdspm->iobase +
6122 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6123 levels->output_rms[i] =
6124 ((uint64_t)readl(hdspm->iobase +
6125 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6126 (uint64_t)readl(hdspm->iobase +
6127 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6130 if (hdspm->system_sample_rate > 96000) {
6132 } else if (hdspm->system_sample_rate > 48000) {
6137 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6139 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6141 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6142 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6148 case SNDRV_HDSPM_IOCTL_GET_LTC:
6149 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6150 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6151 if (i & HDSPM_TCO1_LTC_Input_valid) {
6152 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6153 HDSPM_TCO1_LTC_Format_MSB)) {
6155 ltc.format = fps_24;
6157 case HDSPM_TCO1_LTC_Format_LSB:
6158 ltc.format = fps_25;
6160 case HDSPM_TCO1_LTC_Format_MSB:
6161 ltc.format = fps_2997;
6167 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6168 ltc.frame = drop_frame;
6170 ltc.frame = full_frame;
6173 ltc.format = format_invalid;
6174 ltc.frame = frame_invalid;
6176 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6177 ltc.input_format = ntsc;
6178 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6179 ltc.input_format = pal;
6181 ltc.input_format = no_video;
6184 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6187 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6193 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6195 memset(&info, 0, sizeof(info));
6196 spin_lock_irq(&hdspm->lock);
6197 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6198 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6200 info.system_sample_rate = hdspm->system_sample_rate;
6201 info.autosync_sample_rate =
6202 hdspm_external_sample_rate(hdspm);
6203 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6204 info.clock_source = hdspm_clock_source(hdspm);
6205 info.autosync_ref = hdspm_autosync_ref(hdspm);
6206 info.line_out = hdspm_line_out(hdspm);
6208 spin_unlock_irq(&hdspm->lock);
6209 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6213 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6214 status.card_type = hdspm->io_type;
6216 status.autosync_source = hdspm_autosync_ref(hdspm);
6218 status.card_clock = 110069313433624ULL;
6219 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6221 switch (hdspm->io_type) {
6224 status.card_specific.madi.sync_wc =
6225 hdspm_wc_sync_check(hdspm);
6226 status.card_specific.madi.sync_madi =
6227 hdspm_madi_sync_check(hdspm);
6228 status.card_specific.madi.sync_tco =
6229 hdspm_tco_sync_check(hdspm);
6230 status.card_specific.madi.sync_in =
6231 hdspm_sync_in_sync_check(hdspm);
6234 hdspm_read(hdspm, HDSPM_statusRegister);
6235 status.card_specific.madi.madi_input =
6236 (statusregister & HDSPM_AB_int) ? 1 : 0;
6237 status.card_specific.madi.channel_format =
6238 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6239 /* TODO: Mac driver sets it when f_s>48kHz */
6240 status.card_specific.madi.frame_format = 0;
6246 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6252 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6253 hdspm_version.card_type = hdspm->io_type;
6254 strncpy(hdspm_version.cardname, hdspm->card_name,
6255 sizeof(hdspm_version.cardname));
6256 hdspm_version.serial = (hdspm_read(hdspm,
6257 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6258 hdspm_version.firmware_rev = hdspm->firmware_rev;
6259 hdspm_version.addons = 0;
6261 hdspm_version.addons |= HDSPM_ADDON_TCO;
6263 if (copy_to_user((void __user *) arg, &hdspm_version,
6264 sizeof(hdspm_version)))
6268 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6269 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6271 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6272 sizeof(struct hdspm_mixer)))
6282 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6283 .open = snd_hdspm_playback_open,
6284 .close = snd_hdspm_playback_release,
6285 .ioctl = snd_hdspm_ioctl,
6286 .hw_params = snd_hdspm_hw_params,
6287 .hw_free = snd_hdspm_hw_free,
6288 .prepare = snd_hdspm_prepare,
6289 .trigger = snd_hdspm_trigger,
6290 .pointer = snd_hdspm_hw_pointer,
6291 .page = snd_pcm_sgbuf_ops_page,
6294 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6295 .open = snd_hdspm_capture_open,
6296 .close = snd_hdspm_capture_release,
6297 .ioctl = snd_hdspm_ioctl,
6298 .hw_params = snd_hdspm_hw_params,
6299 .hw_free = snd_hdspm_hw_free,
6300 .prepare = snd_hdspm_prepare,
6301 .trigger = snd_hdspm_trigger,
6302 .pointer = snd_hdspm_hw_pointer,
6303 .page = snd_pcm_sgbuf_ops_page,
6306 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6307 struct hdspm * hdspm)
6309 struct snd_hwdep *hw;
6312 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6317 hw->private_data = hdspm;
6318 strcpy(hw->name, "HDSPM hwdep interface");
6320 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6321 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6322 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6328 /*------------------------------------------------------------
6330 ------------------------------------------------------------*/
6331 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6334 struct snd_pcm *pcm;
6339 wanted = HDSPM_DMA_AREA_BYTES;
6342 snd_pcm_lib_preallocate_pages_for_all(pcm,
6343 SNDRV_DMA_TYPE_DEV_SG,
6344 snd_dma_pci_data(hdspm->pci),
6348 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6352 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6358 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6359 struct snd_pcm_substream *substream,
6360 unsigned int reg, int channels)
6364 /* continuous memory segment */
6365 for (i = 0; i < (channels * 16); i++)
6366 hdspm_write(hdspm, reg + 4 * i,
6367 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6371 /* ------------- ALSA Devices ---------------------------- */
6372 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6373 struct hdspm *hdspm)
6375 struct snd_pcm *pcm;
6378 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6383 pcm->private_data = hdspm;
6384 strcpy(pcm->name, hdspm->card_name);
6386 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6387 &snd_hdspm_playback_ops);
6388 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6389 &snd_hdspm_capture_ops);
6391 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6393 err = snd_hdspm_preallocate_memory(hdspm);
6400 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6404 for (i = 0; i < hdspm->midiPorts; i++)
6405 snd_hdspm_flush_midi_input(hdspm, i);
6408 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6409 struct hdspm * hdspm)
6413 snd_printdd("Create card...\n");
6414 err = snd_hdspm_create_pcm(card, hdspm);
6419 while (i < hdspm->midiPorts) {
6420 err = snd_hdspm_create_midi(card, hdspm, i);
6427 err = snd_hdspm_create_controls(card, hdspm);
6431 err = snd_hdspm_create_hwdep(card, hdspm);
6435 snd_printdd("proc init...\n");
6436 snd_hdspm_proc_init(hdspm);
6438 hdspm->system_sample_rate = -1;
6439 hdspm->last_external_sample_rate = -1;
6440 hdspm->last_internal_sample_rate = -1;
6441 hdspm->playback_pid = -1;
6442 hdspm->capture_pid = -1;
6443 hdspm->capture_substream = NULL;
6444 hdspm->playback_substream = NULL;
6446 snd_printdd("Set defaults...\n");
6447 err = snd_hdspm_set_defaults(hdspm);
6451 snd_printdd("Update mixer controls...\n");
6452 hdspm_update_simple_mixer_controls(hdspm);
6454 snd_printdd("Initializeing complete ???\n");
6456 err = snd_card_register(card);
6458 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6462 snd_printdd("... yes now\n");
6467 static int __devinit snd_hdspm_create(struct snd_card *card,
6468 struct hdspm *hdspm) {
6470 struct pci_dev *pci = hdspm->pci;
6472 unsigned long io_extent;
6477 spin_lock_init(&hdspm->lock);
6479 pci_read_config_word(hdspm->pci,
6480 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6482 strcpy(card->mixername, "Xilinx FPGA");
6483 strcpy(card->driver, "HDSPM");
6485 switch (hdspm->firmware_rev) {
6486 case HDSPM_MADI_REV:
6487 case HDSPM_MADI_OLD_REV:
6488 case HDSPM_MADI_ANCIENT_REV:
6489 hdspm->io_type = MADI;
6490 hdspm->card_name = "RME MADI";
6491 hdspm->midiPorts = 3;
6493 case HDSPM_RAYDAT_REV:
6494 hdspm->io_type = RayDAT;
6495 hdspm->card_name = "RME RayDAT";
6496 hdspm->midiPorts = 2;
6499 hdspm->io_type = AIO;
6500 hdspm->card_name = "RME AIO";
6501 hdspm->midiPorts = 1;
6503 case HDSPM_MADIFACE_REV:
6504 hdspm->io_type = MADIface;
6505 hdspm->card_name = "RME MADIface";
6506 hdspm->midiPorts = 1;
6509 case HDSPM_AES32_REV:
6510 case HDSPM_AES32_OLD_REV:
6511 hdspm->io_type = AES32;
6512 hdspm->card_name = "RME AES32";
6513 hdspm->midiPorts = 2;
6516 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6517 hdspm->firmware_rev);
6521 err = pci_enable_device(pci);
6525 pci_set_master(hdspm->pci);
6527 err = pci_request_regions(pci, "hdspm");
6531 hdspm->port = pci_resource_start(pci, 0);
6532 io_extent = pci_resource_len(pci, 0);
6534 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6535 hdspm->port, hdspm->port + io_extent - 1);
6537 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6538 if (!hdspm->iobase) {
6539 snd_printk(KERN_ERR "HDSPM: "
6540 "unable to remap region 0x%lx-0x%lx\n",
6541 hdspm->port, hdspm->port + io_extent - 1);
6544 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6545 (unsigned long)hdspm->iobase, hdspm->port,
6546 hdspm->port + io_extent - 1);
6548 if (request_irq(pci->irq, snd_hdspm_interrupt,
6549 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6550 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6554 snd_printdd("use IRQ %d\n", pci->irq);
6556 hdspm->irq = pci->irq;
6558 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6559 sizeof(struct hdspm_mixer));
6560 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6561 if (!hdspm->mixer) {
6562 snd_printk(KERN_ERR "HDSPM: "
6563 "unable to kmalloc Mixer memory of %d Bytes\n",
6564 (int)sizeof(struct hdspm_mixer));
6568 hdspm->port_names_in = NULL;
6569 hdspm->port_names_out = NULL;
6571 switch (hdspm->io_type) {
6573 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6574 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6575 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6577 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6579 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6581 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6583 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6585 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6587 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6590 hdspm->max_channels_out = hdspm->max_channels_in =
6592 hdspm->port_names_in = hdspm->port_names_out =
6594 hdspm->channel_map_in = hdspm->channel_map_out =
6601 hdspm->ss_in_channels = hdspm->ss_out_channels =
6603 hdspm->ds_in_channels = hdspm->ds_out_channels =
6605 hdspm->qs_in_channels = hdspm->qs_out_channels =
6608 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6609 channel_map_unity_ss;
6610 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6611 channel_map_unity_ss;
6612 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6613 channel_map_unity_ss;
6615 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6617 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6619 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6624 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6625 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6628 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6629 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6630 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6631 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6632 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6633 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6635 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6636 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6637 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6639 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6640 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6641 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6643 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6644 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6645 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6646 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6647 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6648 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6653 hdspm->ss_in_channels = hdspm->ss_out_channels =
6655 hdspm->ds_in_channels = hdspm->ds_out_channels =
6657 hdspm->qs_in_channels = hdspm->qs_out_channels =
6660 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6661 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6663 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6664 channel_map_raydat_ss;
6665 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6666 channel_map_raydat_ds;
6667 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6668 channel_map_raydat_qs;
6669 hdspm->channel_map_in = hdspm->channel_map_out =
6670 channel_map_raydat_ss;
6672 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6673 texts_ports_raydat_ss;
6674 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6675 texts_ports_raydat_ds;
6676 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6677 texts_ports_raydat_qs;
6685 switch (hdspm->io_type) {
6688 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6689 HDSPM_s2_tco_detect) {
6691 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6693 if (NULL != hdspm->tco) {
6694 hdspm_tco_write(hdspm);
6696 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6703 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6705 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6707 if (NULL != hdspm->tco) {
6708 hdspm_tco_write(hdspm);
6710 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6721 switch (hdspm->io_type) {
6724 hdspm->texts_autosync = texts_autosync_aes_tco;
6725 hdspm->texts_autosync_items = 10;
6727 hdspm->texts_autosync = texts_autosync_aes;
6728 hdspm->texts_autosync_items = 9;
6734 hdspm->texts_autosync = texts_autosync_madi_tco;
6735 hdspm->texts_autosync_items = 4;
6737 hdspm->texts_autosync = texts_autosync_madi;
6738 hdspm->texts_autosync_items = 3;
6748 hdspm->texts_autosync = texts_autosync_raydat_tco;
6749 hdspm->texts_autosync_items = 9;
6751 hdspm->texts_autosync = texts_autosync_raydat;
6752 hdspm->texts_autosync_items = 8;
6758 hdspm->texts_autosync = texts_autosync_aio_tco;
6759 hdspm->texts_autosync_items = 6;
6761 hdspm->texts_autosync = texts_autosync_aio;
6762 hdspm->texts_autosync_items = 5;
6768 tasklet_init(&hdspm->midi_tasklet,
6769 hdspm_midi_tasklet, (unsigned long) hdspm);
6771 snd_printdd("create alsa devices.\n");
6772 err = snd_hdspm_create_alsa_devices(card, hdspm);
6776 snd_hdspm_initialize_midi_flush(hdspm);
6782 static int snd_hdspm_free(struct hdspm * hdspm)
6787 /* stop th audio, and cancel all interrupts */
6788 hdspm->control_register &=
6789 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6790 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6791 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6792 hdspm_write(hdspm, HDSPM_controlRegister,
6793 hdspm->control_register);
6796 if (hdspm->irq >= 0)
6797 free_irq(hdspm->irq, (void *) hdspm);
6799 kfree(hdspm->mixer);
6802 iounmap(hdspm->iobase);
6805 pci_release_regions(hdspm->pci);
6807 pci_disable_device(hdspm->pci);
6812 static void snd_hdspm_card_free(struct snd_card *card)
6814 struct hdspm *hdspm = card->private_data;
6817 snd_hdspm_free(hdspm);
6821 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6822 const struct pci_device_id *pci_id)
6825 struct hdspm *hdspm;
6826 struct snd_card *card;
6829 if (dev >= SNDRV_CARDS)
6836 err = snd_card_create(index[dev], id[dev],
6837 THIS_MODULE, sizeof(struct hdspm), &card);
6841 hdspm = card->private_data;
6842 card->private_free = snd_hdspm_card_free;
6846 snd_card_set_dev(card, &pci->dev);
6848 err = snd_hdspm_create(card, hdspm);
6850 snd_card_free(card);
6854 if (hdspm->io_type != MADIface) {
6855 sprintf(card->shortname, "%s_%x",
6857 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6858 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6860 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6861 hdspm->port, hdspm->irq);
6863 sprintf(card->shortname, "%s", hdspm->card_name);
6864 sprintf(card->longname, "%s at 0x%lx, irq %d",
6865 hdspm->card_name, hdspm->port, hdspm->irq);
6868 err = snd_card_register(card);
6870 snd_card_free(card);
6874 pci_set_drvdata(pci, card);
6880 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6882 snd_card_free(pci_get_drvdata(pci));
6883 pci_set_drvdata(pci, NULL);
6886 static struct pci_driver driver = {
6887 .name = KBUILD_MODNAME,
6888 .id_table = snd_hdspm_ids,
6889 .probe = snd_hdspm_probe,
6890 .remove = __devexit_p(snd_hdspm_remove),
6894 static int __init alsa_card_hdspm_init(void)
6896 return pci_register_driver(&driver);
6899 static void __exit alsa_card_hdspm_exit(void)
6901 pci_unregister_driver(&driver);
6904 module_init(alsa_card_hdspm_init)
6905 module_exit(alsa_card_hdspm_exit)