sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/moduleparam.h>
  44 #include <sound/core.h>
  45 #include <sound/info.h>
  46 #include <sound/control.h>
  47 #include <sound/pcm.h>
  48 #include <sound/mpu401.h>
  49 #include <sound/ac97_codec.h>
  50 #include <sound/initval.h>
  51
  52 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  53 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  54 MODULE_LICENSE("GPL");
  55 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  56                 "{ESS,ES1988},"
  57                 "{ESS,Allegro PCI},"
  58                 "{ESS,Allegro-1 PCI},"
  59                 "{ESS,Canyon3D-2/LE PCI}}");
  60
  61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  63 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  64 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  65 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  66
  67 module_param_array(index, int, NULL, 0444);
  68 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  71 module_param_array(enable, bool, NULL, 0444);
  72 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  73 module_param_array(external_amp, bool, NULL, 0444);
  74 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  75 module_param_array(amp_gpio, int, NULL, 0444);
  76 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  77
  78 #define MAX_PLAYBACKS   2
  79 #define MAX_CAPTURES    1
  80 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  81
  82
  83 /*
  84  * maestro3 registers
  85  */
  86
  87 /* Allegro PCI configuration registers */
  88 #define PCI_LEGACY_AUDIO_CTRL   0x40
  89 #define SOUND_BLASTER_ENABLE    0x00000001
  90 #define FM_SYNTHESIS_ENABLE     0x00000002
  91 #define GAME_PORT_ENABLE        0x00000004
  92 #define MPU401_IO_ENABLE        0x00000008
  93 #define MPU401_IRQ_ENABLE       0x00000010
  94 #define ALIAS_10BIT_IO          0x00000020
  95 #define SB_DMA_MASK             0x000000C0
  96 #define SB_DMA_0                0x00000040
  97 #define SB_DMA_1                0x00000040
  98 #define SB_DMA_R                0x00000080
  99 #define SB_DMA_3                0x000000C0
 100 #define SB_IRQ_MASK             0x00000700
 101 #define SB_IRQ_5                0x00000000
 102 #define SB_IRQ_7                0x00000100
 103 #define SB_IRQ_9                0x00000200
 104 #define SB_IRQ_10               0x00000300
 105 #define MIDI_IRQ_MASK           0x00003800
 106 #define SERIAL_IRQ_ENABLE       0x00004000
 107 #define DISABLE_LEGACY          0x00008000
 108
 109 #define PCI_ALLEGRO_CONFIG      0x50
 110 #define SB_ADDR_240             0x00000004
 111 #define MPU_ADDR_MASK           0x00000018
 112 #define MPU_ADDR_330            0x00000000
 113 #define MPU_ADDR_300            0x00000008
 114 #define MPU_ADDR_320            0x00000010
 115 #define MPU_ADDR_340            0x00000018
 116 #define USE_PCI_TIMING          0x00000040
 117 #define POSTED_WRITE_ENABLE     0x00000080
 118 #define DMA_POLICY_MASK         0x00000700
 119 #define DMA_DDMA                0x00000000
 120 #define DMA_TDMA                0x00000100
 121 #define DMA_PCPCI               0x00000200
 122 #define DMA_WBDMA16             0x00000400
 123 #define DMA_WBDMA4              0x00000500
 124 #define DMA_WBDMA2              0x00000600
 125 #define DMA_WBDMA1              0x00000700
 126 #define DMA_SAFE_GUARD          0x00000800
 127 #define HI_PERF_GP_ENABLE       0x00001000
 128 #define PIC_SNOOP_MODE_0        0x00002000
 129 #define PIC_SNOOP_MODE_1        0x00004000
 130 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 131 #define RING_IN_ENABLE          0x00010000
 132 #define SPDIF_TEST_MODE         0x00020000
 133 #define CLK_MULT_MODE_SELECT_2  0x00040000
 134 #define EEPROM_WRITE_ENABLE     0x00080000
 135 #define CODEC_DIR_IN            0x00100000
 136 #define HV_BUTTON_FROM_GD       0x00200000
 137 #define REDUCED_DEBOUNCE        0x00400000
 138 #define HV_CTRL_ENABLE          0x00800000
 139 #define SPDIF_ENABLE            0x01000000
 140 #define CLK_DIV_SELECT          0x06000000
 141 #define CLK_DIV_BY_48           0x00000000
 142 #define CLK_DIV_BY_49           0x02000000
 143 #define CLK_DIV_BY_50           0x04000000
 144 #define CLK_DIV_RESERVED        0x06000000
 145 #define PM_CTRL_ENABLE          0x08000000
 146 #define CLK_MULT_MODE_SELECT    0x30000000
 147 #define CLK_MULT_MODE_SHIFT     28
 148 #define CLK_MULT_MODE_0         0x00000000
 149 #define CLK_MULT_MODE_1         0x10000000
 150 #define CLK_MULT_MODE_2         0x20000000
 151 #define CLK_MULT_MODE_3         0x30000000
 152 #define INT_CLK_SELECT          0x40000000
 153 #define INT_CLK_MULT_RESET      0x80000000
 154
 155 /* M3 */
 156 #define INT_CLK_SRC_NOT_PCI     0x00100000
 157 #define INT_CLK_MULT_ENABLE     0x80000000
 158
 159 #define PCI_ACPI_CONTROL        0x54
 160 #define PCI_ACPI_D0             0x00000000
 161 #define PCI_ACPI_D1             0xB4F70000
 162 #define PCI_ACPI_D2             0xB4F7B4F7
 163
 164 #define PCI_USER_CONFIG         0x58
 165 #define EXT_PCI_MASTER_ENABLE   0x00000001
 166 #define SPDIF_OUT_SELECT        0x00000002
 167 #define TEST_PIN_DIR_CTRL       0x00000004
 168 #define AC97_CODEC_TEST         0x00000020
 169 #define TRI_STATE_BUFFER        0x00000080
 170 #define IN_CLK_12MHZ_SELECT     0x00000100
 171 #define MULTI_FUNC_DISABLE      0x00000200
 172 #define EXT_MASTER_PAIR_SEL     0x00000400
 173 #define PCI_MASTER_SUPPORT      0x00000800
 174 #define STOP_CLOCK_ENABLE       0x00001000
 175 #define EAPD_DRIVE_ENABLE       0x00002000
 176 #define REQ_TRI_STATE_ENABLE    0x00004000
 177 #define REQ_LOW_ENABLE          0x00008000
 178 #define MIDI_1_ENABLE           0x00010000
 179 #define MIDI_2_ENABLE           0x00020000
 180 #define SB_AUDIO_SYNC           0x00040000
 181 #define HV_CTRL_TEST            0x00100000
 182 #define SOUNDBLASTER_TEST       0x00400000
 183
 184 #define PCI_USER_CONFIG_C       0x5C
 185
 186 #define PCI_DDMA_CTRL           0x60
 187 #define DDMA_ENABLE             0x00000001
 188
 189
 190 /* Allegro registers */
 191 #define HOST_INT_CTRL           0x18
 192 #define SB_INT_ENABLE           0x0001
 193 #define MPU401_INT_ENABLE       0x0002
 194 #define ASSP_INT_ENABLE         0x0010
 195 #define RING_INT_ENABLE         0x0020
 196 #define HV_INT_ENABLE           0x0040
 197 #define CLKRUN_GEN_ENABLE       0x0100
 198 #define HV_CTRL_TO_PME          0x0400
 199 #define SOFTWARE_RESET_ENABLE   0x8000
 200
 201 /*
 202  * should be using the above defines, probably.
 203  */
 204 #define REGB_ENABLE_RESET               0x01
 205 #define REGB_STOP_CLOCK                 0x10
 206
 207 #define HOST_INT_STATUS         0x1A
 208 #define SB_INT_PENDING          0x01
 209 #define MPU401_INT_PENDING      0x02
 210 #define ASSP_INT_PENDING        0x10
 211 #define RING_INT_PENDING        0x20
 212 #define HV_INT_PENDING          0x40
 213
 214 #define HARDWARE_VOL_CTRL       0x1B
 215 #define SHADOW_MIX_REG_VOICE    0x1C
 216 #define HW_VOL_COUNTER_VOICE    0x1D
 217 #define SHADOW_MIX_REG_MASTER   0x1E
 218 #define HW_VOL_COUNTER_MASTER   0x1F
 219
 220 #define CODEC_COMMAND           0x30
 221 #define CODEC_READ_B            0x80
 222
 223 #define CODEC_STATUS            0x30
 224 #define CODEC_BUSY_B            0x01
 225
 226 #define CODEC_DATA              0x32
 227
 228 #define RING_BUS_CTRL_A         0x36
 229 #define RAC_PME_ENABLE          0x0100
 230 #define RAC_SDFS_ENABLE         0x0200
 231 #define LAC_PME_ENABLE          0x0400
 232 #define LAC_SDFS_ENABLE         0x0800
 233 #define SERIAL_AC_LINK_ENABLE   0x1000
 234 #define IO_SRAM_ENABLE          0x2000
 235 #define IIS_INPUT_ENABLE        0x8000
 236
 237 #define RING_BUS_CTRL_B         0x38
 238 #define SECOND_CODEC_ID_MASK    0x0003
 239 #define SPDIF_FUNC_ENABLE       0x0010
 240 #define SECOND_AC_ENABLE        0x0020
 241 #define SB_MODULE_INTF_ENABLE   0x0040
 242 #define SSPE_ENABLE             0x0040
 243 #define M3I_DOCK_ENABLE         0x0080
 244
 245 #define SDO_OUT_DEST_CTRL       0x3A
 246 #define COMMAND_ADDR_OUT        0x0003
 247 #define PCM_LR_OUT_LOCAL        0x0000
 248 #define PCM_LR_OUT_REMOTE       0x0004
 249 #define PCM_LR_OUT_MUTE         0x0008
 250 #define PCM_LR_OUT_BOTH         0x000C
 251 #define LINE1_DAC_OUT_LOCAL     0x0000
 252 #define LINE1_DAC_OUT_REMOTE    0x0010
 253 #define LINE1_DAC_OUT_MUTE      0x0020
 254 #define LINE1_DAC_OUT_BOTH      0x0030
 255 #define PCM_CLS_OUT_LOCAL       0x0000
 256 #define PCM_CLS_OUT_REMOTE      0x0040
 257 #define PCM_CLS_OUT_MUTE        0x0080
 258 #define PCM_CLS_OUT_BOTH        0x00C0
 259 #define PCM_RLF_OUT_LOCAL       0x0000
 260 #define PCM_RLF_OUT_REMOTE      0x0100
 261 #define PCM_RLF_OUT_MUTE        0x0200
 262 #define PCM_RLF_OUT_BOTH        0x0300
 263 #define LINE2_DAC_OUT_LOCAL     0x0000
 264 #define LINE2_DAC_OUT_REMOTE    0x0400
 265 #define LINE2_DAC_OUT_MUTE      0x0800
 266 #define LINE2_DAC_OUT_BOTH      0x0C00
 267 #define HANDSET_OUT_LOCAL       0x0000
 268 #define HANDSET_OUT_REMOTE      0x1000
 269 #define HANDSET_OUT_MUTE        0x2000
 270 #define HANDSET_OUT_BOTH        0x3000
 271 #define IO_CTRL_OUT_LOCAL       0x0000
 272 #define IO_CTRL_OUT_REMOTE      0x4000
 273 #define IO_CTRL_OUT_MUTE        0x8000
 274 #define IO_CTRL_OUT_BOTH        0xC000
 275
 276 #define SDO_IN_DEST_CTRL        0x3C
 277 #define STATUS_ADDR_IN          0x0003
 278 #define PCM_LR_IN_LOCAL         0x0000
 279 #define PCM_LR_IN_REMOTE        0x0004
 280 #define PCM_LR_RESERVED         0x0008
 281 #define PCM_LR_IN_BOTH          0x000C
 282 #define LINE1_ADC_IN_LOCAL      0x0000
 283 #define LINE1_ADC_IN_REMOTE     0x0010
 284 #define LINE1_ADC_IN_MUTE       0x0020
 285 #define MIC_ADC_IN_LOCAL        0x0000
 286 #define MIC_ADC_IN_REMOTE       0x0040
 287 #define MIC_ADC_IN_MUTE         0x0080
 288 #define LINE2_DAC_IN_LOCAL      0x0000
 289 #define LINE2_DAC_IN_REMOTE     0x0400
 290 #define LINE2_DAC_IN_MUTE       0x0800
 291 #define HANDSET_IN_LOCAL        0x0000
 292 #define HANDSET_IN_REMOTE       0x1000
 293 #define HANDSET_IN_MUTE         0x2000
 294 #define IO_STATUS_IN_LOCAL      0x0000
 295 #define IO_STATUS_IN_REMOTE     0x4000
 296
 297 #define SPDIF_IN_CTRL           0x3E
 298 #define SPDIF_IN_ENABLE         0x0001
 299
 300 #define GPIO_DATA               0x60
 301 #define GPIO_DATA_MASK          0x0FFF
 302 #define GPIO_HV_STATUS          0x3000
 303 #define GPIO_PME_STATUS         0x4000
 304
 305 #define GPIO_MASK               0x64
 306 #define GPIO_DIRECTION          0x68
 307 #define GPO_PRIMARY_AC97        0x0001
 308 #define GPI_LINEOUT_SENSE       0x0004
 309 #define GPO_SECONDARY_AC97      0x0008
 310 #define GPI_VOL_DOWN            0x0010
 311 #define GPI_VOL_UP              0x0020
 312 #define GPI_IIS_CLK             0x0040
 313 #define GPI_IIS_LRCLK           0x0080
 314 #define GPI_IIS_DATA            0x0100
 315 #define GPI_DOCKING_STATUS      0x0100
 316 #define GPI_HEADPHONE_SENSE     0x0200
 317 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 318
 319 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 320 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 321
 322 /* M3 */
 323 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 324
 325 #define ASSP_INDEX_PORT         0x80
 326 #define ASSP_MEMORY_PORT        0x82
 327 #define ASSP_DATA_PORT          0x84
 328
 329 #define MPU401_DATA_PORT        0x98
 330 #define MPU401_STATUS_PORT      0x99
 331
 332 #define CLK_MULT_DATA_PORT      0x9C
 333
 334 #define ASSP_CONTROL_A          0xA2
 335 #define ASSP_0_WS_ENABLE        0x01
 336 #define ASSP_CTRL_A_RESERVED1   0x02
 337 #define ASSP_CTRL_A_RESERVED2   0x04
 338 #define ASSP_CLK_49MHZ_SELECT   0x08
 339 #define FAST_PLU_ENABLE         0x10
 340 #define ASSP_CTRL_A_RESERVED3   0x20
 341 #define DSP_CLK_36MHZ_SELECT    0x40
 342
 343 #define ASSP_CONTROL_B          0xA4
 344 #define RESET_ASSP              0x00
 345 #define RUN_ASSP                0x01
 346 #define ENABLE_ASSP_CLOCK       0x00
 347 #define STOP_ASSP_CLOCK         0x10
 348 #define RESET_TOGGLE            0x40
 349
 350 #define ASSP_CONTROL_C          0xA6
 351 #define ASSP_HOST_INT_ENABLE    0x01
 352 #define FM_ADDR_REMAP_DISABLE   0x02
 353 #define HOST_WRITE_PORT_ENABLE  0x08
 354
 355 #define ASSP_HOST_INT_STATUS    0xAC
 356 #define DSP2HOST_REQ_PIORECORD  0x01
 357 #define DSP2HOST_REQ_I2SRATE    0x02
 358 #define DSP2HOST_REQ_TIMER      0x04
 359
 360 /* AC97 registers */
 361 /* XXX fix this crap up */
 362 /*#define AC97_RESET              0x00*/
 363
 364 #define AC97_VOL_MUTE_B         0x8000
 365 #define AC97_VOL_M              0x1F
 366 #define AC97_LEFT_VOL_S         8
 367
 368 #define AC97_MASTER_VOL         0x02
 369 #define AC97_LINE_LEVEL_VOL     0x04
 370 #define AC97_MASTER_MONO_VOL    0x06
 371 #define AC97_PC_BEEP_VOL        0x0A
 372 #define AC97_PC_BEEP_VOL_M      0x0F
 373 #define AC97_SROUND_MASTER_VOL  0x38
 374 #define AC97_PC_BEEP_VOL_S      1
 375
 376 /*#define AC97_PHONE_VOL          0x0C
 377 #define AC97_MIC_VOL            0x0E*/
 378 #define AC97_MIC_20DB_ENABLE    0x40
 379
 380 /*#define AC97_LINEIN_VOL         0x10
 381 #define AC97_CD_VOL             0x12
 382 #define AC97_VIDEO_VOL          0x14
 383 #define AC97_AUX_VOL            0x16*/
 384 #define AC97_PCM_OUT_VOL        0x18
 385 /*#define AC97_RECORD_SELECT      0x1A*/
 386 #define AC97_RECORD_MIC         0x00
 387 #define AC97_RECORD_CD          0x01
 388 #define AC97_RECORD_VIDEO       0x02
 389 #define AC97_RECORD_AUX         0x03
 390 #define AC97_RECORD_MONO_MUX    0x02
 391 #define AC97_RECORD_DIGITAL     0x03
 392 #define AC97_RECORD_LINE        0x04
 393 #define AC97_RECORD_STEREO      0x05
 394 #define AC97_RECORD_MONO        0x06
 395 #define AC97_RECORD_PHONE       0x07
 396
 397 /*#define AC97_RECORD_GAIN        0x1C*/
 398 #define AC97_RECORD_VOL_M       0x0F
 399
 400 /*#define AC97_GENERAL_PURPOSE    0x20*/
 401 #define AC97_POWER_DOWN_CTRL    0x26
 402 #define AC97_ADC_READY          0x0001
 403 #define AC97_DAC_READY          0x0002
 404 #define AC97_ANALOG_READY       0x0004
 405 #define AC97_VREF_ON            0x0008
 406 #define AC97_PR0                0x0100
 407 #define AC97_PR1                0x0200
 408 #define AC97_PR2                0x0400
 409 #define AC97_PR3                0x0800
 410 #define AC97_PR4                0x1000
 411
 412 #define AC97_RESERVED1          0x28
 413
 414 #define AC97_VENDOR_TEST        0x5A
 415
 416 #define AC97_CLOCK_DELAY        0x5C
 417 #define AC97_LINEOUT_MUX_SEL    0x0001
 418 #define AC97_MONO_MUX_SEL       0x0002
 419 #define AC97_CLOCK_DELAY_SEL    0x1F
 420 #define AC97_DAC_CDS_SHIFT      6
 421 #define AC97_ADC_CDS_SHIFT      11
 422
 423 #define AC97_MULTI_CHANNEL_SEL  0x74
 424
 425 /*#define AC97_VENDOR_ID1         0x7C
 426 #define AC97_VENDOR_ID2         0x7E*/
 427
 428 /*
 429  * ASSP control regs
 430  */
 431 #define DSP_PORT_TIMER_COUNT    0x06
 432
 433 #define DSP_PORT_MEMORY_INDEX   0x80
 434
 435 #define DSP_PORT_MEMORY_TYPE    0x82
 436 #define MEMTYPE_INTERNAL_CODE   0x0002
 437 #define MEMTYPE_INTERNAL_DATA   0x0003
 438 #define MEMTYPE_MASK            0x0003
 439
 440 #define DSP_PORT_MEMORY_DATA    0x84
 441
 442 #define DSP_PORT_CONTROL_REG_A  0xA2
 443 #define DSP_PORT_CONTROL_REG_B  0xA4
 444 #define DSP_PORT_CONTROL_REG_C  0xA6
 445
 446 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 447 #define REV_A_CODE_MEMORY_END           0x0FFF
 448 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 449 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 450
 451 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 452 #define REV_B_CODE_MEMORY_END           0x0BFF
 453 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 454 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 455
 456 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 457 #define REV_A_DATA_MEMORY_END           0x2FFF
 458 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 459 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 460
 461 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 462 #define REV_B_DATA_MEMORY_END           0x2BFF
 463 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 464 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 465
 466
 467 #define NUM_UNITS_KERNEL_CODE          16
 468 #define NUM_UNITS_KERNEL_DATA           2
 469
 470 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 471 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 472
 473 /*
 474  * Kernel data layout
 475  */
 476
 477 #define DP_SHIFT_COUNT                  7
 478
 479 #define KDATA_BASE_ADDR                 0x1000
 480 #define KDATA_BASE_ADDR2                0x1080
 481
 482 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 483 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 484 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 485 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 486 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 487 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 488 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 489 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 490 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 491
 492 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 493 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 494
 495 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 496 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 497 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 498 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 499 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 500 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 501 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 502 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 503 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 504 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 505
 506 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 507 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 508
 509 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 510 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 511
 512 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 513 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 514
 515 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 516 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 517 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 518
 519 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 520 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 521 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 522 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 523 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 524
 525 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 526 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 527 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 528
 529 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 530 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 531 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 532
 533 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 534 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 535 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 536 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 537 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 538 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 539 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 540 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 541 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 542 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 543
 544 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 545 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 546 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 547
 548 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 549 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 550
 551 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 552 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 553 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 554
 555 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 556 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 557 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 558 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 559 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 560 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 561
 562 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 563 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 564 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 565 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 566 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 567 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 568
 569 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 570 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 571 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 572 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 573 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 574 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 575
 576 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 577 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 578 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 579 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 580
 581 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 582 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 583
 584 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 585 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 586
 587 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 588 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 589 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 590 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 591 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 592
 593 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 594 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 595
 596 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 597 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 598 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 599
 600 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 601 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 602
 603 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 604
 605 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 606 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 607 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 608 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 609 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 610 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 611 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 612 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 613 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 614 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 615 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 616 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 617
 618 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 619 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 620 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 621 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 622
 623 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 624 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 625
 626 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 627 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 628 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 629 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 630
 631 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 632 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 633 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 634 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 635 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 636
 637 /*
 638  * second 'segment' (?) reserved for mixer
 639  * buffers..
 640  */
 641
 642 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 643 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 644 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 645 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 646 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 647 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 648 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 649 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 650 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 651 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 652 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 653 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 654 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 655 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 656 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 657 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 658
 659 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 660 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 661 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 662 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 663 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 664 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 665 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 666 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 667 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 668 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 669 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 670
 671 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 672 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 673 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 674 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 675 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 676 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 677
 678 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 679 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 680 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 681 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 682
 683 /*
 684  * client data area offsets
 685  */
 686 #define CDATA_INSTANCE_READY            0x00
 687
 688 #define CDATA_HOST_SRC_ADDRL            0x01
 689 #define CDATA_HOST_SRC_ADDRH            0x02
 690 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 691 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 692 #define CDATA_HOST_SRC_CURRENTL         0x05
 693 #define CDATA_HOST_SRC_CURRENTH         0x06
 694
 695 #define CDATA_IN_BUF_CONNECT            0x07
 696 #define CDATA_OUT_BUF_CONNECT           0x08
 697
 698 #define CDATA_IN_BUF_BEGIN              0x09
 699 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 700 #define CDATA_IN_BUF_HEAD               0x0B
 701 #define CDATA_IN_BUF_TAIL               0x0C
 702 #define CDATA_OUT_BUF_BEGIN             0x0D
 703 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 704 #define CDATA_OUT_BUF_HEAD              0x0F
 705 #define CDATA_OUT_BUF_TAIL              0x10
 706
 707 #define CDATA_DMA_CONTROL               0x11
 708 #define CDATA_RESERVED                  0x12
 709
 710 #define CDATA_FREQUENCY                 0x13
 711 #define CDATA_LEFT_VOLUME               0x14
 712 #define CDATA_RIGHT_VOLUME              0x15
 713 #define CDATA_LEFT_SUR_VOL              0x16
 714 #define CDATA_RIGHT_SUR_VOL             0x17
 715
 716 #define CDATA_HEADER_LEN                0x18
 717
 718 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 719 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 720 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 721 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 722 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 723 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 724 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 725 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 726
 727 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 728 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 729 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 730 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 731 #define MINISRC_BIQUAD_STAGE    2
 732 #define MINISRC_COEF_LOC          0x175
 733
 734 #define DMACONTROL_BLOCK_MASK           0x000F
 735 #define  DMAC_BLOCK0_SELECTOR           0x0000
 736 #define  DMAC_BLOCK1_SELECTOR           0x0001
 737 #define  DMAC_BLOCK2_SELECTOR           0x0002
 738 #define  DMAC_BLOCK3_SELECTOR           0x0003
 739 #define  DMAC_BLOCK4_SELECTOR           0x0004
 740 #define  DMAC_BLOCK5_SELECTOR           0x0005
 741 #define  DMAC_BLOCK6_SELECTOR           0x0006
 742 #define  DMAC_BLOCK7_SELECTOR           0x0007
 743 #define  DMAC_BLOCK8_SELECTOR           0x0008
 744 #define  DMAC_BLOCK9_SELECTOR           0x0009
 745 #define  DMAC_BLOCKA_SELECTOR           0x000A
 746 #define  DMAC_BLOCKB_SELECTOR           0x000B
 747 #define  DMAC_BLOCKC_SELECTOR           0x000C
 748 #define  DMAC_BLOCKD_SELECTOR           0x000D
 749 #define  DMAC_BLOCKE_SELECTOR           0x000E
 750 #define  DMAC_BLOCKF_SELECTOR           0x000F
 751 #define DMACONTROL_PAGE_MASK            0x00F0
 752 #define  DMAC_PAGE0_SELECTOR            0x0030
 753 #define  DMAC_PAGE1_SELECTOR            0x0020
 754 #define  DMAC_PAGE2_SELECTOR            0x0010
 755 #define  DMAC_PAGE3_SELECTOR            0x0000
 756 #define DMACONTROL_AUTOREPEAT           0x1000
 757 #define DMACONTROL_STOPPED              0x2000
 758 #define DMACONTROL_DIRECTION            0x0100
 759
 760 /*
 761  * an arbitrary volume we set the internal
 762  * volume settings to so that the ac97 volume
 763  * range is a little less insane.  0x7fff is
 764  * max.
 765  */
 766 #define ARB_VOLUME ( 0x6800 )
 767
 768 /*
 769  */
 770
 771 /* quirk lists */
 772 struct m3_quirk {
 773         const char *name;       /* device name */
 774         u16 vendor, device;     /* subsystem ids */
 775         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 776         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 777                                    (e.g. for IrDA on Dell Inspirons) */
 778 };
 779
 780 struct m3_hv_quirk {
 781         u16 vendor, device, subsystem_vendor, subsystem_device;
 782         u32 config;             /* ALLEGRO_CONFIG hardware volume bits */
 783         int is_omnibook;        /* Do HP OmniBook GPIO magic? */
 784 };
 785
 786 struct m3_list {
 787         int curlen;
 788         int mem_addr;
 789         int max;
 790 };
 791
 792 struct m3_dma {
 793
 794         int number;
 795         struct snd_pcm_substream *substream;
 796
 797         struct assp_instance {
 798                 unsigned short code, data;
 799         } inst;
 800
 801         int running;
 802         int opened;
 803
 804         unsigned long buffer_addr;
 805         int dma_size;
 806         int period_size;
 807         unsigned int hwptr;
 808         int count;
 809
 810         int index[3];
 811         struct m3_list *index_list[3];
 812
 813         int in_lists;
 814
 815         struct list_head list;
 816
 817 };
 818
 819 struct snd_m3 {
 820
 821         struct snd_card *card;
 822
 823         unsigned long iobase;
 824
 825         int irq;
 826         unsigned int allegro_flag : 1;
 827
 828         struct snd_ac97 *ac97;
 829
 830         struct snd_pcm *pcm;
 831
 832         struct pci_dev *pci;
 833         const struct m3_quirk *quirk;
 834         const struct m3_hv_quirk *hv_quirk;
 835
 836         int dacs_active;
 837         int timer_users;
 838
 839         struct m3_list  msrc_list;
 840         struct m3_list  mixer_list;
 841         struct m3_list  adc1_list;
 842         struct m3_list  dma_list;
 843
 844         /* for storing reset state..*/
 845         u8 reset_state;
 846
 847         int external_amp;
 848         int amp_gpio;
 849
 850         /* midi */
 851         struct snd_rawmidi *rmidi;
 852
 853         /* pcm streams */
 854         int num_substreams;
 855         struct m3_dma *substreams;
 856
 857         spinlock_t reg_lock;
 858         spinlock_t ac97_lock;
 859
 860         struct snd_kcontrol *master_switch;
 861         struct snd_kcontrol *master_volume;
 862         struct tasklet_struct hwvol_tq;
 863
 864 #ifdef CONFIG_PM
 865         u16 *suspend_mem;
 866 #endif
 867 };
 868
 869 /*
 870  * pci ids
 871  */
 872 static struct pci_device_id snd_m3_ids[] = {
 873         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 874          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 875         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 876          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 877         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 878          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 879         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 880          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 881         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 882          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 883         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 884          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 885         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 886          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 887         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 888          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 889         {0,},
 890 };
 891
 892 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 893
 894 static const struct m3_quirk m3_quirk_list[] = {
 895         /* panasonic CF-28 "toughbook" */
 896         {
 897                 .name = "Panasonic CF-28",
 898                 .vendor = 0x10f7,
 899                 .device = 0x833e,
 900                 .amp_gpio = 0x0d,
 901         },
 902         /* panasonic CF-72 "toughbook" */
 903         {
 904                 .name = "Panasonic CF-72",
 905                 .vendor = 0x10f7,
 906                 .device = 0x833d,
 907                 .amp_gpio = 0x0d,
 908         },
 909         /* Dell Inspiron 4000 */
 910         {
 911                 .name = "Dell Inspiron 4000",
 912                 .vendor = 0x1028,
 913                 .device = 0x00b0,
 914                 .amp_gpio = -1,
 915                 .irda_workaround = 1,
 916         },
 917         /* Dell Inspiron 8000 */
 918         {
 919                 .name = "Dell Inspiron 8000",
 920                 .vendor = 0x1028,
 921                 .device = 0x00a4,
 922                 .amp_gpio = -1,
 923                 .irda_workaround = 1,
 924         },
 925         /* Dell Inspiron 8100 */
 926         {
 927                 .name = "Dell Inspiron 8100",
 928                 .vendor = 0x1028,
 929                 .device = 0x00e6,
 930                 .amp_gpio = -1,
 931                 .irda_workaround = 1,
 932         },
 933         /* NEC LM800J/7 */
 934         {
 935                 .name = "NEC LM800J/7",
 936                 .vendor = 0x1033,
 937                 .device = 0x80f1,
 938                 .amp_gpio = 0x03,
 939         },
 940         /* LEGEND ZhaoYang 3100CF */
 941         {
 942                 .name = "LEGEND ZhaoYang 3100CF",
 943                 .vendor = 0x1509,
 944                 .device = 0x1740,
 945                 .amp_gpio = 0x03,
 946         },
 947         /* END */
 948         { NULL }
 949 };
 950
 951 /* These values came from the Windows driver. */
 952 static const struct m3_hv_quirk m3_hv_quirk_list[] = {
 953         /* Allegro chips */
 954         { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 955         { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 956         { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 957         { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 958         { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 959         { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 960         { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 961         { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 962         { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 963         { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 964         { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 965         { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 966         { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 967         { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 968         { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 969         { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 970         { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 971         { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 972         { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 973         { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 974         { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 975         { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 976         { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 977         { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 978         { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 979         { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 980         { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */
 981         { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 982         { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 983         { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 984         { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 985         { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 986         { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 987         { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 988         { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 989         { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 990         { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 991         { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 },
 992         { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 },
 993         { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 },
 994         { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 },
 995         { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 },
 996         /* Maestro3 chips */
 997         { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 },
 998         { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */
 999         { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */
1000         { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 },
1001         { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 },
1002         { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 },
1003         { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 },
1004         { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 },
1005         { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 },
1006         { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 },
1007         { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 },
1008         { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 },
1009         { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 },
1010         { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1011         { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1012         { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1013         { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1014         { 0 }
1015 };
1016
1017 /*
1018  * lowlevel functions
1019  */
1020
1021 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
1022 {
1023         outw(value, chip->iobase + reg);
1024 }
1025
1026 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1027 {
1028         return inw(chip->iobase + reg);
1029 }
1030
1031 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1032 {
1033         outb(value, chip->iobase + reg);
1034 }
1035
1036 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1037 {
1038         return inb(chip->iobase + reg);
1039 }
1040
1041 /*
1042  * access 16bit words to the code or data regions of the dsp's memory.
1043  * index addresses 16bit words.
1044  */
1045 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1046 {
1047         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1048         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1049         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1050 }
1051
1052 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1053 {
1054         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1055         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1056         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1057 }
1058
1059 static void snd_m3_assp_halt(struct snd_m3 *chip)
1060 {
1061         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1062         msleep(10);
1063         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1064 }
1065
1066 static void snd_m3_assp_continue(struct snd_m3 *chip)
1067 {
1068         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1069 }
1070
1071
1072 /*
1073  * This makes me sad. the maestro3 has lists
1074  * internally that must be packed.. 0 terminates,
1075  * apparently, or maybe all unused entries have
1076  * to be 0, the lists have static lengths set
1077  * by the binary code images.
1078  */
1079
1080 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1081 {
1082         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1083                           list->mem_addr + list->curlen,
1084                           val);
1085         return list->curlen++;
1086 }
1087
1088 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1089 {
1090         u16  val;
1091         int lastindex = list->curlen - 1;
1092
1093         if (index != lastindex) {
1094                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1095                                        list->mem_addr + lastindex);
1096                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1097                                   list->mem_addr + index,
1098                                   val);
1099         }
1100
1101         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1102                           list->mem_addr + lastindex,
1103                           0);
1104
1105         list->curlen--;
1106 }
1107
1108 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1109 {
1110         chip->timer_users++;
1111         if (chip->timer_users != 1)
1112                 return;
1113
1114         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1115                           KDATA_TIMER_COUNT_RELOAD,
1116                           240);
1117
1118         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1119                           KDATA_TIMER_COUNT_CURRENT,
1120                           240);
1121
1122         snd_m3_outw(chip,
1123                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1124                     HOST_INT_CTRL);
1125 }
1126
1127 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1128 {
1129         chip->timer_users--;
1130         if (chip->timer_users > 0)
1131                 return;
1132
1133         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1134                           KDATA_TIMER_COUNT_RELOAD,
1135                           0);
1136
1137         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1138                           KDATA_TIMER_COUNT_CURRENT,
1139                           0);
1140
1141         snd_m3_outw(chip,
1142                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1143                     HOST_INT_CTRL);
1144 }
1145
1146 /*
1147  * start/stop
1148  */
1149
1150 /* spinlock held! */
1151 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1152                             struct snd_pcm_substream *subs)
1153 {
1154         if (! s || ! subs)
1155                 return -EINVAL;
1156
1157         snd_m3_inc_timer_users(chip);
1158         switch (subs->stream) {
1159         case SNDRV_PCM_STREAM_PLAYBACK:
1160                 chip->dacs_active++;
1161                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1163                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164                                   KDATA_MIXER_TASK_NUMBER,
1165                                   chip->dacs_active);
1166                 break;
1167         case SNDRV_PCM_STREAM_CAPTURE:
1168                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1169                                   KDATA_ADC1_REQUEST, 1);
1170                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1171                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1172                 break;
1173         }
1174         return 0;
1175 }
1176
1177 /* spinlock held! */
1178 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1179                            struct snd_pcm_substream *subs)
1180 {
1181         if (! s || ! subs)
1182                 return -EINVAL;
1183
1184         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1185                           s->inst.data + CDATA_INSTANCE_READY, 0);
1186         snd_m3_dec_timer_users(chip);
1187         switch (subs->stream) {
1188         case SNDRV_PCM_STREAM_PLAYBACK:
1189                 chip->dacs_active--;
1190                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1191                                   KDATA_MIXER_TASK_NUMBER,
1192                                   chip->dacs_active);
1193                 break;
1194         case SNDRV_PCM_STREAM_CAPTURE:
1195                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1196                                   KDATA_ADC1_REQUEST, 0);
1197                 break;
1198         }
1199         return 0;
1200 }
1201
1202 static int
1203 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1204 {
1205         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1206         struct m3_dma *s = subs->runtime->private_data;
1207         int err = -EINVAL;
1208
1209         snd_assert(s != NULL, return -ENXIO);
1210
1211         spin_lock(&chip->reg_lock);
1212         switch (cmd) {
1213         case SNDRV_PCM_TRIGGER_START:
1214         case SNDRV_PCM_TRIGGER_RESUME:
1215                 if (s->running)
1216                         err = -EBUSY;
1217                 else {
1218                         s->running = 1;
1219                         err = snd_m3_pcm_start(chip, s, subs);
1220                 }
1221                 break;
1222         case SNDRV_PCM_TRIGGER_STOP:
1223         case SNDRV_PCM_TRIGGER_SUSPEND:
1224                 if (! s->running)
1225                         err = 0; /* should return error? */
1226                 else {
1227                         s->running = 0;
1228                         err = snd_m3_pcm_stop(chip, s, subs);
1229                 }
1230                 break;
1231         }
1232         spin_unlock(&chip->reg_lock);
1233         return err;
1234 }
1235
1236 /*
1237  * setup
1238  */
1239 static void
1240 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1241 {
1242         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1243         struct snd_pcm_runtime *runtime = subs->runtime;
1244
1245         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1246                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1247                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1248         } else {
1249                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1250                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1251         }
1252         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1253         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1254
1255         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1256         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1257         s->hwptr = 0;
1258         s->count = 0;
1259
1260 #define LO(x) ((x) & 0xffff)
1261 #define HI(x) LO((x) >> 16)
1262
1263         /* host dma buffer pointers */
1264         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1266                           LO(s->buffer_addr));
1267
1268         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1270                           HI(s->buffer_addr));
1271
1272         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1274                           LO(s->buffer_addr + s->dma_size));
1275
1276         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1277                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1278                           HI(s->buffer_addr + s->dma_size));
1279
1280         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1281                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1282                           LO(s->buffer_addr));
1283
1284         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1285                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1286                           HI(s->buffer_addr));
1287 #undef LO
1288 #undef HI
1289
1290         /* dsp buffers */
1291
1292         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1293                           s->inst.data + CDATA_IN_BUF_BEGIN,
1294                           dsp_in_buffer);
1295
1296         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1297                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1298                           dsp_in_buffer + (dsp_in_size / 2));
1299
1300         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1301                           s->inst.data + CDATA_IN_BUF_HEAD,
1302                           dsp_in_buffer);
1303
1304         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1305                           s->inst.data + CDATA_IN_BUF_TAIL,
1306                           dsp_in_buffer);
1307
1308         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1309                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1310                           dsp_out_buffer);
1311
1312         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1313                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1314                           dsp_out_buffer + (dsp_out_size / 2));
1315
1316         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1317                           s->inst.data + CDATA_OUT_BUF_HEAD,
1318                           dsp_out_buffer);
1319
1320         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1321                           s->inst.data + CDATA_OUT_BUF_TAIL,
1322                           dsp_out_buffer);
1323 }
1324
1325 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1326                               struct snd_pcm_runtime *runtime)
1327 {
1328         u32 freq;
1329
1330         /*
1331          * put us in the lists if we're not already there
1332          */
1333         if (! s->in_lists) {
1334                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1335                                               s->inst.data >> DP_SHIFT_COUNT);
1336                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1337                                               s->inst.data >> DP_SHIFT_COUNT);
1338                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1339                                               s->inst.data >> DP_SHIFT_COUNT);
1340                 s->in_lists = 1;
1341         }
1342
1343         /* write to 'mono' word */
1344         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1345                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1346                           runtime->channels == 2 ? 0 : 1);
1347         /* write to '8bit' word */
1348         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1349                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1350                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1351
1352         /* set up dac/adc rate */
1353         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1354         if (freq)
1355                 freq--;
1356
1357         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1358                           s->inst.data + CDATA_FREQUENCY,
1359                           freq);
1360 }
1361
1362
1363 static const struct play_vals {
1364         u16 addr, val;
1365 } pv[] = {
1366         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1367         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1368         {SRC3_DIRECTION_OFFSET, 0} ,
1369         /* +1, +2 are stereo/16 bit */
1370         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1371         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1372         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1373         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1374         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1375         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1376         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1377         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1378         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1379         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1380         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1381         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1382         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1383         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1384         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1385         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1386         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1387 };
1388
1389
1390 /* the mode passed should be already shifted and masked */
1391 static void
1392 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1393                       struct snd_pcm_substream *subs)
1394 {
1395         unsigned int i;
1396
1397         /*
1398          * some per client initializers
1399          */
1400
1401         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1402                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1403                           s->inst.data + 40 + 8);
1404
1405         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1406                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1407                           s->inst.code + MINISRC_COEF_LOC);
1408
1409         /* enable or disable low pass filter? */
1410         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1411                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1412                           subs->runtime->rate > 45000 ? 0xff : 0);
1413
1414         /* tell it which way dma is going? */
1415         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1416                           s->inst.data + CDATA_DMA_CONTROL,
1417                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1418
1419         /*
1420          * set an armload of static initializers
1421          */
1422         for (i = 0; i < ARRAY_SIZE(pv); i++)
1423                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1424                                   s->inst.data + pv[i].addr, pv[i].val);
1425 }
1426
1427 /*
1428  *    Native record driver
1429  */
1430 static const struct rec_vals {
1431         u16 addr, val;
1432 } rv[] = {
1433         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1434         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1435         {SRC3_DIRECTION_OFFSET, 1} ,
1436         /* +1, +2 are stereo/16 bit */
1437         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1438         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1439         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1440         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1441         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1442         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1443         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1444         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1445         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1446         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1447         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1448         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1449         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1450         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1451         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1452         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1453         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1454         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1455         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1456 };
1457
1458 static void
1459 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1460 {
1461         unsigned int i;
1462
1463         /*
1464          * some per client initializers
1465          */
1466
1467         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1468                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1469                           s->inst.data + 40 + 8);
1470
1471         /* tell it which way dma is going? */
1472         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1473                           s->inst.data + CDATA_DMA_CONTROL,
1474                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1475                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1476
1477         /*
1478          * set an armload of static initializers
1479          */
1480         for (i = 0; i < ARRAY_SIZE(rv); i++)
1481                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1482                                   s->inst.data + rv[i].addr, rv[i].val);
1483 }
1484
1485 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1486                                 struct snd_pcm_hw_params *hw_params)
1487 {
1488         struct m3_dma *s = substream->runtime->private_data;
1489         int err;
1490
1491         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1492                 return err;
1493         /* set buffer address */
1494         s->buffer_addr = substream->runtime->dma_addr;
1495         if (s->buffer_addr & 0x3) {
1496                 snd_printk(KERN_ERR "oh my, not aligned\n");
1497                 s->buffer_addr = s->buffer_addr & ~0x3;
1498         }
1499         return 0;
1500 }
1501
1502 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1503 {
1504         struct m3_dma *s;
1505
1506         if (substream->runtime->private_data == NULL)
1507                 return 0;
1508         s = substream->runtime->private_data;
1509         snd_pcm_lib_free_pages(substream);
1510         s->buffer_addr = 0;
1511         return 0;
1512 }
1513
1514 static int
1515 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1516 {
1517         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1518         struct snd_pcm_runtime *runtime = subs->runtime;
1519         struct m3_dma *s = runtime->private_data;
1520
1521         snd_assert(s != NULL, return -ENXIO);
1522
1523         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1524             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1525                 return -EINVAL;
1526         if (runtime->rate > 48000 ||
1527             runtime->rate < 8000)
1528                 return -EINVAL;
1529
1530         spin_lock_irq(&chip->reg_lock);
1531
1532         snd_m3_pcm_setup1(chip, s, subs);
1533
1534         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1535                 snd_m3_playback_setup(chip, s, subs);
1536         else
1537                 snd_m3_capture_setup(chip, s, subs);
1538
1539         snd_m3_pcm_setup2(chip, s, runtime);
1540
1541         spin_unlock_irq(&chip->reg_lock);
1542
1543         return 0;
1544 }
1545
1546 /*
1547  * get current pointer
1548  */
1549 static unsigned int
1550 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1551 {
1552         u16 hi = 0, lo = 0;
1553         int retry = 10;
1554         u32 addr;
1555
1556         /*
1557          * try and get a valid answer
1558          */
1559         while (retry--) {
1560                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1561                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1562
1563                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1564                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1565
1566                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1567                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1568                         break;
1569         }
1570         addr = lo | ((u32)hi<<16);
1571         return (unsigned int)(addr - s->buffer_addr);
1572 }
1573
1574 static snd_pcm_uframes_t
1575 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1576 {
1577         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1578         unsigned int ptr;
1579         struct m3_dma *s = subs->runtime->private_data;
1580         snd_assert(s != NULL, return 0);
1581
1582         spin_lock(&chip->reg_lock);
1583         ptr = snd_m3_get_pointer(chip, s, subs);
1584         spin_unlock(&chip->reg_lock);
1585         return bytes_to_frames(subs->runtime, ptr);
1586 }
1587
1588
1589 /* update pointer */
1590 /* spinlock held! */
1591 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1592 {
1593         struct snd_pcm_substream *subs = s->substream;
1594         unsigned int hwptr;
1595         int diff;
1596
1597         if (! s->running)
1598                 return;
1599
1600         hwptr = snd_m3_get_pointer(chip, s, subs);
1601
1602         /* try to avoid expensive modulo divisions */
1603         if (hwptr >= s->dma_size)
1604                 hwptr %= s->dma_size;
1605
1606         diff = s->dma_size + hwptr - s->hwptr;
1607         if (diff >= s->dma_size)
1608                 diff %= s->dma_size;
1609
1610         s->hwptr = hwptr;
1611         s->count += diff;
1612
1613         if (s->count >= (signed)s->period_size) {
1614
1615                 if (s->count < 2 * (signed)s->period_size)
1616                         s->count -= (signed)s->period_size;
1617                 else
1618                         s->count %= s->period_size;
1619
1620                 spin_unlock(&chip->reg_lock);
1621                 snd_pcm_period_elapsed(subs);
1622                 spin_lock(&chip->reg_lock);
1623         }
1624 }
1625
1626 static void snd_m3_update_hw_volume(unsigned long private_data)
1627 {
1628         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1629         int x, val;
1630         unsigned long flags;
1631
1632         /* Figure out which volume control button was pushed,
1633            based on differences from the default register
1634            values. */
1635         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1636
1637         /* Reset the volume control registers. */
1638         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1639         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1640         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1641         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1642
1643         if (!chip->master_switch || !chip->master_volume)
1644                 return;
1645
1646         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1647         spin_lock_irqsave(&chip->ac97_lock, flags);
1648
1649         val = chip->ac97->regs[AC97_MASTER_VOL];
1650         switch (x) {
1651         case 0x88:
1652                 /* mute */
1653                 val ^= 0x8000;
1654                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1655                 outw(val, chip->iobase + CODEC_DATA);
1656                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1657                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1658                                &chip->master_switch->id);
1659                 break;
1660         case 0xaa:
1661                 /* volume up */
1662                 if ((val & 0x7f) > 0)
1663                         val--;
1664                 if ((val & 0x7f00) > 0)
1665                         val -= 0x0100;
1666                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1667                 outw(val, chip->iobase + CODEC_DATA);
1668                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1669                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1670                                &chip->master_volume->id);
1671                 break;
1672         case 0x66:
1673                 /* volume down */
1674                 if ((val & 0x7f) < 0x1f)
1675                         val++;
1676                 if ((val & 0x7f00) < 0x1f00)
1677                         val += 0x0100;
1678                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1679                 outw(val, chip->iobase + CODEC_DATA);
1680                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1681                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1682                                &chip->master_volume->id);
1683                 break;
1684         }
1685         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1686 }
1687
1688 static irqreturn_t
1689 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1690 {
1691         struct snd_m3 *chip = dev_id;
1692         u8 status;
1693         int i;
1694
1695         status = inb(chip->iobase + HOST_INT_STATUS);
1696
1697         if (status == 0xff)
1698                 return IRQ_NONE;
1699
1700         if (status & HV_INT_PENDING)
1701                 tasklet_hi_schedule(&chip->hwvol_tq);
1702
1703         /*
1704          * ack an assp int if its running
1705          * and has an int pending
1706          */
1707         if (status & ASSP_INT_PENDING) {
1708                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1709                 if (!(ctl & STOP_ASSP_CLOCK)) {
1710                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1711                         if (ctl & DSP2HOST_REQ_TIMER) {
1712                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1713                                 /* update adc/dac info if it was a timer int */
1714                                 spin_lock(&chip->reg_lock);
1715                                 for (i = 0; i < chip->num_substreams; i++) {
1716                                         struct m3_dma *s = &chip->substreams[i];
1717                                         if (s->running)
1718                                                 snd_m3_update_ptr(chip, s);
1719                                 }
1720                                 spin_unlock(&chip->reg_lock);
1721                         }
1722                 }
1723         }
1724
1725 #if 0 /* TODO: not supported yet */
1726         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1727                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1728 #endif
1729
1730         /* ack ints */
1731         outb(status, chip->iobase + HOST_INT_STATUS);
1732
1733         return IRQ_HANDLED;
1734 }
1735
1736
1737 /*
1738  */
1739
1740 static struct snd_pcm_hardware snd_m3_playback =
1741 {
1742         .info =                 (SNDRV_PCM_INFO_MMAP |
1743                                  SNDRV_PCM_INFO_INTERLEAVED |
1744                                  SNDRV_PCM_INFO_MMAP_VALID |
1745                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1746                                  /*SNDRV_PCM_INFO_PAUSE |*/
1747                                  SNDRV_PCM_INFO_RESUME),
1748         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1749         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1750         .rate_min =             8000,
1751         .rate_max =             48000,
1752         .channels_min =         1,
1753         .channels_max =         2,
1754         .buffer_bytes_max =     (512*1024),
1755         .period_bytes_min =     64,
1756         .period_bytes_max =     (512*1024),
1757         .periods_min =          1,
1758         .periods_max =          1024,
1759 };
1760
1761 static struct snd_pcm_hardware snd_m3_capture =
1762 {
1763         .info =                 (SNDRV_PCM_INFO_MMAP |
1764                                  SNDRV_PCM_INFO_INTERLEAVED |
1765                                  SNDRV_PCM_INFO_MMAP_VALID |
1766                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1767                                  /*SNDRV_PCM_INFO_PAUSE |*/
1768                                  SNDRV_PCM_INFO_RESUME),
1769         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1770         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1771         .rate_min =             8000,
1772         .rate_max =             48000,
1773         .channels_min =         1,
1774         .channels_max =         2,
1775         .buffer_bytes_max =     (512*1024),
1776         .period_bytes_min =     64,
1777         .period_bytes_max =     (512*1024),
1778         .periods_min =          1,
1779         .periods_max =          1024,
1780 };
1781
1782
1783 /*
1784  */
1785
1786 static int
1787 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1788 {
1789         int i;
1790         struct m3_dma *s;
1791
1792         spin_lock_irq(&chip->reg_lock);
1793         for (i = 0; i < chip->num_substreams; i++) {
1794                 s = &chip->substreams[i];
1795                 if (! s->opened)
1796                         goto __found;
1797         }
1798         spin_unlock_irq(&chip->reg_lock);
1799         return -ENOMEM;
1800 __found:
1801         s->opened = 1;
1802         s->running = 0;
1803         spin_unlock_irq(&chip->reg_lock);
1804
1805         subs->runtime->private_data = s;
1806         s->substream = subs;
1807
1808         /* set list owners */
1809         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1810                 s->index_list[0] = &chip->mixer_list;
1811         } else
1812                 s->index_list[0] = &chip->adc1_list;
1813         s->index_list[1] = &chip->msrc_list;
1814         s->index_list[2] = &chip->dma_list;
1815
1816         return 0;
1817 }
1818
1819 static void
1820 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1821 {
1822         struct m3_dma *s = subs->runtime->private_data;
1823
1824         if (s == NULL)
1825                 return; /* not opened properly */
1826
1827         spin_lock_irq(&chip->reg_lock);
1828         if (s->substream && s->running)
1829                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1830         if (s->in_lists) {
1831                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1832                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1833                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1834                 s->in_lists = 0;
1835         }
1836         s->running = 0;
1837         s->opened = 0;
1838         spin_unlock_irq(&chip->reg_lock);
1839 }
1840
1841 static int
1842 snd_m3_playback_open(struct snd_pcm_substream *subs)
1843 {
1844         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1845         struct snd_pcm_runtime *runtime = subs->runtime;
1846         int err;
1847
1848         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1849                 return err;
1850
1851         runtime->hw = snd_m3_playback;
1852         snd_pcm_set_sync(subs);
1853
1854         return 0;
1855 }
1856
1857 static int
1858 snd_m3_playback_close(struct snd_pcm_substream *subs)
1859 {
1860         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1861
1862         snd_m3_substream_close(chip, subs);
1863         return 0;
1864 }
1865
1866 static int
1867 snd_m3_capture_open(struct snd_pcm_substream *subs)
1868 {
1869         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1870         struct snd_pcm_runtime *runtime = subs->runtime;
1871         int err;
1872
1873         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1874                 return err;
1875
1876         runtime->hw = snd_m3_capture;
1877         snd_pcm_set_sync(subs);
1878
1879         return 0;
1880 }
1881
1882 static int
1883 snd_m3_capture_close(struct snd_pcm_substream *subs)
1884 {
1885         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1886
1887         snd_m3_substream_close(chip, subs);
1888         return 0;
1889 }
1890
1891 /*
1892  * create pcm instance
1893  */
1894
1895 static struct snd_pcm_ops snd_m3_playback_ops = {
1896         .open =         snd_m3_playback_open,
1897         .close =        snd_m3_playback_close,
1898         .ioctl =        snd_pcm_lib_ioctl,
1899         .hw_params =    snd_m3_pcm_hw_params,
1900         .hw_free =      snd_m3_pcm_hw_free,
1901         .prepare =      snd_m3_pcm_prepare,
1902         .trigger =      snd_m3_pcm_trigger,
1903         .pointer =      snd_m3_pcm_pointer,
1904 };
1905
1906 static struct snd_pcm_ops snd_m3_capture_ops = {
1907         .open =         snd_m3_capture_open,
1908         .close =        snd_m3_capture_close,
1909         .ioctl =        snd_pcm_lib_ioctl,
1910         .hw_params =    snd_m3_pcm_hw_params,
1911         .hw_free =      snd_m3_pcm_hw_free,
1912         .prepare =      snd_m3_pcm_prepare,
1913         .trigger =      snd_m3_pcm_trigger,
1914         .pointer =      snd_m3_pcm_pointer,
1915 };
1916
1917 static int __devinit
1918 snd_m3_pcm(struct snd_m3 * chip, int device)
1919 {
1920         struct snd_pcm *pcm;
1921         int err;
1922
1923         err = snd_pcm_new(chip->card, chip->card->driver, device,
1924                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1925         if (err < 0)
1926                 return err;
1927
1928         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1929         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1930
1931         pcm->private_data = chip;
1932         pcm->info_flags = 0;
1933         strcpy(pcm->name, chip->card->driver);
1934         chip->pcm = pcm;
1935
1936         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1937                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1938
1939         return 0;
1940 }
1941
1942
1943 /*
1944  * ac97 interface
1945  */
1946
1947 /*
1948  * Wait for the ac97 serial bus to be free.
1949  * return nonzero if the bus is still busy.
1950  */
1951 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1952 {
1953         int i = 10000;
1954
1955         do {
1956                 if (! (snd_m3_inb(chip, 0x30) & 1))
1957                         return 0;
1958                 cpu_relax();
1959         } while (i-- > 0);
1960
1961         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1962         return 1;
1963 }
1964
1965 static unsigned short
1966 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1967 {
1968         struct snd_m3 *chip = ac97->private_data;
1969         unsigned long flags;
1970         unsigned short data = 0xffff;
1971
1972         if (snd_m3_ac97_wait(chip))
1973                 goto fail;
1974         spin_lock_irqsave(&chip->ac97_lock, flags);
1975         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1976         if (snd_m3_ac97_wait(chip))
1977                 goto fail_unlock;
1978         data = snd_m3_inw(chip, CODEC_DATA);
1979 fail_unlock:
1980         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1981 fail:
1982         return data;
1983 }
1984
1985 static void
1986 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1987 {
1988         struct snd_m3 *chip = ac97->private_data;
1989         unsigned long flags;
1990
1991         if (snd_m3_ac97_wait(chip))
1992                 return;
1993         spin_lock_irqsave(&chip->ac97_lock, flags);
1994         snd_m3_outw(chip, val, CODEC_DATA);
1995         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1996         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1997 }
1998
1999
2000 static void snd_m3_remote_codec_config(int io, int isremote)
2001 {
2002         isremote = isremote ? 1 : 0;
2003
2004         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2005              io + RING_BUS_CTRL_B);
2006         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2007              io + SDO_OUT_DEST_CTRL);
2008         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2009              io + SDO_IN_DEST_CTRL);
2010 }
2011
2012 /*
2013  * hack, returns non zero on err
2014  */
2015 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2016 {
2017         u16 ret;
2018
2019         if (snd_m3_ac97_wait(chip))
2020                 return 1;
2021
2022         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2023
2024         if (snd_m3_ac97_wait(chip))
2025                 return 1;
2026
2027         ret = snd_m3_inw(chip, 0x32);
2028
2029         return (ret == 0) || (ret == 0xffff);
2030 }
2031
2032 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2033 {
2034         u16 dir;
2035         int delay1 = 0, delay2 = 0, i;
2036         int io = chip->iobase;
2037
2038         if (chip->allegro_flag) {
2039                 /*
2040                  * the onboard codec on the allegro seems
2041                  * to want to wait a very long time before
2042                  * coming back to life
2043                  */
2044                 delay1 = 50;
2045                 delay2 = 800;
2046         } else {
2047                 /* maestro3 */
2048                 delay1 = 20;
2049                 delay2 = 500;
2050         }
2051
2052         for (i = 0; i < 5; i++) {
2053                 dir = inw(io + GPIO_DIRECTION);
2054                 if (! chip->quirk || ! chip->quirk->irda_workaround)
2055                         dir |= 0x10; /* assuming pci bus master? */
2056
2057                 snd_m3_remote_codec_config(io, 0);
2058
2059                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2060                 udelay(20);
2061
2062                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2063                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2064                 outw(0, io + GPIO_DATA);
2065                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2066
2067                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2068
2069                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2070                 udelay(5);
2071                 /* ok, bring back the ac-link */
2072                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2073                 outw(~0, io + GPIO_MASK);
2074
2075                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2076
2077                 if (! snd_m3_try_read_vendor(chip))
2078                         break;
2079
2080                 delay1 += 10;
2081                 delay2 += 100;
2082
2083                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2084                            delay1, delay2);
2085         }
2086
2087 #if 0
2088         /* more gung-ho reset that doesn't
2089          * seem to work anywhere :)
2090          */
2091         tmp = inw(io + RING_BUS_CTRL_A);
2092         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2093         msleep(20);
2094         outw(tmp, io + RING_BUS_CTRL_A);
2095         msleep(50);
2096 #endif
2097 }
2098
2099 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2100 {
2101         struct snd_ac97_bus *pbus;
2102         struct snd_ac97_template ac97;
2103         struct snd_ctl_elem_id id;
2104         int err;
2105         static struct snd_ac97_bus_ops ops = {
2106                 .write = snd_m3_ac97_write,
2107                 .read = snd_m3_ac97_read,
2108         };
2109
2110         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2111                 return err;
2112
2113         memset(&ac97, 0, sizeof(ac97));
2114         ac97.private_data = chip;
2115         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2116                 return err;
2117
2118         /* seems ac97 PCM needs initialization.. hack hack.. */
2119         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2120         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2121         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2122
2123         memset(&id, 0, sizeof(id));
2124         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2125         strcpy(id.name, "Master Playback Switch");
2126         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2127         memset(&id, 0, sizeof(id));
2128         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2129         strcpy(id.name, "Master Playback Volume");
2130         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2131
2132         return 0;
2133 }
2134
2135
2136 /*
2137  * DSP Code images
2138  */
2139
2140 static const u16 assp_kernel_image[] = {
2141     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2142     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2143     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2144     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2145     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2146     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2147     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2148     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2149     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2150     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2151     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2152     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2153     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2154     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2155     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2156     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2157     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2158     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2159     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2160     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2161     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2162     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2163     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2164     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2165     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2166     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2167     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2168     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2169     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2170     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2171     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2172     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2173     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2174     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2175     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2176     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2177     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2178     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2179     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2180     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2181     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2182     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2183     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2184     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2185     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2186     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2187     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2188     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2189     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2190     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2191     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2192     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2193     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2194     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2195     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2196     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2197     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2198     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2199     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2200     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2201     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2202     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2203     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2204     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2205     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2206     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2207     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2208     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2209     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2210     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2211     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2212     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2213     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2214     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2215     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2216     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2217     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2218     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2219     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2220     0xBE3A,
2221 };
2222
2223 /*
2224  * Mini sample rate converter code image
2225  * that is to be loaded at 0x400 on the DSP.
2226  */
2227 static const u16 assp_minisrc_image[] = {
2228
2229     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2230     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2231     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2232     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2233     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2234     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2235     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2236     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2237     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2238     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2239     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2240     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2241     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2242     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2243     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2244     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2245     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2246     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2247     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2248     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2249     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2250     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2251     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2252     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2253     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2254     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2255     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2256     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2257     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2258     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2259     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2260     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2261     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2262 };
2263
2264
2265 /*
2266  * initialize ASSP
2267  */
2268
2269 #define MINISRC_LPF_LEN 10
2270 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2271         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2272         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2273 };
2274
2275 static void snd_m3_assp_init(struct snd_m3 *chip)
2276 {
2277         unsigned int i;
2278
2279         /* zero kernel data */
2280         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2281                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2282                                   KDATA_BASE_ADDR + i, 0);
2283
2284         /* zero mixer data? */
2285         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2286                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2287                                   KDATA_BASE_ADDR2 + i, 0);
2288
2289         /* init dma pointer */
2290         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2291                           KDATA_CURRENT_DMA,
2292                           KDATA_DMA_XFER0);
2293
2294         /* write kernel into code memory.. */
2295         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2296                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2297                                   REV_B_CODE_MEMORY_BEGIN + i,
2298                                   assp_kernel_image[i]);
2299         }
2300
2301         /*
2302          * We only have this one client and we know that 0x400
2303          * is free in our kernel's mem map, so lets just
2304          * drop it there.  It seems that the minisrc doesn't
2305          * need vectors, so we won't bother with them..
2306          */
2307         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2308                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2309                                   0x400 + i,
2310                                   assp_minisrc_image[i]);
2311         }
2312
2313         /*
2314          * write the coefficients for the low pass filter?
2315          */
2316         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2317                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2318                                   0x400 + MINISRC_COEF_LOC + i,
2319                                   minisrc_lpf[i]);
2320         }
2321
2322         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2323                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2324                           0x8000);
2325
2326         /*
2327          * the minisrc is the only thing on
2328          * our task list..
2329          */
2330         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2331                           KDATA_TASK0,
2332                           0x400);
2333
2334         /*
2335          * init the mixer number..
2336          */
2337
2338         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2339                           KDATA_MIXER_TASK_NUMBER,0);
2340
2341         /*
2342          * EXTREME KERNEL MASTER VOLUME
2343          */
2344         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2345                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2346         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2347                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2348
2349         chip->mixer_list.curlen = 0;
2350         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2351         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2352         chip->adc1_list.curlen = 0;
2353         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2354         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2355         chip->dma_list.curlen = 0;
2356         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2357         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2358         chip->msrc_list.curlen = 0;
2359         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2360         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2361 }
2362
2363
2364 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2365 {
2366         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2367                                MINISRC_IN_BUFFER_SIZE / 2 +
2368                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2369         int address, i;
2370
2371         /*
2372          * the revb memory map has 0x1100 through 0x1c00
2373          * free.
2374          */
2375
2376         /*
2377          * align instance address to 256 bytes so that its
2378          * shifted list address is aligned.
2379          * list address = (mem address >> 1) >> 7;
2380          */
2381         data_bytes = (data_bytes + 255) & ~255;
2382         address = 0x1100 + ((data_bytes/2) * index);
2383
2384         if ((address + (data_bytes/2)) >= 0x1c00) {
2385                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2386                            data_bytes, index, address);
2387                 return -ENOMEM;
2388         }
2389
2390         s->number = index;
2391         s->inst.code = 0x400;
2392         s->inst.data = address;
2393
2394         for (i = data_bytes / 2; i > 0; address++, i--) {
2395                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2396                                   address, 0);
2397         }
2398
2399         return 0;
2400 }
2401
2402
2403 /*
2404  * this works for the reference board, have to find
2405  * out about others
2406  *
2407  * this needs more magic for 4 speaker, but..
2408  */
2409 static void
2410 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2411 {
2412         int io = chip->iobase;
2413         u16 gpo, polarity;
2414
2415         if (! chip->external_amp)
2416                 return;
2417
2418         polarity = enable ? 0 : 1;
2419         polarity = polarity << chip->amp_gpio;
2420         gpo = 1 << chip->amp_gpio;
2421
2422         outw(~gpo, io + GPIO_MASK);
2423
2424         outw(inw(io + GPIO_DIRECTION) | gpo,
2425              io + GPIO_DIRECTION);
2426
2427         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2428              io + GPIO_DATA);
2429
2430         outw(0xffff, io + GPIO_MASK);
2431 }
2432
2433 static int
2434 snd_m3_chip_init(struct snd_m3 *chip)
2435 {
2436         struct pci_dev *pcidev = chip->pci;
2437         unsigned long io = chip->iobase;
2438         u32 n;
2439         u16 w;
2440         u8 t; /* makes as much sense as 'n', no? */
2441
2442         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2443         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2444                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2445                DISABLE_LEGACY);
2446         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2447
2448         if (chip->hv_quirk && chip->hv_quirk->is_omnibook) {
2449                 /*
2450                  * Volume buttons on some HP OmniBook laptops don't work
2451                  * correctly. This makes them work for the most part.
2452                  *
2453                  * Volume up and down buttons on the laptop side work.
2454                  * Fn+cursor_up (volme up) works.
2455                  * Fn+cursor_down (volume down) doesn't work.
2456                  * Fn+F7 (mute) works acts as volume up.
2457                  */
2458                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2459                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2460                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2461                 outw(0xffff, io + GPIO_MASK);
2462         }
2463         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2464         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2465         if (chip->hv_quirk)
2466                 n |= chip->hv_quirk->config;
2467         /* For some reason we must always use reduced debounce. */
2468         n |= REDUCED_DEBOUNCE;
2469         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2470         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2471
2472         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2473         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2474         n &= ~INT_CLK_SELECT;
2475         if (!chip->allegro_flag) {
2476                 n &= ~INT_CLK_MULT_ENABLE;
2477                 n |= INT_CLK_SRC_NOT_PCI;
2478         }
2479         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2480         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2481
2482         if (chip->allegro_flag) {
2483                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2484                 n |= IN_CLK_12MHZ_SELECT;
2485                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2486         }
2487
2488         t = inb(chip->iobase + ASSP_CONTROL_A);
2489         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2490         t |= ASSP_CLK_49MHZ_SELECT;
2491         t |= ASSP_0_WS_ENABLE;
2492         outb(t, chip->iobase + ASSP_CONTROL_A);
2493
2494         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2495         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2496
2497         outb(0x00, io + HARDWARE_VOL_CTRL);
2498         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2499         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2500         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2501         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2502
2503         return 0;
2504 }
2505
2506 static void
2507 snd_m3_enable_ints(struct snd_m3 *chip)
2508 {
2509         unsigned long io = chip->iobase;
2510         unsigned short val;
2511
2512         /* TODO: MPU401 not supported yet */
2513         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2514         if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
2515                 val |= HV_INT_ENABLE;
2516         outw(val, io + HOST_INT_CTRL);
2517         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2518              io + ASSP_CONTROL_C);
2519 }
2520
2521
2522 /*
2523  */
2524
2525 static int snd_m3_free(struct snd_m3 *chip)
2526 {
2527         struct m3_dma *s;
2528         int i;
2529
2530         if (chip->substreams) {
2531                 spin_lock_irq(&chip->reg_lock);
2532                 for (i = 0; i < chip->num_substreams; i++) {
2533                         s = &chip->substreams[i];
2534                         /* check surviving pcms; this should not happen though.. */
2535                         if (s->substream && s->running)
2536                                 snd_m3_pcm_stop(chip, s, s->substream);
2537                 }
2538                 spin_unlock_irq(&chip->reg_lock);
2539                 kfree(chip->substreams);
2540         }
2541         if (chip->iobase) {
2542                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2543         }
2544
2545 #ifdef CONFIG_PM
2546         vfree(chip->suspend_mem);
2547 #endif
2548
2549         if (chip->irq >= 0) {
2550                 synchronize_irq(chip->irq);
2551                 free_irq(chip->irq, chip);
2552         }
2553
2554         if (chip->iobase)
2555                 pci_release_regions(chip->pci);
2556
2557         pci_disable_device(chip->pci);
2558         kfree(chip);
2559         return 0;
2560 }
2561
2562
2563 /*
2564  * APM support
2565  */
2566 #ifdef CONFIG_PM
2567 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2568 {
2569         struct snd_card *card = pci_get_drvdata(pci);
2570         struct snd_m3 *chip = card->private_data;
2571         int i, index;
2572
2573         if (chip->suspend_mem == NULL)
2574                 return 0;
2575
2576         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2577         snd_pcm_suspend_all(chip->pcm);
2578         snd_ac97_suspend(chip->ac97);
2579
2580         msleep(10); /* give the assp a chance to idle.. */
2581
2582         snd_m3_assp_halt(chip);
2583
2584         /* save dsp image */
2585         index = 0;
2586         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2587                 chip->suspend_mem[index++] =
2588                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2589         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2590                 chip->suspend_mem[index++] =
2591                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2592
2593         /* power down apci registers */
2594         snd_m3_outw(chip, 0xffff, 0x54);
2595         snd_m3_outw(chip, 0xffff, 0x56);
2596
2597         pci_disable_device(pci);
2598         pci_save_state(pci);
2599         return 0;
2600 }
2601
2602 static int m3_resume(struct pci_dev *pci)
2603 {
2604         struct snd_card *card = pci_get_drvdata(pci);
2605         struct snd_m3 *chip = card->private_data;
2606         int i, index;
2607
2608         if (chip->suspend_mem == NULL)
2609                 return 0;
2610
2611         pci_restore_state(pci);
2612         pci_enable_device(pci);
2613         pci_set_master(pci);
2614
2615         /* first lets just bring everything back. .*/
2616         snd_m3_outw(chip, 0, 0x54);
2617         snd_m3_outw(chip, 0, 0x56);
2618
2619         snd_m3_chip_init(chip);
2620         snd_m3_assp_halt(chip);
2621         snd_m3_ac97_reset(chip);
2622
2623         /* restore dsp image */
2624         index = 0;
2625         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2626                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2627                                   chip->suspend_mem[index++]);
2628         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2629                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2630                                   chip->suspend_mem[index++]);
2631
2632         /* tell the dma engine to restart itself */
2633         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2634                           KDATA_DMA_ACTIVE, 0);
2635
2636         /* restore ac97 registers */
2637         snd_ac97_resume(chip->ac97);
2638
2639         snd_m3_assp_continue(chip);
2640         snd_m3_enable_ints(chip);
2641         snd_m3_amp_enable(chip, 1);
2642
2643         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2644         return 0;
2645 }
2646 #endif /* CONFIG_PM */
2647
2648
2649 /*
2650  */
2651
2652 static int snd_m3_dev_free(struct snd_device *device)
2653 {
2654         struct snd_m3 *chip = device->device_data;
2655         return snd_m3_free(chip);
2656 }
2657
2658 static int __devinit
2659 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2660               int enable_amp,
2661               int amp_gpio,
2662               struct snd_m3 **chip_ret)
2663 {
2664         struct snd_m3 *chip;
2665         int i, err;
2666         const struct m3_quirk *quirk;
2667         const struct m3_hv_quirk *hv_quirk;
2668         static struct snd_device_ops ops = {
2669                 .dev_free =     snd_m3_dev_free,
2670         };
2671
2672         *chip_ret = NULL;
2673
2674         if (pci_enable_device(pci))
2675                 return -EIO;
2676
2677         /* check, if we can restrict PCI DMA transfers to 28 bits */
2678         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2679             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2680                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2681                 pci_disable_device(pci);
2682                 return -ENXIO;
2683         }
2684
2685         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2686         if (chip == NULL) {
2687                 pci_disable_device(pci);
2688                 return -ENOMEM;
2689         }
2690
2691         spin_lock_init(&chip->reg_lock);
2692         spin_lock_init(&chip->ac97_lock);
2693
2694         switch (pci->device) {
2695         case PCI_DEVICE_ID_ESS_ALLEGRO:
2696         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2697         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2698         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2699                 chip->allegro_flag = 1;
2700                 break;
2701         }
2702
2703         chip->card = card;
2704         chip->pci = pci;
2705         chip->irq = -1;
2706
2707         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2708                 if (pci->subsystem_vendor == quirk->vendor &&
2709                     pci->subsystem_device == quirk->device) {
2710                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2711                         chip->quirk = quirk;
2712                         break;
2713                 }
2714         }
2715
2716         for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) {
2717                 if (pci->vendor == hv_quirk->vendor &&
2718                     pci->device == hv_quirk->device &&
2719                     pci->subsystem_vendor == hv_quirk->subsystem_vendor &&
2720                     pci->subsystem_device == hv_quirk->subsystem_device) {
2721                         chip->hv_quirk = hv_quirk;
2722                         break;
2723                 }
2724         }
2725
2726         chip->external_amp = enable_amp;
2727         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2728                 chip->amp_gpio = amp_gpio;
2729         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2730                 chip->amp_gpio = chip->quirk->amp_gpio;
2731         else if (chip->allegro_flag)
2732                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2733         else /* presumably this is for all 'maestro3's.. */
2734                 chip->amp_gpio = GPO_EXT_AMP_M3;
2735
2736         chip->num_substreams = NR_DSPS;
2737         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2738                                    GFP_KERNEL);
2739         if (chip->substreams == NULL) {
2740                 kfree(chip);
2741                 pci_disable_device(pci);
2742                 return -ENOMEM;
2743         }
2744
2745         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2746                 snd_m3_free(chip);
2747                 return err;
2748         }
2749         chip->iobase = pci_resource_start(pci, 0);
2750
2751         /* just to be sure */
2752         pci_set_master(pci);
2753
2754         snd_m3_chip_init(chip);
2755         snd_m3_assp_halt(chip);
2756
2757         snd_m3_ac97_reset(chip);
2758
2759         snd_m3_amp_enable(chip, 1);
2760
2761         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2762
2763         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_DISABLED|IRQF_SHARED,
2764                         card->driver, chip)) {
2765                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2766                 snd_m3_free(chip);
2767                 return -ENOMEM;
2768         }
2769         chip->irq = pci->irq;
2770
2771 #ifdef CONFIG_PM
2772         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2773         if (chip->suspend_mem == NULL)
2774                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2775 #endif
2776
2777         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2778                 snd_m3_free(chip);
2779                 return err;
2780         }
2781
2782         if ((err = snd_m3_mixer(chip)) < 0)
2783                 return err;
2784
2785         for (i = 0; i < chip->num_substreams; i++) {
2786                 struct m3_dma *s = &chip->substreams[i];
2787                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2788                         return err;
2789         }
2790
2791         if ((err = snd_m3_pcm(chip, 0)) < 0)
2792                 return err;
2793
2794         snd_m3_enable_ints(chip);
2795         snd_m3_assp_continue(chip);
2796
2797         snd_card_set_dev(card, &pci->dev);
2798
2799         *chip_ret = chip;
2800
2801         return 0;
2802 }
2803
2804 /*
2805  */
2806 static int __devinit
2807 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2808 {
2809         static int dev;
2810         struct snd_card *card;
2811         struct snd_m3 *chip;
2812         int err;
2813
2814         /* don't pick up modems */
2815         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2816                 return -ENODEV;
2817
2818         if (dev >= SNDRV_CARDS)
2819                 return -ENODEV;
2820         if (!enable[dev]) {
2821                 dev++;
2822                 return -ENOENT;
2823         }
2824
2825         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2826         if (card == NULL)
2827                 return -ENOMEM;
2828
2829         switch (pci->device) {
2830         case PCI_DEVICE_ID_ESS_ALLEGRO:
2831         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2832                 strcpy(card->driver, "Allegro");
2833                 break;
2834         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2835         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2836                 strcpy(card->driver, "Canyon3D-2");
2837                 break;
2838         default:
2839                 strcpy(card->driver, "Maestro3");
2840                 break;
2841         }
2842
2843         if ((err = snd_m3_create(card, pci,
2844                                  external_amp[dev],
2845                                  amp_gpio[dev],
2846                                  &chip)) < 0) {
2847                 snd_card_free(card);
2848                 return err;
2849         }
2850         card->private_data = chip;
2851
2852         sprintf(card->shortname, "ESS %s PCI", card->driver);
2853         sprintf(card->longname, "%s at 0x%lx, irq %d",
2854                 card->shortname, chip->iobase, chip->irq);
2855
2856         if ((err = snd_card_register(card)) < 0) {
2857                 snd_card_free(card);
2858                 return err;
2859         }
2860
2861 #if 0 /* TODO: not supported yet */
2862         /* TODO enable MIDI IRQ and I/O */
2863         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2864                                   chip->iobase + MPU401_DATA_PORT,
2865                                   MPU401_INFO_INTEGRATED,
2866                                   chip->irq, 0, &chip->rmidi);
2867         if (err < 0)
2868                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2869 #endif
2870
2871         pci_set_drvdata(pci, card);
2872         dev++;
2873         return 0;
2874 }
2875
2876 static void __devexit snd_m3_remove(struct pci_dev *pci)
2877 {
2878         snd_card_free(pci_get_drvdata(pci));
2879         pci_set_drvdata(pci, NULL);
2880 }
2881
2882 static struct pci_driver driver = {
2883         .name = "Maestro3",
2884         .id_table = snd_m3_ids,
2885         .probe = snd_m3_probe,
2886         .remove = __devexit_p(snd_m3_remove),
2887 #ifdef CONFIG_PM
2888         .suspend = m3_suspend,
2889         .resume = m3_resume,
2890 #endif
2891 };
2892
2893 static int __init alsa_card_m3_init(void)
2894 {
2895         return pci_register_driver(&driver);
2896 }
2897
2898 static void __exit alsa_card_m3_exit(void)
2899 {
2900         pci_unregister_driver(&driver);
2901 }
2902
2903 module_init(alsa_card_m3_init)
2904 module_exit(alsa_card_m3_exit)