sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 142 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 143 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 144 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 145 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 146 #define ICH6_REG_VMIN                   0x02
 147 #define ICH6_REG_VMAJ                   0x03
 148 #define ICH6_REG_OUTPAY                 0x04
 149 #define ICH6_REG_INPAY                  0x06
 150 #define ICH6_REG_GCTL                   0x08
 151 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 152 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 153 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 154 #define ICH6_REG_WAKEEN                 0x0c
 155 #define ICH6_REG_STATESTS               0x0e
 156 #define ICH6_REG_GSTS                   0x10
 157 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 158 #define ICH6_REG_INTCTL                 0x20
 159 #define ICH6_REG_INTSTS                 0x24
 160 #define ICH6_REG_WALCLK                 0x30
 161 #define ICH6_REG_SYNC                   0x34
 162 #define ICH6_REG_CORBLBASE              0x40
 163 #define ICH6_REG_CORBUBASE              0x44
 164 #define ICH6_REG_CORBWP                 0x48
 165 #define ICH6_REG_CORBRP                 0x4a
 166 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 167 #define ICH6_REG_CORBCTL                0x4c
 168 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 169 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 170 #define ICH6_REG_CORBSTS                0x4d
 171 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 172 #define ICH6_REG_CORBSIZE               0x4e
 173
 174 #define ICH6_REG_RIRBLBASE              0x50
 175 #define ICH6_REG_RIRBUBASE              0x54
 176 #define ICH6_REG_RIRBWP                 0x58
 177 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 178 #define ICH6_REG_RINTCNT                0x5a
 179 #define ICH6_REG_RIRBCTL                0x5c
 180 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 181 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 182 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 183 #define ICH6_REG_RIRBSTS                0x5d
 184 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 185 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 186 #define ICH6_REG_RIRBSIZE               0x5e
 187
 188 #define ICH6_REG_IC                     0x60
 189 #define ICH6_REG_IR                     0x64
 190 #define ICH6_REG_IRS                    0x68
 191 #define   ICH6_IRS_VALID        (1<<1)
 192 #define   ICH6_IRS_BUSY         (1<<0)
 193
 194 #define ICH6_REG_DPLBASE                0x70
 195 #define ICH6_REG_DPUBASE                0x74
 196 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 197
 198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 200
 201 /* stream register offsets from stream base */
 202 #define ICH6_REG_SD_CTL                 0x00
 203 #define ICH6_REG_SD_STS                 0x03
 204 #define ICH6_REG_SD_LPIB                0x04
 205 #define ICH6_REG_SD_CBL                 0x08
 206 #define ICH6_REG_SD_LVI                 0x0c
 207 #define ICH6_REG_SD_FIFOW               0x0e
 208 #define ICH6_REG_SD_FIFOSIZE            0x10
 209 #define ICH6_REG_SD_FORMAT              0x12
 210 #define ICH6_REG_SD_BDLPL               0x18
 211 #define ICH6_REG_SD_BDLPU               0x1c
 212
 213 /* PCI space */
 214 #define ICH6_PCIREG_TCSEL       0x44
 215
 216 /*
 217  * other constants
 218  */
 219
 220 /* max number of SDs */
 221 /* ICH, ATI and VIA have 4 playback and 4 capture */
 222 #define ICH6_NUM_CAPTURE        4
 223 #define ICH6_NUM_PLAYBACK       4
 224
 225 /* ULI has 6 playback and 5 capture */
 226 #define ULI_NUM_CAPTURE         5
 227 #define ULI_NUM_PLAYBACK        6
 228
 229 /* ATI HDMI has 1 playback and 0 capture */
 230 #define ATIHDMI_NUM_CAPTURE     0
 231 #define ATIHDMI_NUM_PLAYBACK    1
 232
 233 /* TERA has 4 playback and 3 capture */
 234 #define TERA_NUM_CAPTURE        3
 235 #define TERA_NUM_PLAYBACK       4
 236
 237 /* this number is statically defined for simplicity */
 238 #define MAX_AZX_DEV             16
 239
 240 /* max number of fragments - we may use more if allocating more pages for BDL */
 241 #define BDL_SIZE                4096
 242 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 243 #define AZX_MAX_FRAG            32
 244 /* max buffer size - no h/w limit, you can increase as you like */
 245 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 246 /* max number of PCM devics per card */
 247 #define AZX_MAX_PCMS            8
 248
 249 /* RIRB int mask: overrun[2], response[0] */
 250 #define RIRB_INT_RESPONSE       0x01
 251 #define RIRB_INT_OVERRUN        0x04
 252 #define RIRB_INT_MASK           0x05
 253
 254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 255 #define AZX_MAX_CODECS          4
 256 #define STATESTS_INT_MASK       0x0f
 257
 258 /* SD_CTL bits */
 259 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 260 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 261 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 262 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 263 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 264 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 265 #define SD_CTL_STREAM_TAG_SHIFT 20
 266
 267 /* SD_CTL and SD_STS */
 268 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 269 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 270 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 271 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 272                                  SD_INT_COMPLETE)
 273
 274 /* SD_STS */
 275 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 276
 277 /* INTCTL and INTSTS */
 278 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 279 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 280 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 281
 282 /* below are so far hardcoded - should read registers in future */
 283 #define ICH6_MAX_CORB_ENTRIES   256
 284 #define ICH6_MAX_RIRB_ENTRIES   256
 285
 286 /* position fix mode */
 287 enum {
 288         POS_FIX_AUTO,
 289         POS_FIX_LPIB,
 290         POS_FIX_POSBUF,
 291 };
 292
 293 /* Defines for ATI HD Audio support in SB450 south bridge */
 294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 296
 297 /* Defines for Nvidia HDA support */
 298 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 299 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 300 #define NVIDIA_HDA_ISTRM_COH          0x4d
 301 #define NVIDIA_HDA_OSTRM_COH          0x4c
 302 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 303
 304 /* Defines for Intel SCH HDA snoop control */
 305 #define INTEL_SCH_HDA_DEVC      0x78
 306 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 307
 308 /* Define IN stream 0 FIFO size offset in VIA controller */
 309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 310 /* Define VIA HD Audio Device ID*/
 311 #define VIA_HDAC_DEVICE_ID              0x3288
 312
 313 /* HD Audio class code */
 314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 315
 316 /*
 317  */
 318
 319 struct azx_dev {
 320         struct snd_dma_buffer bdl; /* BDL buffer */
 321         u32 *posbuf;            /* position buffer pointer */
 322
 323         unsigned int bufsize;   /* size of the play buffer in bytes */
 324         unsigned int period_bytes; /* size of the period in bytes */
 325         unsigned int frags;     /* number for period in the play buffer */
 326         unsigned int fifo_size; /* FIFO size */
 327         unsigned long start_jiffies;    /* start + minimum jiffies */
 328         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 329
 330         void __iomem *sd_addr;  /* stream descriptor pointer */
 331
 332         u32 sd_int_sta_mask;    /* stream int status mask */
 333
 334         /* pcm support */
 335         struct snd_pcm_substream *substream;    /* assigned substream,
 336                                                  * set in PCM open
 337                                                  */
 338         unsigned int format_val;        /* format value to be set in the
 339                                          * controller and the codec
 340                                          */
 341         unsigned char stream_tag;       /* assigned stream */
 342         unsigned char index;            /* stream index */
 343
 344         unsigned int opened :1;
 345         unsigned int running :1;
 346         unsigned int irq_pending :1;
 347         unsigned int start_flag: 1;     /* stream full start flag */
 348         /*
 349          * For VIA:
 350          *  A flag to ensure DMA position is 0
 351          *  when link position is not greater than FIFO size
 352          */
 353         unsigned int insufficient :1;
 354 };
 355
 356 /* CORB/RIRB */
 357 struct azx_rb {
 358         u32 *buf;               /* CORB/RIRB buffer
 359                                  * Each CORB entry is 4byte, RIRB is 8byte
 360                                  */
 361         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 362         /* for RIRB */
 363         unsigned short rp, wp;  /* read/write pointers */
 364         int cmds;               /* number of pending requests */
 365         u32 res;                /* last read value */
 366 };
 367
 368 struct azx {
 369         struct snd_card *card;
 370         struct pci_dev *pci;
 371         int dev_index;
 372
 373         /* chip type specific */
 374         int driver_type;
 375         int playback_streams;
 376         int playback_index_offset;
 377         int capture_streams;
 378         int capture_index_offset;
 379         int num_streams;
 380
 381         /* pci resources */
 382         unsigned long addr;
 383         void __iomem *remap_addr;
 384         int irq;
 385
 386         /* locks */
 387         spinlock_t reg_lock;
 388         struct mutex open_mutex;
 389
 390         /* streams (x num_streams) */
 391         struct azx_dev *azx_dev;
 392
 393         /* PCM */
 394         struct snd_pcm *pcm[AZX_MAX_PCMS];
 395
 396         /* HD codec */
 397         unsigned short codec_mask;
 398         int  codec_probe_mask; /* copied from probe_mask option */
 399         struct hda_bus *bus;
 400
 401         /* CORB/RIRB */
 402         struct azx_rb corb;
 403         struct azx_rb rirb;
 404
 405         /* CORB/RIRB and position buffers */
 406         struct snd_dma_buffer rb;
 407         struct snd_dma_buffer posbuf;
 408
 409         /* flags */
 410         int position_fix;
 411         unsigned int running :1;
 412         unsigned int initialized :1;
 413         unsigned int single_cmd :1;
 414         unsigned int polling_mode :1;
 415         unsigned int msi :1;
 416         unsigned int irq_pending_warned :1;
 417         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 418         unsigned int probing :1; /* codec probing phase */
 419
 420         /* for debugging */
 421         unsigned int last_cmd;  /* last issued command (to sync) */
 422
 423         /* for pending irqs */
 424         struct work_struct irq_pending_work;
 425
 426         /* reboot notifier (for mysterious hangup problem at power-down) */
 427         struct notifier_block reboot_notifier;
 428 };
 429
 430 /* driver types */
 431 enum {
 432         AZX_DRIVER_ICH,
 433         AZX_DRIVER_SCH,
 434         AZX_DRIVER_ATI,
 435         AZX_DRIVER_ATIHDMI,
 436         AZX_DRIVER_VIA,
 437         AZX_DRIVER_SIS,
 438         AZX_DRIVER_ULI,
 439         AZX_DRIVER_NVIDIA,
 440         AZX_DRIVER_TERA,
 441         AZX_DRIVER_GENERIC,
 442         AZX_NUM_DRIVERS, /* keep this as last entry */
 443 };
 444
 445 static char *driver_short_names[] __devinitdata = {
 446         [AZX_DRIVER_ICH] = "HDA Intel",
 447         [AZX_DRIVER_SCH] = "HDA Intel MID",
 448         [AZX_DRIVER_ATI] = "HDA ATI SB",
 449         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 450         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 451         [AZX_DRIVER_SIS] = "HDA SIS966",
 452         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 453         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 454         [AZX_DRIVER_TERA] = "HDA Teradici",
 455         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 456 };
 457
 458 /*
 459  * macros for easy use
 460  */
 461 #define azx_writel(chip,reg,value) \
 462         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 463 #define azx_readl(chip,reg) \
 464         readl((chip)->remap_addr + ICH6_REG_##reg)
 465 #define azx_writew(chip,reg,value) \
 466         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 467 #define azx_readw(chip,reg) \
 468         readw((chip)->remap_addr + ICH6_REG_##reg)
 469 #define azx_writeb(chip,reg,value) \
 470         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 471 #define azx_readb(chip,reg) \
 472         readb((chip)->remap_addr + ICH6_REG_##reg)
 473
 474 #define azx_sd_writel(dev,reg,value) \
 475         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 476 #define azx_sd_readl(dev,reg) \
 477         readl((dev)->sd_addr + ICH6_REG_##reg)
 478 #define azx_sd_writew(dev,reg,value) \
 479         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 480 #define azx_sd_readw(dev,reg) \
 481         readw((dev)->sd_addr + ICH6_REG_##reg)
 482 #define azx_sd_writeb(dev,reg,value) \
 483         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 484 #define azx_sd_readb(dev,reg) \
 485         readb((dev)->sd_addr + ICH6_REG_##reg)
 486
 487 /* for pcm support */
 488 #define get_azx_dev(substream) (substream->runtime->private_data)
 489
 490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 491
 492 /*
 493  * Interface for HD codec
 494  */
 495
 496 /*
 497  * CORB / RIRB interface
 498  */
 499 static int azx_alloc_cmd_io(struct azx *chip)
 500 {
 501         int err;
 502
 503         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 504         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 505                                   snd_dma_pci_data(chip->pci),
 506                                   PAGE_SIZE, &chip->rb);
 507         if (err < 0) {
 508                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 509                 return err;
 510         }
 511         return 0;
 512 }
 513
 514 static void azx_init_cmd_io(struct azx *chip)
 515 {
 516         /* CORB set up */
 517         chip->corb.addr = chip->rb.addr;
 518         chip->corb.buf = (u32 *)chip->rb.area;
 519         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 520         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 521
 522         /* set the corb size to 256 entries (ULI requires explicitly) */
 523         azx_writeb(chip, CORBSIZE, 0x02);
 524         /* set the corb write pointer to 0 */
 525         azx_writew(chip, CORBWP, 0);
 526         /* reset the corb hw read pointer */
 527         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 528         /* enable corb dma */
 529         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 530
 531         /* RIRB set up */
 532         chip->rirb.addr = chip->rb.addr + 2048;
 533         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 534         chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
 535         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 536         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 537
 538         /* set the rirb size to 256 entries (ULI requires explicitly) */
 539         azx_writeb(chip, RIRBSIZE, 0x02);
 540         /* reset the rirb hw write pointer */
 541         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 542         /* set N=1, get RIRB response interrupt for new entry */
 543         azx_writew(chip, RINTCNT, 1);
 544         /* enable rirb dma and response irq */
 545         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 546 }
 547
 548 static void azx_free_cmd_io(struct azx *chip)
 549 {
 550         /* disable ringbuffer DMAs */
 551         azx_writeb(chip, RIRBCTL, 0);
 552         azx_writeb(chip, CORBCTL, 0);
 553 }
 554
 555 /* send a command */
 556 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 557 {
 558         struct azx *chip = bus->private_data;
 559         unsigned int wp;
 560
 561         /* add command to corb */
 562         wp = azx_readb(chip, CORBWP);
 563         wp++;
 564         wp %= ICH6_MAX_CORB_ENTRIES;
 565
 566         spin_lock_irq(&chip->reg_lock);
 567         chip->rirb.cmds++;
 568         chip->corb.buf[wp] = cpu_to_le32(val);
 569         azx_writel(chip, CORBWP, wp);
 570         spin_unlock_irq(&chip->reg_lock);
 571
 572         return 0;
 573 }
 574
 575 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 576
 577 /* retrieve RIRB entry - called from interrupt handler */
 578 static void azx_update_rirb(struct azx *chip)
 579 {
 580         unsigned int rp, wp;
 581         u32 res, res_ex;
 582
 583         wp = azx_readb(chip, RIRBWP);
 584         if (wp == chip->rirb.wp)
 585                 return;
 586         chip->rirb.wp = wp;
 587
 588         while (chip->rirb.rp != wp) {
 589                 chip->rirb.rp++;
 590                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 591
 592                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 593                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 594                 res = le32_to_cpu(chip->rirb.buf[rp]);
 595                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 596                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 597                 else if (chip->rirb.cmds) {
 598                         chip->rirb.res = res;
 599                         smp_wmb();
 600                         chip->rirb.cmds--;
 601                 }
 602         }
 603 }
 604
 605 /* receive a response */
 606 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 607 {
 608         struct azx *chip = bus->private_data;
 609         unsigned long timeout;
 610
 611  again:
 612         timeout = jiffies + msecs_to_jiffies(1000);
 613         for (;;) {
 614                 if (chip->polling_mode) {
 615                         spin_lock_irq(&chip->reg_lock);
 616                         azx_update_rirb(chip);
 617                         spin_unlock_irq(&chip->reg_lock);
 618                 }
 619                 if (!chip->rirb.cmds) {
 620                         smp_rmb();
 621                         bus->rirb_error = 0;
 622                         return chip->rirb.res; /* the last value */
 623                 }
 624                 if (time_after(jiffies, timeout))
 625                         break;
 626                 if (bus->needs_damn_long_delay)
 627                         msleep(2); /* temporary workaround */
 628                 else {
 629                         udelay(10);
 630                         cond_resched();
 631                 }
 632         }
 633
 634         if (chip->msi) {
 635                 snd_printk(KERN_WARNING SFX "No response from codec, "
 636                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 637                 free_irq(chip->irq, chip);
 638                 chip->irq = -1;
 639                 pci_disable_msi(chip->pci);
 640                 chip->msi = 0;
 641                 if (azx_acquire_irq(chip, 1) < 0) {
 642                         bus->rirb_error = 1;
 643                         return -1;
 644                 }
 645                 goto again;
 646         }
 647
 648         if (!chip->polling_mode) {
 649                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 650                            "switching to polling mode: last cmd=0x%08x\n",
 651                            chip->last_cmd);
 652                 chip->polling_mode = 1;
 653                 goto again;
 654         }
 655
 656         if (chip->probing) {
 657                 /* If this critical timeout happens during the codec probing
 658                  * phase, this is likely an access to a non-existing codec
 659                  * slot.  Better to return an error and reset the system.
 660                  */
 661                 return -1;
 662         }
 663
 664         /* a fatal communication error; need either to reset or to fallback
 665          * to the single_cmd mode
 666          */
 667         bus->rirb_error = 1;
 668         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 669                 bus->response_reset = 1;
 670                 return -1; /* give a chance to retry */
 671         }
 672
 673         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 674                    "switching to single_cmd mode: last cmd=0x%08x\n",
 675                    chip->last_cmd);
 676         chip->single_cmd = 1;
 677         bus->response_reset = 0;
 678         /* re-initialize CORB/RIRB */
 679         azx_free_cmd_io(chip);
 680         azx_init_cmd_io(chip);
 681         return -1;
 682 }
 683
 684 /*
 685  * Use the single immediate command instead of CORB/RIRB for simplicity
 686  *
 687  * Note: according to Intel, this is not preferred use.  The command was
 688  *       intended for the BIOS only, and may get confused with unsolicited
 689  *       responses.  So, we shouldn't use it for normal operation from the
 690  *       driver.
 691  *       I left the codes, however, for debugging/testing purposes.
 692  */
 693
 694 /* receive a response */
 695 static int azx_single_wait_for_response(struct azx *chip)
 696 {
 697         int timeout = 50;
 698
 699         while (timeout--) {
 700                 /* check IRV busy bit */
 701                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 702                         /* reuse rirb.res as the response return value */
 703                         chip->rirb.res = azx_readl(chip, IR);
 704                         return 0;
 705                 }
 706                 udelay(1);
 707         }
 708         if (printk_ratelimit())
 709                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 710                            azx_readw(chip, IRS));
 711         chip->rirb.res = -1;
 712         return -EIO;
 713 }
 714
 715 /* send a command */
 716 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 717 {
 718         struct azx *chip = bus->private_data;
 719         int timeout = 50;
 720
 721         bus->rirb_error = 0;
 722         while (timeout--) {
 723                 /* check ICB busy bit */
 724                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 725                         /* Clear IRV valid bit */
 726                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 727                                    ICH6_IRS_VALID);
 728                         azx_writel(chip, IC, val);
 729                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 730                                    ICH6_IRS_BUSY);
 731                         return azx_single_wait_for_response(chip);
 732                 }
 733                 udelay(1);
 734         }
 735         if (printk_ratelimit())
 736                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 737                            azx_readw(chip, IRS), val);
 738         return -EIO;
 739 }
 740
 741 /* receive a response */
 742 static unsigned int azx_single_get_response(struct hda_bus *bus)
 743 {
 744         struct azx *chip = bus->private_data;
 745         return chip->rirb.res;
 746 }
 747
 748 /*
 749  * The below are the main callbacks from hda_codec.
 750  *
 751  * They are just the skeleton to call sub-callbacks according to the
 752  * current setting of chip->single_cmd.
 753  */
 754
 755 /* send a command */
 756 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 757 {
 758         struct azx *chip = bus->private_data;
 759
 760         chip->last_cmd = val;
 761         if (chip->single_cmd)
 762                 return azx_single_send_cmd(bus, val);
 763         else
 764                 return azx_corb_send_cmd(bus, val);
 765 }
 766
 767 /* get a response */
 768 static unsigned int azx_get_response(struct hda_bus *bus)
 769 {
 770         struct azx *chip = bus->private_data;
 771         if (chip->single_cmd)
 772                 return azx_single_get_response(bus);
 773         else
 774                 return azx_rirb_get_response(bus);
 775 }
 776
 777 #ifdef CONFIG_SND_HDA_POWER_SAVE
 778 static void azx_power_notify(struct hda_bus *bus);
 779 #endif
 780
 781 /* reset codec link */
 782 static int azx_reset(struct azx *chip)
 783 {
 784         int count;
 785
 786         /* clear STATESTS */
 787         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 788
 789         /* reset controller */
 790         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 791
 792         count = 50;
 793         while (azx_readb(chip, GCTL) && --count)
 794                 msleep(1);
 795
 796         /* delay for >= 100us for codec PLL to settle per spec
 797          * Rev 0.9 section 5.5.1
 798          */
 799         msleep(1);
 800
 801         /* Bring controller out of reset */
 802         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 803
 804         count = 50;
 805         while (!azx_readb(chip, GCTL) && --count)
 806                 msleep(1);
 807
 808         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 809         msleep(1);
 810
 811         /* check to see if controller is ready */
 812         if (!azx_readb(chip, GCTL)) {
 813                 snd_printd(SFX "azx_reset: controller not ready!\n");
 814                 return -EBUSY;
 815         }
 816
 817         /* Accept unsolicited responses */
 818         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
 819
 820         /* detect codecs */
 821         if (!chip->codec_mask) {
 822                 chip->codec_mask = azx_readw(chip, STATESTS);
 823                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 824         }
 825
 826         return 0;
 827 }
 828
 829
 830 /*
 831  * Lowlevel interface
 832  */
 833
 834 /* enable interrupts */
 835 static void azx_int_enable(struct azx *chip)
 836 {
 837         /* enable controller CIE and GIE */
 838         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 839                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 840 }
 841
 842 /* disable interrupts */
 843 static void azx_int_disable(struct azx *chip)
 844 {
 845         int i;
 846
 847         /* disable interrupts in stream descriptor */
 848         for (i = 0; i < chip->num_streams; i++) {
 849                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 850                 azx_sd_writeb(azx_dev, SD_CTL,
 851                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 852         }
 853
 854         /* disable SIE for all streams */
 855         azx_writeb(chip, INTCTL, 0);
 856
 857         /* disable controller CIE and GIE */
 858         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 859                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 860 }
 861
 862 /* clear interrupts */
 863 static void azx_int_clear(struct azx *chip)
 864 {
 865         int i;
 866
 867         /* clear stream status */
 868         for (i = 0; i < chip->num_streams; i++) {
 869                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 870                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 871         }
 872
 873         /* clear STATESTS */
 874         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 875
 876         /* clear rirb status */
 877         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 878
 879         /* clear int status */
 880         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 881 }
 882
 883 /* start a stream */
 884 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 885 {
 886         /*
 887          * Before stream start, initialize parameter
 888          */
 889         azx_dev->insufficient = 1;
 890
 891         /* enable SIE */
 892         azx_writeb(chip, INTCTL,
 893                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 894         /* set DMA start and interrupt mask */
 895         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 896                       SD_CTL_DMA_START | SD_INT_MASK);
 897 }
 898
 899 /* stop DMA */
 900 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 901 {
 902         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 903                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 904         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 905 }
 906
 907 /* stop a stream */
 908 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 909 {
 910         azx_stream_clear(chip, azx_dev);
 911         /* disable SIE */
 912         azx_writeb(chip, INTCTL,
 913                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 914 }
 915
 916
 917 /*
 918  * reset and start the controller registers
 919  */
 920 static void azx_init_chip(struct azx *chip)
 921 {
 922         if (chip->initialized)
 923                 return;
 924
 925         /* reset controller */
 926         azx_reset(chip);
 927
 928         /* initialize interrupts */
 929         azx_int_clear(chip);
 930         azx_int_enable(chip);
 931
 932         /* initialize the codec command I/O */
 933         azx_init_cmd_io(chip);
 934
 935         /* program the position buffer */
 936         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 937         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 938
 939         chip->initialized = 1;
 940 }
 941
 942 /*
 943  * initialize the PCI registers
 944  */
 945 /* update bits in a PCI register byte */
 946 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 947                             unsigned char mask, unsigned char val)
 948 {
 949         unsigned char data;
 950
 951         pci_read_config_byte(pci, reg, &data);
 952         data &= ~mask;
 953         data |= (val & mask);
 954         pci_write_config_byte(pci, reg, data);
 955 }
 956
 957 static void azx_init_pci(struct azx *chip)
 958 {
 959         unsigned short snoop;
 960
 961         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 962          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 963          * Ensuring these bits are 0 clears playback static on some HD Audio
 964          * codecs
 965          */
 966         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 967
 968         switch (chip->driver_type) {
 969         case AZX_DRIVER_ATI:
 970                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 971                 update_pci_byte(chip->pci,
 972                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 973                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 974                 break;
 975         case AZX_DRIVER_NVIDIA:
 976                 /* For NVIDIA HDA, enable snoop */
 977                 update_pci_byte(chip->pci,
 978                                 NVIDIA_HDA_TRANSREG_ADDR,
 979                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 980                 update_pci_byte(chip->pci,
 981                                 NVIDIA_HDA_ISTRM_COH,
 982                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 983                 update_pci_byte(chip->pci,
 984                                 NVIDIA_HDA_OSTRM_COH,
 985                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 986                 break;
 987         case AZX_DRIVER_SCH:
 988                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 989                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 990                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
 991                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 992                         pci_read_config_word(chip->pci,
 993                                 INTEL_SCH_HDA_DEVC, &snoop);
 994                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
 995                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
 996                                 ? "Failed" : "OK");
 997                 }
 998                 break;
 999
1000         }
1001 }
1002
1003
1004 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1005
1006 /*
1007  * interrupt handler
1008  */
1009 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1010 {
1011         struct azx *chip = dev_id;
1012         struct azx_dev *azx_dev;
1013         u32 status;
1014         int i, ok;
1015
1016         spin_lock(&chip->reg_lock);
1017
1018         status = azx_readl(chip, INTSTS);
1019         if (status == 0) {
1020                 spin_unlock(&chip->reg_lock);
1021                 return IRQ_NONE;
1022         }
1023
1024         for (i = 0; i < chip->num_streams; i++) {
1025                 azx_dev = &chip->azx_dev[i];
1026                 if (status & azx_dev->sd_int_sta_mask) {
1027                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1028                         if (!azx_dev->substream || !azx_dev->running)
1029                                 continue;
1030                         /* check whether this IRQ is really acceptable */
1031                         ok = azx_position_ok(chip, azx_dev);
1032                         if (ok == 1) {
1033                                 azx_dev->irq_pending = 0;
1034                                 spin_unlock(&chip->reg_lock);
1035                                 snd_pcm_period_elapsed(azx_dev->substream);
1036                                 spin_lock(&chip->reg_lock);
1037                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1038                                 /* bogus IRQ, process it later */
1039                                 azx_dev->irq_pending = 1;
1040                                 queue_work(chip->bus->workq,
1041                                            &chip->irq_pending_work);
1042                         }
1043                 }
1044         }
1045
1046         /* clear rirb int */
1047         status = azx_readb(chip, RIRBSTS);
1048         if (status & RIRB_INT_MASK) {
1049                 if (status & RIRB_INT_RESPONSE)
1050                         azx_update_rirb(chip);
1051                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1052         }
1053
1054 #if 0
1055         /* clear state status int */
1056         if (azx_readb(chip, STATESTS) & 0x04)
1057                 azx_writeb(chip, STATESTS, 0x04);
1058 #endif
1059         spin_unlock(&chip->reg_lock);
1060
1061         return IRQ_HANDLED;
1062 }
1063
1064
1065 /*
1066  * set up a BDL entry
1067  */
1068 static int setup_bdle(struct snd_pcm_substream *substream,
1069                       struct azx_dev *azx_dev, u32 **bdlp,
1070                       int ofs, int size, int with_ioc)
1071 {
1072         u32 *bdl = *bdlp;
1073
1074         while (size > 0) {
1075                 dma_addr_t addr;
1076                 int chunk;
1077
1078                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1079                         return -EINVAL;
1080
1081                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1082                 /* program the address field of the BDL entry */
1083                 bdl[0] = cpu_to_le32((u32)addr);
1084                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1085                 /* program the size field of the BDL entry */
1086                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1087                 bdl[2] = cpu_to_le32(chunk);
1088                 /* program the IOC to enable interrupt
1089                  * only when the whole fragment is processed
1090                  */
1091                 size -= chunk;
1092                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1093                 bdl += 4;
1094                 azx_dev->frags++;
1095                 ofs += chunk;
1096         }
1097         *bdlp = bdl;
1098         return ofs;
1099 }
1100
1101 /*
1102  * set up BDL entries
1103  */
1104 static int azx_setup_periods(struct azx *chip,
1105                              struct snd_pcm_substream *substream,
1106                              struct azx_dev *azx_dev)
1107 {
1108         u32 *bdl;
1109         int i, ofs, periods, period_bytes;
1110         int pos_adj;
1111
1112         /* reset BDL address */
1113         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1114         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1115
1116         period_bytes = azx_dev->period_bytes;
1117         periods = azx_dev->bufsize / period_bytes;
1118
1119         /* program the initial BDL entries */
1120         bdl = (u32 *)azx_dev->bdl.area;
1121         ofs = 0;
1122         azx_dev->frags = 0;
1123         pos_adj = bdl_pos_adj[chip->dev_index];
1124         if (pos_adj > 0) {
1125                 struct snd_pcm_runtime *runtime = substream->runtime;
1126                 int pos_align = pos_adj;
1127                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1128                 if (!pos_adj)
1129                         pos_adj = pos_align;
1130                 else
1131                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1132                                 pos_align;
1133                 pos_adj = frames_to_bytes(runtime, pos_adj);
1134                 if (pos_adj >= period_bytes) {
1135                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1136                                    bdl_pos_adj[chip->dev_index]);
1137                         pos_adj = 0;
1138                 } else {
1139                         ofs = setup_bdle(substream, azx_dev,
1140                                          &bdl, ofs, pos_adj, 1);
1141                         if (ofs < 0)
1142                                 goto error;
1143                 }
1144         } else
1145                 pos_adj = 0;
1146         for (i = 0; i < periods; i++) {
1147                 if (i == periods - 1 && pos_adj)
1148                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1149                                          period_bytes - pos_adj, 0);
1150                 else
1151                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1152                                          period_bytes, 1);
1153                 if (ofs < 0)
1154                         goto error;
1155         }
1156         return 0;
1157
1158  error:
1159         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1160                    azx_dev->bufsize, period_bytes);
1161         return -EINVAL;
1162 }
1163
1164 /* reset stream */
1165 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1166 {
1167         unsigned char val;
1168         int timeout;
1169
1170         azx_stream_clear(chip, azx_dev);
1171
1172         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1173                       SD_CTL_STREAM_RESET);
1174         udelay(3);
1175         timeout = 300;
1176         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1177                --timeout)
1178                 ;
1179         val &= ~SD_CTL_STREAM_RESET;
1180         azx_sd_writeb(azx_dev, SD_CTL, val);
1181         udelay(3);
1182
1183         timeout = 300;
1184         /* waiting for hardware to report that the stream is out of reset */
1185         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1186                --timeout)
1187                 ;
1188
1189         /* reset first position - may not be synced with hw at this time */
1190         *azx_dev->posbuf = 0;
1191 }
1192
1193 /*
1194  * set up the SD for streaming
1195  */
1196 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1197 {
1198         /* make sure the run bit is zero for SD */
1199         azx_stream_clear(chip, azx_dev);
1200         /* program the stream_tag */
1201         azx_sd_writel(azx_dev, SD_CTL,
1202                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1203                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1204
1205         /* program the length of samples in cyclic buffer */
1206         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1207
1208         /* program the stream format */
1209         /* this value needs to be the same as the one programmed */
1210         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1211
1212         /* program the stream LVI (last valid index) of the BDL */
1213         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1214
1215         /* program the BDL address */
1216         /* lower BDL address */
1217         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1218         /* upper BDL address */
1219         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1220
1221         /* enable the position buffer */
1222         if (chip->position_fix == POS_FIX_POSBUF ||
1223             chip->position_fix == POS_FIX_AUTO ||
1224             chip->via_dmapos_patch) {
1225                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1226                         azx_writel(chip, DPLBASE,
1227                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1228         }
1229
1230         /* set the interrupt enable bits in the descriptor control register */
1231         azx_sd_writel(azx_dev, SD_CTL,
1232                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1233
1234         return 0;
1235 }
1236
1237 /*
1238  * Probe the given codec address
1239  */
1240 static int probe_codec(struct azx *chip, int addr)
1241 {
1242         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1243                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1244         unsigned int res;
1245
1246         chip->probing = 1;
1247         azx_send_cmd(chip->bus, cmd);
1248         res = azx_get_response(chip->bus);
1249         chip->probing = 0;
1250         if (res == -1)
1251                 return -EIO;
1252         snd_printdd(SFX "codec #%d probed OK\n", addr);
1253         return 0;
1254 }
1255
1256 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1257                                  struct hda_pcm *cpcm);
1258 static void azx_stop_chip(struct azx *chip);
1259
1260 static void azx_bus_reset(struct hda_bus *bus)
1261 {
1262         struct azx *chip = bus->private_data;
1263
1264         bus->in_reset = 1;
1265         azx_stop_chip(chip);
1266         azx_init_chip(chip);
1267 #ifdef CONFIG_PM
1268         if (chip->initialized) {
1269                 int i;
1270
1271                 for (i = 0; i < AZX_MAX_PCMS; i++)
1272                         snd_pcm_suspend_all(chip->pcm[i]);
1273                 snd_hda_suspend(chip->bus);
1274                 snd_hda_resume(chip->bus);
1275         }
1276 #endif
1277         bus->in_reset = 0;
1278 }
1279
1280 /*
1281  * Codec initialization
1282  */
1283
1284 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1285 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1286         [AZX_DRIVER_TERA] = 1,
1287 };
1288
1289 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1290                                       int no_init)
1291 {
1292         struct hda_bus_template bus_temp;
1293         int c, codecs, err;
1294         int max_slots;
1295
1296         memset(&bus_temp, 0, sizeof(bus_temp));
1297         bus_temp.private_data = chip;
1298         bus_temp.modelname = model;
1299         bus_temp.pci = chip->pci;
1300         bus_temp.ops.command = azx_send_cmd;
1301         bus_temp.ops.get_response = azx_get_response;
1302         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1303         bus_temp.ops.bus_reset = azx_bus_reset;
1304 #ifdef CONFIG_SND_HDA_POWER_SAVE
1305         bus_temp.power_save = &power_save;
1306         bus_temp.ops.pm_notify = azx_power_notify;
1307 #endif
1308
1309         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1310         if (err < 0)
1311                 return err;
1312
1313         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1314                 chip->bus->needs_damn_long_delay = 1;
1315
1316         codecs = 0;
1317         max_slots = azx_max_codecs[chip->driver_type];
1318         if (!max_slots)
1319                 max_slots = AZX_MAX_CODECS;
1320
1321         /* First try to probe all given codec slots */
1322         for (c = 0; c < max_slots; c++) {
1323                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1324                         if (probe_codec(chip, c) < 0) {
1325                                 /* Some BIOSen give you wrong codec addresses
1326                                  * that don't exist
1327                                  */
1328                                 snd_printk(KERN_WARNING SFX
1329                                            "Codec #%d probe error; "
1330                                            "disabling it...\n", c);
1331                                 chip->codec_mask &= ~(1 << c);
1332                                 /* More badly, accessing to a non-existing
1333                                  * codec often screws up the controller chip,
1334                                  * and distrubs the further communications.
1335                                  * Thus if an error occurs during probing,
1336                                  * better to reset the controller chip to
1337                                  * get back to the sanity state.
1338                                  */
1339                                 azx_stop_chip(chip);
1340                                 azx_init_chip(chip);
1341                         }
1342                 }
1343         }
1344
1345         /* Then create codec instances */
1346         for (c = 0; c < max_slots; c++) {
1347                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1348                         struct hda_codec *codec;
1349                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1350                         if (err < 0)
1351                                 continue;
1352                         codecs++;
1353                 }
1354         }
1355         if (!codecs) {
1356                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1357                 return -ENXIO;
1358         }
1359
1360         return 0;
1361 }
1362
1363
1364 /*
1365  * PCM support
1366  */
1367
1368 /* assign a stream for the PCM */
1369 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1370 {
1371         int dev, i, nums;
1372         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1373                 dev = chip->playback_index_offset;
1374                 nums = chip->playback_streams;
1375         } else {
1376                 dev = chip->capture_index_offset;
1377                 nums = chip->capture_streams;
1378         }
1379         for (i = 0; i < nums; i++, dev++)
1380                 if (!chip->azx_dev[dev].opened) {
1381                         chip->azx_dev[dev].opened = 1;
1382                         return &chip->azx_dev[dev];
1383                 }
1384         return NULL;
1385 }
1386
1387 /* release the assigned stream */
1388 static inline void azx_release_device(struct azx_dev *azx_dev)
1389 {
1390         azx_dev->opened = 0;
1391 }
1392
1393 static struct snd_pcm_hardware azx_pcm_hw = {
1394         .info =                 (SNDRV_PCM_INFO_MMAP |
1395                                  SNDRV_PCM_INFO_INTERLEAVED |
1396                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1397                                  SNDRV_PCM_INFO_MMAP_VALID |
1398                                  /* No full-resume yet implemented */
1399                                  /* SNDRV_PCM_INFO_RESUME |*/
1400                                  SNDRV_PCM_INFO_PAUSE |
1401                                  SNDRV_PCM_INFO_SYNC_START),
1402         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1403         .rates =                SNDRV_PCM_RATE_48000,
1404         .rate_min =             48000,
1405         .rate_max =             48000,
1406         .channels_min =         2,
1407         .channels_max =         2,
1408         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1409         .period_bytes_min =     128,
1410         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1411         .periods_min =          2,
1412         .periods_max =          AZX_MAX_FRAG,
1413         .fifo_size =            0,
1414 };
1415
1416 struct azx_pcm {
1417         struct azx *chip;
1418         struct hda_codec *codec;
1419         struct hda_pcm_stream *hinfo[2];
1420 };
1421
1422 static int azx_pcm_open(struct snd_pcm_substream *substream)
1423 {
1424         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1425         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1426         struct azx *chip = apcm->chip;
1427         struct azx_dev *azx_dev;
1428         struct snd_pcm_runtime *runtime = substream->runtime;
1429         unsigned long flags;
1430         int err;
1431
1432         mutex_lock(&chip->open_mutex);
1433         azx_dev = azx_assign_device(chip, substream->stream);
1434         if (azx_dev == NULL) {
1435                 mutex_unlock(&chip->open_mutex);
1436                 return -EBUSY;
1437         }
1438         runtime->hw = azx_pcm_hw;
1439         runtime->hw.channels_min = hinfo->channels_min;
1440         runtime->hw.channels_max = hinfo->channels_max;
1441         runtime->hw.formats = hinfo->formats;
1442         runtime->hw.rates = hinfo->rates;
1443         snd_pcm_limit_hw_rates(runtime);
1444         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1445         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1446                                    128);
1447         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1448                                    128);
1449         snd_hda_power_up(apcm->codec);
1450         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1451         if (err < 0) {
1452                 azx_release_device(azx_dev);
1453                 snd_hda_power_down(apcm->codec);
1454                 mutex_unlock(&chip->open_mutex);
1455                 return err;
1456         }
1457         spin_lock_irqsave(&chip->reg_lock, flags);
1458         azx_dev->substream = substream;
1459         azx_dev->running = 0;
1460         spin_unlock_irqrestore(&chip->reg_lock, flags);
1461
1462         runtime->private_data = azx_dev;
1463         snd_pcm_set_sync(substream);
1464         mutex_unlock(&chip->open_mutex);
1465
1466         return 0;
1467 }
1468
1469 static int azx_pcm_close(struct snd_pcm_substream *substream)
1470 {
1471         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1472         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1473         struct azx *chip = apcm->chip;
1474         struct azx_dev *azx_dev = get_azx_dev(substream);
1475         unsigned long flags;
1476
1477         mutex_lock(&chip->open_mutex);
1478         spin_lock_irqsave(&chip->reg_lock, flags);
1479         azx_dev->substream = NULL;
1480         azx_dev->running = 0;
1481         spin_unlock_irqrestore(&chip->reg_lock, flags);
1482         azx_release_device(azx_dev);
1483         hinfo->ops.close(hinfo, apcm->codec, substream);
1484         snd_hda_power_down(apcm->codec);
1485         mutex_unlock(&chip->open_mutex);
1486         return 0;
1487 }
1488
1489 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1490                              struct snd_pcm_hw_params *hw_params)
1491 {
1492         struct azx_dev *azx_dev = get_azx_dev(substream);
1493
1494         azx_dev->bufsize = 0;
1495         azx_dev->period_bytes = 0;
1496         azx_dev->format_val = 0;
1497         return snd_pcm_lib_malloc_pages(substream,
1498                                         params_buffer_bytes(hw_params));
1499 }
1500
1501 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1502 {
1503         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1504         struct azx_dev *azx_dev = get_azx_dev(substream);
1505         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1506
1507         /* reset BDL address */
1508         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1509         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1510         azx_sd_writel(azx_dev, SD_CTL, 0);
1511         azx_dev->bufsize = 0;
1512         azx_dev->period_bytes = 0;
1513         azx_dev->format_val = 0;
1514
1515         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1516
1517         return snd_pcm_lib_free_pages(substream);
1518 }
1519
1520 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1521 {
1522         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1523         struct azx *chip = apcm->chip;
1524         struct azx_dev *azx_dev = get_azx_dev(substream);
1525         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1526         struct snd_pcm_runtime *runtime = substream->runtime;
1527         unsigned int bufsize, period_bytes, format_val;
1528         int err;
1529
1530         azx_stream_reset(chip, azx_dev);
1531         format_val = snd_hda_calc_stream_format(runtime->rate,
1532                                                 runtime->channels,
1533                                                 runtime->format,
1534                                                 hinfo->maxbps);
1535         if (!format_val) {
1536                 snd_printk(KERN_ERR SFX
1537                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1538                            runtime->rate, runtime->channels, runtime->format);
1539                 return -EINVAL;
1540         }
1541
1542         bufsize = snd_pcm_lib_buffer_bytes(substream);
1543         period_bytes = snd_pcm_lib_period_bytes(substream);
1544
1545         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1546                     bufsize, format_val);
1547
1548         if (bufsize != azx_dev->bufsize ||
1549             period_bytes != azx_dev->period_bytes ||
1550             format_val != azx_dev->format_val) {
1551                 azx_dev->bufsize = bufsize;
1552                 azx_dev->period_bytes = period_bytes;
1553                 azx_dev->format_val = format_val;
1554                 err = azx_setup_periods(chip, substream, azx_dev);
1555                 if (err < 0)
1556                         return err;
1557         }
1558
1559         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1560                                                 (runtime->rate * 2);
1561         azx_setup_controller(chip, azx_dev);
1562         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1563                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1564         else
1565                 azx_dev->fifo_size = 0;
1566
1567         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1568                                   azx_dev->format_val, substream);
1569 }
1570
1571 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1572 {
1573         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1574         struct azx *chip = apcm->chip;
1575         struct azx_dev *azx_dev;
1576         struct snd_pcm_substream *s;
1577         int rstart = 0, start, nsync = 0, sbits = 0;
1578         int nwait, timeout;
1579
1580         switch (cmd) {
1581         case SNDRV_PCM_TRIGGER_START:
1582                 rstart = 1;
1583         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1584         case SNDRV_PCM_TRIGGER_RESUME:
1585                 start = 1;
1586                 break;
1587         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1588         case SNDRV_PCM_TRIGGER_SUSPEND:
1589         case SNDRV_PCM_TRIGGER_STOP:
1590                 start = 0;
1591                 break;
1592         default:
1593                 return -EINVAL;
1594         }
1595
1596         snd_pcm_group_for_each_entry(s, substream) {
1597                 if (s->pcm->card != substream->pcm->card)
1598                         continue;
1599                 azx_dev = get_azx_dev(s);
1600                 sbits |= 1 << azx_dev->index;
1601                 nsync++;
1602                 snd_pcm_trigger_done(s, substream);
1603         }
1604
1605         spin_lock(&chip->reg_lock);
1606         if (nsync > 1) {
1607                 /* first, set SYNC bits of corresponding streams */
1608                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1609         }
1610         snd_pcm_group_for_each_entry(s, substream) {
1611                 if (s->pcm->card != substream->pcm->card)
1612                         continue;
1613                 azx_dev = get_azx_dev(s);
1614                 if (rstart) {
1615                         azx_dev->start_flag = 1;
1616                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1617                 }
1618                 if (start)
1619                         azx_stream_start(chip, azx_dev);
1620                 else
1621                         azx_stream_stop(chip, azx_dev);
1622                 azx_dev->running = start;
1623         }
1624         spin_unlock(&chip->reg_lock);
1625         if (start) {
1626                 if (nsync == 1)
1627                         return 0;
1628                 /* wait until all FIFOs get ready */
1629                 for (timeout = 5000; timeout; timeout--) {
1630                         nwait = 0;
1631                         snd_pcm_group_for_each_entry(s, substream) {
1632                                 if (s->pcm->card != substream->pcm->card)
1633                                         continue;
1634                                 azx_dev = get_azx_dev(s);
1635                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1636                                       SD_STS_FIFO_READY))
1637                                         nwait++;
1638                         }
1639                         if (!nwait)
1640                                 break;
1641                         cpu_relax();
1642                 }
1643         } else {
1644                 /* wait until all RUN bits are cleared */
1645                 for (timeout = 5000; timeout; timeout--) {
1646                         nwait = 0;
1647                         snd_pcm_group_for_each_entry(s, substream) {
1648                                 if (s->pcm->card != substream->pcm->card)
1649                                         continue;
1650                                 azx_dev = get_azx_dev(s);
1651                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1652                                     SD_CTL_DMA_START)
1653                                         nwait++;
1654                         }
1655                         if (!nwait)
1656                                 break;
1657                         cpu_relax();
1658                 }
1659         }
1660         if (nsync > 1) {
1661                 spin_lock(&chip->reg_lock);
1662                 /* reset SYNC bits */
1663                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1664                 spin_unlock(&chip->reg_lock);
1665         }
1666         return 0;
1667 }
1668
1669 /* get the current DMA position with correction on VIA chips */
1670 static unsigned int azx_via_get_position(struct azx *chip,
1671                                          struct azx_dev *azx_dev)
1672 {
1673         unsigned int link_pos, mini_pos, bound_pos;
1674         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1675         unsigned int fifo_size;
1676
1677         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1678         if (azx_dev->index >= 4) {
1679                 /* Playback, no problem using link position */
1680                 return link_pos;
1681         }
1682
1683         /* Capture */
1684         /* For new chipset,
1685          * use mod to get the DMA position just like old chipset
1686          */
1687         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1688         mod_dma_pos %= azx_dev->period_bytes;
1689
1690         /* azx_dev->fifo_size can't get FIFO size of in stream.
1691          * Get from base address + offset.
1692          */
1693         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1694
1695         if (azx_dev->insufficient) {
1696                 /* Link position never gather than FIFO size */
1697                 if (link_pos <= fifo_size)
1698                         return 0;
1699
1700                 azx_dev->insufficient = 0;
1701         }
1702
1703         if (link_pos <= fifo_size)
1704                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1705         else
1706                 mini_pos = link_pos - fifo_size;
1707
1708         /* Find nearest previous boudary */
1709         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1710         mod_link_pos = link_pos % azx_dev->period_bytes;
1711         if (mod_link_pos >= fifo_size)
1712                 bound_pos = link_pos - mod_link_pos;
1713         else if (mod_dma_pos >= mod_mini_pos)
1714                 bound_pos = mini_pos - mod_mini_pos;
1715         else {
1716                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1717                 if (bound_pos >= azx_dev->bufsize)
1718                         bound_pos = 0;
1719         }
1720
1721         /* Calculate real DMA position we want */
1722         return bound_pos + mod_dma_pos;
1723 }
1724
1725 static unsigned int azx_get_position(struct azx *chip,
1726                                      struct azx_dev *azx_dev)
1727 {
1728         unsigned int pos;
1729
1730         if (chip->via_dmapos_patch)
1731                 pos = azx_via_get_position(chip, azx_dev);
1732         else if (chip->position_fix == POS_FIX_POSBUF ||
1733                  chip->position_fix == POS_FIX_AUTO) {
1734                 /* use the position buffer */
1735                 pos = le32_to_cpu(*azx_dev->posbuf);
1736         } else {
1737                 /* read LPIB */
1738                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1739         }
1740         if (pos >= azx_dev->bufsize)
1741                 pos = 0;
1742         return pos;
1743 }
1744
1745 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1746 {
1747         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1748         struct azx *chip = apcm->chip;
1749         struct azx_dev *azx_dev = get_azx_dev(substream);
1750         return bytes_to_frames(substream->runtime,
1751                                azx_get_position(chip, azx_dev));
1752 }
1753
1754 /*
1755  * Check whether the current DMA position is acceptable for updating
1756  * periods.  Returns non-zero if it's OK.
1757  *
1758  * Many HD-audio controllers appear pretty inaccurate about
1759  * the update-IRQ timing.  The IRQ is issued before actually the
1760  * data is processed.  So, we need to process it afterwords in a
1761  * workqueue.
1762  */
1763 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1764 {
1765         unsigned int pos;
1766
1767         if (azx_dev->start_flag &&
1768             time_before_eq(jiffies, azx_dev->start_jiffies))
1769                 return -1;      /* bogus (too early) interrupt */
1770         azx_dev->start_flag = 0;
1771
1772         pos = azx_get_position(chip, azx_dev);
1773         if (chip->position_fix == POS_FIX_AUTO) {
1774                 if (!pos) {
1775                         printk(KERN_WARNING
1776                                "hda-intel: Invalid position buffer, "
1777                                "using LPIB read method instead.\n");
1778                         chip->position_fix = POS_FIX_LPIB;
1779                         pos = azx_get_position(chip, azx_dev);
1780                 } else
1781                         chip->position_fix = POS_FIX_POSBUF;
1782         }
1783
1784         if (!bdl_pos_adj[chip->dev_index])
1785                 return 1; /* no delayed ack */
1786         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1787                 return 0; /* NG - it's below the period boundary */
1788         return 1; /* OK, it's fine */
1789 }
1790
1791 /*
1792  * The work for pending PCM period updates.
1793  */
1794 static void azx_irq_pending_work(struct work_struct *work)
1795 {
1796         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1797         int i, pending;
1798
1799         if (!chip->irq_pending_warned) {
1800                 printk(KERN_WARNING
1801                        "hda-intel: IRQ timing workaround is activated "
1802                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1803                        chip->card->number);
1804                 chip->irq_pending_warned = 1;
1805         }
1806
1807         for (;;) {
1808                 pending = 0;
1809                 spin_lock_irq(&chip->reg_lock);
1810                 for (i = 0; i < chip->num_streams; i++) {
1811                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1812                         if (!azx_dev->irq_pending ||
1813                             !azx_dev->substream ||
1814                             !azx_dev->running)
1815                                 continue;
1816                         if (azx_position_ok(chip, azx_dev)) {
1817                                 azx_dev->irq_pending = 0;
1818                                 spin_unlock(&chip->reg_lock);
1819                                 snd_pcm_period_elapsed(azx_dev->substream);
1820                                 spin_lock(&chip->reg_lock);
1821                         } else
1822                                 pending++;
1823                 }
1824                 spin_unlock_irq(&chip->reg_lock);
1825                 if (!pending)
1826                         return;
1827                 cond_resched();
1828         }
1829 }
1830
1831 /* clear irq_pending flags and assure no on-going workq */
1832 static void azx_clear_irq_pending(struct azx *chip)
1833 {
1834         int i;
1835
1836         spin_lock_irq(&chip->reg_lock);
1837         for (i = 0; i < chip->num_streams; i++)
1838                 chip->azx_dev[i].irq_pending = 0;
1839         spin_unlock_irq(&chip->reg_lock);
1840 }
1841
1842 static struct snd_pcm_ops azx_pcm_ops = {
1843         .open = azx_pcm_open,
1844         .close = azx_pcm_close,
1845         .ioctl = snd_pcm_lib_ioctl,
1846         .hw_params = azx_pcm_hw_params,
1847         .hw_free = azx_pcm_hw_free,
1848         .prepare = azx_pcm_prepare,
1849         .trigger = azx_pcm_trigger,
1850         .pointer = azx_pcm_pointer,
1851         .page = snd_pcm_sgbuf_ops_page,
1852 };
1853
1854 static void azx_pcm_free(struct snd_pcm *pcm)
1855 {
1856         struct azx_pcm *apcm = pcm->private_data;
1857         if (apcm) {
1858                 apcm->chip->pcm[pcm->device] = NULL;
1859                 kfree(apcm);
1860         }
1861 }
1862
1863 static int
1864 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1865                       struct hda_pcm *cpcm)
1866 {
1867         struct azx *chip = bus->private_data;
1868         struct snd_pcm *pcm;
1869         struct azx_pcm *apcm;
1870         int pcm_dev = cpcm->device;
1871         int s, err;
1872
1873         if (pcm_dev >= AZX_MAX_PCMS) {
1874                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1875                            pcm_dev);
1876                 return -EINVAL;
1877         }
1878         if (chip->pcm[pcm_dev]) {
1879                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1880                 return -EBUSY;
1881         }
1882         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1883                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1884                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1885                           &pcm);
1886         if (err < 0)
1887                 return err;
1888         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1889         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1890         if (apcm == NULL)
1891                 return -ENOMEM;
1892         apcm->chip = chip;
1893         apcm->codec = codec;
1894         pcm->private_data = apcm;
1895         pcm->private_free = azx_pcm_free;
1896         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1897                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1898         chip->pcm[pcm_dev] = pcm;
1899         cpcm->pcm = pcm;
1900         for (s = 0; s < 2; s++) {
1901                 apcm->hinfo[s] = &cpcm->stream[s];
1902                 if (cpcm->stream[s].substreams)
1903                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1904         }
1905         /* buffer pre-allocation */
1906         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1907                                               snd_dma_pci_data(chip->pci),
1908                                               1024 * 64, 32 * 1024 * 1024);
1909         return 0;
1910 }
1911
1912 /*
1913  * mixer creation - all stuff is implemented in hda module
1914  */
1915 static int __devinit azx_mixer_create(struct azx *chip)
1916 {
1917         return snd_hda_build_controls(chip->bus);
1918 }
1919
1920
1921 /*
1922  * initialize SD streams
1923  */
1924 static int __devinit azx_init_stream(struct azx *chip)
1925 {
1926         int i;
1927
1928         /* initialize each stream (aka device)
1929          * assign the starting bdl address to each stream (device)
1930          * and initialize
1931          */
1932         for (i = 0; i < chip->num_streams; i++) {
1933                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1934                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1935                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1936                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1937                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1938                 azx_dev->sd_int_sta_mask = 1 << i;
1939                 /* stream tag: must be non-zero and unique */
1940                 azx_dev->index = i;
1941                 azx_dev->stream_tag = i + 1;
1942         }
1943
1944         return 0;
1945 }
1946
1947 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1948 {
1949         if (request_irq(chip->pci->irq, azx_interrupt,
1950                         chip->msi ? 0 : IRQF_SHARED,
1951                         "HDA Intel", chip)) {
1952                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1953                        "disabling device\n", chip->pci->irq);
1954                 if (do_disconnect)
1955                         snd_card_disconnect(chip->card);
1956                 return -1;
1957         }
1958         chip->irq = chip->pci->irq;
1959         pci_intx(chip->pci, !chip->msi);
1960         return 0;
1961 }
1962
1963
1964 static void azx_stop_chip(struct azx *chip)
1965 {
1966         if (!chip->initialized)
1967                 return;
1968
1969         /* disable interrupts */
1970         azx_int_disable(chip);
1971         azx_int_clear(chip);
1972
1973         /* disable CORB/RIRB */
1974         azx_free_cmd_io(chip);
1975
1976         /* disable position buffer */
1977         azx_writel(chip, DPLBASE, 0);
1978         azx_writel(chip, DPUBASE, 0);
1979
1980         chip->initialized = 0;
1981 }
1982
1983 #ifdef CONFIG_SND_HDA_POWER_SAVE
1984 /* power-up/down the controller */
1985 static void azx_power_notify(struct hda_bus *bus)
1986 {
1987         struct azx *chip = bus->private_data;
1988         struct hda_codec *c;
1989         int power_on = 0;
1990
1991         list_for_each_entry(c, &bus->codec_list, list) {
1992                 if (c->power_on) {
1993                         power_on = 1;
1994                         break;
1995                 }
1996         }
1997         if (power_on)
1998                 azx_init_chip(chip);
1999         else if (chip->running && power_save_controller)
2000                 azx_stop_chip(chip);
2001 }
2002 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2003
2004 #ifdef CONFIG_PM
2005 /*
2006  * power management
2007  */
2008
2009 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2010 {
2011         struct hda_codec *codec;
2012
2013         list_for_each_entry(codec, &bus->codec_list, list) {
2014                 if (snd_hda_codec_needs_resume(codec))
2015                         return 1;
2016         }
2017         return 0;
2018 }
2019
2020 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2021 {
2022         struct snd_card *card = pci_get_drvdata(pci);
2023         struct azx *chip = card->private_data;
2024         int i;
2025
2026         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2027         azx_clear_irq_pending(chip);
2028         for (i = 0; i < AZX_MAX_PCMS; i++)
2029                 snd_pcm_suspend_all(chip->pcm[i]);
2030         if (chip->initialized)
2031                 snd_hda_suspend(chip->bus);
2032         azx_stop_chip(chip);
2033         if (chip->irq >= 0) {
2034                 free_irq(chip->irq, chip);
2035                 chip->irq = -1;
2036         }
2037         if (chip->msi)
2038                 pci_disable_msi(chip->pci);
2039         pci_disable_device(pci);
2040         pci_save_state(pci);
2041         pci_set_power_state(pci, pci_choose_state(pci, state));
2042         return 0;
2043 }
2044
2045 static int azx_resume(struct pci_dev *pci)
2046 {
2047         struct snd_card *card = pci_get_drvdata(pci);
2048         struct azx *chip = card->private_data;
2049
2050         pci_set_power_state(pci, PCI_D0);
2051         pci_restore_state(pci);
2052         if (pci_enable_device(pci) < 0) {
2053                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2054                        "disabling device\n");
2055                 snd_card_disconnect(card);
2056                 return -EIO;
2057         }
2058         pci_set_master(pci);
2059         if (chip->msi)
2060                 if (pci_enable_msi(pci) < 0)
2061                         chip->msi = 0;
2062         if (azx_acquire_irq(chip, 1) < 0)
2063                 return -EIO;
2064         azx_init_pci(chip);
2065
2066         if (snd_hda_codecs_inuse(chip->bus))
2067                 azx_init_chip(chip);
2068
2069         snd_hda_resume(chip->bus);
2070         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2071         return 0;
2072 }
2073 #endif /* CONFIG_PM */
2074
2075
2076 /*
2077  * reboot notifier for hang-up problem at power-down
2078  */
2079 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2080 {
2081         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2082         azx_stop_chip(chip);
2083         return NOTIFY_OK;
2084 }
2085
2086 static void azx_notifier_register(struct azx *chip)
2087 {
2088         chip->reboot_notifier.notifier_call = azx_halt;
2089         register_reboot_notifier(&chip->reboot_notifier);
2090 }
2091
2092 static void azx_notifier_unregister(struct azx *chip)
2093 {
2094         if (chip->reboot_notifier.notifier_call)
2095                 unregister_reboot_notifier(&chip->reboot_notifier);
2096 }
2097
2098 /*
2099  * destructor
2100  */
2101 static int azx_free(struct azx *chip)
2102 {
2103         int i;
2104
2105         azx_notifier_unregister(chip);
2106
2107         if (chip->initialized) {
2108                 azx_clear_irq_pending(chip);
2109                 for (i = 0; i < chip->num_streams; i++)
2110                         azx_stream_stop(chip, &chip->azx_dev[i]);
2111                 azx_stop_chip(chip);
2112         }
2113
2114         if (chip->irq >= 0)
2115                 free_irq(chip->irq, (void*)chip);
2116         if (chip->msi)
2117                 pci_disable_msi(chip->pci);
2118         if (chip->remap_addr)
2119                 iounmap(chip->remap_addr);
2120
2121         if (chip->azx_dev) {
2122                 for (i = 0; i < chip->num_streams; i++)
2123                         if (chip->azx_dev[i].bdl.area)
2124                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2125         }
2126         if (chip->rb.area)
2127                 snd_dma_free_pages(&chip->rb);
2128         if (chip->posbuf.area)
2129                 snd_dma_free_pages(&chip->posbuf);
2130         pci_release_regions(chip->pci);
2131         pci_disable_device(chip->pci);
2132         kfree(chip->azx_dev);
2133         kfree(chip);
2134
2135         return 0;
2136 }
2137
2138 static int azx_dev_free(struct snd_device *device)
2139 {
2140         return azx_free(device->device_data);
2141 }
2142
2143 /*
2144  * white/black-listing for position_fix
2145  */
2146 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2147         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2148         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2149         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2150         {}
2151 };
2152
2153 static int __devinit check_position_fix(struct azx *chip, int fix)
2154 {
2155         const struct snd_pci_quirk *q;
2156
2157         switch (fix) {
2158         case POS_FIX_LPIB:
2159         case POS_FIX_POSBUF:
2160                 return fix;
2161         }
2162
2163         /* Check VIA/ATI HD Audio Controller exist */
2164         switch (chip->driver_type) {
2165         case AZX_DRIVER_VIA:
2166         case AZX_DRIVER_ATI:
2167                 chip->via_dmapos_patch = 1;
2168                 /* Use link position directly, avoid any transfer problem. */
2169                 return POS_FIX_LPIB;
2170         }
2171         chip->via_dmapos_patch = 0;
2172
2173         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2174         if (q) {
2175                 printk(KERN_INFO
2176                        "hda_intel: position_fix set to %d "
2177                        "for device %04x:%04x\n",
2178                        q->value, q->subvendor, q->subdevice);
2179                 return q->value;
2180         }
2181         return POS_FIX_AUTO;
2182 }
2183
2184 /*
2185  * black-lists for probe_mask
2186  */
2187 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2188         /* Thinkpad often breaks the controller communication when accessing
2189          * to the non-working (or non-existing) modem codec slot.
2190          */
2191         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2192         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2193         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2194         /* broken BIOS */
2195         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2196         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2197         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2198         /* forced codec slots */
2199         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2200         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2201         {}
2202 };
2203
2204 #define AZX_FORCE_CODEC_MASK    0x100
2205
2206 static void __devinit check_probe_mask(struct azx *chip, int dev)
2207 {
2208         const struct snd_pci_quirk *q;
2209
2210         chip->codec_probe_mask = probe_mask[dev];
2211         if (chip->codec_probe_mask == -1) {
2212                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2213                 if (q) {
2214                         printk(KERN_INFO
2215                                "hda_intel: probe_mask set to 0x%x "
2216                                "for device %04x:%04x\n",
2217                                q->value, q->subvendor, q->subdevice);
2218                         chip->codec_probe_mask = q->value;
2219                 }
2220         }
2221
2222         /* check forced option */
2223         if (chip->codec_probe_mask != -1 &&
2224             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2225                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2226                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2227                        chip->codec_mask);
2228         }
2229 }
2230
2231
2232 /*
2233  * constructor
2234  */
2235 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2236                                 int dev, int driver_type,
2237                                 struct azx **rchip)
2238 {
2239         struct azx *chip;
2240         int i, err;
2241         unsigned short gcap;
2242         static struct snd_device_ops ops = {
2243                 .dev_free = azx_dev_free,
2244         };
2245
2246         *rchip = NULL;
2247
2248         err = pci_enable_device(pci);
2249         if (err < 0)
2250                 return err;
2251
2252         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2253         if (!chip) {
2254                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2255                 pci_disable_device(pci);
2256                 return -ENOMEM;
2257         }
2258
2259         spin_lock_init(&chip->reg_lock);
2260         mutex_init(&chip->open_mutex);
2261         chip->card = card;
2262         chip->pci = pci;
2263         chip->irq = -1;
2264         chip->driver_type = driver_type;
2265         chip->msi = enable_msi;
2266         chip->dev_index = dev;
2267         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2268
2269         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2270         check_probe_mask(chip, dev);
2271
2272         chip->single_cmd = single_cmd;
2273
2274         if (bdl_pos_adj[dev] < 0) {
2275                 switch (chip->driver_type) {
2276                 case AZX_DRIVER_ICH:
2277                         bdl_pos_adj[dev] = 1;
2278                         break;
2279                 default:
2280                         bdl_pos_adj[dev] = 32;
2281                         break;
2282                 }
2283         }
2284
2285 #if BITS_PER_LONG != 64
2286         /* Fix up base address on ULI M5461 */
2287         if (chip->driver_type == AZX_DRIVER_ULI) {
2288                 u16 tmp3;
2289                 pci_read_config_word(pci, 0x40, &tmp3);
2290                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2291                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2292         }
2293 #endif
2294
2295         err = pci_request_regions(pci, "ICH HD audio");
2296         if (err < 0) {
2297                 kfree(chip);
2298                 pci_disable_device(pci);
2299                 return err;
2300         }
2301
2302         chip->addr = pci_resource_start(pci, 0);
2303         chip->remap_addr = pci_ioremap_bar(pci, 0);
2304         if (chip->remap_addr == NULL) {
2305                 snd_printk(KERN_ERR SFX "ioremap error\n");
2306                 err = -ENXIO;
2307                 goto errout;
2308         }
2309
2310         if (chip->msi)
2311                 if (pci_enable_msi(pci) < 0)
2312                         chip->msi = 0;
2313
2314         if (azx_acquire_irq(chip, 0) < 0) {
2315                 err = -EBUSY;
2316                 goto errout;
2317         }
2318
2319         pci_set_master(pci);
2320         synchronize_irq(chip->irq);
2321
2322         gcap = azx_readw(chip, GCAP);
2323         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2324
2325         /* ATI chips seems buggy about 64bit DMA addresses */
2326         if (chip->driver_type == AZX_DRIVER_ATI)
2327                 gcap &= ~ICH6_GCAP_64OK;
2328
2329         /* allow 64bit DMA address if supported by H/W */
2330         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2331                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2332         else {
2333                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2334                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2335         }
2336
2337         /* read number of streams from GCAP register instead of using
2338          * hardcoded value
2339          */
2340         chip->capture_streams = (gcap >> 8) & 0x0f;
2341         chip->playback_streams = (gcap >> 12) & 0x0f;
2342         if (!chip->playback_streams && !chip->capture_streams) {
2343                 /* gcap didn't give any info, switching to old method */
2344
2345                 switch (chip->driver_type) {
2346                 case AZX_DRIVER_ULI:
2347                         chip->playback_streams = ULI_NUM_PLAYBACK;
2348                         chip->capture_streams = ULI_NUM_CAPTURE;
2349                         break;
2350                 case AZX_DRIVER_ATIHDMI:
2351                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2352                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2353                         break;
2354                 case AZX_DRIVER_GENERIC:
2355                 default:
2356                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2357                         chip->capture_streams = ICH6_NUM_CAPTURE;
2358                         break;
2359                 }
2360         }
2361         chip->capture_index_offset = 0;
2362         chip->playback_index_offset = chip->capture_streams;
2363         chip->num_streams = chip->playback_streams + chip->capture_streams;
2364         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2365                                 GFP_KERNEL);
2366         if (!chip->azx_dev) {
2367                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2368                 goto errout;
2369         }
2370
2371         for (i = 0; i < chip->num_streams; i++) {
2372                 /* allocate memory for the BDL for each stream */
2373                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2374                                           snd_dma_pci_data(chip->pci),
2375                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2376                 if (err < 0) {
2377                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2378                         goto errout;
2379                 }
2380         }
2381         /* allocate memory for the position buffer */
2382         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2383                                   snd_dma_pci_data(chip->pci),
2384                                   chip->num_streams * 8, &chip->posbuf);
2385         if (err < 0) {
2386                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2387                 goto errout;
2388         }
2389         /* allocate CORB/RIRB */
2390         err = azx_alloc_cmd_io(chip);
2391         if (err < 0)
2392                 goto errout;
2393
2394         /* initialize streams */
2395         azx_init_stream(chip);
2396
2397         /* initialize chip */
2398         azx_init_pci(chip);
2399         azx_init_chip(chip);
2400
2401         /* codec detection */
2402         if (!chip->codec_mask) {
2403                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2404                 err = -ENODEV;
2405                 goto errout;
2406         }
2407
2408         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2409         if (err <0) {
2410                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2411                 goto errout;
2412         }
2413
2414         strcpy(card->driver, "HDA-Intel");
2415         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2416                 sizeof(card->shortname));
2417         snprintf(card->longname, sizeof(card->longname),
2418                  "%s at 0x%lx irq %i",
2419                  card->shortname, chip->addr, chip->irq);
2420
2421         *rchip = chip;
2422         return 0;
2423
2424  errout:
2425         azx_free(chip);
2426         return err;
2427 }
2428
2429 static void power_down_all_codecs(struct azx *chip)
2430 {
2431 #ifdef CONFIG_SND_HDA_POWER_SAVE
2432         /* The codecs were powered up in snd_hda_codec_new().
2433          * Now all initialization done, so turn them down if possible
2434          */
2435         struct hda_codec *codec;
2436         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2437                 snd_hda_power_down(codec);
2438         }
2439 #endif
2440 }
2441
2442 static int __devinit azx_probe(struct pci_dev *pci,
2443                                const struct pci_device_id *pci_id)
2444 {
2445         static int dev;
2446         struct snd_card *card;
2447         struct azx *chip;
2448         int err;
2449
2450         if (dev >= SNDRV_CARDS)
2451                 return -ENODEV;
2452         if (!enable[dev]) {
2453                 dev++;
2454                 return -ENOENT;
2455         }
2456
2457         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2458         if (err < 0) {
2459                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2460                 return err;
2461         }
2462
2463         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2464         if (err < 0)
2465                 goto out_free;
2466         card->private_data = chip;
2467
2468         /* create codec instances */
2469         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2470         if (err < 0)
2471                 goto out_free;
2472
2473         /* create PCM streams */
2474         err = snd_hda_build_pcms(chip->bus);
2475         if (err < 0)
2476                 goto out_free;
2477
2478         /* create mixer controls */
2479         err = azx_mixer_create(chip);
2480         if (err < 0)
2481                 goto out_free;
2482
2483         snd_card_set_dev(card, &pci->dev);
2484
2485         err = snd_card_register(card);
2486         if (err < 0)
2487                 goto out_free;
2488
2489         pci_set_drvdata(pci, card);
2490         chip->running = 1;
2491         power_down_all_codecs(chip);
2492         azx_notifier_register(chip);
2493
2494         dev++;
2495         return err;
2496 out_free:
2497         snd_card_free(card);
2498         return err;
2499 }
2500
2501 static void __devexit azx_remove(struct pci_dev *pci)
2502 {
2503         snd_card_free(pci_get_drvdata(pci));
2504         pci_set_drvdata(pci, NULL);
2505 }
2506
2507 /* PCI IDs */
2508 static struct pci_device_id azx_ids[] = {
2509         /* ICH 6..10 */
2510         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2511         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2512         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2513         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2514         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2515         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2516         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2517         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2518         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2519         /* PCH */
2520         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2521         /* SCH */
2522         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2523         /* ATI SB 450/600 */
2524         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2525         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2526         /* ATI HDMI */
2527         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2528         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2529         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2530         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2531         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2532         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2533         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2534         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2535         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2536         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2537         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2538         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2539         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2540         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2541         /* VIA VT8251/VT8237A */
2542         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2543         /* SIS966 */
2544         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2545         /* ULI M5461 */
2546         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2547         /* NVIDIA MCP */
2548         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2549         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2550         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2551         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2552         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2553         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2554         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2555         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2556         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2557         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2558         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2559         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2560         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2561         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2562         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2563         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2564         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2565         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2566         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2567         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2568         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2569         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2570         /* Teradici */
2571         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2572         /* Creative X-Fi (CA0110-IBG) */
2573 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2574         /* the following entry conflicts with snd-ctxfi driver,
2575          * as ctxfi driver mutates from HD-audio to native mode with
2576          * a special command sequence.
2577          */
2578         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2579           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2580           .class_mask = 0xffffff,
2581           .driver_data = AZX_DRIVER_GENERIC },
2582 #else
2583         /* this entry seems still valid -- i.e. without emu20kx chip */
2584         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2585 #endif
2586         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2587         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2588           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2589           .class_mask = 0xffffff,
2590           .driver_data = AZX_DRIVER_GENERIC },
2591         { 0, }
2592 };
2593 MODULE_DEVICE_TABLE(pci, azx_ids);
2594
2595 /* pci_driver definition */
2596 static struct pci_driver driver = {
2597         .name = "HDA Intel",
2598         .id_table = azx_ids,
2599         .probe = azx_probe,
2600         .remove = __devexit_p(azx_remove),
2601 #ifdef CONFIG_PM
2602         .suspend = azx_suspend,
2603         .resume = azx_resume,
2604 #endif
2605 };
2606
2607 static int __init alsa_card_azx_init(void)
2608 {
2609         return pci_register_driver(&driver);
2610 }
2611
2612 static void __exit alsa_card_azx_exit(void)
2613 {
2614         pci_unregister_driver(&driver);
2615 }
2616
2617 module_init(alsa_card_azx_init)
2618 module_exit(alsa_card_azx_exit)