sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  82                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, int, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, PPT},"
 130                          "{Intel, PBG},"
 131                          "{Intel, SCH},"
 132                          "{ATI, SB450},"
 133                          "{ATI, SB600},"
 134                          "{ATI, RS600},"
 135                          "{ATI, RS690},"
 136                          "{ATI, RS780},"
 137                          "{ATI, R600},"
 138                          "{ATI, RV630},"
 139                          "{ATI, RV610},"
 140                          "{ATI, RV670},"
 141                          "{ATI, RV635},"
 142                          "{ATI, RV620},"
 143                          "{ATI, RV770},"
 144                          "{VIA, VT8251},"
 145                          "{VIA, VT8237A},"
 146                          "{SiS, SIS966},"
 147                          "{ULI, M5461}}");
 148 MODULE_DESCRIPTION("Intel HDA driver");
 149
 150 #ifdef CONFIG_SND_VERBOSE_PRINTK
 151 #define SFX     /* nop */
 152 #else
 153 #define SFX     "hda-intel: "
 154 #endif
 155
 156 /*
 157  * registers
 158  */
 159 #define ICH6_REG_GCAP                   0x00
 160 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 161 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 162 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 163 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 164 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 165 #define ICH6_REG_VMIN                   0x02
 166 #define ICH6_REG_VMAJ                   0x03
 167 #define ICH6_REG_OUTPAY                 0x04
 168 #define ICH6_REG_INPAY                  0x06
 169 #define ICH6_REG_GCTL                   0x08
 170 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 171 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 172 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 173 #define ICH6_REG_WAKEEN                 0x0c
 174 #define ICH6_REG_STATESTS               0x0e
 175 #define ICH6_REG_GSTS                   0x10
 176 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 177 #define ICH6_REG_INTCTL                 0x20
 178 #define ICH6_REG_INTSTS                 0x24
 179 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 180 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 181 #define ICH6_REG_SSYNC                  0x38
 182 #define ICH6_REG_CORBLBASE              0x40
 183 #define ICH6_REG_CORBUBASE              0x44
 184 #define ICH6_REG_CORBWP                 0x48
 185 #define ICH6_REG_CORBRP                 0x4a
 186 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 187 #define ICH6_REG_CORBCTL                0x4c
 188 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 189 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 190 #define ICH6_REG_CORBSTS                0x4d
 191 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 192 #define ICH6_REG_CORBSIZE               0x4e
 193
 194 #define ICH6_REG_RIRBLBASE              0x50
 195 #define ICH6_REG_RIRBUBASE              0x54
 196 #define ICH6_REG_RIRBWP                 0x58
 197 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 198 #define ICH6_REG_RINTCNT                0x5a
 199 #define ICH6_REG_RIRBCTL                0x5c
 200 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 201 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 202 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 203 #define ICH6_REG_RIRBSTS                0x5d
 204 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 205 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 206 #define ICH6_REG_RIRBSIZE               0x5e
 207
 208 #define ICH6_REG_IC                     0x60
 209 #define ICH6_REG_IR                     0x64
 210 #define ICH6_REG_IRS                    0x68
 211 #define   ICH6_IRS_VALID        (1<<1)
 212 #define   ICH6_IRS_BUSY         (1<<0)
 213
 214 #define ICH6_REG_DPLBASE                0x70
 215 #define ICH6_REG_DPUBASE                0x74
 216 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 217
 218 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 219 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 220
 221 /* stream register offsets from stream base */
 222 #define ICH6_REG_SD_CTL                 0x00
 223 #define ICH6_REG_SD_STS                 0x03
 224 #define ICH6_REG_SD_LPIB                0x04
 225 #define ICH6_REG_SD_CBL                 0x08
 226 #define ICH6_REG_SD_LVI                 0x0c
 227 #define ICH6_REG_SD_FIFOW               0x0e
 228 #define ICH6_REG_SD_FIFOSIZE            0x10
 229 #define ICH6_REG_SD_FORMAT              0x12
 230 #define ICH6_REG_SD_BDLPL               0x18
 231 #define ICH6_REG_SD_BDLPU               0x1c
 232
 233 /* PCI space */
 234 #define ICH6_PCIREG_TCSEL       0x44
 235
 236 /*
 237  * other constants
 238  */
 239
 240 /* max number of SDs */
 241 /* ICH, ATI and VIA have 4 playback and 4 capture */
 242 #define ICH6_NUM_CAPTURE        4
 243 #define ICH6_NUM_PLAYBACK       4
 244
 245 /* ULI has 6 playback and 5 capture */
 246 #define ULI_NUM_CAPTURE         5
 247 #define ULI_NUM_PLAYBACK        6
 248
 249 /* ATI HDMI has 1 playback and 0 capture */
 250 #define ATIHDMI_NUM_CAPTURE     0
 251 #define ATIHDMI_NUM_PLAYBACK    1
 252
 253 /* TERA has 4 playback and 3 capture */
 254 #define TERA_NUM_CAPTURE        3
 255 #define TERA_NUM_PLAYBACK       4
 256
 257 /* this number is statically defined for simplicity */
 258 #define MAX_AZX_DEV             16
 259
 260 /* max number of fragments - we may use more if allocating more pages for BDL */
 261 #define BDL_SIZE                4096
 262 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 263 #define AZX_MAX_FRAG            32
 264 /* max buffer size - no h/w limit, you can increase as you like */
 265 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 266
 267 /* RIRB int mask: overrun[2], response[0] */
 268 #define RIRB_INT_RESPONSE       0x01
 269 #define RIRB_INT_OVERRUN        0x04
 270 #define RIRB_INT_MASK           0x05
 271
 272 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 273 #define AZX_MAX_CODECS          8
 274 #define AZX_DEFAULT_CODECS      4
 275 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 276
 277 /* SD_CTL bits */
 278 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 279 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 280 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 281 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 282 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 283 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 284 #define SD_CTL_STREAM_TAG_SHIFT 20
 285
 286 /* SD_CTL and SD_STS */
 287 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 288 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 289 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 290 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 291                                  SD_INT_COMPLETE)
 292
 293 /* SD_STS */
 294 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 295
 296 /* INTCTL and INTSTS */
 297 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 298 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 299 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 300
 301 /* below are so far hardcoded - should read registers in future */
 302 #define ICH6_MAX_CORB_ENTRIES   256
 303 #define ICH6_MAX_RIRB_ENTRIES   256
 304
 305 /* position fix mode */
 306 enum {
 307         POS_FIX_AUTO,
 308         POS_FIX_LPIB,
 309         POS_FIX_POSBUF,
 310         POS_FIX_VIACOMBO,
 311 };
 312
 313 /* Defines for ATI HD Audio support in SB450 south bridge */
 314 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 315 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 316
 317 /* Defines for Nvidia HDA support */
 318 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 319 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 320 #define NVIDIA_HDA_ISTRM_COH          0x4d
 321 #define NVIDIA_HDA_OSTRM_COH          0x4c
 322 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 323
 324 /* Defines for Intel SCH HDA snoop control */
 325 #define INTEL_SCH_HDA_DEVC      0x78
 326 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 327
 328 /* Define IN stream 0 FIFO size offset in VIA controller */
 329 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 330 /* Define VIA HD Audio Device ID*/
 331 #define VIA_HDAC_DEVICE_ID              0x3288
 332
 333 /* HD Audio class code */
 334 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 335
 336 /*
 337  */
 338
 339 struct azx_dev {
 340         struct snd_dma_buffer bdl; /* BDL buffer */
 341         u32 *posbuf;            /* position buffer pointer */
 342
 343         unsigned int bufsize;   /* size of the play buffer in bytes */
 344         unsigned int period_bytes; /* size of the period in bytes */
 345         unsigned int frags;     /* number for period in the play buffer */
 346         unsigned int fifo_size; /* FIFO size */
 347         unsigned long start_wallclk;    /* start + minimum wallclk */
 348         unsigned long period_wallclk;   /* wallclk for period */
 349
 350         void __iomem *sd_addr;  /* stream descriptor pointer */
 351
 352         u32 sd_int_sta_mask;    /* stream int status mask */
 353
 354         /* pcm support */
 355         struct snd_pcm_substream *substream;    /* assigned substream,
 356                                                  * set in PCM open
 357                                                  */
 358         unsigned int format_val;        /* format value to be set in the
 359                                          * controller and the codec
 360                                          */
 361         unsigned char stream_tag;       /* assigned stream */
 362         unsigned char index;            /* stream index */
 363         int device;                     /* last device number assigned to */
 364
 365         unsigned int opened :1;
 366         unsigned int running :1;
 367         unsigned int irq_pending :1;
 368         /*
 369          * For VIA:
 370          *  A flag to ensure DMA position is 0
 371          *  when link position is not greater than FIFO size
 372          */
 373         unsigned int insufficient :1;
 374 };
 375
 376 /* CORB/RIRB */
 377 struct azx_rb {
 378         u32 *buf;               /* CORB/RIRB buffer
 379                                  * Each CORB entry is 4byte, RIRB is 8byte
 380                                  */
 381         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 382         /* for RIRB */
 383         unsigned short rp, wp;  /* read/write pointers */
 384         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 385         u32 res[AZX_MAX_CODECS];        /* last read value */
 386 };
 387
 388 struct azx {
 389         struct snd_card *card;
 390         struct pci_dev *pci;
 391         int dev_index;
 392
 393         /* chip type specific */
 394         int driver_type;
 395         unsigned int driver_caps;
 396         int playback_streams;
 397         int playback_index_offset;
 398         int capture_streams;
 399         int capture_index_offset;
 400         int num_streams;
 401
 402         /* pci resources */
 403         unsigned long addr;
 404         void __iomem *remap_addr;
 405         int irq;
 406
 407         /* locks */
 408         spinlock_t reg_lock;
 409         struct mutex open_mutex;
 410
 411         /* streams (x num_streams) */
 412         struct azx_dev *azx_dev;
 413
 414         /* PCM */
 415         struct snd_pcm *pcm[HDA_MAX_PCMS];
 416
 417         /* HD codec */
 418         unsigned short codec_mask;
 419         int  codec_probe_mask; /* copied from probe_mask option */
 420         struct hda_bus *bus;
 421         unsigned int beep_mode;
 422
 423         /* CORB/RIRB */
 424         struct azx_rb corb;
 425         struct azx_rb rirb;
 426
 427         /* CORB/RIRB and position buffers */
 428         struct snd_dma_buffer rb;
 429         struct snd_dma_buffer posbuf;
 430
 431         /* flags */
 432         int position_fix[2]; /* for both playback/capture streams */
 433         int poll_count;
 434         unsigned int running :1;
 435         unsigned int initialized :1;
 436         unsigned int single_cmd :1;
 437         unsigned int polling_mode :1;
 438         unsigned int msi :1;
 439         unsigned int irq_pending_warned :1;
 440         unsigned int probing :1; /* codec probing phase */
 441
 442         /* for debugging */
 443         unsigned int last_cmd[AZX_MAX_CODECS];
 444
 445         /* for pending irqs */
 446         struct work_struct irq_pending_work;
 447
 448         /* reboot notifier (for mysterious hangup problem at power-down) */
 449         struct notifier_block reboot_notifier;
 450 };
 451
 452 /* driver types */
 453 enum {
 454         AZX_DRIVER_ICH,
 455         AZX_DRIVER_PCH,
 456         AZX_DRIVER_SCH,
 457         AZX_DRIVER_ATI,
 458         AZX_DRIVER_ATIHDMI,
 459         AZX_DRIVER_VIA,
 460         AZX_DRIVER_SIS,
 461         AZX_DRIVER_ULI,
 462         AZX_DRIVER_NVIDIA,
 463         AZX_DRIVER_TERA,
 464         AZX_DRIVER_CTX,
 465         AZX_DRIVER_GENERIC,
 466         AZX_NUM_DRIVERS, /* keep this as last entry */
 467 };
 468
 469 /* driver quirks (capabilities) */
 470 /* bits 0-7 are used for indicating driver type */
 471 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 472 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 473 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 474 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 475 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 476 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 477 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 478 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 479 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 480 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 481 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 482 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 483 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 484
 485 /* quirks for ATI SB / AMD Hudson */
 486 #define AZX_DCAPS_PRESET_ATI_SB \
 487         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 488          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 489
 490 /* quirks for ATI/AMD HDMI */
 491 #define AZX_DCAPS_PRESET_ATI_HDMI \
 492         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 493
 494 /* quirks for Nvidia */
 495 #define AZX_DCAPS_PRESET_NVIDIA \
 496         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 497
 498 static char *driver_short_names[] __devinitdata = {
 499         [AZX_DRIVER_ICH] = "HDA Intel",
 500         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 501         [AZX_DRIVER_SCH] = "HDA Intel MID",
 502         [AZX_DRIVER_ATI] = "HDA ATI SB",
 503         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 504         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 505         [AZX_DRIVER_SIS] = "HDA SIS966",
 506         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 507         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 508         [AZX_DRIVER_TERA] = "HDA Teradici",
 509         [AZX_DRIVER_CTX] = "HDA Creative",
 510         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 511 };
 512
 513 /*
 514  * macros for easy use
 515  */
 516 #define azx_writel(chip,reg,value) \
 517         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 518 #define azx_readl(chip,reg) \
 519         readl((chip)->remap_addr + ICH6_REG_##reg)
 520 #define azx_writew(chip,reg,value) \
 521         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 522 #define azx_readw(chip,reg) \
 523         readw((chip)->remap_addr + ICH6_REG_##reg)
 524 #define azx_writeb(chip,reg,value) \
 525         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 526 #define azx_readb(chip,reg) \
 527         readb((chip)->remap_addr + ICH6_REG_##reg)
 528
 529 #define azx_sd_writel(dev,reg,value) \
 530         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 531 #define azx_sd_readl(dev,reg) \
 532         readl((dev)->sd_addr + ICH6_REG_##reg)
 533 #define azx_sd_writew(dev,reg,value) \
 534         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 535 #define azx_sd_readw(dev,reg) \
 536         readw((dev)->sd_addr + ICH6_REG_##reg)
 537 #define azx_sd_writeb(dev,reg,value) \
 538         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 539 #define azx_sd_readb(dev,reg) \
 540         readb((dev)->sd_addr + ICH6_REG_##reg)
 541
 542 /* for pcm support */
 543 #define get_azx_dev(substream) (substream->runtime->private_data)
 544
 545 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 546 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 547 /*
 548  * Interface for HD codec
 549  */
 550
 551 /*
 552  * CORB / RIRB interface
 553  */
 554 static int azx_alloc_cmd_io(struct azx *chip)
 555 {
 556         int err;
 557
 558         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 559         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 560                                   snd_dma_pci_data(chip->pci),
 561                                   PAGE_SIZE, &chip->rb);
 562         if (err < 0) {
 563                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 564                 return err;
 565         }
 566         return 0;
 567 }
 568
 569 static void azx_init_cmd_io(struct azx *chip)
 570 {
 571         spin_lock_irq(&chip->reg_lock);
 572         /* CORB set up */
 573         chip->corb.addr = chip->rb.addr;
 574         chip->corb.buf = (u32 *)chip->rb.area;
 575         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 576         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 577
 578         /* set the corb size to 256 entries (ULI requires explicitly) */
 579         azx_writeb(chip, CORBSIZE, 0x02);
 580         /* set the corb write pointer to 0 */
 581         azx_writew(chip, CORBWP, 0);
 582         /* reset the corb hw read pointer */
 583         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 584         /* enable corb dma */
 585         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 586
 587         /* RIRB set up */
 588         chip->rirb.addr = chip->rb.addr + 2048;
 589         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 590         chip->rirb.wp = chip->rirb.rp = 0;
 591         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 592         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 593         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 594
 595         /* set the rirb size to 256 entries (ULI requires explicitly) */
 596         azx_writeb(chip, RIRBSIZE, 0x02);
 597         /* reset the rirb hw write pointer */
 598         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 599         /* set N=1, get RIRB response interrupt for new entry */
 600         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 601                 azx_writew(chip, RINTCNT, 0xc0);
 602         else
 603                 azx_writew(chip, RINTCNT, 1);
 604         /* enable rirb dma and response irq */
 605         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 606         spin_unlock_irq(&chip->reg_lock);
 607 }
 608
 609 static void azx_free_cmd_io(struct azx *chip)
 610 {
 611         spin_lock_irq(&chip->reg_lock);
 612         /* disable ringbuffer DMAs */
 613         azx_writeb(chip, RIRBCTL, 0);
 614         azx_writeb(chip, CORBCTL, 0);
 615         spin_unlock_irq(&chip->reg_lock);
 616 }
 617
 618 static unsigned int azx_command_addr(u32 cmd)
 619 {
 620         unsigned int addr = cmd >> 28;
 621
 622         if (addr >= AZX_MAX_CODECS) {
 623                 snd_BUG();
 624                 addr = 0;
 625         }
 626
 627         return addr;
 628 }
 629
 630 static unsigned int azx_response_addr(u32 res)
 631 {
 632         unsigned int addr = res & 0xf;
 633
 634         if (addr >= AZX_MAX_CODECS) {
 635                 snd_BUG();
 636                 addr = 0;
 637         }
 638
 639         return addr;
 640 }
 641
 642 /* send a command */
 643 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 644 {
 645         struct azx *chip = bus->private_data;
 646         unsigned int addr = azx_command_addr(val);
 647         unsigned int wp;
 648
 649         spin_lock_irq(&chip->reg_lock);
 650
 651         /* add command to corb */
 652         wp = azx_readb(chip, CORBWP);
 653         wp++;
 654         wp %= ICH6_MAX_CORB_ENTRIES;
 655
 656         chip->rirb.cmds[addr]++;
 657         chip->corb.buf[wp] = cpu_to_le32(val);
 658         azx_writel(chip, CORBWP, wp);
 659
 660         spin_unlock_irq(&chip->reg_lock);
 661
 662         return 0;
 663 }
 664
 665 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 666
 667 /* retrieve RIRB entry - called from interrupt handler */
 668 static void azx_update_rirb(struct azx *chip)
 669 {
 670         unsigned int rp, wp;
 671         unsigned int addr;
 672         u32 res, res_ex;
 673
 674         wp = azx_readb(chip, RIRBWP);
 675         if (wp == chip->rirb.wp)
 676                 return;
 677         chip->rirb.wp = wp;
 678
 679         while (chip->rirb.rp != wp) {
 680                 chip->rirb.rp++;
 681                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 682
 683                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 684                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 685                 res = le32_to_cpu(chip->rirb.buf[rp]);
 686                 addr = azx_response_addr(res_ex);
 687                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 688                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 689                 else if (chip->rirb.cmds[addr]) {
 690                         chip->rirb.res[addr] = res;
 691                         smp_wmb();
 692                         chip->rirb.cmds[addr]--;
 693                 } else
 694                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 695                                    "last cmd=%#08x\n",
 696                                    res, res_ex,
 697                                    chip->last_cmd[addr]);
 698         }
 699 }
 700
 701 /* receive a response */
 702 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 703                                           unsigned int addr)
 704 {
 705         struct azx *chip = bus->private_data;
 706         unsigned long timeout;
 707         int do_poll = 0;
 708
 709  again:
 710         timeout = jiffies + msecs_to_jiffies(1000);
 711         for (;;) {
 712                 if (chip->polling_mode || do_poll) {
 713                         spin_lock_irq(&chip->reg_lock);
 714                         azx_update_rirb(chip);
 715                         spin_unlock_irq(&chip->reg_lock);
 716                 }
 717                 if (!chip->rirb.cmds[addr]) {
 718                         smp_rmb();
 719                         bus->rirb_error = 0;
 720
 721                         if (!do_poll)
 722                                 chip->poll_count = 0;
 723                         return chip->rirb.res[addr]; /* the last value */
 724                 }
 725                 if (time_after(jiffies, timeout))
 726                         break;
 727                 if (bus->needs_damn_long_delay)
 728                         msleep(2); /* temporary workaround */
 729                 else {
 730                         udelay(10);
 731                         cond_resched();
 732                 }
 733         }
 734
 735         if (!chip->polling_mode && chip->poll_count < 2) {
 736                 snd_printdd(SFX "azx_get_response timeout, "
 737                            "polling the codec once: last cmd=0x%08x\n",
 738                            chip->last_cmd[addr]);
 739                 do_poll = 1;
 740                 chip->poll_count++;
 741                 goto again;
 742         }
 743
 744
 745         if (!chip->polling_mode) {
 746                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 747                            "switching to polling mode: last cmd=0x%08x\n",
 748                            chip->last_cmd[addr]);
 749                 chip->polling_mode = 1;
 750                 goto again;
 751         }
 752
 753         if (chip->msi) {
 754                 snd_printk(KERN_WARNING SFX "No response from codec, "
 755                            "disabling MSI: last cmd=0x%08x\n",
 756                            chip->last_cmd[addr]);
 757                 free_irq(chip->irq, chip);
 758                 chip->irq = -1;
 759                 pci_disable_msi(chip->pci);
 760                 chip->msi = 0;
 761                 if (azx_acquire_irq(chip, 1) < 0) {
 762                         bus->rirb_error = 1;
 763                         return -1;
 764                 }
 765                 goto again;
 766         }
 767
 768         if (chip->probing) {
 769                 /* If this critical timeout happens during the codec probing
 770                  * phase, this is likely an access to a non-existing codec
 771                  * slot.  Better to return an error and reset the system.
 772                  */
 773                 return -1;
 774         }
 775
 776         /* a fatal communication error; need either to reset or to fallback
 777          * to the single_cmd mode
 778          */
 779         bus->rirb_error = 1;
 780         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 781                 bus->response_reset = 1;
 782                 return -1; /* give a chance to retry */
 783         }
 784
 785         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 786                    "switching to single_cmd mode: last cmd=0x%08x\n",
 787                    chip->last_cmd[addr]);
 788         chip->single_cmd = 1;
 789         bus->response_reset = 0;
 790         /* release CORB/RIRB */
 791         azx_free_cmd_io(chip);
 792         /* disable unsolicited responses */
 793         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 794         return -1;
 795 }
 796
 797 /*
 798  * Use the single immediate command instead of CORB/RIRB for simplicity
 799  *
 800  * Note: according to Intel, this is not preferred use.  The command was
 801  *       intended for the BIOS only, and may get confused with unsolicited
 802  *       responses.  So, we shouldn't use it for normal operation from the
 803  *       driver.
 804  *       I left the codes, however, for debugging/testing purposes.
 805  */
 806
 807 /* receive a response */
 808 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 809 {
 810         int timeout = 50;
 811
 812         while (timeout--) {
 813                 /* check IRV busy bit */
 814                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 815                         /* reuse rirb.res as the response return value */
 816                         chip->rirb.res[addr] = azx_readl(chip, IR);
 817                         return 0;
 818                 }
 819                 udelay(1);
 820         }
 821         if (printk_ratelimit())
 822                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 823                            azx_readw(chip, IRS));
 824         chip->rirb.res[addr] = -1;
 825         return -EIO;
 826 }
 827
 828 /* send a command */
 829 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 830 {
 831         struct azx *chip = bus->private_data;
 832         unsigned int addr = azx_command_addr(val);
 833         int timeout = 50;
 834
 835         bus->rirb_error = 0;
 836         while (timeout--) {
 837                 /* check ICB busy bit */
 838                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 839                         /* Clear IRV valid bit */
 840                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 841                                    ICH6_IRS_VALID);
 842                         azx_writel(chip, IC, val);
 843                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 844                                    ICH6_IRS_BUSY);
 845                         return azx_single_wait_for_response(chip, addr);
 846                 }
 847                 udelay(1);
 848         }
 849         if (printk_ratelimit())
 850                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 851                            azx_readw(chip, IRS), val);
 852         return -EIO;
 853 }
 854
 855 /* receive a response */
 856 static unsigned int azx_single_get_response(struct hda_bus *bus,
 857                                             unsigned int addr)
 858 {
 859         struct azx *chip = bus->private_data;
 860         return chip->rirb.res[addr];
 861 }
 862
 863 /*
 864  * The below are the main callbacks from hda_codec.
 865  *
 866  * They are just the skeleton to call sub-callbacks according to the
 867  * current setting of chip->single_cmd.
 868  */
 869
 870 /* send a command */
 871 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 872 {
 873         struct azx *chip = bus->private_data;
 874
 875         chip->last_cmd[azx_command_addr(val)] = val;
 876         if (chip->single_cmd)
 877                 return azx_single_send_cmd(bus, val);
 878         else
 879                 return azx_corb_send_cmd(bus, val);
 880 }
 881
 882 /* get a response */
 883 static unsigned int azx_get_response(struct hda_bus *bus,
 884                                      unsigned int addr)
 885 {
 886         struct azx *chip = bus->private_data;
 887         if (chip->single_cmd)
 888                 return azx_single_get_response(bus, addr);
 889         else
 890                 return azx_rirb_get_response(bus, addr);
 891 }
 892
 893 #ifdef CONFIG_SND_HDA_POWER_SAVE
 894 static void azx_power_notify(struct hda_bus *bus);
 895 #endif
 896
 897 /* reset codec link */
 898 static int azx_reset(struct azx *chip, int full_reset)
 899 {
 900         int count;
 901
 902         if (!full_reset)
 903                 goto __skip;
 904
 905         /* clear STATESTS */
 906         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 907
 908         /* reset controller */
 909         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 910
 911         count = 50;
 912         while (azx_readb(chip, GCTL) && --count)
 913                 msleep(1);
 914
 915         /* delay for >= 100us for codec PLL to settle per spec
 916          * Rev 0.9 section 5.5.1
 917          */
 918         msleep(1);
 919
 920         /* Bring controller out of reset */
 921         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 922
 923         count = 50;
 924         while (!azx_readb(chip, GCTL) && --count)
 925                 msleep(1);
 926
 927         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 928         msleep(1);
 929
 930       __skip:
 931         /* check to see if controller is ready */
 932         if (!azx_readb(chip, GCTL)) {
 933                 snd_printd(SFX "azx_reset: controller not ready!\n");
 934                 return -EBUSY;
 935         }
 936
 937         /* Accept unsolicited responses */
 938         if (!chip->single_cmd)
 939                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 940                            ICH6_GCTL_UNSOL);
 941
 942         /* detect codecs */
 943         if (!chip->codec_mask) {
 944                 chip->codec_mask = azx_readw(chip, STATESTS);
 945                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 946         }
 947
 948         return 0;
 949 }
 950
 951
 952 /*
 953  * Lowlevel interface
 954  */
 955
 956 /* enable interrupts */
 957 static void azx_int_enable(struct azx *chip)
 958 {
 959         /* enable controller CIE and GIE */
 960         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 961                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 962 }
 963
 964 /* disable interrupts */
 965 static void azx_int_disable(struct azx *chip)
 966 {
 967         int i;
 968
 969         /* disable interrupts in stream descriptor */
 970         for (i = 0; i < chip->num_streams; i++) {
 971                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 972                 azx_sd_writeb(azx_dev, SD_CTL,
 973                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 974         }
 975
 976         /* disable SIE for all streams */
 977         azx_writeb(chip, INTCTL, 0);
 978
 979         /* disable controller CIE and GIE */
 980         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 981                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 982 }
 983
 984 /* clear interrupts */
 985 static void azx_int_clear(struct azx *chip)
 986 {
 987         int i;
 988
 989         /* clear stream status */
 990         for (i = 0; i < chip->num_streams; i++) {
 991                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 992                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 993         }
 994
 995         /* clear STATESTS */
 996         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 997
 998         /* clear rirb status */
 999         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1000
1001         /* clear int status */
1002         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1003 }
1004
1005 /* start a stream */
1006 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1007 {
1008         /*
1009          * Before stream start, initialize parameter
1010          */
1011         azx_dev->insufficient = 1;
1012
1013         /* enable SIE */
1014         azx_writel(chip, INTCTL,
1015                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1016         /* set DMA start and interrupt mask */
1017         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1018                       SD_CTL_DMA_START | SD_INT_MASK);
1019 }
1020
1021 /* stop DMA */
1022 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1023 {
1024         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1025                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1026         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1027 }
1028
1029 /* stop a stream */
1030 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1031 {
1032         azx_stream_clear(chip, azx_dev);
1033         /* disable SIE */
1034         azx_writel(chip, INTCTL,
1035                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1036 }
1037
1038
1039 /*
1040  * reset and start the controller registers
1041  */
1042 static void azx_init_chip(struct azx *chip, int full_reset)
1043 {
1044         if (chip->initialized)
1045                 return;
1046
1047         /* reset controller */
1048         azx_reset(chip, full_reset);
1049
1050         /* initialize interrupts */
1051         azx_int_clear(chip);
1052         azx_int_enable(chip);
1053
1054         /* initialize the codec command I/O */
1055         if (!chip->single_cmd)
1056                 azx_init_cmd_io(chip);
1057
1058         /* program the position buffer */
1059         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1060         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1061
1062         chip->initialized = 1;
1063 }
1064
1065 /*
1066  * initialize the PCI registers
1067  */
1068 /* update bits in a PCI register byte */
1069 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1070                             unsigned char mask, unsigned char val)
1071 {
1072         unsigned char data;
1073
1074         pci_read_config_byte(pci, reg, &data);
1075         data &= ~mask;
1076         data |= (val & mask);
1077         pci_write_config_byte(pci, reg, data);
1078 }
1079
1080 static void azx_init_pci(struct azx *chip)
1081 {
1082         unsigned short snoop;
1083
1084         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1085          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1086          * Ensuring these bits are 0 clears playback static on some HD Audio
1087          * codecs.
1088          * The PCI register TCSEL is defined in the Intel manuals.
1089          */
1090         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1091                 snd_printdd(SFX "Clearing TCSEL\n");
1092                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1093         }
1094
1095         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1096          * we need to enable snoop.
1097          */
1098         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1099                 snd_printdd(SFX "Enabling ATI snoop\n");
1100                 update_pci_byte(chip->pci,
1101                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1102                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1103         }
1104
1105         /* For NVIDIA HDA, enable snoop */
1106         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1107                 snd_printdd(SFX "Enabling Nvidia snoop\n");
1108                 update_pci_byte(chip->pci,
1109                                 NVIDIA_HDA_TRANSREG_ADDR,
1110                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1111                 update_pci_byte(chip->pci,
1112                                 NVIDIA_HDA_ISTRM_COH,
1113                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1114                 update_pci_byte(chip->pci,
1115                                 NVIDIA_HDA_OSTRM_COH,
1116                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1117         }
1118
1119         /* Enable SCH/PCH snoop if needed */
1120         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1121                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1122                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1123                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1124                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1125                         pci_read_config_word(chip->pci,
1126                                 INTEL_SCH_HDA_DEVC, &snoop);
1127                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1128                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1129                                 ? "Failed" : "OK");
1130                 }
1131         }
1132 }
1133
1134
1135 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1136
1137 /*
1138  * interrupt handler
1139  */
1140 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1141 {
1142         struct azx *chip = dev_id;
1143         struct azx_dev *azx_dev;
1144         u32 status;
1145         u8 sd_status;
1146         int i, ok;
1147
1148         spin_lock(&chip->reg_lock);
1149
1150         status = azx_readl(chip, INTSTS);
1151         if (status == 0) {
1152                 spin_unlock(&chip->reg_lock);
1153                 return IRQ_NONE;
1154         }
1155
1156         for (i = 0; i < chip->num_streams; i++) {
1157                 azx_dev = &chip->azx_dev[i];
1158                 if (status & azx_dev->sd_int_sta_mask) {
1159                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1160                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1161                         if (!azx_dev->substream || !azx_dev->running ||
1162                             !(sd_status & SD_INT_COMPLETE))
1163                                 continue;
1164                         /* check whether this IRQ is really acceptable */
1165                         ok = azx_position_ok(chip, azx_dev);
1166                         if (ok == 1) {
1167                                 azx_dev->irq_pending = 0;
1168                                 spin_unlock(&chip->reg_lock);
1169                                 snd_pcm_period_elapsed(azx_dev->substream);
1170                                 spin_lock(&chip->reg_lock);
1171                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1172                                 /* bogus IRQ, process it later */
1173                                 azx_dev->irq_pending = 1;
1174                                 queue_work(chip->bus->workq,
1175                                            &chip->irq_pending_work);
1176                         }
1177                 }
1178         }
1179
1180         /* clear rirb int */
1181         status = azx_readb(chip, RIRBSTS);
1182         if (status & RIRB_INT_MASK) {
1183                 if (status & RIRB_INT_RESPONSE) {
1184                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1185                                 udelay(80);
1186                         azx_update_rirb(chip);
1187                 }
1188                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1189         }
1190
1191 #if 0
1192         /* clear state status int */
1193         if (azx_readb(chip, STATESTS) & 0x04)
1194                 azx_writeb(chip, STATESTS, 0x04);
1195 #endif
1196         spin_unlock(&chip->reg_lock);
1197
1198         return IRQ_HANDLED;
1199 }
1200
1201
1202 /*
1203  * set up a BDL entry
1204  */
1205 static int setup_bdle(struct snd_pcm_substream *substream,
1206                       struct azx_dev *azx_dev, u32 **bdlp,
1207                       int ofs, int size, int with_ioc)
1208 {
1209         u32 *bdl = *bdlp;
1210
1211         while (size > 0) {
1212                 dma_addr_t addr;
1213                 int chunk;
1214
1215                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1216                         return -EINVAL;
1217
1218                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1219                 /* program the address field of the BDL entry */
1220                 bdl[0] = cpu_to_le32((u32)addr);
1221                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1222                 /* program the size field of the BDL entry */
1223                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1224                 bdl[2] = cpu_to_le32(chunk);
1225                 /* program the IOC to enable interrupt
1226                  * only when the whole fragment is processed
1227                  */
1228                 size -= chunk;
1229                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1230                 bdl += 4;
1231                 azx_dev->frags++;
1232                 ofs += chunk;
1233         }
1234         *bdlp = bdl;
1235         return ofs;
1236 }
1237
1238 /*
1239  * set up BDL entries
1240  */
1241 static int azx_setup_periods(struct azx *chip,
1242                              struct snd_pcm_substream *substream,
1243                              struct azx_dev *azx_dev)
1244 {
1245         u32 *bdl;
1246         int i, ofs, periods, period_bytes;
1247         int pos_adj;
1248
1249         /* reset BDL address */
1250         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1251         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1252
1253         period_bytes = azx_dev->period_bytes;
1254         periods = azx_dev->bufsize / period_bytes;
1255
1256         /* program the initial BDL entries */
1257         bdl = (u32 *)azx_dev->bdl.area;
1258         ofs = 0;
1259         azx_dev->frags = 0;
1260         pos_adj = bdl_pos_adj[chip->dev_index];
1261         if (pos_adj > 0) {
1262                 struct snd_pcm_runtime *runtime = substream->runtime;
1263                 int pos_align = pos_adj;
1264                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1265                 if (!pos_adj)
1266                         pos_adj = pos_align;
1267                 else
1268                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1269                                 pos_align;
1270                 pos_adj = frames_to_bytes(runtime, pos_adj);
1271                 if (pos_adj >= period_bytes) {
1272                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1273                                    bdl_pos_adj[chip->dev_index]);
1274                         pos_adj = 0;
1275                 } else {
1276                         ofs = setup_bdle(substream, azx_dev,
1277                                          &bdl, ofs, pos_adj,
1278                                          !substream->runtime->no_period_wakeup);
1279                         if (ofs < 0)
1280                                 goto error;
1281                 }
1282         } else
1283                 pos_adj = 0;
1284         for (i = 0; i < periods; i++) {
1285                 if (i == periods - 1 && pos_adj)
1286                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1287                                          period_bytes - pos_adj, 0);
1288                 else
1289                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1290                                          period_bytes,
1291                                          !substream->runtime->no_period_wakeup);
1292                 if (ofs < 0)
1293                         goto error;
1294         }
1295         return 0;
1296
1297  error:
1298         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1299                    azx_dev->bufsize, period_bytes);
1300         return -EINVAL;
1301 }
1302
1303 /* reset stream */
1304 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1305 {
1306         unsigned char val;
1307         int timeout;
1308
1309         azx_stream_clear(chip, azx_dev);
1310
1311         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1312                       SD_CTL_STREAM_RESET);
1313         udelay(3);
1314         timeout = 300;
1315         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1316                --timeout)
1317                 ;
1318         val &= ~SD_CTL_STREAM_RESET;
1319         azx_sd_writeb(azx_dev, SD_CTL, val);
1320         udelay(3);
1321
1322         timeout = 300;
1323         /* waiting for hardware to report that the stream is out of reset */
1324         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1325                --timeout)
1326                 ;
1327
1328         /* reset first position - may not be synced with hw at this time */
1329         *azx_dev->posbuf = 0;
1330 }
1331
1332 /*
1333  * set up the SD for streaming
1334  */
1335 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1336 {
1337         /* make sure the run bit is zero for SD */
1338         azx_stream_clear(chip, azx_dev);
1339         /* program the stream_tag */
1340         azx_sd_writel(azx_dev, SD_CTL,
1341                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1342                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1343
1344         /* program the length of samples in cyclic buffer */
1345         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1346
1347         /* program the stream format */
1348         /* this value needs to be the same as the one programmed */
1349         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1350
1351         /* program the stream LVI (last valid index) of the BDL */
1352         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1353
1354         /* program the BDL address */
1355         /* lower BDL address */
1356         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1357         /* upper BDL address */
1358         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1359
1360         /* enable the position buffer */
1361         if (chip->position_fix[0] != POS_FIX_LPIB ||
1362             chip->position_fix[1] != POS_FIX_LPIB) {
1363                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1364                         azx_writel(chip, DPLBASE,
1365                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1366         }
1367
1368         /* set the interrupt enable bits in the descriptor control register */
1369         azx_sd_writel(azx_dev, SD_CTL,
1370                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1371
1372         return 0;
1373 }
1374
1375 /*
1376  * Probe the given codec address
1377  */
1378 static int probe_codec(struct azx *chip, int addr)
1379 {
1380         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1381                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1382         unsigned int res;
1383
1384         mutex_lock(&chip->bus->cmd_mutex);
1385         chip->probing = 1;
1386         azx_send_cmd(chip->bus, cmd);
1387         res = azx_get_response(chip->bus, addr);
1388         chip->probing = 0;
1389         mutex_unlock(&chip->bus->cmd_mutex);
1390         if (res == -1)
1391                 return -EIO;
1392         snd_printdd(SFX "codec #%d probed OK\n", addr);
1393         return 0;
1394 }
1395
1396 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1397                                  struct hda_pcm *cpcm);
1398 static void azx_stop_chip(struct azx *chip);
1399
1400 static void azx_bus_reset(struct hda_bus *bus)
1401 {
1402         struct azx *chip = bus->private_data;
1403
1404         bus->in_reset = 1;
1405         azx_stop_chip(chip);
1406         azx_init_chip(chip, 1);
1407 #ifdef CONFIG_PM
1408         if (chip->initialized) {
1409                 int i;
1410
1411                 for (i = 0; i < HDA_MAX_PCMS; i++)
1412                         snd_pcm_suspend_all(chip->pcm[i]);
1413                 snd_hda_suspend(chip->bus);
1414                 snd_hda_resume(chip->bus);
1415         }
1416 #endif
1417         bus->in_reset = 0;
1418 }
1419
1420 /*
1421  * Codec initialization
1422  */
1423
1424 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1425 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1426         [AZX_DRIVER_NVIDIA] = 8,
1427         [AZX_DRIVER_TERA] = 1,
1428 };
1429
1430 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1431 {
1432         struct hda_bus_template bus_temp;
1433         int c, codecs, err;
1434         int max_slots;
1435
1436         memset(&bus_temp, 0, sizeof(bus_temp));
1437         bus_temp.private_data = chip;
1438         bus_temp.modelname = model;
1439         bus_temp.pci = chip->pci;
1440         bus_temp.ops.command = azx_send_cmd;
1441         bus_temp.ops.get_response = azx_get_response;
1442         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1443         bus_temp.ops.bus_reset = azx_bus_reset;
1444 #ifdef CONFIG_SND_HDA_POWER_SAVE
1445         bus_temp.power_save = &power_save;
1446         bus_temp.ops.pm_notify = azx_power_notify;
1447 #endif
1448
1449         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1450         if (err < 0)
1451                 return err;
1452
1453         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1454                 snd_printd(SFX "Enable delay in RIRB handling\n");
1455                 chip->bus->needs_damn_long_delay = 1;
1456         }
1457
1458         codecs = 0;
1459         max_slots = azx_max_codecs[chip->driver_type];
1460         if (!max_slots)
1461                 max_slots = AZX_DEFAULT_CODECS;
1462
1463         /* First try to probe all given codec slots */
1464         for (c = 0; c < max_slots; c++) {
1465                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1466                         if (probe_codec(chip, c) < 0) {
1467                                 /* Some BIOSen give you wrong codec addresses
1468                                  * that don't exist
1469                                  */
1470                                 snd_printk(KERN_WARNING SFX
1471                                            "Codec #%d probe error; "
1472                                            "disabling it...\n", c);
1473                                 chip->codec_mask &= ~(1 << c);
1474                                 /* More badly, accessing to a non-existing
1475                                  * codec often screws up the controller chip,
1476                                  * and disturbs the further communications.
1477                                  * Thus if an error occurs during probing,
1478                                  * better to reset the controller chip to
1479                                  * get back to the sanity state.
1480                                  */
1481                                 azx_stop_chip(chip);
1482                                 azx_init_chip(chip, 1);
1483                         }
1484                 }
1485         }
1486
1487         /* AMD chipsets often cause the communication stalls upon certain
1488          * sequence like the pin-detection.  It seems that forcing the synced
1489          * access works around the stall.  Grrr...
1490          */
1491         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1492                 snd_printd(SFX "Enable sync_write for stable communication\n");
1493                 chip->bus->sync_write = 1;
1494                 chip->bus->allow_bus_reset = 1;
1495         }
1496
1497         /* Then create codec instances */
1498         for (c = 0; c < max_slots; c++) {
1499                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1500                         struct hda_codec *codec;
1501                         err = snd_hda_codec_new(chip->bus, c, &codec);
1502                         if (err < 0)
1503                                 continue;
1504                         codec->beep_mode = chip->beep_mode;
1505                         codecs++;
1506                 }
1507         }
1508         if (!codecs) {
1509                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1510                 return -ENXIO;
1511         }
1512         return 0;
1513 }
1514
1515 /* configure each codec instance */
1516 static int __devinit azx_codec_configure(struct azx *chip)
1517 {
1518         struct hda_codec *codec;
1519         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1520                 snd_hda_codec_configure(codec);
1521         }
1522         return 0;
1523 }
1524
1525
1526 /*
1527  * PCM support
1528  */
1529
1530 /* assign a stream for the PCM */
1531 static inline struct azx_dev *
1532 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1533 {
1534         int dev, i, nums;
1535         struct azx_dev *res = NULL;
1536
1537         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1538                 dev = chip->playback_index_offset;
1539                 nums = chip->playback_streams;
1540         } else {
1541                 dev = chip->capture_index_offset;
1542                 nums = chip->capture_streams;
1543         }
1544         for (i = 0; i < nums; i++, dev++)
1545                 if (!chip->azx_dev[dev].opened) {
1546                         res = &chip->azx_dev[dev];
1547                         if (res->device == substream->pcm->device)
1548                                 break;
1549                 }
1550         if (res) {
1551                 res->opened = 1;
1552                 res->device = substream->pcm->device;
1553         }
1554         return res;
1555 }
1556
1557 /* release the assigned stream */
1558 static inline void azx_release_device(struct azx_dev *azx_dev)
1559 {
1560         azx_dev->opened = 0;
1561 }
1562
1563 static struct snd_pcm_hardware azx_pcm_hw = {
1564         .info =                 (SNDRV_PCM_INFO_MMAP |
1565                                  SNDRV_PCM_INFO_INTERLEAVED |
1566                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1567                                  SNDRV_PCM_INFO_MMAP_VALID |
1568                                  /* No full-resume yet implemented */
1569                                  /* SNDRV_PCM_INFO_RESUME |*/
1570                                  SNDRV_PCM_INFO_PAUSE |
1571                                  SNDRV_PCM_INFO_SYNC_START |
1572                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1573         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1574         .rates =                SNDRV_PCM_RATE_48000,
1575         .rate_min =             48000,
1576         .rate_max =             48000,
1577         .channels_min =         2,
1578         .channels_max =         2,
1579         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1580         .period_bytes_min =     128,
1581         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1582         .periods_min =          2,
1583         .periods_max =          AZX_MAX_FRAG,
1584         .fifo_size =            0,
1585 };
1586
1587 struct azx_pcm {
1588         struct azx *chip;
1589         struct hda_codec *codec;
1590         struct hda_pcm_stream *hinfo[2];
1591 };
1592
1593 static int azx_pcm_open(struct snd_pcm_substream *substream)
1594 {
1595         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1596         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1597         struct azx *chip = apcm->chip;
1598         struct azx_dev *azx_dev;
1599         struct snd_pcm_runtime *runtime = substream->runtime;
1600         unsigned long flags;
1601         int err;
1602
1603         mutex_lock(&chip->open_mutex);
1604         azx_dev = azx_assign_device(chip, substream);
1605         if (azx_dev == NULL) {
1606                 mutex_unlock(&chip->open_mutex);
1607                 return -EBUSY;
1608         }
1609         runtime->hw = azx_pcm_hw;
1610         runtime->hw.channels_min = hinfo->channels_min;
1611         runtime->hw.channels_max = hinfo->channels_max;
1612         runtime->hw.formats = hinfo->formats;
1613         runtime->hw.rates = hinfo->rates;
1614         snd_pcm_limit_hw_rates(runtime);
1615         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1616         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1617                                    128);
1618         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1619                                    128);
1620         snd_hda_power_up(apcm->codec);
1621         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1622         if (err < 0) {
1623                 azx_release_device(azx_dev);
1624                 snd_hda_power_down(apcm->codec);
1625                 mutex_unlock(&chip->open_mutex);
1626                 return err;
1627         }
1628         snd_pcm_limit_hw_rates(runtime);
1629         /* sanity check */
1630         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1631             snd_BUG_ON(!runtime->hw.channels_max) ||
1632             snd_BUG_ON(!runtime->hw.formats) ||
1633             snd_BUG_ON(!runtime->hw.rates)) {
1634                 azx_release_device(azx_dev);
1635                 hinfo->ops.close(hinfo, apcm->codec, substream);
1636                 snd_hda_power_down(apcm->codec);
1637                 mutex_unlock(&chip->open_mutex);
1638                 return -EINVAL;
1639         }
1640         spin_lock_irqsave(&chip->reg_lock, flags);
1641         azx_dev->substream = substream;
1642         azx_dev->running = 0;
1643         spin_unlock_irqrestore(&chip->reg_lock, flags);
1644
1645         runtime->private_data = azx_dev;
1646         snd_pcm_set_sync(substream);
1647         mutex_unlock(&chip->open_mutex);
1648         return 0;
1649 }
1650
1651 static int azx_pcm_close(struct snd_pcm_substream *substream)
1652 {
1653         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1654         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1655         struct azx *chip = apcm->chip;
1656         struct azx_dev *azx_dev = get_azx_dev(substream);
1657         unsigned long flags;
1658
1659         mutex_lock(&chip->open_mutex);
1660         spin_lock_irqsave(&chip->reg_lock, flags);
1661         azx_dev->substream = NULL;
1662         azx_dev->running = 0;
1663         spin_unlock_irqrestore(&chip->reg_lock, flags);
1664         azx_release_device(azx_dev);
1665         hinfo->ops.close(hinfo, apcm->codec, substream);
1666         snd_hda_power_down(apcm->codec);
1667         mutex_unlock(&chip->open_mutex);
1668         return 0;
1669 }
1670
1671 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1672                              struct snd_pcm_hw_params *hw_params)
1673 {
1674         struct azx_dev *azx_dev = get_azx_dev(substream);
1675
1676         azx_dev->bufsize = 0;
1677         azx_dev->period_bytes = 0;
1678         azx_dev->format_val = 0;
1679         return snd_pcm_lib_malloc_pages(substream,
1680                                         params_buffer_bytes(hw_params));
1681 }
1682
1683 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1684 {
1685         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1686         struct azx_dev *azx_dev = get_azx_dev(substream);
1687         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1688
1689         /* reset BDL address */
1690         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1691         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1692         azx_sd_writel(azx_dev, SD_CTL, 0);
1693         azx_dev->bufsize = 0;
1694         azx_dev->period_bytes = 0;
1695         azx_dev->format_val = 0;
1696
1697         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1698
1699         return snd_pcm_lib_free_pages(substream);
1700 }
1701
1702 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1703 {
1704         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1705         struct azx *chip = apcm->chip;
1706         struct azx_dev *azx_dev = get_azx_dev(substream);
1707         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1708         struct snd_pcm_runtime *runtime = substream->runtime;
1709         unsigned int bufsize, period_bytes, format_val, stream_tag;
1710         int err;
1711         struct hda_spdif_out *spdif =
1712                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1713         unsigned short ctls = spdif ? spdif->ctls : 0;
1714
1715         azx_stream_reset(chip, azx_dev);
1716         format_val = snd_hda_calc_stream_format(runtime->rate,
1717                                                 runtime->channels,
1718                                                 runtime->format,
1719                                                 hinfo->maxbps,
1720                                                 ctls);
1721         if (!format_val) {
1722                 snd_printk(KERN_ERR SFX
1723                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1724                            runtime->rate, runtime->channels, runtime->format);
1725                 return -EINVAL;
1726         }
1727
1728         bufsize = snd_pcm_lib_buffer_bytes(substream);
1729         period_bytes = snd_pcm_lib_period_bytes(substream);
1730
1731         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1732                     bufsize, format_val);
1733
1734         if (bufsize != azx_dev->bufsize ||
1735             period_bytes != azx_dev->period_bytes ||
1736             format_val != azx_dev->format_val) {
1737                 azx_dev->bufsize = bufsize;
1738                 azx_dev->period_bytes = period_bytes;
1739                 azx_dev->format_val = format_val;
1740                 err = azx_setup_periods(chip, substream, azx_dev);
1741                 if (err < 0)
1742                         return err;
1743         }
1744
1745         /* wallclk has 24Mhz clock source */
1746         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1747                                                 runtime->rate) * 1000);
1748         azx_setup_controller(chip, azx_dev);
1749         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1750                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1751         else
1752                 azx_dev->fifo_size = 0;
1753
1754         stream_tag = azx_dev->stream_tag;
1755         /* CA-IBG chips need the playback stream starting from 1 */
1756         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1757             stream_tag > chip->capture_streams)
1758                 stream_tag -= chip->capture_streams;
1759         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1760                                      azx_dev->format_val, substream);
1761 }
1762
1763 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1764 {
1765         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1766         struct azx *chip = apcm->chip;
1767         struct azx_dev *azx_dev;
1768         struct snd_pcm_substream *s;
1769         int rstart = 0, start, nsync = 0, sbits = 0;
1770         int nwait, timeout;
1771
1772         switch (cmd) {
1773         case SNDRV_PCM_TRIGGER_START:
1774                 rstart = 1;
1775         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1776         case SNDRV_PCM_TRIGGER_RESUME:
1777                 start = 1;
1778                 break;
1779         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1780         case SNDRV_PCM_TRIGGER_SUSPEND:
1781         case SNDRV_PCM_TRIGGER_STOP:
1782                 start = 0;
1783                 break;
1784         default:
1785                 return -EINVAL;
1786         }
1787
1788         snd_pcm_group_for_each_entry(s, substream) {
1789                 if (s->pcm->card != substream->pcm->card)
1790                         continue;
1791                 azx_dev = get_azx_dev(s);
1792                 sbits |= 1 << azx_dev->index;
1793                 nsync++;
1794                 snd_pcm_trigger_done(s, substream);
1795         }
1796
1797         spin_lock(&chip->reg_lock);
1798         if (nsync > 1) {
1799                 /* first, set SYNC bits of corresponding streams */
1800                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1801                         azx_writel(chip, OLD_SSYNC,
1802                                    azx_readl(chip, OLD_SSYNC) | sbits);
1803                 else
1804                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1805         }
1806         snd_pcm_group_for_each_entry(s, substream) {
1807                 if (s->pcm->card != substream->pcm->card)
1808                         continue;
1809                 azx_dev = get_azx_dev(s);
1810                 if (start) {
1811                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1812                         if (!rstart)
1813                                 azx_dev->start_wallclk -=
1814                                                 azx_dev->period_wallclk;
1815                         azx_stream_start(chip, azx_dev);
1816                 } else {
1817                         azx_stream_stop(chip, azx_dev);
1818                 }
1819                 azx_dev->running = start;
1820         }
1821         spin_unlock(&chip->reg_lock);
1822         if (start) {
1823                 if (nsync == 1)
1824                         return 0;
1825                 /* wait until all FIFOs get ready */
1826                 for (timeout = 5000; timeout; timeout--) {
1827                         nwait = 0;
1828                         snd_pcm_group_for_each_entry(s, substream) {
1829                                 if (s->pcm->card != substream->pcm->card)
1830                                         continue;
1831                                 azx_dev = get_azx_dev(s);
1832                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1833                                       SD_STS_FIFO_READY))
1834                                         nwait++;
1835                         }
1836                         if (!nwait)
1837                                 break;
1838                         cpu_relax();
1839                 }
1840         } else {
1841                 /* wait until all RUN bits are cleared */
1842                 for (timeout = 5000; timeout; timeout--) {
1843                         nwait = 0;
1844                         snd_pcm_group_for_each_entry(s, substream) {
1845                                 if (s->pcm->card != substream->pcm->card)
1846                                         continue;
1847                                 azx_dev = get_azx_dev(s);
1848                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1849                                     SD_CTL_DMA_START)
1850                                         nwait++;
1851                         }
1852                         if (!nwait)
1853                                 break;
1854                         cpu_relax();
1855                 }
1856         }
1857         if (nsync > 1) {
1858                 spin_lock(&chip->reg_lock);
1859                 /* reset SYNC bits */
1860                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1861                         azx_writel(chip, OLD_SSYNC,
1862                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1863                 else
1864                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1865                 spin_unlock(&chip->reg_lock);
1866         }
1867         return 0;
1868 }
1869
1870 /* get the current DMA position with correction on VIA chips */
1871 static unsigned int azx_via_get_position(struct azx *chip,
1872                                          struct azx_dev *azx_dev)
1873 {
1874         unsigned int link_pos, mini_pos, bound_pos;
1875         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1876         unsigned int fifo_size;
1877
1878         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1879         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1880                 /* Playback, no problem using link position */
1881                 return link_pos;
1882         }
1883
1884         /* Capture */
1885         /* For new chipset,
1886          * use mod to get the DMA position just like old chipset
1887          */
1888         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1889         mod_dma_pos %= azx_dev->period_bytes;
1890
1891         /* azx_dev->fifo_size can't get FIFO size of in stream.
1892          * Get from base address + offset.
1893          */
1894         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1895
1896         if (azx_dev->insufficient) {
1897                 /* Link position never gather than FIFO size */
1898                 if (link_pos <= fifo_size)
1899                         return 0;
1900
1901                 azx_dev->insufficient = 0;
1902         }
1903
1904         if (link_pos <= fifo_size)
1905                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1906         else
1907                 mini_pos = link_pos - fifo_size;
1908
1909         /* Find nearest previous boudary */
1910         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1911         mod_link_pos = link_pos % azx_dev->period_bytes;
1912         if (mod_link_pos >= fifo_size)
1913                 bound_pos = link_pos - mod_link_pos;
1914         else if (mod_dma_pos >= mod_mini_pos)
1915                 bound_pos = mini_pos - mod_mini_pos;
1916         else {
1917                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1918                 if (bound_pos >= azx_dev->bufsize)
1919                         bound_pos = 0;
1920         }
1921
1922         /* Calculate real DMA position we want */
1923         return bound_pos + mod_dma_pos;
1924 }
1925
1926 static unsigned int azx_get_position(struct azx *chip,
1927                                      struct azx_dev *azx_dev)
1928 {
1929         unsigned int pos;
1930         int stream = azx_dev->substream->stream;
1931
1932         switch (chip->position_fix[stream]) {
1933         case POS_FIX_LPIB:
1934                 /* read LPIB */
1935                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1936                 break;
1937         case POS_FIX_VIACOMBO:
1938                 pos = azx_via_get_position(chip, azx_dev);
1939                 break;
1940         default:
1941                 /* use the position buffer */
1942                 pos = le32_to_cpu(*azx_dev->posbuf);
1943                 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1944                         if (!pos || pos == (u32)-1) {
1945                                 printk(KERN_WARNING
1946                                        "hda-intel: Invalid position buffer, "
1947                                        "using LPIB read method instead.\n");
1948                                 chip->position_fix[stream] = POS_FIX_LPIB;
1949                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1950                         } else
1951                                 chip->position_fix[stream] = POS_FIX_POSBUF;
1952                 }
1953                 break;
1954         }
1955
1956         if (pos >= azx_dev->bufsize)
1957                 pos = 0;
1958         return pos;
1959 }
1960
1961 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1962 {
1963         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1964         struct azx *chip = apcm->chip;
1965         struct azx_dev *azx_dev = get_azx_dev(substream);
1966         return bytes_to_frames(substream->runtime,
1967                                azx_get_position(chip, azx_dev));
1968 }
1969
1970 /*
1971  * Check whether the current DMA position is acceptable for updating
1972  * periods.  Returns non-zero if it's OK.
1973  *
1974  * Many HD-audio controllers appear pretty inaccurate about
1975  * the update-IRQ timing.  The IRQ is issued before actually the
1976  * data is processed.  So, we need to process it afterwords in a
1977  * workqueue.
1978  */
1979 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1980 {
1981         u32 wallclk;
1982         unsigned int pos;
1983         int stream;
1984
1985         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1986         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1987                 return -1;      /* bogus (too early) interrupt */
1988
1989         stream = azx_dev->substream->stream;
1990         pos = azx_get_position(chip, azx_dev);
1991
1992         if (WARN_ONCE(!azx_dev->period_bytes,
1993                       "hda-intel: zero azx_dev->period_bytes"))
1994                 return -1; /* this shouldn't happen! */
1995         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1996             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1997                 /* NG - it's below the first next period boundary */
1998                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1999         azx_dev->start_wallclk += wallclk;
2000         return 1; /* OK, it's fine */
2001 }
2002
2003 /*
2004  * The work for pending PCM period updates.
2005  */
2006 static void azx_irq_pending_work(struct work_struct *work)
2007 {
2008         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2009         int i, pending, ok;
2010
2011         if (!chip->irq_pending_warned) {
2012                 printk(KERN_WARNING
2013                        "hda-intel: IRQ timing workaround is activated "
2014                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2015                        chip->card->number);
2016                 chip->irq_pending_warned = 1;
2017         }
2018
2019         for (;;) {
2020                 pending = 0;
2021                 spin_lock_irq(&chip->reg_lock);
2022                 for (i = 0; i < chip->num_streams; i++) {
2023                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2024                         if (!azx_dev->irq_pending ||
2025                             !azx_dev->substream ||
2026                             !azx_dev->running)
2027                                 continue;
2028                         ok = azx_position_ok(chip, azx_dev);
2029                         if (ok > 0) {
2030                                 azx_dev->irq_pending = 0;
2031                                 spin_unlock(&chip->reg_lock);
2032                                 snd_pcm_period_elapsed(azx_dev->substream);
2033                                 spin_lock(&chip->reg_lock);
2034                         } else if (ok < 0) {
2035                                 pending = 0;    /* too early */
2036                         } else
2037                                 pending++;
2038                 }
2039                 spin_unlock_irq(&chip->reg_lock);
2040                 if (!pending)
2041                         return;
2042                 msleep(1);
2043         }
2044 }
2045
2046 /* clear irq_pending flags and assure no on-going workq */
2047 static void azx_clear_irq_pending(struct azx *chip)
2048 {
2049         int i;
2050
2051         spin_lock_irq(&chip->reg_lock);
2052         for (i = 0; i < chip->num_streams; i++)
2053                 chip->azx_dev[i].irq_pending = 0;
2054         spin_unlock_irq(&chip->reg_lock);
2055 }
2056
2057 static struct snd_pcm_ops azx_pcm_ops = {
2058         .open = azx_pcm_open,
2059         .close = azx_pcm_close,
2060         .ioctl = snd_pcm_lib_ioctl,
2061         .hw_params = azx_pcm_hw_params,
2062         .hw_free = azx_pcm_hw_free,
2063         .prepare = azx_pcm_prepare,
2064         .trigger = azx_pcm_trigger,
2065         .pointer = azx_pcm_pointer,
2066         .page = snd_pcm_sgbuf_ops_page,
2067 };
2068
2069 static void azx_pcm_free(struct snd_pcm *pcm)
2070 {
2071         struct azx_pcm *apcm = pcm->private_data;
2072         if (apcm) {
2073                 apcm->chip->pcm[pcm->device] = NULL;
2074                 kfree(apcm);
2075         }
2076 }
2077
2078 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2079
2080 static int
2081 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2082                       struct hda_pcm *cpcm)
2083 {
2084         struct azx *chip = bus->private_data;
2085         struct snd_pcm *pcm;
2086         struct azx_pcm *apcm;
2087         int pcm_dev = cpcm->device;
2088         unsigned int size;
2089         int s, err;
2090
2091         if (pcm_dev >= HDA_MAX_PCMS) {
2092                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2093                            pcm_dev);
2094                 return -EINVAL;
2095         }
2096         if (chip->pcm[pcm_dev]) {
2097                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2098                 return -EBUSY;
2099         }
2100         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2101                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2102                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2103                           &pcm);
2104         if (err < 0)
2105                 return err;
2106         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2107         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2108         if (apcm == NULL)
2109                 return -ENOMEM;
2110         apcm->chip = chip;
2111         apcm->codec = codec;
2112         pcm->private_data = apcm;
2113         pcm->private_free = azx_pcm_free;
2114         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2115                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2116         chip->pcm[pcm_dev] = pcm;
2117         cpcm->pcm = pcm;
2118         for (s = 0; s < 2; s++) {
2119                 apcm->hinfo[s] = &cpcm->stream[s];
2120                 if (cpcm->stream[s].substreams)
2121                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2122         }
2123         /* buffer pre-allocation */
2124         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2125         if (size > MAX_PREALLOC_SIZE)
2126                 size = MAX_PREALLOC_SIZE;
2127         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2128                                               snd_dma_pci_data(chip->pci),
2129                                               size, MAX_PREALLOC_SIZE);
2130         return 0;
2131 }
2132
2133 /*
2134  * mixer creation - all stuff is implemented in hda module
2135  */
2136 static int __devinit azx_mixer_create(struct azx *chip)
2137 {
2138         return snd_hda_build_controls(chip->bus);
2139 }
2140
2141
2142 /*
2143  * initialize SD streams
2144  */
2145 static int __devinit azx_init_stream(struct azx *chip)
2146 {
2147         int i;
2148
2149         /* initialize each stream (aka device)
2150          * assign the starting bdl address to each stream (device)
2151          * and initialize
2152          */
2153         for (i = 0; i < chip->num_streams; i++) {
2154                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2155                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2156                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2157                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2158                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2159                 azx_dev->sd_int_sta_mask = 1 << i;
2160                 /* stream tag: must be non-zero and unique */
2161                 azx_dev->index = i;
2162                 azx_dev->stream_tag = i + 1;
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2169 {
2170         if (request_irq(chip->pci->irq, azx_interrupt,
2171                         chip->msi ? 0 : IRQF_SHARED,
2172                         KBUILD_MODNAME, chip)) {
2173                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2174                        "disabling device\n", chip->pci->irq);
2175                 if (do_disconnect)
2176                         snd_card_disconnect(chip->card);
2177                 return -1;
2178         }
2179         chip->irq = chip->pci->irq;
2180         pci_intx(chip->pci, !chip->msi);
2181         return 0;
2182 }
2183
2184
2185 static void azx_stop_chip(struct azx *chip)
2186 {
2187         if (!chip->initialized)
2188                 return;
2189
2190         /* disable interrupts */
2191         azx_int_disable(chip);
2192         azx_int_clear(chip);
2193
2194         /* disable CORB/RIRB */
2195         azx_free_cmd_io(chip);
2196
2197         /* disable position buffer */
2198         azx_writel(chip, DPLBASE, 0);
2199         azx_writel(chip, DPUBASE, 0);
2200
2201         chip->initialized = 0;
2202 }
2203
2204 #ifdef CONFIG_SND_HDA_POWER_SAVE
2205 /* power-up/down the controller */
2206 static void azx_power_notify(struct hda_bus *bus)
2207 {
2208         struct azx *chip = bus->private_data;
2209         struct hda_codec *c;
2210         int power_on = 0;
2211
2212         list_for_each_entry(c, &bus->codec_list, list) {
2213                 if (c->power_on) {
2214                         power_on = 1;
2215                         break;
2216                 }
2217         }
2218         if (power_on)
2219                 azx_init_chip(chip, 1);
2220         else if (chip->running && power_save_controller &&
2221                  !bus->power_keep_link_on)
2222                 azx_stop_chip(chip);
2223 }
2224 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2225
2226 #ifdef CONFIG_PM
2227 /*
2228  * power management
2229  */
2230
2231 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2232 {
2233         struct hda_codec *codec;
2234
2235         list_for_each_entry(codec, &bus->codec_list, list) {
2236                 if (snd_hda_codec_needs_resume(codec))
2237                         return 1;
2238         }
2239         return 0;
2240 }
2241
2242 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2243 {
2244         struct snd_card *card = pci_get_drvdata(pci);
2245         struct azx *chip = card->private_data;
2246         int i;
2247
2248         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2249         azx_clear_irq_pending(chip);
2250         for (i = 0; i < HDA_MAX_PCMS; i++)
2251                 snd_pcm_suspend_all(chip->pcm[i]);
2252         if (chip->initialized)
2253                 snd_hda_suspend(chip->bus);
2254         azx_stop_chip(chip);
2255         if (chip->irq >= 0) {
2256                 free_irq(chip->irq, chip);
2257                 chip->irq = -1;
2258         }
2259         if (chip->msi)
2260                 pci_disable_msi(chip->pci);
2261         pci_disable_device(pci);
2262         pci_save_state(pci);
2263         pci_set_power_state(pci, pci_choose_state(pci, state));
2264         return 0;
2265 }
2266
2267 static int azx_resume(struct pci_dev *pci)
2268 {
2269         struct snd_card *card = pci_get_drvdata(pci);
2270         struct azx *chip = card->private_data;
2271
2272         pci_set_power_state(pci, PCI_D0);
2273         pci_restore_state(pci);
2274         if (pci_enable_device(pci) < 0) {
2275                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2276                        "disabling device\n");
2277                 snd_card_disconnect(card);
2278                 return -EIO;
2279         }
2280         pci_set_master(pci);
2281         if (chip->msi)
2282                 if (pci_enable_msi(pci) < 0)
2283                         chip->msi = 0;
2284         if (azx_acquire_irq(chip, 1) < 0)
2285                 return -EIO;
2286         azx_init_pci(chip);
2287
2288         if (snd_hda_codecs_inuse(chip->bus))
2289                 azx_init_chip(chip, 1);
2290
2291         snd_hda_resume(chip->bus);
2292         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2293         return 0;
2294 }
2295 #endif /* CONFIG_PM */
2296
2297
2298 /*
2299  * reboot notifier for hang-up problem at power-down
2300  */
2301 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2302 {
2303         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2304         snd_hda_bus_reboot_notify(chip->bus);
2305         azx_stop_chip(chip);
2306         return NOTIFY_OK;
2307 }
2308
2309 static void azx_notifier_register(struct azx *chip)
2310 {
2311         chip->reboot_notifier.notifier_call = azx_halt;
2312         register_reboot_notifier(&chip->reboot_notifier);
2313 }
2314
2315 static void azx_notifier_unregister(struct azx *chip)
2316 {
2317         if (chip->reboot_notifier.notifier_call)
2318                 unregister_reboot_notifier(&chip->reboot_notifier);
2319 }
2320
2321 /*
2322  * destructor
2323  */
2324 static int azx_free(struct azx *chip)
2325 {
2326         int i;
2327
2328         azx_notifier_unregister(chip);
2329
2330         if (chip->initialized) {
2331                 azx_clear_irq_pending(chip);
2332                 for (i = 0; i < chip->num_streams; i++)
2333                         azx_stream_stop(chip, &chip->azx_dev[i]);
2334                 azx_stop_chip(chip);
2335         }
2336
2337         if (chip->irq >= 0)
2338                 free_irq(chip->irq, (void*)chip);
2339         if (chip->msi)
2340                 pci_disable_msi(chip->pci);
2341         if (chip->remap_addr)
2342                 iounmap(chip->remap_addr);
2343
2344         if (chip->azx_dev) {
2345                 for (i = 0; i < chip->num_streams; i++)
2346                         if (chip->azx_dev[i].bdl.area)
2347                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2348         }
2349         if (chip->rb.area)
2350                 snd_dma_free_pages(&chip->rb);
2351         if (chip->posbuf.area)
2352                 snd_dma_free_pages(&chip->posbuf);
2353         pci_release_regions(chip->pci);
2354         pci_disable_device(chip->pci);
2355         kfree(chip->azx_dev);
2356         kfree(chip);
2357
2358         return 0;
2359 }
2360
2361 static int azx_dev_free(struct snd_device *device)
2362 {
2363         return azx_free(device->device_data);
2364 }
2365
2366 /*
2367  * white/black-listing for position_fix
2368  */
2369 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2370         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2371         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2372         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2373         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2374         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2375         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2376         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2377         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2378         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2379         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2380         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2381         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2382         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2383         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2384         {}
2385 };
2386
2387 static int __devinit check_position_fix(struct azx *chip, int fix)
2388 {
2389         const struct snd_pci_quirk *q;
2390
2391         switch (fix) {
2392         case POS_FIX_LPIB:
2393         case POS_FIX_POSBUF:
2394         case POS_FIX_VIACOMBO:
2395                 return fix;
2396         }
2397
2398         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2399         if (q) {
2400                 printk(KERN_INFO
2401                        "hda_intel: position_fix set to %d "
2402                        "for device %04x:%04x\n",
2403                        q->value, q->subvendor, q->subdevice);
2404                 return q->value;
2405         }
2406
2407         /* Check VIA/ATI HD Audio Controller exist */
2408         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2409                 snd_printd(SFX "Using VIACOMBO position fix\n");
2410                 return POS_FIX_VIACOMBO;
2411         }
2412         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2413                 snd_printd(SFX "Using LPIB position fix\n");
2414                 return POS_FIX_LPIB;
2415         }
2416         return POS_FIX_AUTO;
2417 }
2418
2419 /*
2420  * black-lists for probe_mask
2421  */
2422 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2423         /* Thinkpad often breaks the controller communication when accessing
2424          * to the non-working (or non-existing) modem codec slot.
2425          */
2426         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2427         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2428         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2429         /* broken BIOS */
2430         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2431         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2432         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2433         /* forced codec slots */
2434         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2435         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2436         {}
2437 };
2438
2439 #define AZX_FORCE_CODEC_MASK    0x100
2440
2441 static void __devinit check_probe_mask(struct azx *chip, int dev)
2442 {
2443         const struct snd_pci_quirk *q;
2444
2445         chip->codec_probe_mask = probe_mask[dev];
2446         if (chip->codec_probe_mask == -1) {
2447                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2448                 if (q) {
2449                         printk(KERN_INFO
2450                                "hda_intel: probe_mask set to 0x%x "
2451                                "for device %04x:%04x\n",
2452                                q->value, q->subvendor, q->subdevice);
2453                         chip->codec_probe_mask = q->value;
2454                 }
2455         }
2456
2457         /* check forced option */
2458         if (chip->codec_probe_mask != -1 &&
2459             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2460                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2461                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2462                        chip->codec_mask);
2463         }
2464 }
2465
2466 /*
2467  * white/black-list for enable_msi
2468  */
2469 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2470         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2471         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2472         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2473         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2474         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2475         {}
2476 };
2477
2478 static void __devinit check_msi(struct azx *chip)
2479 {
2480         const struct snd_pci_quirk *q;
2481
2482         if (enable_msi >= 0) {
2483                 chip->msi = !!enable_msi;
2484                 return;
2485         }
2486         chip->msi = 1;  /* enable MSI as default */
2487         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2488         if (q) {
2489                 printk(KERN_INFO
2490                        "hda_intel: msi for device %04x:%04x set to %d\n",
2491                        q->subvendor, q->subdevice, q->value);
2492                 chip->msi = q->value;
2493                 return;
2494         }
2495
2496         /* NVidia chipsets seem to cause troubles with MSI */
2497         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2498                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2499                 chip->msi = 0;
2500         }
2501 }
2502
2503
2504 /*
2505  * constructor
2506  */
2507 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2508                                 int dev, unsigned int driver_caps,
2509                                 struct azx **rchip)
2510 {
2511         struct azx *chip;
2512         int i, err;
2513         unsigned short gcap;
2514         static struct snd_device_ops ops = {
2515                 .dev_free = azx_dev_free,
2516         };
2517
2518         *rchip = NULL;
2519
2520         err = pci_enable_device(pci);
2521         if (err < 0)
2522                 return err;
2523
2524         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2525         if (!chip) {
2526                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2527                 pci_disable_device(pci);
2528                 return -ENOMEM;
2529         }
2530
2531         spin_lock_init(&chip->reg_lock);
2532         mutex_init(&chip->open_mutex);
2533         chip->card = card;
2534         chip->pci = pci;
2535         chip->irq = -1;
2536         chip->driver_caps = driver_caps;
2537         chip->driver_type = driver_caps & 0xff;
2538         check_msi(chip);
2539         chip->dev_index = dev;
2540         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2541
2542         chip->position_fix[0] = chip->position_fix[1] =
2543                 check_position_fix(chip, position_fix[dev]);
2544         check_probe_mask(chip, dev);
2545
2546         chip->single_cmd = single_cmd;
2547
2548         if (bdl_pos_adj[dev] < 0) {
2549                 switch (chip->driver_type) {
2550                 case AZX_DRIVER_ICH:
2551                 case AZX_DRIVER_PCH:
2552                         bdl_pos_adj[dev] = 1;
2553                         break;
2554                 default:
2555                         bdl_pos_adj[dev] = 32;
2556                         break;
2557                 }
2558         }
2559
2560 #if BITS_PER_LONG != 64
2561         /* Fix up base address on ULI M5461 */
2562         if (chip->driver_type == AZX_DRIVER_ULI) {
2563                 u16 tmp3;
2564                 pci_read_config_word(pci, 0x40, &tmp3);
2565                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2566                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2567         }
2568 #endif
2569
2570         err = pci_request_regions(pci, "ICH HD audio");
2571         if (err < 0) {
2572                 kfree(chip);
2573                 pci_disable_device(pci);
2574                 return err;
2575         }
2576
2577         chip->addr = pci_resource_start(pci, 0);
2578         chip->remap_addr = pci_ioremap_bar(pci, 0);
2579         if (chip->remap_addr == NULL) {
2580                 snd_printk(KERN_ERR SFX "ioremap error\n");
2581                 err = -ENXIO;
2582                 goto errout;
2583         }
2584
2585         if (chip->msi)
2586                 if (pci_enable_msi(pci) < 0)
2587                         chip->msi = 0;
2588
2589         if (azx_acquire_irq(chip, 0) < 0) {
2590                 err = -EBUSY;
2591                 goto errout;
2592         }
2593
2594         pci_set_master(pci);
2595         synchronize_irq(chip->irq);
2596
2597         gcap = azx_readw(chip, GCAP);
2598         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2599
2600         /* disable SB600 64bit support for safety */
2601         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2602                 struct pci_dev *p_smbus;
2603                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2604                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2605                                          NULL);
2606                 if (p_smbus) {
2607                         if (p_smbus->revision < 0x30)
2608                                 gcap &= ~ICH6_GCAP_64OK;
2609                         pci_dev_put(p_smbus);
2610                 }
2611         }
2612
2613         /* disable 64bit DMA address on some devices */
2614         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2615                 snd_printd(SFX "Disabling 64bit DMA\n");
2616                 gcap &= ~ICH6_GCAP_64OK;
2617         }
2618
2619         /* allow 64bit DMA address if supported by H/W */
2620         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2621                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2622         else {
2623                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2624                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2625         }
2626
2627         /* read number of streams from GCAP register instead of using
2628          * hardcoded value
2629          */
2630         chip->capture_streams = (gcap >> 8) & 0x0f;
2631         chip->playback_streams = (gcap >> 12) & 0x0f;
2632         if (!chip->playback_streams && !chip->capture_streams) {
2633                 /* gcap didn't give any info, switching to old method */
2634
2635                 switch (chip->driver_type) {
2636                 case AZX_DRIVER_ULI:
2637                         chip->playback_streams = ULI_NUM_PLAYBACK;
2638                         chip->capture_streams = ULI_NUM_CAPTURE;
2639                         break;
2640                 case AZX_DRIVER_ATIHDMI:
2641                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2642                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2643                         break;
2644                 case AZX_DRIVER_GENERIC:
2645                 default:
2646                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2647                         chip->capture_streams = ICH6_NUM_CAPTURE;
2648                         break;
2649                 }
2650         }
2651         chip->capture_index_offset = 0;
2652         chip->playback_index_offset = chip->capture_streams;
2653         chip->num_streams = chip->playback_streams + chip->capture_streams;
2654         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2655                                 GFP_KERNEL);
2656         if (!chip->azx_dev) {
2657                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2658                 goto errout;
2659         }
2660
2661         for (i = 0; i < chip->num_streams; i++) {
2662                 /* allocate memory for the BDL for each stream */
2663                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2664                                           snd_dma_pci_data(chip->pci),
2665                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2666                 if (err < 0) {
2667                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2668                         goto errout;
2669                 }
2670         }
2671         /* allocate memory for the position buffer */
2672         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2673                                   snd_dma_pci_data(chip->pci),
2674                                   chip->num_streams * 8, &chip->posbuf);
2675         if (err < 0) {
2676                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2677                 goto errout;
2678         }
2679         /* allocate CORB/RIRB */
2680         err = azx_alloc_cmd_io(chip);
2681         if (err < 0)
2682                 goto errout;
2683
2684         /* initialize streams */
2685         azx_init_stream(chip);
2686
2687         /* initialize chip */
2688         azx_init_pci(chip);
2689         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2690
2691         /* codec detection */
2692         if (!chip->codec_mask) {
2693                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2694                 err = -ENODEV;
2695                 goto errout;
2696         }
2697
2698         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2699         if (err <0) {
2700                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2701                 goto errout;
2702         }
2703
2704         strcpy(card->driver, "HDA-Intel");
2705         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2706                 sizeof(card->shortname));
2707         snprintf(card->longname, sizeof(card->longname),
2708                  "%s at 0x%lx irq %i",
2709                  card->shortname, chip->addr, chip->irq);
2710
2711         *rchip = chip;
2712         return 0;
2713
2714  errout:
2715         azx_free(chip);
2716         return err;
2717 }
2718
2719 static void power_down_all_codecs(struct azx *chip)
2720 {
2721 #ifdef CONFIG_SND_HDA_POWER_SAVE
2722         /* The codecs were powered up in snd_hda_codec_new().
2723          * Now all initialization done, so turn them down if possible
2724          */
2725         struct hda_codec *codec;
2726         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2727                 snd_hda_power_down(codec);
2728         }
2729 #endif
2730 }
2731
2732 static int __devinit azx_probe(struct pci_dev *pci,
2733                                const struct pci_device_id *pci_id)
2734 {
2735         static int dev;
2736         struct snd_card *card;
2737         struct azx *chip;
2738         int err;
2739
2740         if (dev >= SNDRV_CARDS)
2741                 return -ENODEV;
2742         if (!enable[dev]) {
2743                 dev++;
2744                 return -ENOENT;
2745         }
2746
2747         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2748         if (err < 0) {
2749                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2750                 return err;
2751         }
2752
2753         /* set this here since it's referred in snd_hda_load_patch() */
2754         snd_card_set_dev(card, &pci->dev);
2755
2756         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2757         if (err < 0)
2758                 goto out_free;
2759         card->private_data = chip;
2760
2761 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2762         chip->beep_mode = beep_mode[dev];
2763 #endif
2764
2765         /* create codec instances */
2766         err = azx_codec_create(chip, model[dev]);
2767         if (err < 0)
2768                 goto out_free;
2769 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2770         if (patch[dev] && *patch[dev]) {
2771                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2772                            patch[dev]);
2773                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2774                 if (err < 0)
2775                         goto out_free;
2776         }
2777 #endif
2778         if ((probe_only[dev] & 1) == 0) {
2779                 err = azx_codec_configure(chip);
2780                 if (err < 0)
2781                         goto out_free;
2782         }
2783
2784         /* create PCM streams */
2785         err = snd_hda_build_pcms(chip->bus);
2786         if (err < 0)
2787                 goto out_free;
2788
2789         /* create mixer controls */
2790         err = azx_mixer_create(chip);
2791         if (err < 0)
2792                 goto out_free;
2793
2794         err = snd_card_register(card);
2795         if (err < 0)
2796                 goto out_free;
2797
2798         pci_set_drvdata(pci, card);
2799         chip->running = 1;
2800         power_down_all_codecs(chip);
2801         azx_notifier_register(chip);
2802
2803         dev++;
2804         return err;
2805 out_free:
2806         snd_card_free(card);
2807         return err;
2808 }
2809
2810 static void __devexit azx_remove(struct pci_dev *pci)
2811 {
2812         snd_card_free(pci_get_drvdata(pci));
2813         pci_set_drvdata(pci, NULL);
2814 }
2815
2816 /* PCI IDs */
2817 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2818         /* CPT */
2819         { PCI_DEVICE(0x8086, 0x1c20),
2820           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2821         /* PBG */
2822         { PCI_DEVICE(0x8086, 0x1d20),
2823           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2824         /* Panther Point */
2825         { PCI_DEVICE(0x8086, 0x1e20),
2826           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2827         /* SCH */
2828         { PCI_DEVICE(0x8086, 0x811b),
2829           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
2830         { PCI_DEVICE(0x8086, 0x2668),
2831           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH6 */
2832         { PCI_DEVICE(0x8086, 0x27d8),
2833           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH7 */
2834         { PCI_DEVICE(0x8086, 0x269a),
2835           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ESB2 */
2836         { PCI_DEVICE(0x8086, 0x284b),
2837           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH8 */
2838         { PCI_DEVICE(0x8086, 0x293e),
2839           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH9 */
2840         { PCI_DEVICE(0x8086, 0x293f),
2841           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH9 */
2842         { PCI_DEVICE(0x8086, 0x3a3e),
2843           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH10 */
2844         { PCI_DEVICE(0x8086, 0x3a6e),
2845           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH10 */
2846         /* Generic Intel */
2847         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2848           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2849           .class_mask = 0xffffff,
2850           .driver_data = AZX_DRIVER_ICH },
2851         /* ATI SB 450/600/700/800/900 */
2852         { PCI_DEVICE(0x1002, 0x437b),
2853           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2854         { PCI_DEVICE(0x1002, 0x4383),
2855           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2856         /* AMD Hudson */
2857         { PCI_DEVICE(0x1022, 0x780d),
2858           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2859         /* ATI HDMI */
2860         { PCI_DEVICE(0x1002, 0x793b),
2861           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2862         { PCI_DEVICE(0x1002, 0x7919),
2863           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2864         { PCI_DEVICE(0x1002, 0x960f),
2865           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2866         { PCI_DEVICE(0x1002, 0x970f),
2867           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2868         { PCI_DEVICE(0x1002, 0xaa00),
2869           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2870         { PCI_DEVICE(0x1002, 0xaa08),
2871           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2872         { PCI_DEVICE(0x1002, 0xaa10),
2873           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2874         { PCI_DEVICE(0x1002, 0xaa18),
2875           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2876         { PCI_DEVICE(0x1002, 0xaa20),
2877           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2878         { PCI_DEVICE(0x1002, 0xaa28),
2879           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2880         { PCI_DEVICE(0x1002, 0xaa30),
2881           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2882         { PCI_DEVICE(0x1002, 0xaa38),
2883           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2884         { PCI_DEVICE(0x1002, 0xaa40),
2885           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2886         { PCI_DEVICE(0x1002, 0xaa48),
2887           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2888         /* VIA VT8251/VT8237A */
2889         { PCI_DEVICE(0x1106, 0x3288),
2890           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2891         /* SIS966 */
2892         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2893         /* ULI M5461 */
2894         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2895         /* NVIDIA MCP */
2896         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2897           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2898           .class_mask = 0xffffff,
2899           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2900         /* Teradici */
2901         { PCI_DEVICE(0x6549, 0x1200),
2902           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2903         /* Creative X-Fi (CA0110-IBG) */
2904 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2905         /* the following entry conflicts with snd-ctxfi driver,
2906          * as ctxfi driver mutates from HD-audio to native mode with
2907          * a special command sequence.
2908          */
2909         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2910           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2911           .class_mask = 0xffffff,
2912           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2913           AZX_DCAPS_RIRB_PRE_DELAY },
2914 #else
2915         /* this entry seems still valid -- i.e. without emu20kx chip */
2916         { PCI_DEVICE(0x1102, 0x0009),
2917           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2918           AZX_DCAPS_RIRB_PRE_DELAY },
2919 #endif
2920         /* Vortex86MX */
2921         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2922         /* VMware HDAudio */
2923         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2924         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2925         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2926           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2927           .class_mask = 0xffffff,
2928           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2929         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2930           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2931           .class_mask = 0xffffff,
2932           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2933         { 0, }
2934 };
2935 MODULE_DEVICE_TABLE(pci, azx_ids);
2936
2937 /* pci_driver definition */
2938 static struct pci_driver driver = {
2939         .name = KBUILD_MODNAME,
2940         .id_table = azx_ids,
2941         .probe = azx_probe,
2942         .remove = __devexit_p(azx_remove),
2943 #ifdef CONFIG_PM
2944         .suspend = azx_suspend,
2945         .resume = azx_resume,
2946 #endif
2947 };
2948
2949 static int __init alsa_card_azx_init(void)
2950 {
2951         return pci_register_driver(&driver);
2952 }
2953
2954 static void __exit alsa_card_azx_exit(void)
2955 {
2956         pci_unregister_driver(&driver);
2957 }
2958
2959 module_init(alsa_card_azx_init)
2960 module_exit(alsa_card_azx_exit)