ALSA: hda: warn on spurious response
[pandora-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75                  "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84                  "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
87
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92                  "(in second, 0 = disable).");
93
94 /* reset the HD-audio controller in power save mode.
95  * this may give more power-saving, but will take longer time to
96  * wake up.
97  */
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101 #endif
102
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105                          "{Intel, ICH6M},"
106                          "{Intel, ICH7},"
107                          "{Intel, ESB2},"
108                          "{Intel, ICH8},"
109                          "{Intel, ICH9},"
110                          "{Intel, ICH10},"
111                          "{Intel, PCH},"
112                          "{Intel, SCH},"
113                          "{ATI, SB450},"
114                          "{ATI, SB600},"
115                          "{ATI, RS600},"
116                          "{ATI, RS690},"
117                          "{ATI, RS780},"
118                          "{ATI, R600},"
119                          "{ATI, RV630},"
120                          "{ATI, RV610},"
121                          "{ATI, RV670},"
122                          "{ATI, RV635},"
123                          "{ATI, RV620},"
124                          "{ATI, RV770},"
125                          "{VIA, VT8251},"
126                          "{VIA, VT8237A},"
127                          "{SiS, SIS966},"
128                          "{ULI, M5461}}");
129 MODULE_DESCRIPTION("Intel HDA driver");
130
131 #ifdef CONFIG_SND_VERBOSE_PRINTK
132 #define SFX     /* nop */
133 #else
134 #define SFX     "hda-intel: "
135 #endif
136
137 /*
138  * registers
139  */
140 #define ICH6_REG_GCAP                   0x00
141 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
142 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
143 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
144 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
145 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
146 #define ICH6_REG_VMIN                   0x02
147 #define ICH6_REG_VMAJ                   0x03
148 #define ICH6_REG_OUTPAY                 0x04
149 #define ICH6_REG_INPAY                  0x06
150 #define ICH6_REG_GCTL                   0x08
151 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
152 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
153 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
154 #define ICH6_REG_WAKEEN                 0x0c
155 #define ICH6_REG_STATESTS               0x0e
156 #define ICH6_REG_GSTS                   0x10
157 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
158 #define ICH6_REG_INTCTL                 0x20
159 #define ICH6_REG_INTSTS                 0x24
160 #define ICH6_REG_WALCLK                 0x30
161 #define ICH6_REG_SYNC                   0x34    
162 #define ICH6_REG_CORBLBASE              0x40
163 #define ICH6_REG_CORBUBASE              0x44
164 #define ICH6_REG_CORBWP                 0x48
165 #define ICH6_REG_CORBRP                 0x4a
166 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
167 #define ICH6_REG_CORBCTL                0x4c
168 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
169 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
170 #define ICH6_REG_CORBSTS                0x4d
171 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
172 #define ICH6_REG_CORBSIZE               0x4e
173
174 #define ICH6_REG_RIRBLBASE              0x50
175 #define ICH6_REG_RIRBUBASE              0x54
176 #define ICH6_REG_RIRBWP                 0x58
177 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
178 #define ICH6_REG_RINTCNT                0x5a
179 #define ICH6_REG_RIRBCTL                0x5c
180 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
181 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
182 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
183 #define ICH6_REG_RIRBSTS                0x5d
184 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
185 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
186 #define ICH6_REG_RIRBSIZE               0x5e
187
188 #define ICH6_REG_IC                     0x60
189 #define ICH6_REG_IR                     0x64
190 #define ICH6_REG_IRS                    0x68
191 #define   ICH6_IRS_VALID        (1<<1)
192 #define   ICH6_IRS_BUSY         (1<<0)
193
194 #define ICH6_REG_DPLBASE                0x70
195 #define ICH6_REG_DPUBASE                0x74
196 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
197
198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
200
201 /* stream register offsets from stream base */
202 #define ICH6_REG_SD_CTL                 0x00
203 #define ICH6_REG_SD_STS                 0x03
204 #define ICH6_REG_SD_LPIB                0x04
205 #define ICH6_REG_SD_CBL                 0x08
206 #define ICH6_REG_SD_LVI                 0x0c
207 #define ICH6_REG_SD_FIFOW               0x0e
208 #define ICH6_REG_SD_FIFOSIZE            0x10
209 #define ICH6_REG_SD_FORMAT              0x12
210 #define ICH6_REG_SD_BDLPL               0x18
211 #define ICH6_REG_SD_BDLPU               0x1c
212
213 /* PCI space */
214 #define ICH6_PCIREG_TCSEL       0x44
215
216 /*
217  * other constants
218  */
219
220 /* max number of SDs */
221 /* ICH, ATI and VIA have 4 playback and 4 capture */
222 #define ICH6_NUM_CAPTURE        4
223 #define ICH6_NUM_PLAYBACK       4
224
225 /* ULI has 6 playback and 5 capture */
226 #define ULI_NUM_CAPTURE         5
227 #define ULI_NUM_PLAYBACK        6
228
229 /* ATI HDMI has 1 playback and 0 capture */
230 #define ATIHDMI_NUM_CAPTURE     0
231 #define ATIHDMI_NUM_PLAYBACK    1
232
233 /* TERA has 4 playback and 3 capture */
234 #define TERA_NUM_CAPTURE        3
235 #define TERA_NUM_PLAYBACK       4
236
237 /* this number is statically defined for simplicity */
238 #define MAX_AZX_DEV             16
239
240 /* max number of fragments - we may use more if allocating more pages for BDL */
241 #define BDL_SIZE                4096
242 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
243 #define AZX_MAX_FRAG            32
244 /* max buffer size - no h/w limit, you can increase as you like */
245 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
246 /* max number of PCM devics per card */
247 #define AZX_MAX_PCMS            8
248
249 /* RIRB int mask: overrun[2], response[0] */
250 #define RIRB_INT_RESPONSE       0x01
251 #define RIRB_INT_OVERRUN        0x04
252 #define RIRB_INT_MASK           0x05
253
254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
255 #define AZX_MAX_CODECS          4
256 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
257
258 /* SD_CTL bits */
259 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
260 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
261 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
262 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
263 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
264 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
265 #define SD_CTL_STREAM_TAG_SHIFT 20
266
267 /* SD_CTL and SD_STS */
268 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
269 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
270 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
271 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
272                                  SD_INT_COMPLETE)
273
274 /* SD_STS */
275 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
276
277 /* INTCTL and INTSTS */
278 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
279 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
280 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
281
282 /* below are so far hardcoded - should read registers in future */
283 #define ICH6_MAX_CORB_ENTRIES   256
284 #define ICH6_MAX_RIRB_ENTRIES   256
285
286 /* position fix mode */
287 enum {
288         POS_FIX_AUTO,
289         POS_FIX_LPIB,
290         POS_FIX_POSBUF,
291 };
292
293 /* Defines for ATI HD Audio support in SB450 south bridge */
294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
296
297 /* Defines for Nvidia HDA support */
298 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
299 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
300 #define NVIDIA_HDA_ISTRM_COH          0x4d
301 #define NVIDIA_HDA_OSTRM_COH          0x4c
302 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
303
304 /* Defines for Intel SCH HDA snoop control */
305 #define INTEL_SCH_HDA_DEVC      0x78
306 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
307
308 /* Define IN stream 0 FIFO size offset in VIA controller */
309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
310 /* Define VIA HD Audio Device ID*/
311 #define VIA_HDAC_DEVICE_ID              0x3288
312
313 /* HD Audio class code */
314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
315
316 /*
317  */
318
319 struct azx_dev {
320         struct snd_dma_buffer bdl; /* BDL buffer */
321         u32 *posbuf;            /* position buffer pointer */
322
323         unsigned int bufsize;   /* size of the play buffer in bytes */
324         unsigned int period_bytes; /* size of the period in bytes */
325         unsigned int frags;     /* number for period in the play buffer */
326         unsigned int fifo_size; /* FIFO size */
327         unsigned long start_jiffies;    /* start + minimum jiffies */
328         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
329
330         void __iomem *sd_addr;  /* stream descriptor pointer */
331
332         u32 sd_int_sta_mask;    /* stream int status mask */
333
334         /* pcm support */
335         struct snd_pcm_substream *substream;    /* assigned substream,
336                                                  * set in PCM open
337                                                  */
338         unsigned int format_val;        /* format value to be set in the
339                                          * controller and the codec
340                                          */
341         unsigned char stream_tag;       /* assigned stream */
342         unsigned char index;            /* stream index */
343
344         unsigned int opened :1;
345         unsigned int running :1;
346         unsigned int irq_pending :1;
347         unsigned int start_flag: 1;     /* stream full start flag */
348         /*
349          * For VIA:
350          *  A flag to ensure DMA position is 0
351          *  when link position is not greater than FIFO size
352          */
353         unsigned int insufficient :1;
354 };
355
356 /* CORB/RIRB */
357 struct azx_rb {
358         u32 *buf;               /* CORB/RIRB buffer
359                                  * Each CORB entry is 4byte, RIRB is 8byte
360                                  */
361         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
362         /* for RIRB */
363         unsigned short rp, wp;  /* read/write pointers */
364         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
365         u32 res[AZX_MAX_CODECS];        /* last read value */
366 };
367
368 struct azx {
369         struct snd_card *card;
370         struct pci_dev *pci;
371         int dev_index;
372
373         /* chip type specific */
374         int driver_type;
375         int playback_streams;
376         int playback_index_offset;
377         int capture_streams;
378         int capture_index_offset;
379         int num_streams;
380
381         /* pci resources */
382         unsigned long addr;
383         void __iomem *remap_addr;
384         int irq;
385
386         /* locks */
387         spinlock_t reg_lock;
388         struct mutex open_mutex;
389
390         /* streams (x num_streams) */
391         struct azx_dev *azx_dev;
392
393         /* PCM */
394         struct snd_pcm *pcm[AZX_MAX_PCMS];
395
396         /* HD codec */
397         unsigned short codec_mask;
398         int  codec_probe_mask; /* copied from probe_mask option */
399         struct hda_bus *bus;
400
401         /* CORB/RIRB */
402         struct azx_rb corb;
403         struct azx_rb rirb;
404
405         /* CORB/RIRB and position buffers */
406         struct snd_dma_buffer rb;
407         struct snd_dma_buffer posbuf;
408
409         /* flags */
410         int position_fix;
411         unsigned int running :1;
412         unsigned int initialized :1;
413         unsigned int single_cmd :1;
414         unsigned int polling_mode :1;
415         unsigned int msi :1;
416         unsigned int irq_pending_warned :1;
417         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
418         unsigned int probing :1; /* codec probing phase */
419
420         /* for debugging */
421         unsigned int last_cmd[AZX_MAX_CODECS];
422
423         /* for pending irqs */
424         struct work_struct irq_pending_work;
425
426         /* reboot notifier (for mysterious hangup problem at power-down) */
427         struct notifier_block reboot_notifier;
428 };
429
430 /* driver types */
431 enum {
432         AZX_DRIVER_ICH,
433         AZX_DRIVER_SCH,
434         AZX_DRIVER_ATI,
435         AZX_DRIVER_ATIHDMI,
436         AZX_DRIVER_VIA,
437         AZX_DRIVER_SIS,
438         AZX_DRIVER_ULI,
439         AZX_DRIVER_NVIDIA,
440         AZX_DRIVER_TERA,
441         AZX_DRIVER_GENERIC,
442         AZX_NUM_DRIVERS, /* keep this as last entry */
443 };
444
445 static char *driver_short_names[] __devinitdata = {
446         [AZX_DRIVER_ICH] = "HDA Intel",
447         [AZX_DRIVER_SCH] = "HDA Intel MID",
448         [AZX_DRIVER_ATI] = "HDA ATI SB",
449         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
450         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
451         [AZX_DRIVER_SIS] = "HDA SIS966",
452         [AZX_DRIVER_ULI] = "HDA ULI M5461",
453         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
454         [AZX_DRIVER_TERA] = "HDA Teradici", 
455         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
456 };
457
458 /*
459  * macros for easy use
460  */
461 #define azx_writel(chip,reg,value) \
462         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
463 #define azx_readl(chip,reg) \
464         readl((chip)->remap_addr + ICH6_REG_##reg)
465 #define azx_writew(chip,reg,value) \
466         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
467 #define azx_readw(chip,reg) \
468         readw((chip)->remap_addr + ICH6_REG_##reg)
469 #define azx_writeb(chip,reg,value) \
470         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
471 #define azx_readb(chip,reg) \
472         readb((chip)->remap_addr + ICH6_REG_##reg)
473
474 #define azx_sd_writel(dev,reg,value) \
475         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
476 #define azx_sd_readl(dev,reg) \
477         readl((dev)->sd_addr + ICH6_REG_##reg)
478 #define azx_sd_writew(dev,reg,value) \
479         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
480 #define azx_sd_readw(dev,reg) \
481         readw((dev)->sd_addr + ICH6_REG_##reg)
482 #define azx_sd_writeb(dev,reg,value) \
483         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
484 #define azx_sd_readb(dev,reg) \
485         readb((dev)->sd_addr + ICH6_REG_##reg)
486
487 /* for pcm support */
488 #define get_azx_dev(substream) (substream->runtime->private_data)
489
490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
491
492 /*
493  * Interface for HD codec
494  */
495
496 /*
497  * CORB / RIRB interface
498  */
499 static int azx_alloc_cmd_io(struct azx *chip)
500 {
501         int err;
502
503         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
504         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
505                                   snd_dma_pci_data(chip->pci),
506                                   PAGE_SIZE, &chip->rb);
507         if (err < 0) {
508                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
509                 return err;
510         }
511         return 0;
512 }
513
514 static void azx_init_cmd_io(struct azx *chip)
515 {
516         spin_lock_irq(&chip->reg_lock);
517         /* CORB set up */
518         chip->corb.addr = chip->rb.addr;
519         chip->corb.buf = (u32 *)chip->rb.area;
520         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
521         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
522
523         /* set the corb size to 256 entries (ULI requires explicitly) */
524         azx_writeb(chip, CORBSIZE, 0x02);
525         /* set the corb write pointer to 0 */
526         azx_writew(chip, CORBWP, 0);
527         /* reset the corb hw read pointer */
528         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
529         /* enable corb dma */
530         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
531
532         /* RIRB set up */
533         chip->rirb.addr = chip->rb.addr + 2048;
534         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
535         chip->rirb.wp = chip->rirb.rp = 0;
536         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
537         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
538         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
539
540         /* set the rirb size to 256 entries (ULI requires explicitly) */
541         azx_writeb(chip, RIRBSIZE, 0x02);
542         /* reset the rirb hw write pointer */
543         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
544         /* set N=1, get RIRB response interrupt for new entry */
545         azx_writew(chip, RINTCNT, 1);
546         /* enable rirb dma and response irq */
547         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
548         spin_unlock_irq(&chip->reg_lock);
549 }
550
551 static void azx_free_cmd_io(struct azx *chip)
552 {
553         spin_lock_irq(&chip->reg_lock);
554         /* disable ringbuffer DMAs */
555         azx_writeb(chip, RIRBCTL, 0);
556         azx_writeb(chip, CORBCTL, 0);
557         spin_unlock_irq(&chip->reg_lock);
558 }
559
560 static unsigned int azx_command_addr(u32 cmd)
561 {
562         unsigned int addr = cmd >> 28;
563
564         if (addr >= AZX_MAX_CODECS) {
565                 snd_BUG();
566                 addr = 0;
567         }
568
569         return addr;
570 }
571
572 static unsigned int azx_response_addr(u32 res)
573 {
574         unsigned int addr = res & 0xf;
575
576         if (addr >= AZX_MAX_CODECS) {
577                 snd_BUG();
578                 addr = 0;
579         }
580
581         return addr;
582 }
583
584 /* send a command */
585 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
586 {
587         struct azx *chip = bus->private_data;
588         unsigned int addr = azx_command_addr(val);
589         unsigned int wp;
590
591         spin_lock_irq(&chip->reg_lock);
592
593         /* add command to corb */
594         wp = azx_readb(chip, CORBWP);
595         wp++;
596         wp %= ICH6_MAX_CORB_ENTRIES;
597
598         chip->rirb.cmds[addr]++;
599         chip->corb.buf[wp] = cpu_to_le32(val);
600         azx_writel(chip, CORBWP, wp);
601
602         spin_unlock_irq(&chip->reg_lock);
603
604         return 0;
605 }
606
607 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
608
609 /* retrieve RIRB entry - called from interrupt handler */
610 static void azx_update_rirb(struct azx *chip)
611 {
612         unsigned int rp, wp;
613         unsigned int addr;
614         u32 res, res_ex;
615
616         wp = azx_readb(chip, RIRBWP);
617         if (wp == chip->rirb.wp)
618                 return;
619         chip->rirb.wp = wp;
620
621         while (chip->rirb.rp != wp) {
622                 chip->rirb.rp++;
623                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
624
625                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
626                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
627                 res = le32_to_cpu(chip->rirb.buf[rp]);
628                 addr = azx_response_addr(res_ex);
629                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
630                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
631                 else if (chip->rirb.cmds[addr]) {
632                         chip->rirb.res[addr] = res;
633                         smp_wmb();
634                         chip->rirb.cmds[addr]--;
635                 } else
636                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
637                                    "last cmd=%#08x\n",
638                                    res, res_ex,
639                                    chip->last_cmd[addr]);
640         }
641 }
642
643 /* receive a response */
644 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
645                                           unsigned int addr)
646 {
647         struct azx *chip = bus->private_data;
648         unsigned long timeout;
649
650  again:
651         timeout = jiffies + msecs_to_jiffies(1000);
652         for (;;) {
653                 if (chip->polling_mode) {
654                         spin_lock_irq(&chip->reg_lock);
655                         azx_update_rirb(chip);
656                         spin_unlock_irq(&chip->reg_lock);
657                 }
658                 if (!chip->rirb.cmds[addr]) {
659                         smp_rmb();
660                         bus->rirb_error = 0;
661                         return chip->rirb.res[addr]; /* the last value */
662                 }
663                 if (time_after(jiffies, timeout))
664                         break;
665                 if (bus->needs_damn_long_delay)
666                         msleep(2); /* temporary workaround */
667                 else {
668                         udelay(10);
669                         cond_resched();
670                 }
671         }
672
673         if (chip->msi) {
674                 snd_printk(KERN_WARNING SFX "No response from codec, "
675                            "disabling MSI: last cmd=0x%08x\n",
676                            chip->last_cmd[addr]);
677                 free_irq(chip->irq, chip);
678                 chip->irq = -1;
679                 pci_disable_msi(chip->pci);
680                 chip->msi = 0;
681                 if (azx_acquire_irq(chip, 1) < 0) {
682                         bus->rirb_error = 1;
683                         return -1;
684                 }
685                 goto again;
686         }
687
688         if (!chip->polling_mode) {
689                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
690                            "switching to polling mode: last cmd=0x%08x\n",
691                            chip->last_cmd[addr]);
692                 chip->polling_mode = 1;
693                 goto again;
694         }
695
696         if (chip->probing) {
697                 /* If this critical timeout happens during the codec probing
698                  * phase, this is likely an access to a non-existing codec
699                  * slot.  Better to return an error and reset the system.
700                  */
701                 return -1;
702         }
703
704         /* a fatal communication error; need either to reset or to fallback
705          * to the single_cmd mode
706          */
707         bus->rirb_error = 1;
708         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
709                 bus->response_reset = 1;
710                 return -1; /* give a chance to retry */
711         }
712
713         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
714                    "switching to single_cmd mode: last cmd=0x%08x\n",
715                    chip->last_cmd[addr]);
716         chip->single_cmd = 1;
717         bus->response_reset = 0;
718         /* re-initialize CORB/RIRB */
719         azx_free_cmd_io(chip);
720         azx_init_cmd_io(chip);
721         return -1;
722 }
723
724 /*
725  * Use the single immediate command instead of CORB/RIRB for simplicity
726  *
727  * Note: according to Intel, this is not preferred use.  The command was
728  *       intended for the BIOS only, and may get confused with unsolicited
729  *       responses.  So, we shouldn't use it for normal operation from the
730  *       driver.
731  *       I left the codes, however, for debugging/testing purposes.
732  */
733
734 /* receive a response */
735 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
736 {
737         int timeout = 50;
738
739         while (timeout--) {
740                 /* check IRV busy bit */
741                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
742                         /* reuse rirb.res as the response return value */
743                         chip->rirb.res[addr] = azx_readl(chip, IR);
744                         return 0;
745                 }
746                 udelay(1);
747         }
748         if (printk_ratelimit())
749                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
750                            azx_readw(chip, IRS));
751         chip->rirb.res[addr] = -1;
752         return -EIO;
753 }
754
755 /* send a command */
756 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
757 {
758         struct azx *chip = bus->private_data;
759         unsigned int addr = azx_command_addr(val);
760         int timeout = 50;
761
762         bus->rirb_error = 0;
763         while (timeout--) {
764                 /* check ICB busy bit */
765                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
766                         /* Clear IRV valid bit */
767                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
768                                    ICH6_IRS_VALID);
769                         azx_writel(chip, IC, val);
770                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
771                                    ICH6_IRS_BUSY);
772                         return azx_single_wait_for_response(chip, addr);
773                 }
774                 udelay(1);
775         }
776         if (printk_ratelimit())
777                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
778                            azx_readw(chip, IRS), val);
779         return -EIO;
780 }
781
782 /* receive a response */
783 static unsigned int azx_single_get_response(struct hda_bus *bus,
784                                             unsigned int addr)
785 {
786         struct azx *chip = bus->private_data;
787         return chip->rirb.res[addr];
788 }
789
790 /*
791  * The below are the main callbacks from hda_codec.
792  *
793  * They are just the skeleton to call sub-callbacks according to the
794  * current setting of chip->single_cmd.
795  */
796
797 /* send a command */
798 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
799 {
800         struct azx *chip = bus->private_data;
801
802         chip->last_cmd[azx_command_addr(val)] = val;
803         if (chip->single_cmd)
804                 return azx_single_send_cmd(bus, val);
805         else
806                 return azx_corb_send_cmd(bus, val);
807 }
808
809 /* get a response */
810 static unsigned int azx_get_response(struct hda_bus *bus,
811                                      unsigned int addr)
812 {
813         struct azx *chip = bus->private_data;
814         if (chip->single_cmd)
815                 return azx_single_get_response(bus, addr);
816         else
817                 return azx_rirb_get_response(bus, addr);
818 }
819
820 #ifdef CONFIG_SND_HDA_POWER_SAVE
821 static void azx_power_notify(struct hda_bus *bus);
822 #endif
823
824 /* reset codec link */
825 static int azx_reset(struct azx *chip)
826 {
827         int count;
828
829         /* clear STATESTS */
830         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
831
832         /* reset controller */
833         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
834
835         count = 50;
836         while (azx_readb(chip, GCTL) && --count)
837                 msleep(1);
838
839         /* delay for >= 100us for codec PLL to settle per spec
840          * Rev 0.9 section 5.5.1
841          */
842         msleep(1);
843
844         /* Bring controller out of reset */
845         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
846
847         count = 50;
848         while (!azx_readb(chip, GCTL) && --count)
849                 msleep(1);
850
851         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
852         msleep(1);
853
854         /* check to see if controller is ready */
855         if (!azx_readb(chip, GCTL)) {
856                 snd_printd(SFX "azx_reset: controller not ready!\n");
857                 return -EBUSY;
858         }
859
860         /* Accept unsolicited responses */
861         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
862
863         /* detect codecs */
864         if (!chip->codec_mask) {
865                 chip->codec_mask = azx_readw(chip, STATESTS);
866                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
867         }
868
869         return 0;
870 }
871
872
873 /*
874  * Lowlevel interface
875  */  
876
877 /* enable interrupts */
878 static void azx_int_enable(struct azx *chip)
879 {
880         /* enable controller CIE and GIE */
881         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
882                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
883 }
884
885 /* disable interrupts */
886 static void azx_int_disable(struct azx *chip)
887 {
888         int i;
889
890         /* disable interrupts in stream descriptor */
891         for (i = 0; i < chip->num_streams; i++) {
892                 struct azx_dev *azx_dev = &chip->azx_dev[i];
893                 azx_sd_writeb(azx_dev, SD_CTL,
894                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
895         }
896
897         /* disable SIE for all streams */
898         azx_writeb(chip, INTCTL, 0);
899
900         /* disable controller CIE and GIE */
901         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
902                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
903 }
904
905 /* clear interrupts */
906 static void azx_int_clear(struct azx *chip)
907 {
908         int i;
909
910         /* clear stream status */
911         for (i = 0; i < chip->num_streams; i++) {
912                 struct azx_dev *azx_dev = &chip->azx_dev[i];
913                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
914         }
915
916         /* clear STATESTS */
917         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
918
919         /* clear rirb status */
920         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
921
922         /* clear int status */
923         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
924 }
925
926 /* start a stream */
927 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
928 {
929         /*
930          * Before stream start, initialize parameter
931          */
932         azx_dev->insufficient = 1;
933
934         /* enable SIE */
935         azx_writeb(chip, INTCTL,
936                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
937         /* set DMA start and interrupt mask */
938         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
939                       SD_CTL_DMA_START | SD_INT_MASK);
940 }
941
942 /* stop DMA */
943 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
944 {
945         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
946                       ~(SD_CTL_DMA_START | SD_INT_MASK));
947         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
948 }
949
950 /* stop a stream */
951 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
952 {
953         azx_stream_clear(chip, azx_dev);
954         /* disable SIE */
955         azx_writeb(chip, INTCTL,
956                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
957 }
958
959
960 /*
961  * reset and start the controller registers
962  */
963 static void azx_init_chip(struct azx *chip)
964 {
965         if (chip->initialized)
966                 return;
967
968         /* reset controller */
969         azx_reset(chip);
970
971         /* initialize interrupts */
972         azx_int_clear(chip);
973         azx_int_enable(chip);
974
975         /* initialize the codec command I/O */
976         azx_init_cmd_io(chip);
977
978         /* program the position buffer */
979         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
980         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
981
982         chip->initialized = 1;
983 }
984
985 /*
986  * initialize the PCI registers
987  */
988 /* update bits in a PCI register byte */
989 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
990                             unsigned char mask, unsigned char val)
991 {
992         unsigned char data;
993
994         pci_read_config_byte(pci, reg, &data);
995         data &= ~mask;
996         data |= (val & mask);
997         pci_write_config_byte(pci, reg, data);
998 }
999
1000 static void azx_init_pci(struct azx *chip)
1001 {
1002         unsigned short snoop;
1003
1004         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1005          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1006          * Ensuring these bits are 0 clears playback static on some HD Audio
1007          * codecs
1008          */
1009         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1010
1011         switch (chip->driver_type) {
1012         case AZX_DRIVER_ATI:
1013                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1014                 update_pci_byte(chip->pci,
1015                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1016                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1017                 break;
1018         case AZX_DRIVER_NVIDIA:
1019                 /* For NVIDIA HDA, enable snoop */
1020                 update_pci_byte(chip->pci,
1021                                 NVIDIA_HDA_TRANSREG_ADDR,
1022                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1023                 update_pci_byte(chip->pci,
1024                                 NVIDIA_HDA_ISTRM_COH,
1025                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1026                 update_pci_byte(chip->pci,
1027                                 NVIDIA_HDA_OSTRM_COH,
1028                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1029                 break;
1030         case AZX_DRIVER_SCH:
1031                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1032                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1033                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1034                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1035                         pci_read_config_word(chip->pci,
1036                                 INTEL_SCH_HDA_DEVC, &snoop);
1037                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1038                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1039                                 ? "Failed" : "OK");
1040                 }
1041                 break;
1042
1043         }
1044 }
1045
1046
1047 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1048
1049 /*
1050  * interrupt handler
1051  */
1052 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1053 {
1054         struct azx *chip = dev_id;
1055         struct azx_dev *azx_dev;
1056         u32 status;
1057         int i, ok;
1058
1059         spin_lock(&chip->reg_lock);
1060
1061         status = azx_readl(chip, INTSTS);
1062         if (status == 0) {
1063                 spin_unlock(&chip->reg_lock);
1064                 return IRQ_NONE;
1065         }
1066         
1067         for (i = 0; i < chip->num_streams; i++) {
1068                 azx_dev = &chip->azx_dev[i];
1069                 if (status & azx_dev->sd_int_sta_mask) {
1070                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1071                         if (!azx_dev->substream || !azx_dev->running)
1072                                 continue;
1073                         /* check whether this IRQ is really acceptable */
1074                         ok = azx_position_ok(chip, azx_dev);
1075                         if (ok == 1) {
1076                                 azx_dev->irq_pending = 0;
1077                                 spin_unlock(&chip->reg_lock);
1078                                 snd_pcm_period_elapsed(azx_dev->substream);
1079                                 spin_lock(&chip->reg_lock);
1080                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1081                                 /* bogus IRQ, process it later */
1082                                 azx_dev->irq_pending = 1;
1083                                 queue_work(chip->bus->workq,
1084                                            &chip->irq_pending_work);
1085                         }
1086                 }
1087         }
1088
1089         /* clear rirb int */
1090         status = azx_readb(chip, RIRBSTS);
1091         if (status & RIRB_INT_MASK) {
1092                 if (status & RIRB_INT_RESPONSE)
1093                         azx_update_rirb(chip);
1094                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1095         }
1096
1097 #if 0
1098         /* clear state status int */
1099         if (azx_readb(chip, STATESTS) & 0x04)
1100                 azx_writeb(chip, STATESTS, 0x04);
1101 #endif
1102         spin_unlock(&chip->reg_lock);
1103         
1104         return IRQ_HANDLED;
1105 }
1106
1107
1108 /*
1109  * set up a BDL entry
1110  */
1111 static int setup_bdle(struct snd_pcm_substream *substream,
1112                       struct azx_dev *azx_dev, u32 **bdlp,
1113                       int ofs, int size, int with_ioc)
1114 {
1115         u32 *bdl = *bdlp;
1116
1117         while (size > 0) {
1118                 dma_addr_t addr;
1119                 int chunk;
1120
1121                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1122                         return -EINVAL;
1123
1124                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1125                 /* program the address field of the BDL entry */
1126                 bdl[0] = cpu_to_le32((u32)addr);
1127                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1128                 /* program the size field of the BDL entry */
1129                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1130                 bdl[2] = cpu_to_le32(chunk);
1131                 /* program the IOC to enable interrupt
1132                  * only when the whole fragment is processed
1133                  */
1134                 size -= chunk;
1135                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1136                 bdl += 4;
1137                 azx_dev->frags++;
1138                 ofs += chunk;
1139         }
1140         *bdlp = bdl;
1141         return ofs;
1142 }
1143
1144 /*
1145  * set up BDL entries
1146  */
1147 static int azx_setup_periods(struct azx *chip,
1148                              struct snd_pcm_substream *substream,
1149                              struct azx_dev *azx_dev)
1150 {
1151         u32 *bdl;
1152         int i, ofs, periods, period_bytes;
1153         int pos_adj;
1154
1155         /* reset BDL address */
1156         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1157         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1158
1159         period_bytes = azx_dev->period_bytes;
1160         periods = azx_dev->bufsize / period_bytes;
1161
1162         /* program the initial BDL entries */
1163         bdl = (u32 *)azx_dev->bdl.area;
1164         ofs = 0;
1165         azx_dev->frags = 0;
1166         pos_adj = bdl_pos_adj[chip->dev_index];
1167         if (pos_adj > 0) {
1168                 struct snd_pcm_runtime *runtime = substream->runtime;
1169                 int pos_align = pos_adj;
1170                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1171                 if (!pos_adj)
1172                         pos_adj = pos_align;
1173                 else
1174                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1175                                 pos_align;
1176                 pos_adj = frames_to_bytes(runtime, pos_adj);
1177                 if (pos_adj >= period_bytes) {
1178                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1179                                    bdl_pos_adj[chip->dev_index]);
1180                         pos_adj = 0;
1181                 } else {
1182                         ofs = setup_bdle(substream, azx_dev,
1183                                          &bdl, ofs, pos_adj, 1);
1184                         if (ofs < 0)
1185                                 goto error;
1186                 }
1187         } else
1188                 pos_adj = 0;
1189         for (i = 0; i < periods; i++) {
1190                 if (i == periods - 1 && pos_adj)
1191                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1192                                          period_bytes - pos_adj, 0);
1193                 else
1194                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1195                                          period_bytes, 1);
1196                 if (ofs < 0)
1197                         goto error;
1198         }
1199         return 0;
1200
1201  error:
1202         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1203                    azx_dev->bufsize, period_bytes);
1204         return -EINVAL;
1205 }
1206
1207 /* reset stream */
1208 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1209 {
1210         unsigned char val;
1211         int timeout;
1212
1213         azx_stream_clear(chip, azx_dev);
1214
1215         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1216                       SD_CTL_STREAM_RESET);
1217         udelay(3);
1218         timeout = 300;
1219         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1220                --timeout)
1221                 ;
1222         val &= ~SD_CTL_STREAM_RESET;
1223         azx_sd_writeb(azx_dev, SD_CTL, val);
1224         udelay(3);
1225
1226         timeout = 300;
1227         /* waiting for hardware to report that the stream is out of reset */
1228         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1229                --timeout)
1230                 ;
1231
1232         /* reset first position - may not be synced with hw at this time */
1233         *azx_dev->posbuf = 0;
1234 }
1235
1236 /*
1237  * set up the SD for streaming
1238  */
1239 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1240 {
1241         /* make sure the run bit is zero for SD */
1242         azx_stream_clear(chip, azx_dev);
1243         /* program the stream_tag */
1244         azx_sd_writel(azx_dev, SD_CTL,
1245                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1246                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1247
1248         /* program the length of samples in cyclic buffer */
1249         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1250
1251         /* program the stream format */
1252         /* this value needs to be the same as the one programmed */
1253         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1254
1255         /* program the stream LVI (last valid index) of the BDL */
1256         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1257
1258         /* program the BDL address */
1259         /* lower BDL address */
1260         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1261         /* upper BDL address */
1262         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1263
1264         /* enable the position buffer */
1265         if (chip->position_fix == POS_FIX_POSBUF ||
1266             chip->position_fix == POS_FIX_AUTO ||
1267             chip->via_dmapos_patch) {
1268                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1269                         azx_writel(chip, DPLBASE,
1270                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1271         }
1272
1273         /* set the interrupt enable bits in the descriptor control register */
1274         azx_sd_writel(azx_dev, SD_CTL,
1275                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1276
1277         return 0;
1278 }
1279
1280 /*
1281  * Probe the given codec address
1282  */
1283 static int probe_codec(struct azx *chip, int addr)
1284 {
1285         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1286                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1287         unsigned int res;
1288
1289         mutex_lock(&chip->bus->cmd_mutex);
1290         chip->probing = 1;
1291         azx_send_cmd(chip->bus, cmd);
1292         res = azx_get_response(chip->bus, addr);
1293         chip->probing = 0;
1294         mutex_unlock(&chip->bus->cmd_mutex);
1295         if (res == -1)
1296                 return -EIO;
1297         snd_printdd(SFX "codec #%d probed OK\n", addr);
1298         return 0;
1299 }
1300
1301 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1302                                  struct hda_pcm *cpcm);
1303 static void azx_stop_chip(struct azx *chip);
1304
1305 static void azx_bus_reset(struct hda_bus *bus)
1306 {
1307         struct azx *chip = bus->private_data;
1308
1309         bus->in_reset = 1;
1310         azx_stop_chip(chip);
1311         azx_init_chip(chip);
1312 #ifdef CONFIG_PM
1313         if (chip->initialized) {
1314                 int i;
1315
1316                 for (i = 0; i < AZX_MAX_PCMS; i++)
1317                         snd_pcm_suspend_all(chip->pcm[i]);
1318                 snd_hda_suspend(chip->bus);
1319                 snd_hda_resume(chip->bus);
1320         }
1321 #endif
1322         bus->in_reset = 0;
1323 }
1324
1325 /*
1326  * Codec initialization
1327  */
1328
1329 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1330 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1331         [AZX_DRIVER_TERA] = 1,
1332 };
1333
1334 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1335                                       int no_init)
1336 {
1337         struct hda_bus_template bus_temp;
1338         int c, codecs, err;
1339         int max_slots;
1340
1341         memset(&bus_temp, 0, sizeof(bus_temp));
1342         bus_temp.private_data = chip;
1343         bus_temp.modelname = model;
1344         bus_temp.pci = chip->pci;
1345         bus_temp.ops.command = azx_send_cmd;
1346         bus_temp.ops.get_response = azx_get_response;
1347         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1348         bus_temp.ops.bus_reset = azx_bus_reset;
1349 #ifdef CONFIG_SND_HDA_POWER_SAVE
1350         bus_temp.power_save = &power_save;
1351         bus_temp.ops.pm_notify = azx_power_notify;
1352 #endif
1353
1354         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1355         if (err < 0)
1356                 return err;
1357
1358         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1359                 chip->bus->needs_damn_long_delay = 1;
1360
1361         codecs = 0;
1362         max_slots = azx_max_codecs[chip->driver_type];
1363         if (!max_slots)
1364                 max_slots = AZX_MAX_CODECS;
1365
1366         /* First try to probe all given codec slots */
1367         for (c = 0; c < max_slots; c++) {
1368                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1369                         if (probe_codec(chip, c) < 0) {
1370                                 /* Some BIOSen give you wrong codec addresses
1371                                  * that don't exist
1372                                  */
1373                                 snd_printk(KERN_WARNING SFX
1374                                            "Codec #%d probe error; "
1375                                            "disabling it...\n", c);
1376                                 chip->codec_mask &= ~(1 << c);
1377                                 /* More badly, accessing to a non-existing
1378                                  * codec often screws up the controller chip,
1379                                  * and distrubs the further communications.
1380                                  * Thus if an error occurs during probing,
1381                                  * better to reset the controller chip to
1382                                  * get back to the sanity state.
1383                                  */
1384                                 azx_stop_chip(chip);
1385                                 azx_init_chip(chip);
1386                         }
1387                 }
1388         }
1389
1390         /* Then create codec instances */
1391         for (c = 0; c < max_slots; c++) {
1392                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1393                         struct hda_codec *codec;
1394                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1395                         if (err < 0)
1396                                 continue;
1397                         codecs++;
1398                 }
1399         }
1400         if (!codecs) {
1401                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1402                 return -ENXIO;
1403         }
1404
1405         return 0;
1406 }
1407
1408
1409 /*
1410  * PCM support
1411  */
1412
1413 /* assign a stream for the PCM */
1414 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1415 {
1416         int dev, i, nums;
1417         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1418                 dev = chip->playback_index_offset;
1419                 nums = chip->playback_streams;
1420         } else {
1421                 dev = chip->capture_index_offset;
1422                 nums = chip->capture_streams;
1423         }
1424         for (i = 0; i < nums; i++, dev++)
1425                 if (!chip->azx_dev[dev].opened) {
1426                         chip->azx_dev[dev].opened = 1;
1427                         return &chip->azx_dev[dev];
1428                 }
1429         return NULL;
1430 }
1431
1432 /* release the assigned stream */
1433 static inline void azx_release_device(struct azx_dev *azx_dev)
1434 {
1435         azx_dev->opened = 0;
1436 }
1437
1438 static struct snd_pcm_hardware azx_pcm_hw = {
1439         .info =                 (SNDRV_PCM_INFO_MMAP |
1440                                  SNDRV_PCM_INFO_INTERLEAVED |
1441                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1442                                  SNDRV_PCM_INFO_MMAP_VALID |
1443                                  /* No full-resume yet implemented */
1444                                  /* SNDRV_PCM_INFO_RESUME |*/
1445                                  SNDRV_PCM_INFO_PAUSE |
1446                                  SNDRV_PCM_INFO_SYNC_START),
1447         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1448         .rates =                SNDRV_PCM_RATE_48000,
1449         .rate_min =             48000,
1450         .rate_max =             48000,
1451         .channels_min =         2,
1452         .channels_max =         2,
1453         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1454         .period_bytes_min =     128,
1455         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1456         .periods_min =          2,
1457         .periods_max =          AZX_MAX_FRAG,
1458         .fifo_size =            0,
1459 };
1460
1461 struct azx_pcm {
1462         struct azx *chip;
1463         struct hda_codec *codec;
1464         struct hda_pcm_stream *hinfo[2];
1465 };
1466
1467 static int azx_pcm_open(struct snd_pcm_substream *substream)
1468 {
1469         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1470         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1471         struct azx *chip = apcm->chip;
1472         struct azx_dev *azx_dev;
1473         struct snd_pcm_runtime *runtime = substream->runtime;
1474         unsigned long flags;
1475         int err;
1476
1477         mutex_lock(&chip->open_mutex);
1478         azx_dev = azx_assign_device(chip, substream->stream);
1479         if (azx_dev == NULL) {
1480                 mutex_unlock(&chip->open_mutex);
1481                 return -EBUSY;
1482         }
1483         runtime->hw = azx_pcm_hw;
1484         runtime->hw.channels_min = hinfo->channels_min;
1485         runtime->hw.channels_max = hinfo->channels_max;
1486         runtime->hw.formats = hinfo->formats;
1487         runtime->hw.rates = hinfo->rates;
1488         snd_pcm_limit_hw_rates(runtime);
1489         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1490         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1491                                    128);
1492         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1493                                    128);
1494         snd_hda_power_up(apcm->codec);
1495         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1496         if (err < 0) {
1497                 azx_release_device(azx_dev);
1498                 snd_hda_power_down(apcm->codec);
1499                 mutex_unlock(&chip->open_mutex);
1500                 return err;
1501         }
1502         snd_pcm_limit_hw_rates(runtime);
1503         /* sanity check */
1504         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1505             snd_BUG_ON(!runtime->hw.channels_max) ||
1506             snd_BUG_ON(!runtime->hw.formats) ||
1507             snd_BUG_ON(!runtime->hw.rates)) {
1508                 azx_release_device(azx_dev);
1509                 hinfo->ops.close(hinfo, apcm->codec, substream);
1510                 snd_hda_power_down(apcm->codec);
1511                 mutex_unlock(&chip->open_mutex);
1512                 return -EINVAL;
1513         }
1514         spin_lock_irqsave(&chip->reg_lock, flags);
1515         azx_dev->substream = substream;
1516         azx_dev->running = 0;
1517         spin_unlock_irqrestore(&chip->reg_lock, flags);
1518
1519         runtime->private_data = azx_dev;
1520         snd_pcm_set_sync(substream);
1521         mutex_unlock(&chip->open_mutex);
1522         return 0;
1523 }
1524
1525 static int azx_pcm_close(struct snd_pcm_substream *substream)
1526 {
1527         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1528         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1529         struct azx *chip = apcm->chip;
1530         struct azx_dev *azx_dev = get_azx_dev(substream);
1531         unsigned long flags;
1532
1533         mutex_lock(&chip->open_mutex);
1534         spin_lock_irqsave(&chip->reg_lock, flags);
1535         azx_dev->substream = NULL;
1536         azx_dev->running = 0;
1537         spin_unlock_irqrestore(&chip->reg_lock, flags);
1538         azx_release_device(azx_dev);
1539         hinfo->ops.close(hinfo, apcm->codec, substream);
1540         snd_hda_power_down(apcm->codec);
1541         mutex_unlock(&chip->open_mutex);
1542         return 0;
1543 }
1544
1545 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1546                              struct snd_pcm_hw_params *hw_params)
1547 {
1548         struct azx_dev *azx_dev = get_azx_dev(substream);
1549
1550         azx_dev->bufsize = 0;
1551         azx_dev->period_bytes = 0;
1552         azx_dev->format_val = 0;
1553         return snd_pcm_lib_malloc_pages(substream,
1554                                         params_buffer_bytes(hw_params));
1555 }
1556
1557 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1558 {
1559         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1560         struct azx_dev *azx_dev = get_azx_dev(substream);
1561         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1562
1563         /* reset BDL address */
1564         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1565         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1566         azx_sd_writel(azx_dev, SD_CTL, 0);
1567         azx_dev->bufsize = 0;
1568         azx_dev->period_bytes = 0;
1569         azx_dev->format_val = 0;
1570
1571         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1572
1573         return snd_pcm_lib_free_pages(substream);
1574 }
1575
1576 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1577 {
1578         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1579         struct azx *chip = apcm->chip;
1580         struct azx_dev *azx_dev = get_azx_dev(substream);
1581         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1582         struct snd_pcm_runtime *runtime = substream->runtime;
1583         unsigned int bufsize, period_bytes, format_val;
1584         int err;
1585
1586         azx_stream_reset(chip, azx_dev);
1587         format_val = snd_hda_calc_stream_format(runtime->rate,
1588                                                 runtime->channels,
1589                                                 runtime->format,
1590                                                 hinfo->maxbps);
1591         if (!format_val) {
1592                 snd_printk(KERN_ERR SFX
1593                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1594                            runtime->rate, runtime->channels, runtime->format);
1595                 return -EINVAL;
1596         }
1597
1598         bufsize = snd_pcm_lib_buffer_bytes(substream);
1599         period_bytes = snd_pcm_lib_period_bytes(substream);
1600
1601         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1602                     bufsize, format_val);
1603
1604         if (bufsize != azx_dev->bufsize ||
1605             period_bytes != azx_dev->period_bytes ||
1606             format_val != azx_dev->format_val) {
1607                 azx_dev->bufsize = bufsize;
1608                 azx_dev->period_bytes = period_bytes;
1609                 azx_dev->format_val = format_val;
1610                 err = azx_setup_periods(chip, substream, azx_dev);
1611                 if (err < 0)
1612                         return err;
1613         }
1614
1615         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1616                                                 (runtime->rate * 2);
1617         azx_setup_controller(chip, azx_dev);
1618         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1619                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1620         else
1621                 azx_dev->fifo_size = 0;
1622
1623         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1624                                   azx_dev->format_val, substream);
1625 }
1626
1627 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1628 {
1629         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1630         struct azx *chip = apcm->chip;
1631         struct azx_dev *azx_dev;
1632         struct snd_pcm_substream *s;
1633         int rstart = 0, start, nsync = 0, sbits = 0;
1634         int nwait, timeout;
1635
1636         switch (cmd) {
1637         case SNDRV_PCM_TRIGGER_START:
1638                 rstart = 1;
1639         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1640         case SNDRV_PCM_TRIGGER_RESUME:
1641                 start = 1;
1642                 break;
1643         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1644         case SNDRV_PCM_TRIGGER_SUSPEND:
1645         case SNDRV_PCM_TRIGGER_STOP:
1646                 start = 0;
1647                 break;
1648         default:
1649                 return -EINVAL;
1650         }
1651
1652         snd_pcm_group_for_each_entry(s, substream) {
1653                 if (s->pcm->card != substream->pcm->card)
1654                         continue;
1655                 azx_dev = get_azx_dev(s);
1656                 sbits |= 1 << azx_dev->index;
1657                 nsync++;
1658                 snd_pcm_trigger_done(s, substream);
1659         }
1660
1661         spin_lock(&chip->reg_lock);
1662         if (nsync > 1) {
1663                 /* first, set SYNC bits of corresponding streams */
1664                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1665         }
1666         snd_pcm_group_for_each_entry(s, substream) {
1667                 if (s->pcm->card != substream->pcm->card)
1668                         continue;
1669                 azx_dev = get_azx_dev(s);
1670                 if (rstart) {
1671                         azx_dev->start_flag = 1;
1672                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1673                 }
1674                 if (start)
1675                         azx_stream_start(chip, azx_dev);
1676                 else
1677                         azx_stream_stop(chip, azx_dev);
1678                 azx_dev->running = start;
1679         }
1680         spin_unlock(&chip->reg_lock);
1681         if (start) {
1682                 if (nsync == 1)
1683                         return 0;
1684                 /* wait until all FIFOs get ready */
1685                 for (timeout = 5000; timeout; timeout--) {
1686                         nwait = 0;
1687                         snd_pcm_group_for_each_entry(s, substream) {
1688                                 if (s->pcm->card != substream->pcm->card)
1689                                         continue;
1690                                 azx_dev = get_azx_dev(s);
1691                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1692                                       SD_STS_FIFO_READY))
1693                                         nwait++;
1694                         }
1695                         if (!nwait)
1696                                 break;
1697                         cpu_relax();
1698                 }
1699         } else {
1700                 /* wait until all RUN bits are cleared */
1701                 for (timeout = 5000; timeout; timeout--) {
1702                         nwait = 0;
1703                         snd_pcm_group_for_each_entry(s, substream) {
1704                                 if (s->pcm->card != substream->pcm->card)
1705                                         continue;
1706                                 azx_dev = get_azx_dev(s);
1707                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1708                                     SD_CTL_DMA_START)
1709                                         nwait++;
1710                         }
1711                         if (!nwait)
1712                                 break;
1713                         cpu_relax();
1714                 }
1715         }
1716         if (nsync > 1) {
1717                 spin_lock(&chip->reg_lock);
1718                 /* reset SYNC bits */
1719                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1720                 spin_unlock(&chip->reg_lock);
1721         }
1722         return 0;
1723 }
1724
1725 /* get the current DMA position with correction on VIA chips */
1726 static unsigned int azx_via_get_position(struct azx *chip,
1727                                          struct azx_dev *azx_dev)
1728 {
1729         unsigned int link_pos, mini_pos, bound_pos;
1730         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1731         unsigned int fifo_size;
1732
1733         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1734         if (azx_dev->index >= 4) {
1735                 /* Playback, no problem using link position */
1736                 return link_pos;
1737         }
1738
1739         /* Capture */
1740         /* For new chipset,
1741          * use mod to get the DMA position just like old chipset
1742          */
1743         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1744         mod_dma_pos %= azx_dev->period_bytes;
1745
1746         /* azx_dev->fifo_size can't get FIFO size of in stream.
1747          * Get from base address + offset.
1748          */
1749         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1750
1751         if (azx_dev->insufficient) {
1752                 /* Link position never gather than FIFO size */
1753                 if (link_pos <= fifo_size)
1754                         return 0;
1755
1756                 azx_dev->insufficient = 0;
1757         }
1758
1759         if (link_pos <= fifo_size)
1760                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1761         else
1762                 mini_pos = link_pos - fifo_size;
1763
1764         /* Find nearest previous boudary */
1765         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1766         mod_link_pos = link_pos % azx_dev->period_bytes;
1767         if (mod_link_pos >= fifo_size)
1768                 bound_pos = link_pos - mod_link_pos;
1769         else if (mod_dma_pos >= mod_mini_pos)
1770                 bound_pos = mini_pos - mod_mini_pos;
1771         else {
1772                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1773                 if (bound_pos >= azx_dev->bufsize)
1774                         bound_pos = 0;
1775         }
1776
1777         /* Calculate real DMA position we want */
1778         return bound_pos + mod_dma_pos;
1779 }
1780
1781 static unsigned int azx_get_position(struct azx *chip,
1782                                      struct azx_dev *azx_dev)
1783 {
1784         unsigned int pos;
1785
1786         if (chip->via_dmapos_patch)
1787                 pos = azx_via_get_position(chip, azx_dev);
1788         else if (chip->position_fix == POS_FIX_POSBUF ||
1789                  chip->position_fix == POS_FIX_AUTO) {
1790                 /* use the position buffer */
1791                 pos = le32_to_cpu(*azx_dev->posbuf);
1792         } else {
1793                 /* read LPIB */
1794                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1795         }
1796         if (pos >= azx_dev->bufsize)
1797                 pos = 0;
1798         return pos;
1799 }
1800
1801 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1802 {
1803         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1804         struct azx *chip = apcm->chip;
1805         struct azx_dev *azx_dev = get_azx_dev(substream);
1806         return bytes_to_frames(substream->runtime,
1807                                azx_get_position(chip, azx_dev));
1808 }
1809
1810 /*
1811  * Check whether the current DMA position is acceptable for updating
1812  * periods.  Returns non-zero if it's OK.
1813  *
1814  * Many HD-audio controllers appear pretty inaccurate about
1815  * the update-IRQ timing.  The IRQ is issued before actually the
1816  * data is processed.  So, we need to process it afterwords in a
1817  * workqueue.
1818  */
1819 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1820 {
1821         unsigned int pos;
1822
1823         if (azx_dev->start_flag &&
1824             time_before_eq(jiffies, azx_dev->start_jiffies))
1825                 return -1;      /* bogus (too early) interrupt */
1826         azx_dev->start_flag = 0;
1827
1828         pos = azx_get_position(chip, azx_dev);
1829         if (chip->position_fix == POS_FIX_AUTO) {
1830                 if (!pos) {
1831                         printk(KERN_WARNING
1832                                "hda-intel: Invalid position buffer, "
1833                                "using LPIB read method instead.\n");
1834                         chip->position_fix = POS_FIX_LPIB;
1835                         pos = azx_get_position(chip, azx_dev);
1836                 } else
1837                         chip->position_fix = POS_FIX_POSBUF;
1838         }
1839
1840         if (!bdl_pos_adj[chip->dev_index])
1841                 return 1; /* no delayed ack */
1842         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1843                 return 0; /* NG - it's below the period boundary */
1844         return 1; /* OK, it's fine */
1845 }
1846
1847 /*
1848  * The work for pending PCM period updates.
1849  */
1850 static void azx_irq_pending_work(struct work_struct *work)
1851 {
1852         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1853         int i, pending;
1854
1855         if (!chip->irq_pending_warned) {
1856                 printk(KERN_WARNING
1857                        "hda-intel: IRQ timing workaround is activated "
1858                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1859                        chip->card->number);
1860                 chip->irq_pending_warned = 1;
1861         }
1862
1863         for (;;) {
1864                 pending = 0;
1865                 spin_lock_irq(&chip->reg_lock);
1866                 for (i = 0; i < chip->num_streams; i++) {
1867                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1868                         if (!azx_dev->irq_pending ||
1869                             !azx_dev->substream ||
1870                             !azx_dev->running)
1871                                 continue;
1872                         if (azx_position_ok(chip, azx_dev)) {
1873                                 azx_dev->irq_pending = 0;
1874                                 spin_unlock(&chip->reg_lock);
1875                                 snd_pcm_period_elapsed(azx_dev->substream);
1876                                 spin_lock(&chip->reg_lock);
1877                         } else
1878                                 pending++;
1879                 }
1880                 spin_unlock_irq(&chip->reg_lock);
1881                 if (!pending)
1882                         return;
1883                 cond_resched();
1884         }
1885 }
1886
1887 /* clear irq_pending flags and assure no on-going workq */
1888 static void azx_clear_irq_pending(struct azx *chip)
1889 {
1890         int i;
1891
1892         spin_lock_irq(&chip->reg_lock);
1893         for (i = 0; i < chip->num_streams; i++)
1894                 chip->azx_dev[i].irq_pending = 0;
1895         spin_unlock_irq(&chip->reg_lock);
1896 }
1897
1898 static struct snd_pcm_ops azx_pcm_ops = {
1899         .open = azx_pcm_open,
1900         .close = azx_pcm_close,
1901         .ioctl = snd_pcm_lib_ioctl,
1902         .hw_params = azx_pcm_hw_params,
1903         .hw_free = azx_pcm_hw_free,
1904         .prepare = azx_pcm_prepare,
1905         .trigger = azx_pcm_trigger,
1906         .pointer = azx_pcm_pointer,
1907         .page = snd_pcm_sgbuf_ops_page,
1908 };
1909
1910 static void azx_pcm_free(struct snd_pcm *pcm)
1911 {
1912         struct azx_pcm *apcm = pcm->private_data;
1913         if (apcm) {
1914                 apcm->chip->pcm[pcm->device] = NULL;
1915                 kfree(apcm);
1916         }
1917 }
1918
1919 static int
1920 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1921                       struct hda_pcm *cpcm)
1922 {
1923         struct azx *chip = bus->private_data;
1924         struct snd_pcm *pcm;
1925         struct azx_pcm *apcm;
1926         int pcm_dev = cpcm->device;
1927         int s, err;
1928
1929         if (pcm_dev >= AZX_MAX_PCMS) {
1930                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1931                            pcm_dev);
1932                 return -EINVAL;
1933         }
1934         if (chip->pcm[pcm_dev]) {
1935                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1936                 return -EBUSY;
1937         }
1938         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1939                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1940                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1941                           &pcm);
1942         if (err < 0)
1943                 return err;
1944         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1945         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1946         if (apcm == NULL)
1947                 return -ENOMEM;
1948         apcm->chip = chip;
1949         apcm->codec = codec;
1950         pcm->private_data = apcm;
1951         pcm->private_free = azx_pcm_free;
1952         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1953                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1954         chip->pcm[pcm_dev] = pcm;
1955         cpcm->pcm = pcm;
1956         for (s = 0; s < 2; s++) {
1957                 apcm->hinfo[s] = &cpcm->stream[s];
1958                 if (cpcm->stream[s].substreams)
1959                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1960         }
1961         /* buffer pre-allocation */
1962         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1963                                               snd_dma_pci_data(chip->pci),
1964                                               1024 * 64, 32 * 1024 * 1024);
1965         return 0;
1966 }
1967
1968 /*
1969  * mixer creation - all stuff is implemented in hda module
1970  */
1971 static int __devinit azx_mixer_create(struct azx *chip)
1972 {
1973         return snd_hda_build_controls(chip->bus);
1974 }
1975
1976
1977 /*
1978  * initialize SD streams
1979  */
1980 static int __devinit azx_init_stream(struct azx *chip)
1981 {
1982         int i;
1983
1984         /* initialize each stream (aka device)
1985          * assign the starting bdl address to each stream (device)
1986          * and initialize
1987          */
1988         for (i = 0; i < chip->num_streams; i++) {
1989                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1990                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1991                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1992                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1993                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1994                 azx_dev->sd_int_sta_mask = 1 << i;
1995                 /* stream tag: must be non-zero and unique */
1996                 azx_dev->index = i;
1997                 azx_dev->stream_tag = i + 1;
1998         }
1999
2000         return 0;
2001 }
2002
2003 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2004 {
2005         if (request_irq(chip->pci->irq, azx_interrupt,
2006                         chip->msi ? 0 : IRQF_SHARED,
2007                         "HDA Intel", chip)) {
2008                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2009                        "disabling device\n", chip->pci->irq);
2010                 if (do_disconnect)
2011                         snd_card_disconnect(chip->card);
2012                 return -1;
2013         }
2014         chip->irq = chip->pci->irq;
2015         pci_intx(chip->pci, !chip->msi);
2016         return 0;
2017 }
2018
2019
2020 static void azx_stop_chip(struct azx *chip)
2021 {
2022         if (!chip->initialized)
2023                 return;
2024
2025         /* disable interrupts */
2026         azx_int_disable(chip);
2027         azx_int_clear(chip);
2028
2029         /* disable CORB/RIRB */
2030         azx_free_cmd_io(chip);
2031
2032         /* disable position buffer */
2033         azx_writel(chip, DPLBASE, 0);
2034         azx_writel(chip, DPUBASE, 0);
2035
2036         chip->initialized = 0;
2037 }
2038
2039 #ifdef CONFIG_SND_HDA_POWER_SAVE
2040 /* power-up/down the controller */
2041 static void azx_power_notify(struct hda_bus *bus)
2042 {
2043         struct azx *chip = bus->private_data;
2044         struct hda_codec *c;
2045         int power_on = 0;
2046
2047         list_for_each_entry(c, &bus->codec_list, list) {
2048                 if (c->power_on) {
2049                         power_on = 1;
2050                         break;
2051                 }
2052         }
2053         if (power_on)
2054                 azx_init_chip(chip);
2055         else if (chip->running && power_save_controller)
2056                 azx_stop_chip(chip);
2057 }
2058 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2059
2060 #ifdef CONFIG_PM
2061 /*
2062  * power management
2063  */
2064
2065 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2066 {
2067         struct hda_codec *codec;
2068
2069         list_for_each_entry(codec, &bus->codec_list, list) {
2070                 if (snd_hda_codec_needs_resume(codec))
2071                         return 1;
2072         }
2073         return 0;
2074 }
2075
2076 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2077 {
2078         struct snd_card *card = pci_get_drvdata(pci);
2079         struct azx *chip = card->private_data;
2080         int i;
2081
2082         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2083         azx_clear_irq_pending(chip);
2084         for (i = 0; i < AZX_MAX_PCMS; i++)
2085                 snd_pcm_suspend_all(chip->pcm[i]);
2086         if (chip->initialized)
2087                 snd_hda_suspend(chip->bus);
2088         azx_stop_chip(chip);
2089         if (chip->irq >= 0) {
2090                 free_irq(chip->irq, chip);
2091                 chip->irq = -1;
2092         }
2093         if (chip->msi)
2094                 pci_disable_msi(chip->pci);
2095         pci_disable_device(pci);
2096         pci_save_state(pci);
2097         pci_set_power_state(pci, pci_choose_state(pci, state));
2098         return 0;
2099 }
2100
2101 static int azx_resume(struct pci_dev *pci)
2102 {
2103         struct snd_card *card = pci_get_drvdata(pci);
2104         struct azx *chip = card->private_data;
2105
2106         pci_set_power_state(pci, PCI_D0);
2107         pci_restore_state(pci);
2108         if (pci_enable_device(pci) < 0) {
2109                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2110                        "disabling device\n");
2111                 snd_card_disconnect(card);
2112                 return -EIO;
2113         }
2114         pci_set_master(pci);
2115         if (chip->msi)
2116                 if (pci_enable_msi(pci) < 0)
2117                         chip->msi = 0;
2118         if (azx_acquire_irq(chip, 1) < 0)
2119                 return -EIO;
2120         azx_init_pci(chip);
2121
2122         if (snd_hda_codecs_inuse(chip->bus))
2123                 azx_init_chip(chip);
2124
2125         snd_hda_resume(chip->bus);
2126         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2127         return 0;
2128 }
2129 #endif /* CONFIG_PM */
2130
2131
2132 /*
2133  * reboot notifier for hang-up problem at power-down
2134  */
2135 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2136 {
2137         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2138         azx_stop_chip(chip);
2139         return NOTIFY_OK;
2140 }
2141
2142 static void azx_notifier_register(struct azx *chip)
2143 {
2144         chip->reboot_notifier.notifier_call = azx_halt;
2145         register_reboot_notifier(&chip->reboot_notifier);
2146 }
2147
2148 static void azx_notifier_unregister(struct azx *chip)
2149 {
2150         if (chip->reboot_notifier.notifier_call)
2151                 unregister_reboot_notifier(&chip->reboot_notifier);
2152 }
2153
2154 /*
2155  * destructor
2156  */
2157 static int azx_free(struct azx *chip)
2158 {
2159         int i;
2160
2161         azx_notifier_unregister(chip);
2162
2163         if (chip->initialized) {
2164                 azx_clear_irq_pending(chip);
2165                 for (i = 0; i < chip->num_streams; i++)
2166                         azx_stream_stop(chip, &chip->azx_dev[i]);
2167                 azx_stop_chip(chip);
2168         }
2169
2170         if (chip->irq >= 0)
2171                 free_irq(chip->irq, (void*)chip);
2172         if (chip->msi)
2173                 pci_disable_msi(chip->pci);
2174         if (chip->remap_addr)
2175                 iounmap(chip->remap_addr);
2176
2177         if (chip->azx_dev) {
2178                 for (i = 0; i < chip->num_streams; i++)
2179                         if (chip->azx_dev[i].bdl.area)
2180                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2181         }
2182         if (chip->rb.area)
2183                 snd_dma_free_pages(&chip->rb);
2184         if (chip->posbuf.area)
2185                 snd_dma_free_pages(&chip->posbuf);
2186         pci_release_regions(chip->pci);
2187         pci_disable_device(chip->pci);
2188         kfree(chip->azx_dev);
2189         kfree(chip);
2190
2191         return 0;
2192 }
2193
2194 static int azx_dev_free(struct snd_device *device)
2195 {
2196         return azx_free(device->device_data);
2197 }
2198
2199 /*
2200  * white/black-listing for position_fix
2201  */
2202 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2203         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2204         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2205         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2206         {}
2207 };
2208
2209 static int __devinit check_position_fix(struct azx *chip, int fix)
2210 {
2211         const struct snd_pci_quirk *q;
2212
2213         switch (fix) {
2214         case POS_FIX_LPIB:
2215         case POS_FIX_POSBUF:
2216                 return fix;
2217         }
2218
2219         /* Check VIA/ATI HD Audio Controller exist */
2220         switch (chip->driver_type) {
2221         case AZX_DRIVER_VIA:
2222         case AZX_DRIVER_ATI:
2223                 chip->via_dmapos_patch = 1;
2224                 /* Use link position directly, avoid any transfer problem. */
2225                 return POS_FIX_LPIB;
2226         }
2227         chip->via_dmapos_patch = 0;
2228
2229         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2230         if (q) {
2231                 printk(KERN_INFO
2232                        "hda_intel: position_fix set to %d "
2233                        "for device %04x:%04x\n",
2234                        q->value, q->subvendor, q->subdevice);
2235                 return q->value;
2236         }
2237         return POS_FIX_AUTO;
2238 }
2239
2240 /*
2241  * black-lists for probe_mask
2242  */
2243 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2244         /* Thinkpad often breaks the controller communication when accessing
2245          * to the non-working (or non-existing) modem codec slot.
2246          */
2247         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2248         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2249         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2250         /* broken BIOS */
2251         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2252         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2253         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2254         /* forced codec slots */
2255         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2256         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2257         {}
2258 };
2259
2260 #define AZX_FORCE_CODEC_MASK    0x100
2261
2262 static void __devinit check_probe_mask(struct azx *chip, int dev)
2263 {
2264         const struct snd_pci_quirk *q;
2265
2266         chip->codec_probe_mask = probe_mask[dev];
2267         if (chip->codec_probe_mask == -1) {
2268                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2269                 if (q) {
2270                         printk(KERN_INFO
2271                                "hda_intel: probe_mask set to 0x%x "
2272                                "for device %04x:%04x\n",
2273                                q->value, q->subvendor, q->subdevice);
2274                         chip->codec_probe_mask = q->value;
2275                 }
2276         }
2277
2278         /* check forced option */
2279         if (chip->codec_probe_mask != -1 &&
2280             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2281                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2282                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2283                        chip->codec_mask);
2284         }
2285 }
2286
2287
2288 /*
2289  * constructor
2290  */
2291 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2292                                 int dev, int driver_type,
2293                                 struct azx **rchip)
2294 {
2295         struct azx *chip;
2296         int i, err;
2297         unsigned short gcap;
2298         static struct snd_device_ops ops = {
2299                 .dev_free = azx_dev_free,
2300         };
2301
2302         *rchip = NULL;
2303
2304         err = pci_enable_device(pci);
2305         if (err < 0)
2306                 return err;
2307
2308         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2309         if (!chip) {
2310                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2311                 pci_disable_device(pci);
2312                 return -ENOMEM;
2313         }
2314
2315         spin_lock_init(&chip->reg_lock);
2316         mutex_init(&chip->open_mutex);
2317         chip->card = card;
2318         chip->pci = pci;
2319         chip->irq = -1;
2320         chip->driver_type = driver_type;
2321         chip->msi = enable_msi;
2322         chip->dev_index = dev;
2323         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2324
2325         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2326         check_probe_mask(chip, dev);
2327
2328         chip->single_cmd = single_cmd;
2329
2330         if (bdl_pos_adj[dev] < 0) {
2331                 switch (chip->driver_type) {
2332                 case AZX_DRIVER_ICH:
2333                         bdl_pos_adj[dev] = 1;
2334                         break;
2335                 default:
2336                         bdl_pos_adj[dev] = 32;
2337                         break;
2338                 }
2339         }
2340
2341 #if BITS_PER_LONG != 64
2342         /* Fix up base address on ULI M5461 */
2343         if (chip->driver_type == AZX_DRIVER_ULI) {
2344                 u16 tmp3;
2345                 pci_read_config_word(pci, 0x40, &tmp3);
2346                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2347                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2348         }
2349 #endif
2350
2351         err = pci_request_regions(pci, "ICH HD audio");
2352         if (err < 0) {
2353                 kfree(chip);
2354                 pci_disable_device(pci);
2355                 return err;
2356         }
2357
2358         chip->addr = pci_resource_start(pci, 0);
2359         chip->remap_addr = pci_ioremap_bar(pci, 0);
2360         if (chip->remap_addr == NULL) {
2361                 snd_printk(KERN_ERR SFX "ioremap error\n");
2362                 err = -ENXIO;
2363                 goto errout;
2364         }
2365
2366         if (chip->msi)
2367                 if (pci_enable_msi(pci) < 0)
2368                         chip->msi = 0;
2369
2370         if (azx_acquire_irq(chip, 0) < 0) {
2371                 err = -EBUSY;
2372                 goto errout;
2373         }
2374
2375         pci_set_master(pci);
2376         synchronize_irq(chip->irq);
2377
2378         gcap = azx_readw(chip, GCAP);
2379         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2380
2381         /* disable SB600 64bit support for safety */
2382         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2383             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2384                 struct pci_dev *p_smbus;
2385                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2386                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2387                                          NULL);
2388                 if (p_smbus) {
2389                         if (p_smbus->revision < 0x30)
2390                                 gcap &= ~ICH6_GCAP_64OK;
2391                         pci_dev_put(p_smbus);
2392                 }
2393         }
2394
2395         /* allow 64bit DMA address if supported by H/W */
2396         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2397                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2398         else {
2399                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2400                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2401         }
2402
2403         /* read number of streams from GCAP register instead of using
2404          * hardcoded value
2405          */
2406         chip->capture_streams = (gcap >> 8) & 0x0f;
2407         chip->playback_streams = (gcap >> 12) & 0x0f;
2408         if (!chip->playback_streams && !chip->capture_streams) {
2409                 /* gcap didn't give any info, switching to old method */
2410
2411                 switch (chip->driver_type) {
2412                 case AZX_DRIVER_ULI:
2413                         chip->playback_streams = ULI_NUM_PLAYBACK;
2414                         chip->capture_streams = ULI_NUM_CAPTURE;
2415                         break;
2416                 case AZX_DRIVER_ATIHDMI:
2417                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2418                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2419                         break;
2420                 case AZX_DRIVER_GENERIC:
2421                 default:
2422                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2423                         chip->capture_streams = ICH6_NUM_CAPTURE;
2424                         break;
2425                 }
2426         }
2427         chip->capture_index_offset = 0;
2428         chip->playback_index_offset = chip->capture_streams;
2429         chip->num_streams = chip->playback_streams + chip->capture_streams;
2430         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2431                                 GFP_KERNEL);
2432         if (!chip->azx_dev) {
2433                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2434                 goto errout;
2435         }
2436
2437         for (i = 0; i < chip->num_streams; i++) {
2438                 /* allocate memory for the BDL for each stream */
2439                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2440                                           snd_dma_pci_data(chip->pci),
2441                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2442                 if (err < 0) {
2443                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2444                         goto errout;
2445                 }
2446         }
2447         /* allocate memory for the position buffer */
2448         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2449                                   snd_dma_pci_data(chip->pci),
2450                                   chip->num_streams * 8, &chip->posbuf);
2451         if (err < 0) {
2452                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2453                 goto errout;
2454         }
2455         /* allocate CORB/RIRB */
2456         err = azx_alloc_cmd_io(chip);
2457         if (err < 0)
2458                 goto errout;
2459
2460         /* initialize streams */
2461         azx_init_stream(chip);
2462
2463         /* initialize chip */
2464         azx_init_pci(chip);
2465         azx_init_chip(chip);
2466
2467         /* codec detection */
2468         if (!chip->codec_mask) {
2469                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2470                 err = -ENODEV;
2471                 goto errout;
2472         }
2473
2474         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2475         if (err <0) {
2476                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2477                 goto errout;
2478         }
2479
2480         strcpy(card->driver, "HDA-Intel");
2481         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2482                 sizeof(card->shortname));
2483         snprintf(card->longname, sizeof(card->longname),
2484                  "%s at 0x%lx irq %i",
2485                  card->shortname, chip->addr, chip->irq);
2486
2487         *rchip = chip;
2488         return 0;
2489
2490  errout:
2491         azx_free(chip);
2492         return err;
2493 }
2494
2495 static void power_down_all_codecs(struct azx *chip)
2496 {
2497 #ifdef CONFIG_SND_HDA_POWER_SAVE
2498         /* The codecs were powered up in snd_hda_codec_new().
2499          * Now all initialization done, so turn them down if possible
2500          */
2501         struct hda_codec *codec;
2502         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2503                 snd_hda_power_down(codec);
2504         }
2505 #endif
2506 }
2507
2508 static int __devinit azx_probe(struct pci_dev *pci,
2509                                const struct pci_device_id *pci_id)
2510 {
2511         static int dev;
2512         struct snd_card *card;
2513         struct azx *chip;
2514         int err;
2515
2516         if (dev >= SNDRV_CARDS)
2517                 return -ENODEV;
2518         if (!enable[dev]) {
2519                 dev++;
2520                 return -ENOENT;
2521         }
2522
2523         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2524         if (err < 0) {
2525                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2526                 return err;
2527         }
2528
2529         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2530         if (err < 0)
2531                 goto out_free;
2532         card->private_data = chip;
2533
2534         /* create codec instances */
2535         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2536         if (err < 0)
2537                 goto out_free;
2538
2539         /* create PCM streams */
2540         err = snd_hda_build_pcms(chip->bus);
2541         if (err < 0)
2542                 goto out_free;
2543
2544         /* create mixer controls */
2545         err = azx_mixer_create(chip);
2546         if (err < 0)
2547                 goto out_free;
2548
2549         snd_card_set_dev(card, &pci->dev);
2550
2551         err = snd_card_register(card);
2552         if (err < 0)
2553                 goto out_free;
2554
2555         pci_set_drvdata(pci, card);
2556         chip->running = 1;
2557         power_down_all_codecs(chip);
2558         azx_notifier_register(chip);
2559
2560         dev++;
2561         return err;
2562 out_free:
2563         snd_card_free(card);
2564         return err;
2565 }
2566
2567 static void __devexit azx_remove(struct pci_dev *pci)
2568 {
2569         snd_card_free(pci_get_drvdata(pci));
2570         pci_set_drvdata(pci, NULL);
2571 }
2572
2573 /* PCI IDs */
2574 static struct pci_device_id azx_ids[] = {
2575         /* ICH 6..10 */
2576         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2577         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2578         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2579         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2580         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2581         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2582         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2583         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2584         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2585         /* PCH */
2586         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2587         /* SCH */
2588         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2589         /* ATI SB 450/600 */
2590         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2591         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2592         /* ATI HDMI */
2593         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2594         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2595         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2596         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2597         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2598         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2599         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2600         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2601         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2602         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2603         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2604         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2605         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2606         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2607         /* VIA VT8251/VT8237A */
2608         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2609         /* SIS966 */
2610         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2611         /* ULI M5461 */
2612         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2613         /* NVIDIA MCP */
2614         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2615         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2616         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2617         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2618         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2619         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2620         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2621         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2622         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2623         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2624         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2625         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2626         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2627         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2628         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2629         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2630         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2631         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2632         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2633         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2634         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2635         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2636         /* Teradici */
2637         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2638         /* Creative X-Fi (CA0110-IBG) */
2639 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2640         /* the following entry conflicts with snd-ctxfi driver,
2641          * as ctxfi driver mutates from HD-audio to native mode with
2642          * a special command sequence.
2643          */
2644         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2645           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2646           .class_mask = 0xffffff,
2647           .driver_data = AZX_DRIVER_GENERIC },
2648 #else
2649         /* this entry seems still valid -- i.e. without emu20kx chip */
2650         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2651 #endif
2652         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2653         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2654           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2655           .class_mask = 0xffffff,
2656           .driver_data = AZX_DRIVER_GENERIC },
2657         { 0, }
2658 };
2659 MODULE_DEVICE_TABLE(pci, azx_ids);
2660
2661 /* pci_driver definition */
2662 static struct pci_driver driver = {
2663         .name = "HDA Intel",
2664         .id_table = azx_ids,
2665         .probe = azx_probe,
2666         .remove = __devexit_p(azx_remove),
2667 #ifdef CONFIG_PM
2668         .suspend = azx_suspend,
2669         .resume = azx_resume,
2670 #endif
2671 };
2672
2673 static int __init alsa_card_azx_init(void)
2674 {
2675         return pci_register_driver(&driver);
2676 }
2677
2678 static void __exit alsa_card_azx_exit(void)
2679 {
2680         pci_unregister_driver(&driver);
2681 }
2682
2683 module_init(alsa_card_azx_init)
2684 module_exit(alsa_card_azx_exit)