sound/pci/ctxfi/cthw20k2.c

   1 /**
   2  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
   3  *
   4  * This source file is released under GPL v2 license (no other versions).
   5  * See the COPYING file included in the main directory of this source
   6  * distribution for the license terms and conditions.
   7  *
   8  * @File        cthw20k2.c
   9  *
  10  * @Brief
  11  * This file contains the implementation of hardware access methord for 20k2.
  12  *
  13  * @Author      Liu Chun
  14  * @Date        May 14 2008
  15  *
  16  */
  17
  18 #include <linux/types.h>
  19 #include <linux/slab.h>
  20 #include <linux/pci.h>
  21 #include <linux/io.h>
  22 #include <linux/string.h>
  23 #include <linux/kernel.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include "cthw20k2.h"
  27 #include "ct20k2reg.h"
  28
  29 #if BITS_PER_LONG == 32
  30 #define CT_XFI_DMA_MASK         DMA_BIT_MASK(32) /* 32 bit PTE */
  31 #else
  32 #define CT_XFI_DMA_MASK         DMA_BIT_MASK(64) /* 64 bit PTE */
  33 #endif
  34
  35 struct hw20k2 {
  36         struct hw hw;
  37         /* for i2c */
  38         unsigned char dev_id;
  39         unsigned char addr_size;
  40         unsigned char data_size;
  41 };
  42
  43 static u32 hw_read_20kx(struct hw *hw, u32 reg);
  44 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
  45
  46 /*
  47  * Type definition block.
  48  * The layout of control structures can be directly applied on 20k2 chip.
  49  */
  50
  51 /*
  52  * SRC control block definitions.
  53  */
  54
  55 /* SRC resource control block */
  56 #define SRCCTL_STATE    0x00000007
  57 #define SRCCTL_BM       0x00000008
  58 #define SRCCTL_RSR      0x00000030
  59 #define SRCCTL_SF       0x000001C0
  60 #define SRCCTL_WR       0x00000200
  61 #define SRCCTL_PM       0x00000400
  62 #define SRCCTL_ROM      0x00001800
  63 #define SRCCTL_VO       0x00002000
  64 #define SRCCTL_ST       0x00004000
  65 #define SRCCTL_IE       0x00008000
  66 #define SRCCTL_ILSZ     0x000F0000
  67 #define SRCCTL_BP       0x00100000
  68
  69 #define SRCCCR_CISZ     0x000007FF
  70 #define SRCCCR_CWA      0x001FF800
  71 #define SRCCCR_D        0x00200000
  72 #define SRCCCR_RS       0x01C00000
  73 #define SRCCCR_NAL      0x3E000000
  74 #define SRCCCR_RA       0xC0000000
  75
  76 #define SRCCA_CA        0x0FFFFFFF
  77 #define SRCCA_RS        0xE0000000
  78
  79 #define SRCSA_SA        0x0FFFFFFF
  80
  81 #define SRCLA_LA        0x0FFFFFFF
  82
  83 /* Mixer Parameter Ring ram Low and Hight register.
  84  * Fixed-point value in 8.24 format for parameter channel */
  85 #define MPRLH_PITCH     0xFFFFFFFF
  86
  87 /* SRC resource register dirty flags */
  88 union src_dirty {
  89         struct {
  90                 u16 ctl:1;
  91                 u16 ccr:1;
  92                 u16 sa:1;
  93                 u16 la:1;
  94                 u16 ca:1;
  95                 u16 mpr:1;
  96                 u16 czbfs:1;    /* Clear Z-Buffers */
  97                 u16 rsv:9;
  98         } bf;
  99         u16 data;
 100 };
 101
 102 struct src_rsc_ctrl_blk {
 103         unsigned int    ctl;
 104         unsigned int    ccr;
 105         unsigned int    ca;
 106         unsigned int    sa;
 107         unsigned int    la;
 108         unsigned int    mpr;
 109         union src_dirty dirty;
 110 };
 111
 112 /* SRC manager control block */
 113 union src_mgr_dirty {
 114         struct {
 115                 u16 enb0:1;
 116                 u16 enb1:1;
 117                 u16 enb2:1;
 118                 u16 enb3:1;
 119                 u16 enb4:1;
 120                 u16 enb5:1;
 121                 u16 enb6:1;
 122                 u16 enb7:1;
 123                 u16 enbsa:1;
 124                 u16 rsv:7;
 125         } bf;
 126         u16 data;
 127 };
 128
 129 struct src_mgr_ctrl_blk {
 130         unsigned int            enbsa;
 131         unsigned int            enb[8];
 132         union src_mgr_dirty     dirty;
 133 };
 134
 135 /* SRCIMP manager control block */
 136 #define SRCAIM_ARC      0x00000FFF
 137 #define SRCAIM_NXT      0x00FF0000
 138 #define SRCAIM_SRC      0xFF000000
 139
 140 struct srcimap {
 141         unsigned int srcaim;
 142         unsigned int idx;
 143 };
 144
 145 /* SRCIMP manager register dirty flags */
 146 union srcimp_mgr_dirty {
 147         struct {
 148                 u16 srcimap:1;
 149                 u16 rsv:15;
 150         } bf;
 151         u16 data;
 152 };
 153
 154 struct srcimp_mgr_ctrl_blk {
 155         struct srcimap          srcimap;
 156         union srcimp_mgr_dirty  dirty;
 157 };
 158
 159 /*
 160  * Function implementation block.
 161  */
 162
 163 static int src_get_rsc_ctrl_blk(void **rblk)
 164 {
 165         struct src_rsc_ctrl_blk *blk;
 166
 167         *rblk = NULL;
 168         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 169         if (NULL == blk)
 170                 return -ENOMEM;
 171
 172         *rblk = blk;
 173
 174         return 0;
 175 }
 176
 177 static int src_put_rsc_ctrl_blk(void *blk)
 178 {
 179         kfree(blk);
 180
 181         return 0;
 182 }
 183
 184 static int src_set_state(void *blk, unsigned int state)
 185 {
 186         struct src_rsc_ctrl_blk *ctl = blk;
 187
 188         set_field(&ctl->ctl, SRCCTL_STATE, state);
 189         ctl->dirty.bf.ctl = 1;
 190         return 0;
 191 }
 192
 193 static int src_set_bm(void *blk, unsigned int bm)
 194 {
 195         struct src_rsc_ctrl_blk *ctl = blk;
 196
 197         set_field(&ctl->ctl, SRCCTL_BM, bm);
 198         ctl->dirty.bf.ctl = 1;
 199         return 0;
 200 }
 201
 202 static int src_set_rsr(void *blk, unsigned int rsr)
 203 {
 204         struct src_rsc_ctrl_blk *ctl = blk;
 205
 206         set_field(&ctl->ctl, SRCCTL_RSR, rsr);
 207         ctl->dirty.bf.ctl = 1;
 208         return 0;
 209 }
 210
 211 static int src_set_sf(void *blk, unsigned int sf)
 212 {
 213         struct src_rsc_ctrl_blk *ctl = blk;
 214
 215         set_field(&ctl->ctl, SRCCTL_SF, sf);
 216         ctl->dirty.bf.ctl = 1;
 217         return 0;
 218 }
 219
 220 static int src_set_wr(void *blk, unsigned int wr)
 221 {
 222         struct src_rsc_ctrl_blk *ctl = blk;
 223
 224         set_field(&ctl->ctl, SRCCTL_WR, wr);
 225         ctl->dirty.bf.ctl = 1;
 226         return 0;
 227 }
 228
 229 static int src_set_pm(void *blk, unsigned int pm)
 230 {
 231         struct src_rsc_ctrl_blk *ctl = blk;
 232
 233         set_field(&ctl->ctl, SRCCTL_PM, pm);
 234         ctl->dirty.bf.ctl = 1;
 235         return 0;
 236 }
 237
 238 static int src_set_rom(void *blk, unsigned int rom)
 239 {
 240         struct src_rsc_ctrl_blk *ctl = blk;
 241
 242         set_field(&ctl->ctl, SRCCTL_ROM, rom);
 243         ctl->dirty.bf.ctl = 1;
 244         return 0;
 245 }
 246
 247 static int src_set_vo(void *blk, unsigned int vo)
 248 {
 249         struct src_rsc_ctrl_blk *ctl = blk;
 250
 251         set_field(&ctl->ctl, SRCCTL_VO, vo);
 252         ctl->dirty.bf.ctl = 1;
 253         return 0;
 254 }
 255
 256 static int src_set_st(void *blk, unsigned int st)
 257 {
 258         struct src_rsc_ctrl_blk *ctl = blk;
 259
 260         set_field(&ctl->ctl, SRCCTL_ST, st);
 261         ctl->dirty.bf.ctl = 1;
 262         return 0;
 263 }
 264
 265 static int src_set_ie(void *blk, unsigned int ie)
 266 {
 267         struct src_rsc_ctrl_blk *ctl = blk;
 268
 269         set_field(&ctl->ctl, SRCCTL_IE, ie);
 270         ctl->dirty.bf.ctl = 1;
 271         return 0;
 272 }
 273
 274 static int src_set_ilsz(void *blk, unsigned int ilsz)
 275 {
 276         struct src_rsc_ctrl_blk *ctl = blk;
 277
 278         set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
 279         ctl->dirty.bf.ctl = 1;
 280         return 0;
 281 }
 282
 283 static int src_set_bp(void *blk, unsigned int bp)
 284 {
 285         struct src_rsc_ctrl_blk *ctl = blk;
 286
 287         set_field(&ctl->ctl, SRCCTL_BP, bp);
 288         ctl->dirty.bf.ctl = 1;
 289         return 0;
 290 }
 291
 292 static int src_set_cisz(void *blk, unsigned int cisz)
 293 {
 294         struct src_rsc_ctrl_blk *ctl = blk;
 295
 296         set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
 297         ctl->dirty.bf.ccr = 1;
 298         return 0;
 299 }
 300
 301 static int src_set_ca(void *blk, unsigned int ca)
 302 {
 303         struct src_rsc_ctrl_blk *ctl = blk;
 304
 305         set_field(&ctl->ca, SRCCA_CA, ca);
 306         ctl->dirty.bf.ca = 1;
 307         return 0;
 308 }
 309
 310 static int src_set_sa(void *blk, unsigned int sa)
 311 {
 312         struct src_rsc_ctrl_blk *ctl = blk;
 313
 314         set_field(&ctl->sa, SRCSA_SA, sa);
 315         ctl->dirty.bf.sa = 1;
 316         return 0;
 317 }
 318
 319 static int src_set_la(void *blk, unsigned int la)
 320 {
 321         struct src_rsc_ctrl_blk *ctl = blk;
 322
 323         set_field(&ctl->la, SRCLA_LA, la);
 324         ctl->dirty.bf.la = 1;
 325         return 0;
 326 }
 327
 328 static int src_set_pitch(void *blk, unsigned int pitch)
 329 {
 330         struct src_rsc_ctrl_blk *ctl = blk;
 331
 332         set_field(&ctl->mpr, MPRLH_PITCH, pitch);
 333         ctl->dirty.bf.mpr = 1;
 334         return 0;
 335 }
 336
 337 static int src_set_clear_zbufs(void *blk, unsigned int clear)
 338 {
 339         ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
 340         return 0;
 341 }
 342
 343 static int src_set_dirty(void *blk, unsigned int flags)
 344 {
 345         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
 346         return 0;
 347 }
 348
 349 static int src_set_dirty_all(void *blk)
 350 {
 351         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
 352         return 0;
 353 }
 354
 355 #define AR_SLOT_SIZE            4096
 356 #define AR_SLOT_BLOCK_SIZE      16
 357 #define AR_PTS_PITCH            6
 358 #define AR_PARAM_SRC_OFFSET     0x60
 359
 360 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
 361 {
 362         return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
 363                         - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
 364
 365 }
 366
 367 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
 368 {
 369         struct src_rsc_ctrl_blk *ctl = blk;
 370         int i;
 371
 372         if (ctl->dirty.bf.czbfs) {
 373                 /* Clear Z-Buffer registers */
 374                 for (i = 0; i < 8; i++)
 375                         hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
 376
 377                 for (i = 0; i < 4; i++)
 378                         hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
 379
 380                 for (i = 0; i < 8; i++)
 381                         hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
 382
 383                 ctl->dirty.bf.czbfs = 0;
 384         }
 385         if (ctl->dirty.bf.mpr) {
 386                 /* Take the parameter mixer resource in the same group as that
 387                  * the idx src is in for simplicity. Unlike src, all conjugate
 388                  * parameter mixer resources must be programmed for
 389                  * corresponding conjugate src resources. */
 390                 unsigned int pm_idx = src_param_pitch_mixer(idx);
 391                 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
 392                 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
 393                 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
 394                 ctl->dirty.bf.mpr = 0;
 395         }
 396         if (ctl->dirty.bf.sa) {
 397                 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
 398                 ctl->dirty.bf.sa = 0;
 399         }
 400         if (ctl->dirty.bf.la) {
 401                 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
 402                 ctl->dirty.bf.la = 0;
 403         }
 404         if (ctl->dirty.bf.ca) {
 405                 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
 406                 ctl->dirty.bf.ca = 0;
 407         }
 408
 409         /* Write srccf register */
 410         hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
 411
 412         if (ctl->dirty.bf.ccr) {
 413                 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
 414                 ctl->dirty.bf.ccr = 0;
 415         }
 416         if (ctl->dirty.bf.ctl) {
 417                 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
 418                 ctl->dirty.bf.ctl = 0;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
 425 {
 426         struct src_rsc_ctrl_blk *ctl = blk;
 427
 428         ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
 429         ctl->dirty.bf.ca = 0;
 430
 431         return get_field(ctl->ca, SRCCA_CA);
 432 }
 433
 434 static unsigned int src_get_dirty(void *blk)
 435 {
 436         return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
 437 }
 438
 439 static unsigned int src_dirty_conj_mask(void)
 440 {
 441         return 0x20;
 442 }
 443
 444 static int src_mgr_enbs_src(void *blk, unsigned int idx)
 445 {
 446         ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
 447         ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
 448         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
 449         return 0;
 450 }
 451
 452 static int src_mgr_enb_src(void *blk, unsigned int idx)
 453 {
 454         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
 455         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
 456         return 0;
 457 }
 458
 459 static int src_mgr_dsb_src(void *blk, unsigned int idx)
 460 {
 461         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
 462         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
 463         return 0;
 464 }
 465
 466 static int src_mgr_commit_write(struct hw *hw, void *blk)
 467 {
 468         struct src_mgr_ctrl_blk *ctl = blk;
 469         int i;
 470         unsigned int ret;
 471
 472         if (ctl->dirty.bf.enbsa) {
 473                 do {
 474                         ret = hw_read_20kx(hw, SRC_ENBSTAT);
 475                 } while (ret & 0x1);
 476                 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
 477                 ctl->dirty.bf.enbsa = 0;
 478         }
 479         for (i = 0; i < 8; i++) {
 480                 if ((ctl->dirty.data & (0x1 << i))) {
 481                         hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
 482                         ctl->dirty.data &= ~(0x1 << i);
 483                 }
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int src_mgr_get_ctrl_blk(void **rblk)
 490 {
 491         struct src_mgr_ctrl_blk *blk;
 492
 493         *rblk = NULL;
 494         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 495         if (NULL == blk)
 496                 return -ENOMEM;
 497
 498         *rblk = blk;
 499
 500         return 0;
 501 }
 502
 503 static int src_mgr_put_ctrl_blk(void *blk)
 504 {
 505         kfree(blk);
 506
 507         return 0;
 508 }
 509
 510 static int srcimp_mgr_get_ctrl_blk(void **rblk)
 511 {
 512         struct srcimp_mgr_ctrl_blk *blk;
 513
 514         *rblk = NULL;
 515         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 516         if (NULL == blk)
 517                 return -ENOMEM;
 518
 519         *rblk = blk;
 520
 521         return 0;
 522 }
 523
 524 static int srcimp_mgr_put_ctrl_blk(void *blk)
 525 {
 526         kfree(blk);
 527
 528         return 0;
 529 }
 530
 531 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
 532 {
 533         struct srcimp_mgr_ctrl_blk *ctl = blk;
 534
 535         set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
 536         ctl->dirty.bf.srcimap = 1;
 537         return 0;
 538 }
 539
 540 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
 541 {
 542         struct srcimp_mgr_ctrl_blk *ctl = blk;
 543
 544         set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
 545         ctl->dirty.bf.srcimap = 1;
 546         return 0;
 547 }
 548
 549 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
 550 {
 551         struct srcimp_mgr_ctrl_blk *ctl = blk;
 552
 553         set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
 554         ctl->dirty.bf.srcimap = 1;
 555         return 0;
 556 }
 557
 558 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
 559 {
 560         ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
 561         ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
 562         return 0;
 563 }
 564
 565 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
 566 {
 567         struct srcimp_mgr_ctrl_blk *ctl = blk;
 568
 569         if (ctl->dirty.bf.srcimap) {
 570                 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
 571                                                 ctl->srcimap.srcaim);
 572                 ctl->dirty.bf.srcimap = 0;
 573         }
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * AMIXER control block definitions.
 580  */
 581
 582 #define AMOPLO_M        0x00000003
 583 #define AMOPLO_IV       0x00000004
 584 #define AMOPLO_X        0x0003FFF0
 585 #define AMOPLO_Y        0xFFFC0000
 586
 587 #define AMOPHI_SADR     0x000000FF
 588 #define AMOPHI_SE       0x80000000
 589
 590 /* AMIXER resource register dirty flags */
 591 union amixer_dirty {
 592         struct {
 593                 u16 amoplo:1;
 594                 u16 amophi:1;
 595                 u16 rsv:14;
 596         } bf;
 597         u16 data;
 598 };
 599
 600 /* AMIXER resource control block */
 601 struct amixer_rsc_ctrl_blk {
 602         unsigned int            amoplo;
 603         unsigned int            amophi;
 604         union amixer_dirty      dirty;
 605 };
 606
 607 static int amixer_set_mode(void *blk, unsigned int mode)
 608 {
 609         struct amixer_rsc_ctrl_blk *ctl = blk;
 610
 611         set_field(&ctl->amoplo, AMOPLO_M, mode);
 612         ctl->dirty.bf.amoplo = 1;
 613         return 0;
 614 }
 615
 616 static int amixer_set_iv(void *blk, unsigned int iv)
 617 {
 618         struct amixer_rsc_ctrl_blk *ctl = blk;
 619
 620         set_field(&ctl->amoplo, AMOPLO_IV, iv);
 621         ctl->dirty.bf.amoplo = 1;
 622         return 0;
 623 }
 624
 625 static int amixer_set_x(void *blk, unsigned int x)
 626 {
 627         struct amixer_rsc_ctrl_blk *ctl = blk;
 628
 629         set_field(&ctl->amoplo, AMOPLO_X, x);
 630         ctl->dirty.bf.amoplo = 1;
 631         return 0;
 632 }
 633
 634 static int amixer_set_y(void *blk, unsigned int y)
 635 {
 636         struct amixer_rsc_ctrl_blk *ctl = blk;
 637
 638         set_field(&ctl->amoplo, AMOPLO_Y, y);
 639         ctl->dirty.bf.amoplo = 1;
 640         return 0;
 641 }
 642
 643 static int amixer_set_sadr(void *blk, unsigned int sadr)
 644 {
 645         struct amixer_rsc_ctrl_blk *ctl = blk;
 646
 647         set_field(&ctl->amophi, AMOPHI_SADR, sadr);
 648         ctl->dirty.bf.amophi = 1;
 649         return 0;
 650 }
 651
 652 static int amixer_set_se(void *blk, unsigned int se)
 653 {
 654         struct amixer_rsc_ctrl_blk *ctl = blk;
 655
 656         set_field(&ctl->amophi, AMOPHI_SE, se);
 657         ctl->dirty.bf.amophi = 1;
 658         return 0;
 659 }
 660
 661 static int amixer_set_dirty(void *blk, unsigned int flags)
 662 {
 663         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
 664         return 0;
 665 }
 666
 667 static int amixer_set_dirty_all(void *blk)
 668 {
 669         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
 670         return 0;
 671 }
 672
 673 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
 674 {
 675         struct amixer_rsc_ctrl_blk *ctl = blk;
 676
 677         if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
 678                 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
 679                 ctl->dirty.bf.amoplo = 0;
 680                 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
 681                 ctl->dirty.bf.amophi = 0;
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int amixer_get_y(void *blk)
 688 {
 689         struct amixer_rsc_ctrl_blk *ctl = blk;
 690
 691         return get_field(ctl->amoplo, AMOPLO_Y);
 692 }
 693
 694 static unsigned int amixer_get_dirty(void *blk)
 695 {
 696         return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
 697 }
 698
 699 static int amixer_rsc_get_ctrl_blk(void **rblk)
 700 {
 701         struct amixer_rsc_ctrl_blk *blk;
 702
 703         *rblk = NULL;
 704         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 705         if (NULL == blk)
 706                 return -ENOMEM;
 707
 708         *rblk = blk;
 709
 710         return 0;
 711 }
 712
 713 static int amixer_rsc_put_ctrl_blk(void *blk)
 714 {
 715         kfree(blk);
 716
 717         return 0;
 718 }
 719
 720 static int amixer_mgr_get_ctrl_blk(void **rblk)
 721 {
 722         *rblk = NULL;
 723
 724         return 0;
 725 }
 726
 727 static int amixer_mgr_put_ctrl_blk(void *blk)
 728 {
 729         return 0;
 730 }
 731
 732 /*
 733  * DAIO control block definitions.
 734  */
 735
 736 /* Receiver Sample Rate Tracker Control register */
 737 #define SRTCTL_SRCO     0x000000FF
 738 #define SRTCTL_SRCM     0x0000FF00
 739 #define SRTCTL_RSR      0x00030000
 740 #define SRTCTL_DRAT     0x00300000
 741 #define SRTCTL_EC       0x01000000
 742 #define SRTCTL_ET       0x10000000
 743
 744 /* DAIO Receiver register dirty flags */
 745 union dai_dirty {
 746         struct {
 747                 u16 srt:1;
 748                 u16 rsv:15;
 749         } bf;
 750         u16 data;
 751 };
 752
 753 /* DAIO Receiver control block */
 754 struct dai_ctrl_blk {
 755         unsigned int    srt;
 756         union dai_dirty dirty;
 757 };
 758
 759 /* Audio Input Mapper RAM */
 760 #define AIM_ARC         0x00000FFF
 761 #define AIM_NXT         0x007F0000
 762
 763 struct daoimap {
 764         unsigned int aim;
 765         unsigned int idx;
 766 };
 767
 768 /* Audio Transmitter Control and Status register */
 769 #define ATXCTL_EN       0x00000001
 770 #define ATXCTL_MODE     0x00000010
 771 #define ATXCTL_CD       0x00000020
 772 #define ATXCTL_RAW      0x00000100
 773 #define ATXCTL_MT       0x00000200
 774 #define ATXCTL_NUC      0x00003000
 775 #define ATXCTL_BEN      0x00010000
 776 #define ATXCTL_BMUX     0x00700000
 777 #define ATXCTL_B24      0x01000000
 778 #define ATXCTL_CPF      0x02000000
 779 #define ATXCTL_RIV      0x10000000
 780 #define ATXCTL_LIV      0x20000000
 781 #define ATXCTL_RSAT     0x40000000
 782 #define ATXCTL_LSAT     0x80000000
 783
 784 /* XDIF Transmitter register dirty flags */
 785 union dao_dirty {
 786         struct {
 787                 u16 atxcsl:1;
 788                 u16 rsv:15;
 789         } bf;
 790         u16 data;
 791 };
 792
 793 /* XDIF Transmitter control block */
 794 struct dao_ctrl_blk {
 795         /* XDIF Transmitter Channel Status Low Register */
 796         unsigned int    atxcsl;
 797         union dao_dirty dirty;
 798 };
 799
 800 /* Audio Receiver Control register */
 801 #define ARXCTL_EN       0x00000001
 802
 803 /* DAIO manager register dirty flags */
 804 union daio_mgr_dirty {
 805         struct {
 806                 u32 atxctl:8;
 807                 u32 arxctl:8;
 808                 u32 daoimap:1;
 809                 u32 rsv:15;
 810         } bf;
 811         u32 data;
 812 };
 813
 814 /* DAIO manager control block */
 815 struct daio_mgr_ctrl_blk {
 816         struct daoimap          daoimap;
 817         unsigned int            txctl[8];
 818         unsigned int            rxctl[8];
 819         union daio_mgr_dirty    dirty;
 820 };
 821
 822 static int dai_srt_set_srco(void *blk, unsigned int src)
 823 {
 824         struct dai_ctrl_blk *ctl = blk;
 825
 826         set_field(&ctl->srt, SRTCTL_SRCO, src);
 827         ctl->dirty.bf.srt = 1;
 828         return 0;
 829 }
 830
 831 static int dai_srt_set_srcm(void *blk, unsigned int src)
 832 {
 833         struct dai_ctrl_blk *ctl = blk;
 834
 835         set_field(&ctl->srt, SRTCTL_SRCM, src);
 836         ctl->dirty.bf.srt = 1;
 837         return 0;
 838 }
 839
 840 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
 841 {
 842         struct dai_ctrl_blk *ctl = blk;
 843
 844         set_field(&ctl->srt, SRTCTL_RSR, rsr);
 845         ctl->dirty.bf.srt = 1;
 846         return 0;
 847 }
 848
 849 static int dai_srt_set_drat(void *blk, unsigned int drat)
 850 {
 851         struct dai_ctrl_blk *ctl = blk;
 852
 853         set_field(&ctl->srt, SRTCTL_DRAT, drat);
 854         ctl->dirty.bf.srt = 1;
 855         return 0;
 856 }
 857
 858 static int dai_srt_set_ec(void *blk, unsigned int ec)
 859 {
 860         struct dai_ctrl_blk *ctl = blk;
 861
 862         set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
 863         ctl->dirty.bf.srt = 1;
 864         return 0;
 865 }
 866
 867 static int dai_srt_set_et(void *blk, unsigned int et)
 868 {
 869         struct dai_ctrl_blk *ctl = blk;
 870
 871         set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
 872         ctl->dirty.bf.srt = 1;
 873         return 0;
 874 }
 875
 876 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
 877 {
 878         struct dai_ctrl_blk *ctl = blk;
 879
 880         if (ctl->dirty.bf.srt) {
 881                 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
 882                 ctl->dirty.bf.srt = 0;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int dai_get_ctrl_blk(void **rblk)
 889 {
 890         struct dai_ctrl_blk *blk;
 891
 892         *rblk = NULL;
 893         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 894         if (NULL == blk)
 895                 return -ENOMEM;
 896
 897         *rblk = blk;
 898
 899         return 0;
 900 }
 901
 902 static int dai_put_ctrl_blk(void *blk)
 903 {
 904         kfree(blk);
 905
 906         return 0;
 907 }
 908
 909 static int dao_set_spos(void *blk, unsigned int spos)
 910 {
 911         ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
 912         ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
 913         return 0;
 914 }
 915
 916 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
 917 {
 918         struct dao_ctrl_blk *ctl = blk;
 919
 920         if (ctl->dirty.bf.atxcsl) {
 921                 if (idx < 4) {
 922                         /* S/PDIF SPOSx */
 923                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
 924                                                         ctl->atxcsl);
 925                 }
 926                 ctl->dirty.bf.atxcsl = 0;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int dao_get_spos(void *blk, unsigned int *spos)
 933 {
 934         *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
 935         return 0;
 936 }
 937
 938 static int dao_get_ctrl_blk(void **rblk)
 939 {
 940         struct dao_ctrl_blk *blk;
 941
 942         *rblk = NULL;
 943         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
 944         if (NULL == blk)
 945                 return -ENOMEM;
 946
 947         *rblk = blk;
 948
 949         return 0;
 950 }
 951
 952 static int dao_put_ctrl_blk(void *blk)
 953 {
 954         kfree(blk);
 955
 956         return 0;
 957 }
 958
 959 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
 960 {
 961         struct daio_mgr_ctrl_blk *ctl = blk;
 962
 963         set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
 964         ctl->dirty.bf.arxctl |= (0x1 << idx);
 965         return 0;
 966 }
 967
 968 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
 969 {
 970         struct daio_mgr_ctrl_blk *ctl = blk;
 971
 972         set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
 973
 974         ctl->dirty.bf.arxctl |= (0x1 << idx);
 975         return 0;
 976 }
 977
 978 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
 979 {
 980         struct daio_mgr_ctrl_blk *ctl = blk;
 981
 982         set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
 983         ctl->dirty.bf.atxctl |= (0x1 << idx);
 984         return 0;
 985 }
 986
 987 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
 988 {
 989         struct daio_mgr_ctrl_blk *ctl = blk;
 990
 991         set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
 992         ctl->dirty.bf.atxctl |= (0x1 << idx);
 993         return 0;
 994 }
 995
 996 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
 997 {
 998         struct daio_mgr_ctrl_blk *ctl = blk;
 999
1000         if (idx < 4) {
1001                 /* S/PDIF output */
1002                 switch ((conf & 0x7)) {
1003                 case 1:
1004                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
1005                         break;
1006                 case 2:
1007                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1008                         break;
1009                 case 4:
1010                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1011                         break;
1012                 case 8:
1013                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1014                         break;
1015                 default:
1016                         break;
1017                 }
1018                 /* CDIF */
1019                 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1020                 /* Non-audio */
1021                 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1022                 /* Non-audio */
1023                 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1024                 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1025                           ((conf >> 3) & 0x1) ? 0 : 0);
1026                 ctl->dirty.bf.atxctl |= (0x1 << idx);
1027         } else {
1028                 /* I2S output */
1029                 /*idx %= 4; */
1030         }
1031         return 0;
1032 }
1033
1034 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1035 {
1036         struct daio_mgr_ctrl_blk *ctl = blk;
1037
1038         set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1039         ctl->dirty.bf.daoimap = 1;
1040         return 0;
1041 }
1042
1043 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1044 {
1045         struct daio_mgr_ctrl_blk *ctl = blk;
1046
1047         set_field(&ctl->daoimap.aim, AIM_NXT, next);
1048         ctl->dirty.bf.daoimap = 1;
1049         return 0;
1050 }
1051
1052 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1053 {
1054         ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1055         ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1056         return 0;
1057 }
1058
1059 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1060 {
1061         struct daio_mgr_ctrl_blk *ctl = blk;
1062         unsigned int data;
1063         int i;
1064
1065         for (i = 0; i < 8; i++) {
1066                 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1067                         data = ctl->txctl[i];
1068                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1069                         ctl->dirty.bf.atxctl &= ~(0x1 << i);
1070                         mdelay(1);
1071                 }
1072                 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1073                         data = ctl->rxctl[i];
1074                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1075                         ctl->dirty.bf.arxctl &= ~(0x1 << i);
1076                         mdelay(1);
1077                 }
1078         }
1079         if (ctl->dirty.bf.daoimap) {
1080                 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1081                                                 ctl->daoimap.aim);
1082                 ctl->dirty.bf.daoimap = 0;
1083         }
1084
1085         return 0;
1086 }
1087
1088 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1089 {
1090         struct daio_mgr_ctrl_blk *blk;
1091         int i;
1092
1093         *rblk = NULL;
1094         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1095         if (NULL == blk)
1096                 return -ENOMEM;
1097
1098         for (i = 0; i < 8; i++) {
1099                 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1100                 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1101         }
1102
1103         *rblk = blk;
1104
1105         return 0;
1106 }
1107
1108 static int daio_mgr_put_ctrl_blk(void *blk)
1109 {
1110         kfree(blk);
1111
1112         return 0;
1113 }
1114
1115 /* Card hardware initialization block */
1116 struct dac_conf {
1117         unsigned int msr; /* master sample rate in rsrs */
1118 };
1119
1120 struct adc_conf {
1121         unsigned int msr;       /* master sample rate in rsrs */
1122         unsigned char input;    /* the input source of ADC */
1123         unsigned char mic20db;  /* boost mic by 20db if input is microphone */
1124 };
1125
1126 struct daio_conf {
1127         unsigned int msr; /* master sample rate in rsrs */
1128 };
1129
1130 struct trn_conf {
1131         unsigned long vm_pgt_phys;
1132 };
1133
1134 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1135 {
1136         u32 data;
1137         int i;
1138
1139         /* Program I2S with proper sample rate and enable the correct I2S
1140          * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1141         if (1 == info->msr) {
1142                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1143                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1144                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1145         } else if (2 == info->msr) {
1146                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1147                 /* Specify all playing 96khz
1148                  * EA [0]       - Enabled
1149                  * RTA [4:5]    - 96kHz
1150                  * EB [8]       - Enabled
1151                  * RTB [12:13]  - 96kHz
1152                  * EC [16]      - Enabled
1153                  * RTC [20:21]  - 96kHz
1154                  * ED [24]      - Enabled
1155                  * RTD [28:29]  - 96kHz */
1156                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1157                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1158         } else {
1159                 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1160                 return -EINVAL;
1161         }
1162
1163         for (i = 0; i < 8; i++) {
1164                 if (i <= 3) {
1165                         /* 1st 3 channels are SPDIFs (SB0960) */
1166                         if (i == 3)
1167                                 data = 0x1001001;
1168                         else
1169                                 data = 0x1000001;
1170
1171                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1172                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1173
1174                         /* Initialize the SPDIF Out Channel status registers.
1175                          * The value specified here is based on the typical
1176                          * values provided in the specification, namely: Clock
1177                          * Accuracy of 1000ppm, Sample Rate of 48KHz,
1178                          * unspecified source number, Generation status = 1,
1179                          * Category code = 0x12 (Digital Signal Mixer),
1180                          * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1181                          * (indicating that we're transmitting digital audio,
1182                          * and the Professional Use bit is 0. */
1183
1184                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1185                                         0x02109204); /* Default to 48kHz */
1186
1187                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1188                 } else {
1189                         /* Next 5 channels are I2S (SB0960) */
1190                         data = 0x11;
1191                         hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1192                         if (2 == info->msr) {
1193                                 /* Four channels per sample period */
1194                                 data |= 0x1000;
1195                         }
1196                         hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1197                 }
1198         }
1199
1200         return 0;
1201 }
1202
1203 /* TRANSPORT operations */
1204 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1205 {
1206         u32 vmctl, data;
1207         u32 ptp_phys_low, ptp_phys_high;
1208         int i;
1209
1210         /* Set up device page table */
1211         if ((~0UL) == info->vm_pgt_phys) {
1212                 printk(KERN_ALERT "ctxfi: "
1213                        "Wrong device page table page address!!!\n");
1214                 return -1;
1215         }
1216
1217         vmctl = 0x80000C0F;  /* 32-bit, 4k-size page */
1218         ptp_phys_low = (u32)info->vm_pgt_phys;
1219         ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1220         if (sizeof(void *) == 8) /* 64bit address */
1221                 vmctl |= (3 << 8);
1222         /* Write page table physical address to all PTPAL registers */
1223         for (i = 0; i < 64; i++) {
1224                 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1225                 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1226         }
1227         /* Enable virtual memory transfer */
1228         hw_write_20kx(hw, VMEM_CTL, vmctl);
1229         /* Enable transport bus master and queueing of request */
1230         hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1231         hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1232         /* Enable transport ring */
1233         data = hw_read_20kx(hw, TRANSPORT_ENB);
1234         hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1235
1236         return 0;
1237 }
1238
1239 /* Card initialization */
1240 #define GCTL_AIE        0x00000001
1241 #define GCTL_UAA        0x00000002
1242 #define GCTL_DPC        0x00000004
1243 #define GCTL_DBP        0x00000008
1244 #define GCTL_ABP        0x00000010
1245 #define GCTL_TBP        0x00000020
1246 #define GCTL_SBP        0x00000040
1247 #define GCTL_FBP        0x00000080
1248 #define GCTL_ME         0x00000100
1249 #define GCTL_AID        0x00001000
1250
1251 #define PLLCTL_SRC      0x00000007
1252 #define PLLCTL_SPE      0x00000008
1253 #define PLLCTL_RD       0x000000F0
1254 #define PLLCTL_FD       0x0001FF00
1255 #define PLLCTL_OD       0x00060000
1256 #define PLLCTL_B        0x00080000
1257 #define PLLCTL_AS       0x00100000
1258 #define PLLCTL_LF       0x03E00000
1259 #define PLLCTL_SPS      0x1C000000
1260 #define PLLCTL_AD       0x60000000
1261
1262 #define PLLSTAT_CCS     0x00000007
1263 #define PLLSTAT_SPL     0x00000008
1264 #define PLLSTAT_CRD     0x000000F0
1265 #define PLLSTAT_CFD     0x0001FF00
1266 #define PLLSTAT_SL      0x00020000
1267 #define PLLSTAT_FAS     0x00040000
1268 #define PLLSTAT_B       0x00080000
1269 #define PLLSTAT_PD      0x00100000
1270 #define PLLSTAT_OCA     0x00200000
1271 #define PLLSTAT_NCA     0x00400000
1272
1273 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1274 {
1275         unsigned int pllenb;
1276         unsigned int pllctl;
1277         unsigned int pllstat;
1278         int i;
1279
1280         pllenb = 0xB;
1281         hw_write_20kx(hw, PLL_ENB, pllenb);
1282         pllctl = 0x20D00000;
1283         set_field(&pllctl, PLLCTL_FD, 16 - 4);
1284         hw_write_20kx(hw, PLL_CTL, pllctl);
1285         mdelay(40);
1286         pllctl = hw_read_20kx(hw, PLL_CTL);
1287         set_field(&pllctl, PLLCTL_B, 0);
1288         if (48000 == rsr) {
1289                 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1290                 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1291         } else { /* 44100 */
1292                 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1293                 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1294         }
1295         hw_write_20kx(hw, PLL_CTL, pllctl);
1296         mdelay(40);
1297         for (i = 0; i < 1000; i++) {
1298                 pllstat = hw_read_20kx(hw, PLL_STAT);
1299                 if (get_field(pllstat, PLLSTAT_PD))
1300                         continue;
1301
1302                 if (get_field(pllstat, PLLSTAT_B) !=
1303                                         get_field(pllctl, PLLCTL_B))
1304                         continue;
1305
1306                 if (get_field(pllstat, PLLSTAT_CCS) !=
1307                                         get_field(pllctl, PLLCTL_SRC))
1308                         continue;
1309
1310                 if (get_field(pllstat, PLLSTAT_CRD) !=
1311                                         get_field(pllctl, PLLCTL_RD))
1312                         continue;
1313
1314                 if (get_field(pllstat, PLLSTAT_CFD) !=
1315                                         get_field(pllctl, PLLCTL_FD))
1316                         continue;
1317
1318                 break;
1319         }
1320         if (i >= 1000) {
1321                 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1322                 return -EBUSY;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int hw_auto_init(struct hw *hw)
1329 {
1330         unsigned int gctl;
1331         int i;
1332
1333         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1334         set_field(&gctl, GCTL_AIE, 0);
1335         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1336         set_field(&gctl, GCTL_AIE, 1);
1337         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1338         mdelay(10);
1339         for (i = 0; i < 400000; i++) {
1340                 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1341                 if (get_field(gctl, GCTL_AID))
1342                         break;
1343         }
1344         if (!get_field(gctl, GCTL_AID)) {
1345                 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1346                 return -EBUSY;
1347         }
1348
1349         return 0;
1350 }
1351
1352 /* DAC operations */
1353
1354 #define CS4382_MC1              0x1
1355 #define CS4382_MC2              0x2
1356 #define CS4382_MC3              0x3
1357 #define CS4382_FC               0x4
1358 #define CS4382_IC               0x5
1359 #define CS4382_XC1              0x6
1360 #define CS4382_VCA1             0x7
1361 #define CS4382_VCB1             0x8
1362 #define CS4382_XC2              0x9
1363 #define CS4382_VCA2             0xA
1364 #define CS4382_VCB2             0xB
1365 #define CS4382_XC3              0xC
1366 #define CS4382_VCA3             0xD
1367 #define CS4382_VCB3             0xE
1368 #define CS4382_XC4              0xF
1369 #define CS4382_VCA4             0x10
1370 #define CS4382_VCB4             0x11
1371 #define CS4382_CREV             0x12
1372
1373 /* I2C status */
1374 #define STATE_LOCKED            0x00
1375 #define STATE_UNLOCKED          0xAA
1376 #define DATA_READY              0x800000    /* Used with I2C_IF_STATUS */
1377 #define DATA_ABORT              0x10000     /* Used with I2C_IF_STATUS */
1378
1379 #define I2C_STATUS_DCM  0x00000001
1380 #define I2C_STATUS_BC   0x00000006
1381 #define I2C_STATUS_APD  0x00000008
1382 #define I2C_STATUS_AB   0x00010000
1383 #define I2C_STATUS_DR   0x00800000
1384
1385 #define I2C_ADDRESS_PTAD        0x0000FFFF
1386 #define I2C_ADDRESS_SLAD        0x007F0000
1387
1388 struct regs_cs4382 {
1389         u32 mode_control_1;
1390         u32 mode_control_2;
1391         u32 mode_control_3;
1392
1393         u32 filter_control;
1394         u32 invert_control;
1395
1396         u32 mix_control_P1;
1397         u32 vol_control_A1;
1398         u32 vol_control_B1;
1399
1400         u32 mix_control_P2;
1401         u32 vol_control_A2;
1402         u32 vol_control_B2;
1403
1404         u32 mix_control_P3;
1405         u32 vol_control_A3;
1406         u32 vol_control_B3;
1407
1408         u32 mix_control_P4;
1409         u32 vol_control_A4;
1410         u32 vol_control_B4;
1411 };
1412
1413 static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1414 {
1415         u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] =  {0xB3, 0xD4};
1416
1417         /* Send keys for forced BIOS mode */
1418         hw_write_20kx(hw, I2C_IF_WLOCK,
1419                         UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1420         hw_write_20kx(hw, I2C_IF_WLOCK,
1421                         UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1422         /* Check whether the chip is unlocked */
1423         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1424                 return 0;
1425
1426         return -1;
1427 }
1428
1429 static int hw20k2_i2c_lock_chip(struct hw *hw)
1430 {
1431         /* Write twice */
1432         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1433         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1434         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1435                 return 0;
1436
1437         return -1;
1438 }
1439
1440 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1441 {
1442         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1443         int err;
1444         unsigned int i2c_status;
1445         unsigned int i2c_addr;
1446
1447         err = hw20k2_i2c_unlock_full_access(hw);
1448         if (err < 0)
1449                 return err;
1450
1451         hw20k2->addr_size = addr_size;
1452         hw20k2->data_size = data_size;
1453         hw20k2->dev_id = dev_id;
1454
1455         i2c_addr = 0;
1456         set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1457
1458         hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1459
1460         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1461
1462         set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1463
1464         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1465
1466         return 0;
1467 }
1468
1469 static int hw20k2_i2c_uninit(struct hw *hw)
1470 {
1471         unsigned int i2c_status;
1472         unsigned int i2c_addr;
1473
1474         i2c_addr = 0;
1475         set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1476
1477         hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1478
1479         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1480
1481         set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1482
1483         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1484
1485         return hw20k2_i2c_lock_chip(hw);
1486 }
1487
1488 static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1489 {
1490         int i = 0x400000;
1491         unsigned int ret;
1492
1493         do {
1494                 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1495         } while ((!(ret & DATA_READY)) && --i);
1496
1497         return i;
1498 }
1499
1500 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1501 {
1502         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1503         unsigned int i2c_status;
1504
1505         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1506         set_field(&i2c_status, I2C_STATUS_BC,
1507                   (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1508         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1509         if (!hw20k2_i2c_wait_data_ready(hw))
1510                 return -1;
1511
1512         hw_write_20kx(hw, I2C_IF_WDATA, addr);
1513         if (!hw20k2_i2c_wait_data_ready(hw))
1514                 return -1;
1515
1516         /* Force a read operation */
1517         hw_write_20kx(hw, I2C_IF_RDATA, 0);
1518         if (!hw20k2_i2c_wait_data_ready(hw))
1519                 return -1;
1520
1521         *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1522
1523         return 0;
1524 }
1525
1526 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1527 {
1528         struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1529         unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1530         unsigned int i2c_status;
1531
1532         i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1533
1534         set_field(&i2c_status, I2C_STATUS_BC,
1535                   (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1536                   0 : (hw20k2->addr_size + hw20k2->data_size));
1537
1538         hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1539         hw20k2_i2c_wait_data_ready(hw);
1540         /* Dummy write to trigger the write oprtation */
1541         hw_write_20kx(hw, I2C_IF_WDATA, 0);
1542         hw20k2_i2c_wait_data_ready(hw);
1543
1544         /* This is the real data */
1545         hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1546         hw20k2_i2c_wait_data_ready(hw);
1547
1548         return 0;
1549 }
1550
1551 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1552 {
1553         int err;
1554         u32 data;
1555         int i;
1556         struct regs_cs4382 cs_read = {0};
1557         struct regs_cs4382 cs_def = {
1558                                    0x00000001,  /* Mode Control 1 */
1559                                    0x00000000,  /* Mode Control 2 */
1560                                    0x00000084,  /* Mode Control 3 */
1561                                    0x00000000,  /* Filter Control */
1562                                    0x00000000,  /* Invert Control */
1563                                    0x00000024,  /* Mixing Control Pair 1 */
1564                                    0x00000000,  /* Vol Control A1 */
1565                                    0x00000000,  /* Vol Control B1 */
1566                                    0x00000024,  /* Mixing Control Pair 2 */
1567                                    0x00000000,  /* Vol Control A2 */
1568                                    0x00000000,  /* Vol Control B2 */
1569                                    0x00000024,  /* Mixing Control Pair 3 */
1570                                    0x00000000,  /* Vol Control A3 */
1571                                    0x00000000,  /* Vol Control B3 */
1572                                    0x00000024,  /* Mixing Control Pair 4 */
1573                                    0x00000000,  /* Vol Control A4 */
1574                                    0x00000000   /* Vol Control B4 */
1575                                  };
1576
1577         /* Set DAC reset bit as output */
1578         data = hw_read_20kx(hw, GPIO_CTRL);
1579         data |= 0x02;
1580         hw_write_20kx(hw, GPIO_CTRL, data);
1581
1582         err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1583         if (err < 0)
1584                 goto End;
1585
1586         for (i = 0; i < 2; i++) {
1587                 /* Reset DAC twice just in-case the chip
1588                  * didn't initialized properly */
1589                 data = hw_read_20kx(hw, GPIO_DATA);
1590                 /* GPIO data bit 1 */
1591                 data &= 0xFFFFFFFD;
1592                 hw_write_20kx(hw, GPIO_DATA, data);
1593                 mdelay(10);
1594                 data |= 0x2;
1595                 hw_write_20kx(hw, GPIO_DATA, data);
1596                 mdelay(50);
1597
1598                 /* Reset the 2nd time */
1599                 data &= 0xFFFFFFFD;
1600                 hw_write_20kx(hw, GPIO_DATA, data);
1601                 mdelay(10);
1602                 data |= 0x2;
1603                 hw_write_20kx(hw, GPIO_DATA, data);
1604                 mdelay(50);
1605
1606                 if (hw20k2_i2c_read(hw, CS4382_MC1,  &cs_read.mode_control_1))
1607                         continue;
1608
1609                 if (hw20k2_i2c_read(hw, CS4382_MC2,  &cs_read.mode_control_2))
1610                         continue;
1611
1612                 if (hw20k2_i2c_read(hw, CS4382_MC3,  &cs_read.mode_control_3))
1613                         continue;
1614
1615                 if (hw20k2_i2c_read(hw, CS4382_FC,   &cs_read.filter_control))
1616                         continue;
1617
1618                 if (hw20k2_i2c_read(hw, CS4382_IC,   &cs_read.invert_control))
1619                         continue;
1620
1621                 if (hw20k2_i2c_read(hw, CS4382_XC1,  &cs_read.mix_control_P1))
1622                         continue;
1623
1624                 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1625                         continue;
1626
1627                 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1628                         continue;
1629
1630                 if (hw20k2_i2c_read(hw, CS4382_XC2,  &cs_read.mix_control_P2))
1631                         continue;
1632
1633                 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1634                         continue;
1635
1636                 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1637                         continue;
1638
1639                 if (hw20k2_i2c_read(hw, CS4382_XC3,  &cs_read.mix_control_P3))
1640                         continue;
1641
1642                 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1643                         continue;
1644
1645                 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1646                         continue;
1647
1648                 if (hw20k2_i2c_read(hw, CS4382_XC4,  &cs_read.mix_control_P4))
1649                         continue;
1650
1651                 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1652                         continue;
1653
1654                 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1655                         continue;
1656
1657                 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1658                         continue;
1659                 else
1660                         break;
1661         }
1662
1663         if (i >= 2)
1664                 goto End;
1665
1666         /* Note: Every I2C write must have some delay.
1667          * This is not a requirement but the delay works here... */
1668         hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1669         hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1670         if (1 == info->msr) {
1671                 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1672                 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1673                 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1674                 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1675         } else if (2 == info->msr) {
1676                 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1677                 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1678                 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1679                 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1680         } else {
1681                 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1682                 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1683                 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1684                 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1685         }
1686
1687         return 0;
1688 End:
1689
1690         hw20k2_i2c_uninit(hw);
1691         return -1;
1692 }
1693
1694 /* ADC operations */
1695 #define MAKE_WM8775_ADDR(addr, data)    (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1696 #define MAKE_WM8775_DATA(data)  (u32)(data&0xFF)
1697
1698 #define WM8775_IC       0x0B
1699 #define WM8775_MMC      0x0C
1700 #define WM8775_AADCL    0x0E
1701 #define WM8775_AADCR    0x0F
1702 #define WM8775_ADCMC    0x15
1703 #define WM8775_RESET    0x17
1704
1705 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1706 {
1707         u32 data;
1708
1709         data = hw_read_20kx(hw, GPIO_DATA);
1710         switch (type) {
1711         case ADC_MICIN:
1712                 data = (data & (0x1 << 14)) ? 1 : 0;
1713                 break;
1714         case ADC_LINEIN:
1715                 data = (data & (0x1 << 14)) ? 0 : 1;
1716                 break;
1717         default:
1718                 data = 0;
1719         }
1720         return data;
1721 }
1722
1723 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1724 {
1725         u32 data;
1726
1727         data = hw_read_20kx(hw, GPIO_DATA);
1728         switch (type) {
1729         case ADC_MICIN:
1730                 data |= (0x1 << 14);
1731                 hw_write_20kx(hw, GPIO_DATA, data);
1732                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1733                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1734                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1735                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1736                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1737                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1738                 break;
1739         case ADC_LINEIN:
1740                 data &= ~(0x1 << 14);
1741                 hw_write_20kx(hw, GPIO_DATA, data);
1742                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1743                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1744                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1745                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1746                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1747                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1748                 break;
1749         default:
1750                 break;
1751         }
1752
1753         return 0;
1754 }
1755
1756 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1757 {
1758         int err;
1759         u32 mux = 2, data, ctl;
1760
1761         /*  Set ADC reset bit as output */
1762         data = hw_read_20kx(hw, GPIO_CTRL);
1763         data |= (0x1 << 15);
1764         hw_write_20kx(hw, GPIO_CTRL, data);
1765
1766         /* Initialize I2C */
1767         err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1768         if (err < 0) {
1769                 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1770                 goto error;
1771         }
1772
1773         /* Make ADC in normal operation */
1774         data = hw_read_20kx(hw, GPIO_DATA);
1775         data &= ~(0x1 << 15);
1776         mdelay(10);
1777         data |= (0x1 << 15);
1778         hw_write_20kx(hw, GPIO_DATA, data);
1779         mdelay(50);
1780
1781         /* Set the master mode (256fs) */
1782         if (1 == info->msr) {
1783                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1784                                                 MAKE_WM8775_DATA(0x02));
1785         } else if (2 == info->msr) {
1786                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1787                                                 MAKE_WM8775_DATA(0x0A));
1788         } else {
1789                 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1790                                   "rate (msr %d)!!!\n", info->msr);
1791                 err = -EINVAL;
1792                 goto error;
1793         }
1794
1795         /* Configure GPIO bit 14 change to line-in/mic-in */
1796         ctl = hw_read_20kx(hw, GPIO_CTRL);
1797         ctl |= 0x1 << 14;
1798         hw_write_20kx(hw, GPIO_CTRL, ctl);
1799
1800         /* Check using Mic-in or Line-in */
1801         data = hw_read_20kx(hw, GPIO_DATA);
1802
1803         if (mux == 1) {
1804                 /* Configures GPIO data to select Mic-in */
1805                 data |= 0x1 << 14;
1806                 hw_write_20kx(hw, GPIO_DATA, data);
1807
1808                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1809                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1810                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1811                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1812                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1813                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1814         } else if (mux == 2) {
1815                 /* Configures GPIO data to select Line-in */
1816                 data &= ~(0x1 << 14);
1817                 hw_write_20kx(hw, GPIO_DATA, data);
1818
1819                 /* Setup ADC */
1820                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1821                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1822                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1823                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1824                 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1825                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1826         } else {
1827                 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
1828                 err = -EINVAL;
1829                 goto error;
1830         }
1831
1832         return 0;
1833
1834 error:
1835         hw20k2_i2c_uninit(hw);
1836         return err;
1837 }
1838
1839 static int hw_have_digit_io_switch(struct hw *hw)
1840 {
1841         return 0;
1842 }
1843
1844 static int hw_card_start(struct hw *hw)
1845 {
1846         int err = 0;
1847         struct pci_dev *pci = hw->pci;
1848         unsigned int gctl;
1849
1850         err = pci_enable_device(pci);
1851         if (err < 0)
1852                 return err;
1853
1854         /* Set DMA transfer mask */
1855         if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
1856             pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
1857                 printk(KERN_ERR "ctxfi: architecture does not support PCI "
1858                 "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK);
1859                 err = -ENXIO;
1860                 goto error1;
1861         }
1862
1863         err = pci_request_regions(pci, "XFi");
1864         if (err < 0)
1865                 goto error1;
1866
1867         hw->io_base = pci_resource_start(hw->pci, 2);
1868         hw->mem_base = (unsigned long)ioremap(hw->io_base,
1869                                         pci_resource_len(hw->pci, 2));
1870         if (NULL == (void *)hw->mem_base) {
1871                 err = -ENOENT;
1872                 goto error2;
1873         }
1874
1875         /* Switch to 20k2 mode from UAA mode. */
1876         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1877         set_field(&gctl, GCTL_UAA, 0);
1878         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1879
1880         /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1881                                 atc->chip_details->nm_card, hw))) {
1882                 goto error3;
1883         }
1884         hw->irq = pci->irq;
1885         */
1886
1887         pci_set_master(pci);
1888
1889         return 0;
1890
1891 /*error3:
1892         iounmap((void *)hw->mem_base);
1893         hw->mem_base = (unsigned long)NULL;*/
1894 error2:
1895         pci_release_regions(pci);
1896         hw->io_base = 0;
1897 error1:
1898         pci_disable_device(pci);
1899         return err;
1900 }
1901
1902 static int hw_card_stop(struct hw *hw)
1903 {
1904         /* TODO: Disable interrupt and so on... */
1905         return 0;
1906 }
1907
1908 static int hw_card_shutdown(struct hw *hw)
1909 {
1910         if (hw->irq >= 0)
1911                 free_irq(hw->irq, hw);
1912
1913         hw->irq = -1;
1914
1915         if (NULL != ((void *)hw->mem_base))
1916                 iounmap((void *)hw->mem_base);
1917
1918         hw->mem_base = (unsigned long)NULL;
1919
1920         if (hw->io_base)
1921                 pci_release_regions(hw->pci);
1922
1923         hw->io_base = 0;
1924
1925         pci_disable_device(hw->pci);
1926
1927         return 0;
1928 }
1929
1930 static int hw_card_init(struct hw *hw, struct card_conf *info)
1931 {
1932         int err;
1933         unsigned int gctl;
1934         u32 data = 0;
1935         struct dac_conf dac_info = {0};
1936         struct adc_conf adc_info = {0};
1937         struct daio_conf daio_info = {0};
1938         struct trn_conf trn_info = {0};
1939
1940         /* Get PCI io port/memory base address and
1941          * do 20kx core switch if needed. */
1942         if (!hw->io_base) {
1943                 err = hw_card_start(hw);
1944                 if (err)
1945                         return err;
1946         }
1947
1948         /* PLL init */
1949         err = hw_pll_init(hw, info->rsr);
1950         if (err < 0)
1951                 return err;
1952
1953         /* kick off auto-init */
1954         err = hw_auto_init(hw);
1955         if (err < 0)
1956                 return err;
1957
1958         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1959         set_field(&gctl, GCTL_DBP, 1);
1960         set_field(&gctl, GCTL_TBP, 1);
1961         set_field(&gctl, GCTL_FBP, 1);
1962         set_field(&gctl, GCTL_DPC, 0);
1963         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1964
1965         /* Reset all global pending interrupts */
1966         hw_write_20kx(hw, INTERRUPT_GIE, 0);
1967         /* Reset all SRC pending interrupts */
1968         hw_write_20kx(hw, SRC_IP, 0);
1969
1970         /* TODO: detect the card ID and configure GPIO accordingly. */
1971         /* Configures GPIO (0xD802 0x98028) */
1972         /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1973         /* Configures GPIO (SB0880) */
1974         /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1975         hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1976
1977         /* Enable audio ring */
1978         hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1979
1980         trn_info.vm_pgt_phys = info->vm_pgt_phys;
1981         err = hw_trn_init(hw, &trn_info);
1982         if (err < 0)
1983                 return err;
1984
1985         daio_info.msr = info->msr;
1986         err = hw_daio_init(hw, &daio_info);
1987         if (err < 0)
1988                 return err;
1989
1990         dac_info.msr = info->msr;
1991         err = hw_dac_init(hw, &dac_info);
1992         if (err < 0)
1993                 return err;
1994
1995         adc_info.msr = info->msr;
1996         adc_info.input = ADC_LINEIN;
1997         adc_info.mic20db = 0;
1998         err = hw_adc_init(hw, &adc_info);
1999         if (err < 0)
2000                 return err;
2001
2002         data = hw_read_20kx(hw, SRC_MCTL);
2003         data |= 0x1; /* Enables input from the audio ring */
2004         hw_write_20kx(hw, SRC_MCTL, data);
2005
2006         return 0;
2007 }
2008
2009 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2010 {
2011         return readl((void *)(hw->mem_base + reg));
2012 }
2013
2014 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2015 {
2016         writel(data, (void *)(hw->mem_base + reg));
2017 }
2018
2019 static struct hw ct20k2_preset __devinitdata = {
2020         .irq = -1,
2021
2022         .card_init = hw_card_init,
2023         .card_stop = hw_card_stop,
2024         .pll_init = hw_pll_init,
2025         .is_adc_source_selected = hw_is_adc_input_selected,
2026         .select_adc_source = hw_adc_input_select,
2027         .have_digit_io_switch = hw_have_digit_io_switch,
2028
2029         .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2030         .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2031         .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2032         .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2033         .src_set_state = src_set_state,
2034         .src_set_bm = src_set_bm,
2035         .src_set_rsr = src_set_rsr,
2036         .src_set_sf = src_set_sf,
2037         .src_set_wr = src_set_wr,
2038         .src_set_pm = src_set_pm,
2039         .src_set_rom = src_set_rom,
2040         .src_set_vo = src_set_vo,
2041         .src_set_st = src_set_st,
2042         .src_set_ie = src_set_ie,
2043         .src_set_ilsz = src_set_ilsz,
2044         .src_set_bp = src_set_bp,
2045         .src_set_cisz = src_set_cisz,
2046         .src_set_ca = src_set_ca,
2047         .src_set_sa = src_set_sa,
2048         .src_set_la = src_set_la,
2049         .src_set_pitch = src_set_pitch,
2050         .src_set_dirty = src_set_dirty,
2051         .src_set_clear_zbufs = src_set_clear_zbufs,
2052         .src_set_dirty_all = src_set_dirty_all,
2053         .src_commit_write = src_commit_write,
2054         .src_get_ca = src_get_ca,
2055         .src_get_dirty = src_get_dirty,
2056         .src_dirty_conj_mask = src_dirty_conj_mask,
2057         .src_mgr_enbs_src = src_mgr_enbs_src,
2058         .src_mgr_enb_src = src_mgr_enb_src,
2059         .src_mgr_dsb_src = src_mgr_dsb_src,
2060         .src_mgr_commit_write = src_mgr_commit_write,
2061
2062         .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2063         .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2064         .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2065         .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2066         .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2067         .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2068         .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2069
2070         .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2071         .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2072         .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2073         .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2074         .amixer_set_mode = amixer_set_mode,
2075         .amixer_set_iv = amixer_set_iv,
2076         .amixer_set_x = amixer_set_x,
2077         .amixer_set_y = amixer_set_y,
2078         .amixer_set_sadr = amixer_set_sadr,
2079         .amixer_set_se = amixer_set_se,
2080         .amixer_set_dirty = amixer_set_dirty,
2081         .amixer_set_dirty_all = amixer_set_dirty_all,
2082         .amixer_commit_write = amixer_commit_write,
2083         .amixer_get_y = amixer_get_y,
2084         .amixer_get_dirty = amixer_get_dirty,
2085
2086         .dai_get_ctrl_blk = dai_get_ctrl_blk,
2087         .dai_put_ctrl_blk = dai_put_ctrl_blk,
2088         .dai_srt_set_srco = dai_srt_set_srco,
2089         .dai_srt_set_srcm = dai_srt_set_srcm,
2090         .dai_srt_set_rsr = dai_srt_set_rsr,
2091         .dai_srt_set_drat = dai_srt_set_drat,
2092         .dai_srt_set_ec = dai_srt_set_ec,
2093         .dai_srt_set_et = dai_srt_set_et,
2094         .dai_commit_write = dai_commit_write,
2095
2096         .dao_get_ctrl_blk = dao_get_ctrl_blk,
2097         .dao_put_ctrl_blk = dao_put_ctrl_blk,
2098         .dao_set_spos = dao_set_spos,
2099         .dao_commit_write = dao_commit_write,
2100         .dao_get_spos = dao_get_spos,
2101
2102         .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2103         .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2104         .daio_mgr_enb_dai = daio_mgr_enb_dai,
2105         .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2106         .daio_mgr_enb_dao = daio_mgr_enb_dao,
2107         .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2108         .daio_mgr_dao_init = daio_mgr_dao_init,
2109         .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2110         .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2111         .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2112         .daio_mgr_commit_write = daio_mgr_commit_write,
2113 };
2114
2115 int __devinit create_20k2_hw_obj(struct hw **rhw)
2116 {
2117         struct hw20k2 *hw20k2;
2118
2119         *rhw = NULL;
2120         hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2121         if (!hw20k2)
2122                 return -ENOMEM;
2123
2124         hw20k2->hw = ct20k2_preset;
2125         *rhw = &hw20k2->hw;
2126
2127         return 0;
2128 }
2129
2130 int destroy_20k2_hw_obj(struct hw *hw)
2131 {
2132         if (hw->io_base)
2133                 hw_card_shutdown(hw);
2134
2135         kfree(hw);
2136         return 0;
2137 }