sound/pci/cs4281.c

   1 /*
   2  *  Driver for Cirrus Logic CS4281 based PCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
   4  *
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <asm/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28 #include <linux/gameport.h>
  29 #include <linux/moduleparam.h>
  30 #include <sound/core.h>
  31 #include <sound/control.h>
  32 #include <sound/pcm.h>
  33 #include <sound/rawmidi.h>
  34 #include <sound/ac97_codec.h>
  35 #include <sound/tlv.h>
  36 #include <sound/opl3.h>
  37 #include <sound/initval.h>
  38
  39
  40 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
  42 MODULE_LICENSE("GPL");
  43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  44
  45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  47 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  48 static int dual_codec[SNDRV_CARDS];     /* dual codec */
  49
  50 module_param_array(index, int, NULL, 0444);
  51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  52 module_param_array(id, charp, NULL, 0444);
  53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  54 module_param_array(enable, bool, NULL, 0444);
  55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  56 module_param_array(dual_codec, bool, NULL, 0444);
  57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  58
  59 /*
  60  *  Direct registers
  61  */
  62
  63 #define CS4281_BA0_SIZE         0x1000
  64 #define CS4281_BA1_SIZE         0x10000
  65
  66 /*
  67  *  BA0 registers
  68  */
  69 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
  70 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
  71 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
  72 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
  73 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
  74 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
  75 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
  76 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
  77 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
  78 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
  79 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
  80 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
  81 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
  82
  83 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
  84 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
  85 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
  86 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
  87
  88 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
  89                                         /* Use same contants as for BA0_HISR */
  90
  91 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
  92
  93 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
  94 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
  95 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
  96 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
  97
  98 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
  99 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
 100 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
 101 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
 102 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
 103 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
 104
 105 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
 106 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
 107 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
 108 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
 109 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
 110 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
 111 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
 112 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
 113 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
 114 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 115 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
 116 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
 117 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
 118 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
 119 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
 120 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
 121 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
 122 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
 123 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
 124 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
 125 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
 126 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
 127 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
 128 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
 129
 130 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
 131 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
 132 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
 133 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
 134 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
 135 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
 136 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
 137 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
 138 #define BA0_DMR_MONO            (1<<17) /* Mono */
 139 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
 140 #define BA0_DMR_TYPE_DEMAND     (0<<6)
 141 #define BA0_DMR_TYPE_SINGLE     (1<<6)
 142 #define BA0_DMR_TYPE_BLOCK      (2<<6)
 143 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
 144 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
 145 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
 146 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
 147 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
 148 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
 149
 150 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
 151 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
 152 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
 153
 154 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
 155 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
 156 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
 157 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
 158
 159 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
 160 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
 161 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
 162 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
 163 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
 164 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
 165 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
 166
 167 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
 168 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
 169 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
 170 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
 171
 172 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
 173 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
 174 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
 175 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
 176 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
 177 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
 178 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
 179 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
 180 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
 181
 182 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
 183 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
 184 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
 185 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
 186
 187 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
 188 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
 189 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
 190 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
 191 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
 192 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
 193 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
 194 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
 195
 196 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
 197 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
 198
 199 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
 200 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
 201
 202 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
 203
 204 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
 205 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
 206 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
 207 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
 208 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
 209 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
 210 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
 211 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
 212 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
 213 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
 214
 215 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
 216 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
 217 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
 218 #define BA0_TMS                 0x03f8  /* Test Register */
 219 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
 220
 221 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
 222 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
 223 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
 224 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
 225 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
 226 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
 227 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
 228
 229 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
 230 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
 231
 232 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
 233 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
 234 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
 235 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
 236 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
 237 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
 238 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
 239 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
 240 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
 241 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
 242 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
 243 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
 244 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
 245
 246 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
 247 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
 248 #define BA0_SERC1_AC97          (1<<1)
 249 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
 250
 251 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
 252 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
 253 #define BA0_SERC2_AC97          (1<<1)
 254 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
 255
 256 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
 257
 258 #define BA0_ACCTL               0x0460  /* AC'97 Control */
 259 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
 260 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
 261 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
 262 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
 263 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
 264
 265 #define BA0_ACSTS               0x0464  /* AC'97 Status */
 266 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
 267 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
 268
 269 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
 270 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
 271
 272 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
 273 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
 274
 275 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
 276 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
 277
 278 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
 279 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
 280 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
 281 #define BA0_JSCTL               0x0484  /* Joystick control */
 282 #define BA0_JSC1                0x0488  /* Joystick control */
 283 #define BA0_JSC2                0x048c  /* Joystick control */
 284 #define BA0_JSIO                0x04a0
 285
 286 #define BA0_MIDCR               0x0490  /* MIDI Control */
 287 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
 288 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
 289 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
 290 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
 291 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
 292 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
 293
 294 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
 295
 296 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
 297 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
 298 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
 299 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
 300 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
 301
 302 #define BA0_MIDWP               0x0498  /* MIDI Write */
 303 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
 304
 305 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
 306 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
 307
 308 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
 309 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
 310
 311 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
 312 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
 313 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
 314 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
 315 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
 316 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
 317 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
 318 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
 319 #define BA0_FMDP                0x0734  /* FM Data Port */
 320 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
 321 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
 322
 323 #define BA0_SSPM                0x0740  /* Sound System Power Management */
 324 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
 325 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
 326 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
 327 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
 328 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
 329 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
 330
 331 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
 332 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
 333
 334 #define BA0_SSCR                0x074c  /* Sound System Control Register */
 335 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
 336 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
 337 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
 338 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
 339 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
 340 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
 341 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
 342 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
 343 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
 344
 345 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
 346 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
 347 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
 348 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
 349 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
 350 #define BA0_PASR                0x0768  /* playback sample rate */
 351 #define BA0_CASR                0x076C  /* capture sample rate */
 352
 353 /* Source Slot Numbers - Playback */
 354 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
 355 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
 356 #define SRCSLOT_PHONE_LINE_1_DAC                2
 357 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
 358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
 359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
 360 #define SRCSLOT_LFE_PCM_PLAYBACK                6
 361 #define SRCSLOT_PHONE_LINE_2_DAC                7
 362 #define SRCSLOT_HEADSET_DAC                     8
 363 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
 364 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
 365
 366 /* Source Slot Numbers - Capture */
 367 #define SRCSLOT_LEFT_PCM_RECORD                 10
 368 #define SRCSLOT_RIGHT_PCM_RECORD                11
 369 #define SRCSLOT_PHONE_LINE_1_ADC                12
 370 #define SRCSLOT_MIC_ADC                         13
 371 #define SRCSLOT_PHONE_LINE_2_ADC                17
 372 #define SRCSLOT_HEADSET_ADC                     18
 373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
 374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
 375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
 376 #define SRCSLOT_SECONDARY_MIC_ADC               23
 377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
 378 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
 379
 380 /* Source Slot Numbers - Others */
 381 #define SRCSLOT_POWER_DOWN                      31
 382
 383 /* MIDI modes */
 384 #define CS4281_MODE_OUTPUT              (1<<0)
 385 #define CS4281_MODE_INPUT               (1<<1)
 386
 387 /* joystick bits */
 388 /* Bits for JSPT */
 389 #define JSPT_CAX                                0x00000001
 390 #define JSPT_CAY                                0x00000002
 391 #define JSPT_CBX                                0x00000004
 392 #define JSPT_CBY                                0x00000008
 393 #define JSPT_BA1                                0x00000010
 394 #define JSPT_BA2                                0x00000020
 395 #define JSPT_BB1                                0x00000040
 396 #define JSPT_BB2                                0x00000080
 397
 398 /* Bits for JSCTL */
 399 #define JSCTL_SP_MASK                           0x00000003
 400 #define JSCTL_SP_SLOW                           0x00000000
 401 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
 402 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
 403 #define JSCTL_SP_FAST                           0x00000003
 404 #define JSCTL_ARE                               0x00000004
 405
 406 /* Data register pairs masks */
 407 #define JSC1_Y1V_MASK                           0x0000FFFF
 408 #define JSC1_X1V_MASK                           0xFFFF0000
 409 #define JSC1_Y1V_SHIFT                          0
 410 #define JSC1_X1V_SHIFT                          16
 411 #define JSC2_Y2V_MASK                           0x0000FFFF
 412 #define JSC2_X2V_MASK                           0xFFFF0000
 413 #define JSC2_Y2V_SHIFT                          0
 414 #define JSC2_X2V_SHIFT                          16
 415
 416 /* JS GPIO */
 417 #define JSIO_DAX                                0x00000001
 418 #define JSIO_DAY                                0x00000002
 419 #define JSIO_DBX                                0x00000004
 420 #define JSIO_DBY                                0x00000008
 421 #define JSIO_AXOE                               0x00000010
 422 #define JSIO_AYOE                               0x00000020
 423 #define JSIO_BXOE                               0x00000040
 424 #define JSIO_BYOE                               0x00000080
 425
 426 /*
 427  *
 428  */
 429
 430 struct cs4281_dma {
 431         struct snd_pcm_substream *substream;
 432         unsigned int regDBA;            /* offset to DBA register */
 433         unsigned int regDCA;            /* offset to DCA register */
 434         unsigned int regDBC;            /* offset to DBC register */
 435         unsigned int regDCC;            /* offset to DCC register */
 436         unsigned int regDMR;            /* offset to DMR register */
 437         unsigned int regDCR;            /* offset to DCR register */
 438         unsigned int regHDSR;           /* offset to HDSR register */
 439         unsigned int regFCR;            /* offset to FCR register */
 440         unsigned int regFSIC;           /* offset to FSIC register */
 441         unsigned int valDMR;            /* DMA mode */
 442         unsigned int valDCR;            /* DMA command */
 443         unsigned int valFCR;            /* FIFO control */
 444         unsigned int fifo_offset;       /* FIFO offset within BA1 */
 445         unsigned char left_slot;        /* FIFO left slot */
 446         unsigned char right_slot;       /* FIFO right slot */
 447         int frag;                       /* period number */
 448 };
 449
 450 #define SUSPEND_REGISTERS       20
 451
 452 struct cs4281 {
 453         int irq;
 454
 455         void __iomem *ba0;              /* virtual (accessible) address */
 456         void __iomem *ba1;              /* virtual (accessible) address */
 457         unsigned long ba0_addr;
 458         unsigned long ba1_addr;
 459
 460         int dual_codec;
 461
 462         struct snd_ac97_bus *ac97_bus;
 463         struct snd_ac97 *ac97;
 464         struct snd_ac97 *ac97_secondary;
 465
 466         struct pci_dev *pci;
 467         struct snd_card *card;
 468         struct snd_pcm *pcm;
 469         struct snd_rawmidi *rmidi;
 470         struct snd_rawmidi_substream *midi_input;
 471         struct snd_rawmidi_substream *midi_output;
 472
 473         struct cs4281_dma dma[4];
 474
 475         unsigned char src_left_play_slot;
 476         unsigned char src_right_play_slot;
 477         unsigned char src_left_rec_slot;
 478         unsigned char src_right_rec_slot;
 479
 480         unsigned int spurious_dhtc_irq;
 481         unsigned int spurious_dtc_irq;
 482
 483         spinlock_t reg_lock;
 484         unsigned int midcr;
 485         unsigned int uartm;
 486
 487         struct gameport *gameport;
 488
 489 #ifdef CONFIG_PM
 490         u32 suspend_regs[SUSPEND_REGISTERS];
 491 #endif
 492
 493 };
 494
 495 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
 496
 497 static struct pci_device_id snd_cs4281_ids[] = {
 498         { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* CS4281 */
 499         { 0, }
 500 };
 501
 502 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
 503
 504 /*
 505  *  constants
 506  */
 507
 508 #define CS4281_FIFO_SIZE        32
 509
 510 /*
 511  *  common I/O routines
 512  */
 513
 514 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
 515                                       unsigned int val)
 516 {
 517         writel(val, chip->ba0 + offset);
 518 }
 519
 520 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
 521 {
 522         return readl(chip->ba0 + offset);
 523 }
 524
 525 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
 526                                   unsigned short reg, unsigned short val)
 527 {
 528         /*
 529          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 530          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 531          *  3. Write ACCTL = Control Register = 460h for initiating the write
 532          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 533          *  5. if DCV not cleared, break and return error
 534          */
 535         struct cs4281 *chip = ac97->private_data;
 536         int count;
 537
 538         /*
 539          *  Setup the AC97 control registers on the CS461x to send the
 540          *  appropriate command to the AC97 to perform the read.
 541          *  ACCAD = Command Address Register = 46Ch
 542          *  ACCDA = Command Data Register = 470h
 543          *  ACCTL = Control Register = 460h
 544          *  set DCV - will clear when process completed
 545          *  reset CRW - Write command
 546          *  set VFRM - valid frame enabled
 547          *  set ESYN - ASYNC generation enabled
 548          *  set RSTN - ARST# inactive, AC97 codec not reset
 549          */
 550         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 551         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
 552         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
 553                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
 554         for (count = 0; count < 2000; count++) {
 555                 /*
 556                  *  First, we want to wait for a short time.
 557                  */
 558                 udelay(10);
 559                 /*
 560                  *  Now, check to see if the write has completed.
 561                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 562                  */
 563                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
 564                         return;
 565                 }
 566         }
 567         snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
 568 }
 569
 570 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
 571                                            unsigned short reg)
 572 {
 573         struct cs4281 *chip = ac97->private_data;
 574         int count;
 575         unsigned short result;
 576         // FIXME: volatile is necessary in the following due to a bug of
 577         // some gcc versions
 578         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
 579
 580         /*
 581          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 582          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 583          *  3. Write ACCTL = Control Register = 460h for initiating the write
 584          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 585          *  5. if DCV not cleared, break and return error
 586          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 587          */
 588
 589         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 590
 591         /*
 592          *  Setup the AC97 control registers on the CS461x to send the
 593          *  appropriate command to the AC97 to perform the read.
 594          *  ACCAD = Command Address Register = 46Ch
 595          *  ACCDA = Command Data Register = 470h
 596          *  ACCTL = Control Register = 460h
 597          *  set DCV - will clear when process completed
 598          *  set CRW - Read command
 599          *  set VFRM - valid frame enabled
 600          *  set ESYN - ASYNC generation enabled
 601          *  set RSTN - ARST# inactive, AC97 codec not reset
 602          */
 603
 604         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 605         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
 606         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
 607                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
 608                            (ac97_num ? BA0_ACCTL_TC : 0));
 609
 610
 611         /*
 612          *  Wait for the read to occur.
 613          */
 614         for (count = 0; count < 500; count++) {
 615                 /*
 616                  *  First, we want to wait for a short time.
 617                  */
 618                 udelay(10);
 619                 /*
 620                  *  Now, check to see if the read has completed.
 621                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 622                  */
 623                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
 624                         goto __ok1;
 625         }
 626
 627         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 628         result = 0xffff;
 629         goto __end;
 630
 631       __ok1:
 632         /*
 633          *  Wait for the valid status bit to go active.
 634          */
 635         for (count = 0; count < 100; count++) {
 636                 /*
 637                  *  Read the AC97 status register.
 638                  *  ACSTS = Status Register = 464h
 639                  *  VSTS - Valid Status
 640                  */
 641                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
 642                         goto __ok2;
 643                 udelay(10);
 644         }
 645
 646         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
 647         result = 0xffff;
 648         goto __end;
 649
 650       __ok2:
 651         /*
 652          *  Read the data returned from the AC97 register.
 653          *  ACSDA = Status Data Register = 474h
 654          */
 655         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 656
 657       __end:
 658         return result;
 659 }
 660
 661 /*
 662  *  PCM part
 663  */
 664
 665 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
 666 {
 667         struct cs4281_dma *dma = substream->runtime->private_data;
 668         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 669
 670         spin_lock(&chip->reg_lock);
 671         switch (cmd) {
 672         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 673                 dma->valDCR |= BA0_DCR_MSK;
 674                 dma->valFCR |= BA0_FCR_FEN;
 675                 break;
 676         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 677                 dma->valDCR &= ~BA0_DCR_MSK;
 678                 dma->valFCR &= ~BA0_FCR_FEN;
 679                 break;
 680         case SNDRV_PCM_TRIGGER_START:
 681         case SNDRV_PCM_TRIGGER_RESUME:
 682                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
 683                 dma->valDMR |= BA0_DMR_DMA;
 684                 dma->valDCR &= ~BA0_DCR_MSK;
 685                 dma->valFCR |= BA0_FCR_FEN;
 686                 break;
 687         case SNDRV_PCM_TRIGGER_STOP:
 688         case SNDRV_PCM_TRIGGER_SUSPEND:
 689                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
 690                 dma->valDCR |= BA0_DCR_MSK;
 691                 dma->valFCR &= ~BA0_FCR_FEN;
 692                 /* Leave wave playback FIFO enabled for FM */
 693                 if (dma->regFCR != BA0_FCR0)
 694                         dma->valFCR &= ~BA0_FCR_FEN;
 695                 break;
 696         default:
 697                 spin_unlock(&chip->reg_lock);
 698                 return -EINVAL;
 699         }
 700         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
 701         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
 702         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
 703         spin_unlock(&chip->reg_lock);
 704         return 0;
 705 }
 706
 707 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
 708 {
 709         unsigned int val = ~0;
 710
 711         if (real_rate)
 712                 *real_rate = rate;
 713         /* special "hardcoded" rates */
 714         switch (rate) {
 715         case 8000:      return 5;
 716         case 11025:     return 4;
 717         case 16000:     return 3;
 718         case 22050:     return 2;
 719         case 44100:     return 1;
 720         case 48000:     return 0;
 721         default:
 722                 goto __variable;
 723         }
 724       __variable:
 725         val = 1536000 / rate;
 726         if (real_rate)
 727                 *real_rate = 1536000 / val;
 728         return val;
 729 }
 730
 731 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
 732                             struct snd_pcm_runtime *runtime,
 733                             int capture, int src)
 734 {
 735         int rec_mono;
 736
 737         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
 738                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
 739         if (runtime->channels == 1)
 740                 dma->valDMR |= BA0_DMR_MONO;
 741         if (snd_pcm_format_unsigned(runtime->format) > 0)
 742                 dma->valDMR |= BA0_DMR_USIGN;
 743         if (snd_pcm_format_big_endian(runtime->format) > 0)
 744                 dma->valDMR |= BA0_DMR_BEND;
 745         switch (snd_pcm_format_width(runtime->format)) {
 746         case 8: dma->valDMR |= BA0_DMR_SIZE8;
 747                 if (runtime->channels == 1)
 748                         dma->valDMR |= BA0_DMR_SWAPC;
 749                 break;
 750         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
 751         }
 752         dma->frag = 0;  /* for workaround */
 753         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
 754         if (runtime->buffer_size != runtime->period_size)
 755                 dma->valDCR |= BA0_DCR_HTCIE;
 756         /* Initialize DMA */
 757         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
 758         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
 759         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
 760         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
 761                                             (chip->src_right_play_slot << 8) |
 762                                             (chip->src_left_rec_slot << 16) |
 763                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
 764         if (!src)
 765                 goto __skip_src;
 766         if (!capture) {
 767                 if (dma->left_slot == chip->src_left_play_slot) {
 768                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 769                         snd_assert(dma->right_slot == chip->src_right_play_slot, );
 770                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
 771                 }
 772         } else {
 773                 if (dma->left_slot == chip->src_left_rec_slot) {
 774                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 775                         snd_assert(dma->right_slot == chip->src_right_rec_slot, );
 776                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
 777                 }
 778         }
 779       __skip_src:
 780         /* Deactivate wave playback FIFO before changing slot assignments */
 781         if (dma->regFCR == BA0_FCR0)
 782                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
 783         /* Initialize FIFO */
 784         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
 785                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
 786                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
 787                       BA0_FCR_OF(dma->fifo_offset);
 788         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
 789         /* Activate FIFO again for FM playback */
 790         if (dma->regFCR == BA0_FCR0)
 791                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
 792         /* Clear FIFO Status and Interrupt Control Register */
 793         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
 794 }
 795
 796 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
 797                                 struct snd_pcm_hw_params *hw_params)
 798 {
 799         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 800 }
 801
 802 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
 803 {
 804         return snd_pcm_lib_free_pages(substream);
 805 }
 806
 807 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
 808 {
 809         struct snd_pcm_runtime *runtime = substream->runtime;
 810         struct cs4281_dma *dma = runtime->private_data;
 811         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 812
 813         spin_lock_irq(&chip->reg_lock);
 814         snd_cs4281_mode(chip, dma, runtime, 0, 1);
 815         spin_unlock_irq(&chip->reg_lock);
 816         return 0;
 817 }
 818
 819 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
 820 {
 821         struct snd_pcm_runtime *runtime = substream->runtime;
 822         struct cs4281_dma *dma = runtime->private_data;
 823         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 824
 825         spin_lock_irq(&chip->reg_lock);
 826         snd_cs4281_mode(chip, dma, runtime, 1, 1);
 827         spin_unlock_irq(&chip->reg_lock);
 828         return 0;
 829 }
 830
 831 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
 832 {
 833         struct snd_pcm_runtime *runtime = substream->runtime;
 834         struct cs4281_dma *dma = runtime->private_data;
 835         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 836
 837         // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
 838         return runtime->buffer_size -
 839                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
 840 }
 841
 842 static struct snd_pcm_hardware snd_cs4281_playback =
 843 {
 844         .info =                 SNDRV_PCM_INFO_MMAP |
 845                                 SNDRV_PCM_INFO_INTERLEAVED |
 846                                 SNDRV_PCM_INFO_MMAP_VALID |
 847                                 SNDRV_PCM_INFO_PAUSE |
 848                                 SNDRV_PCM_INFO_RESUME,
 849         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 850                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 851                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 852                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 853                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 854         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 855         .rate_min =             4000,
 856         .rate_max =             48000,
 857         .channels_min =         1,
 858         .channels_max =         2,
 859         .buffer_bytes_max =     (512*1024),
 860         .period_bytes_min =     64,
 861         .period_bytes_max =     (512*1024),
 862         .periods_min =          1,
 863         .periods_max =          2,
 864         .fifo_size =            CS4281_FIFO_SIZE,
 865 };
 866
 867 static struct snd_pcm_hardware snd_cs4281_capture =
 868 {
 869         .info =                 SNDRV_PCM_INFO_MMAP |
 870                                 SNDRV_PCM_INFO_INTERLEAVED |
 871                                 SNDRV_PCM_INFO_MMAP_VALID |
 872                                 SNDRV_PCM_INFO_PAUSE |
 873                                 SNDRV_PCM_INFO_RESUME,
 874         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 875                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 876                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 877                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 878                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 879         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 880         .rate_min =             4000,
 881         .rate_max =             48000,
 882         .channels_min =         1,
 883         .channels_max =         2,
 884         .buffer_bytes_max =     (512*1024),
 885         .period_bytes_min =     64,
 886         .period_bytes_max =     (512*1024),
 887         .periods_min =          1,
 888         .periods_max =          2,
 889         .fifo_size =            CS4281_FIFO_SIZE,
 890 };
 891
 892 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
 893 {
 894         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 895         struct snd_pcm_runtime *runtime = substream->runtime;
 896         struct cs4281_dma *dma;
 897
 898         dma = &chip->dma[0];
 899         dma->substream = substream;
 900         dma->left_slot = 0;
 901         dma->right_slot = 1;
 902         runtime->private_data = dma;
 903         runtime->hw = snd_cs4281_playback;
 904         /* should be detected from the AC'97 layer, but it seems
 905            that although CS4297A rev B reports 18-bit ADC resolution,
 906            samples are 20-bit */
 907         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 908         return 0;
 909 }
 910
 911 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
 912 {
 913         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 914         struct snd_pcm_runtime *runtime = substream->runtime;
 915         struct cs4281_dma *dma;
 916
 917         dma = &chip->dma[1];
 918         dma->substream = substream;
 919         dma->left_slot = 10;
 920         dma->right_slot = 11;
 921         runtime->private_data = dma;
 922         runtime->hw = snd_cs4281_capture;
 923         /* should be detected from the AC'97 layer, but it seems
 924            that although CS4297A rev B reports 18-bit ADC resolution,
 925            samples are 20-bit */
 926         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 927         return 0;
 928 }
 929
 930 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
 931 {
 932         struct cs4281_dma *dma = substream->runtime->private_data;
 933
 934         dma->substream = NULL;
 935         return 0;
 936 }
 937
 938 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
 939 {
 940         struct cs4281_dma *dma = substream->runtime->private_data;
 941
 942         dma->substream = NULL;
 943         return 0;
 944 }
 945
 946 static struct snd_pcm_ops snd_cs4281_playback_ops = {
 947         .open =         snd_cs4281_playback_open,
 948         .close =        snd_cs4281_playback_close,
 949         .ioctl =        snd_pcm_lib_ioctl,
 950         .hw_params =    snd_cs4281_hw_params,
 951         .hw_free =      snd_cs4281_hw_free,
 952         .prepare =      snd_cs4281_playback_prepare,
 953         .trigger =      snd_cs4281_trigger,
 954         .pointer =      snd_cs4281_pointer,
 955 };
 956
 957 static struct snd_pcm_ops snd_cs4281_capture_ops = {
 958         .open =         snd_cs4281_capture_open,
 959         .close =        snd_cs4281_capture_close,
 960         .ioctl =        snd_pcm_lib_ioctl,
 961         .hw_params =    snd_cs4281_hw_params,
 962         .hw_free =      snd_cs4281_hw_free,
 963         .prepare =      snd_cs4281_capture_prepare,
 964         .trigger =      snd_cs4281_trigger,
 965         .pointer =      snd_cs4281_pointer,
 966 };
 967
 968 static int __devinit snd_cs4281_pcm(struct cs4281 * chip, int device,
 969                                     struct snd_pcm ** rpcm)
 970 {
 971         struct snd_pcm *pcm;
 972         int err;
 973
 974         if (rpcm)
 975                 *rpcm = NULL;
 976         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
 977         if (err < 0)
 978                 return err;
 979
 980         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
 981         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
 982
 983         pcm->private_data = chip;
 984         pcm->info_flags = 0;
 985         strcpy(pcm->name, "CS4281");
 986         chip->pcm = pcm;
 987
 988         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 989                                               snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
 990
 991         if (rpcm)
 992                 *rpcm = pcm;
 993         return 0;
 994 }
 995
 996 /*
 997  *  Mixer section
 998  */
 999
1000 #define CS_VOL_MASK     0x1f
1001
1002 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1003                                   struct snd_ctl_elem_info *uinfo)
1004 {
1005         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
1006         uinfo->count             = 2;
1007         uinfo->value.integer.min = 0;
1008         uinfo->value.integer.max = CS_VOL_MASK;
1009         return 0;
1010 }
1011
1012 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1013                                  struct snd_ctl_elem_value *ucontrol)
1014 {
1015         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1016         int regL = (kcontrol->private_value >> 16) & 0xffff;
1017         int regR = kcontrol->private_value & 0xffff;
1018         int volL, volR;
1019
1020         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1021         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1022
1023         ucontrol->value.integer.value[0] = volL;
1024         ucontrol->value.integer.value[1] = volR;
1025         return 0;
1026 }
1027
1028 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1029                                  struct snd_ctl_elem_value *ucontrol)
1030 {
1031         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1032         int change = 0;
1033         int regL = (kcontrol->private_value >> 16) & 0xffff;
1034         int regR = kcontrol->private_value & 0xffff;
1035         int volL, volR;
1036
1037         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1038         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1039
1040         if (ucontrol->value.integer.value[0] != volL) {
1041                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1042                 snd_cs4281_pokeBA0(chip, regL, volL);
1043                 change = 1;
1044         }
1045         if (ucontrol->value.integer.value[1] != volR) {
1046                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1047                 snd_cs4281_pokeBA0(chip, regR, volR);
1048                 change = 1;
1049         }
1050         return change;
1051 }
1052
1053 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1054
1055 static struct snd_kcontrol_new snd_cs4281_fm_vol =
1056 {
1057         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1058         .name = "Synth Playback Volume",
1059         .info = snd_cs4281_info_volume,
1060         .get = snd_cs4281_get_volume,
1061         .put = snd_cs4281_put_volume,
1062         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1063         .tlv = { .p = db_scale_dsp },
1064 };
1065
1066 static struct snd_kcontrol_new snd_cs4281_pcm_vol =
1067 {
1068         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1069         .name = "PCM Stream Playback Volume",
1070         .info = snd_cs4281_info_volume,
1071         .get = snd_cs4281_get_volume,
1072         .put = snd_cs4281_put_volume,
1073         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1074         .tlv = { .p = db_scale_dsp },
1075 };
1076
1077 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1078 {
1079         struct cs4281 *chip = bus->private_data;
1080         chip->ac97_bus = NULL;
1081 }
1082
1083 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1084 {
1085         struct cs4281 *chip = ac97->private_data;
1086         if (ac97->num)
1087                 chip->ac97_secondary = NULL;
1088         else
1089                 chip->ac97 = NULL;
1090 }
1091
1092 static int __devinit snd_cs4281_mixer(struct cs4281 * chip)
1093 {
1094         struct snd_card *card = chip->card;
1095         struct snd_ac97_template ac97;
1096         int err;
1097         static struct snd_ac97_bus_ops ops = {
1098                 .write = snd_cs4281_ac97_write,
1099                 .read = snd_cs4281_ac97_read,
1100         };
1101
1102         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1103                 return err;
1104         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1105
1106         memset(&ac97, 0, sizeof(ac97));
1107         ac97.private_data = chip;
1108         ac97.private_free = snd_cs4281_mixer_free_ac97;
1109         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1110                 return err;
1111         if (chip->dual_codec) {
1112                 ac97.num = 1;
1113                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1114                         return err;
1115         }
1116         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1117                 return err;
1118         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1119                 return err;
1120         return 0;
1121 }
1122
1123
1124 /*
1125  * proc interface
1126  */
1127
1128 static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1129                                   struct snd_info_buffer *buffer)
1130 {
1131         struct cs4281 *chip = entry->private_data;
1132
1133         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1134         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1135         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1136 }
1137
1138 static long snd_cs4281_BA0_read(struct snd_info_entry *entry,
1139                                 void *file_private_data,
1140                                 struct file *file, char __user *buf,
1141                                 unsigned long count, unsigned long pos)
1142 {
1143         long size;
1144         struct cs4281 *chip = entry->private_data;
1145
1146         size = count;
1147         if (pos + size > CS4281_BA0_SIZE)
1148                 size = (long)CS4281_BA0_SIZE - pos;
1149         if (size > 0) {
1150                 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1151                         return -EFAULT;
1152         }
1153         return size;
1154 }
1155
1156 static long snd_cs4281_BA1_read(struct snd_info_entry *entry,
1157                                 void *file_private_data,
1158                                 struct file *file, char __user *buf,
1159                                 unsigned long count, unsigned long pos)
1160 {
1161         long size;
1162         struct cs4281 *chip = entry->private_data;
1163
1164         size = count;
1165         if (pos + size > CS4281_BA1_SIZE)
1166                 size = (long)CS4281_BA1_SIZE - pos;
1167         if (size > 0) {
1168                 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1169                         return -EFAULT;
1170         }
1171         return size;
1172 }
1173
1174 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1175         .read = snd_cs4281_BA0_read,
1176 };
1177
1178 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1179         .read = snd_cs4281_BA1_read,
1180 };
1181
1182 static void __devinit snd_cs4281_proc_init(struct cs4281 * chip)
1183 {
1184         struct snd_info_entry *entry;
1185
1186         if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1187                 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1188         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1189                 entry->content = SNDRV_INFO_CONTENT_DATA;
1190                 entry->private_data = chip;
1191                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1192                 entry->size = CS4281_BA0_SIZE;
1193         }
1194         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1195                 entry->content = SNDRV_INFO_CONTENT_DATA;
1196                 entry->private_data = chip;
1197                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1198                 entry->size = CS4281_BA1_SIZE;
1199         }
1200 }
1201
1202 /*
1203  * joystick support
1204  */
1205
1206 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1207
1208 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1209 {
1210         struct cs4281 *chip = gameport_get_port_data(gameport);
1211
1212         snd_assert(chip, return);
1213         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1214 }
1215
1216 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1217 {
1218         struct cs4281 *chip = gameport_get_port_data(gameport);
1219
1220         snd_assert(chip, return 0);
1221         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1222 }
1223
1224 #ifdef COOKED_MODE
1225 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1226                                            int *axes, int *buttons)
1227 {
1228         struct cs4281 *chip = gameport_get_port_data(gameport);
1229         unsigned js1, js2, jst;
1230
1231         snd_assert(chip, return 0);
1232
1233         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1234         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1235         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1236
1237         *buttons = (~jst >> 4) & 0x0F;
1238
1239         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1240         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1241         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1242         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1243
1244         for (jst = 0; jst < 4; ++jst)
1245                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1246         return 0;
1247 }
1248 #else
1249 #define snd_cs4281_gameport_cooked_read NULL
1250 #endif
1251
1252 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1253 {
1254         switch (mode) {
1255 #ifdef COOKED_MODE
1256         case GAMEPORT_MODE_COOKED:
1257                 return 0;
1258 #endif
1259         case GAMEPORT_MODE_RAW:
1260                 return 0;
1261         default:
1262                 return -1;
1263         }
1264         return 0;
1265 }
1266
1267 static int __devinit snd_cs4281_create_gameport(struct cs4281 *chip)
1268 {
1269         struct gameport *gp;
1270
1271         chip->gameport = gp = gameport_allocate_port();
1272         if (!gp) {
1273                 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1274                 return -ENOMEM;
1275         }
1276
1277         gameport_set_name(gp, "CS4281 Gameport");
1278         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1279         gameport_set_dev_parent(gp, &chip->pci->dev);
1280         gp->open = snd_cs4281_gameport_open;
1281         gp->read = snd_cs4281_gameport_read;
1282         gp->trigger = snd_cs4281_gameport_trigger;
1283         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1284         gameport_set_port_data(gp, chip);
1285
1286         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1287         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1288
1289         gameport_register_port(gp);
1290
1291         return 0;
1292 }
1293
1294 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1295 {
1296         if (chip->gameport) {
1297                 gameport_unregister_port(chip->gameport);
1298                 chip->gameport = NULL;
1299         }
1300 }
1301 #else
1302 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1303 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1304 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1305
1306 static int snd_cs4281_free(struct cs4281 *chip)
1307 {
1308         snd_cs4281_free_gameport(chip);
1309
1310         if (chip->irq >= 0)
1311                 synchronize_irq(chip->irq);
1312
1313         /* Mask interrupts */
1314         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1315         /* Stop the DLL Clock logic. */
1316         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1317         /* Sound System Power Management - Turn Everything OFF */
1318         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1319         /* PCI interface - D3 state */
1320         pci_set_power_state(chip->pci, 3);
1321
1322         if (chip->irq >= 0)
1323                 free_irq(chip->irq, chip);
1324         if (chip->ba0)
1325                 iounmap(chip->ba0);
1326         if (chip->ba1)
1327                 iounmap(chip->ba1);
1328         pci_release_regions(chip->pci);
1329         pci_disable_device(chip->pci);
1330
1331         kfree(chip);
1332         return 0;
1333 }
1334
1335 static int snd_cs4281_dev_free(struct snd_device *device)
1336 {
1337         struct cs4281 *chip = device->device_data;
1338         return snd_cs4281_free(chip);
1339 }
1340
1341 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1342
1343 static int __devinit snd_cs4281_create(struct snd_card *card,
1344                                        struct pci_dev *pci,
1345                                        struct cs4281 ** rchip,
1346                                        int dual_codec)
1347 {
1348         struct cs4281 *chip;
1349         unsigned int tmp;
1350         int err;
1351         static struct snd_device_ops ops = {
1352                 .dev_free =     snd_cs4281_dev_free,
1353         };
1354
1355         *rchip = NULL;
1356         if ((err = pci_enable_device(pci)) < 0)
1357                 return err;
1358         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1359         if (chip == NULL) {
1360                 pci_disable_device(pci);
1361                 return -ENOMEM;
1362         }
1363         spin_lock_init(&chip->reg_lock);
1364         chip->card = card;
1365         chip->pci = pci;
1366         chip->irq = -1;
1367         pci_set_master(pci);
1368         if (dual_codec < 0 || dual_codec > 3) {
1369                 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1370                 dual_codec = 0;
1371         }
1372         chip->dual_codec = dual_codec;
1373
1374         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1375                 kfree(chip);
1376                 pci_disable_device(pci);
1377                 return err;
1378         }
1379         chip->ba0_addr = pci_resource_start(pci, 0);
1380         chip->ba1_addr = pci_resource_start(pci, 1);
1381
1382         chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1383         chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1384         if (!chip->ba0 || !chip->ba1) {
1385                 snd_cs4281_free(chip);
1386                 return -ENOMEM;
1387         }
1388
1389         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1390                         "CS4281", chip)) {
1391                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1392                 snd_cs4281_free(chip);
1393                 return -ENOMEM;
1394         }
1395         chip->irq = pci->irq;
1396
1397         tmp = snd_cs4281_chip_init(chip);
1398         if (tmp) {
1399                 snd_cs4281_free(chip);
1400                 return tmp;
1401         }
1402
1403         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1404                 snd_cs4281_free(chip);
1405                 return err;
1406         }
1407
1408         snd_cs4281_proc_init(chip);
1409
1410         snd_card_set_dev(card, &pci->dev);
1411
1412         *rchip = chip;
1413         return 0;
1414 }
1415
1416 static int snd_cs4281_chip_init(struct cs4281 *chip)
1417 {
1418         unsigned int tmp;
1419         unsigned long end_time;
1420         int retry_count = 2;
1421
1422         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1423         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1424         if (tmp & BA0_EPPMC_FPDN)
1425                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1426
1427       __retry:
1428         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1429         if (tmp != BA0_CFLR_DEFAULT) {
1430                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1431                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1432                 if (tmp != BA0_CFLR_DEFAULT) {
1433                         snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1434                         return -EIO;
1435                 }
1436         }
1437
1438         /* Set the 'Configuration Write Protect' register
1439          * to 4281h.  Allows vendor-defined configuration
1440          * space between 0e4h and 0ffh to be written. */
1441         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1442
1443         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1444                 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1445                 return -EIO;
1446         }
1447         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1448                 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1449                 return -EIO;
1450         }
1451
1452         /* Sound System Power Management */
1453         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1454                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1455                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1456
1457         /* Serial Port Power Management */
1458         /* Blast the clock control register to zero so that the
1459          * PLL starts out in a known state, and blast the master serial
1460          * port control register to zero so that the serial ports also
1461          * start out in a known state. */
1462         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1463         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1464
1465         /* Make ESYN go to zero to turn off
1466          * the Sync pulse on the AC97 link. */
1467         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1468         udelay(50);
1469
1470         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1471          *  spec) and then drive it high.  This is done for non AC97 modes since
1472          *  there might be logic external to the CS4281 that uses the ARST# line
1473          *  for a reset. */
1474         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1475         udelay(50);
1476         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1477         msleep(50);
1478
1479         if (chip->dual_codec)
1480                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1481
1482         /*
1483          *  Set the serial port timing configuration.
1484          */
1485         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1486                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1487                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1488
1489         /*
1490          *  Start the DLL Clock logic.
1491          */
1492         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1493         msleep(50);
1494         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1495
1496         /*
1497          * Wait for the DLL ready signal from the clock logic.
1498          */
1499         end_time = jiffies + HZ;
1500         do {
1501                 /*
1502                  *  Read the AC97 status register to see if we've seen a CODEC
1503                  *  signal from the AC97 codec.
1504                  */
1505                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1506                         goto __ok0;
1507                 schedule_timeout_uninterruptible(1);
1508         } while (time_after_eq(end_time, jiffies));
1509
1510         snd_printk(KERN_ERR "DLLRDY not seen\n");
1511         return -EIO;
1512
1513       __ok0:
1514
1515         /*
1516          *  The first thing we do here is to enable sync generation.  As soon
1517          *  as we start receiving bit clock, we'll start producing the SYNC
1518          *  signal.
1519          */
1520         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1521
1522         /*
1523          * Wait for the codec ready signal from the AC97 codec.
1524          */
1525         end_time = jiffies + HZ;
1526         do {
1527                 /*
1528                  *  Read the AC97 status register to see if we've seen a CODEC
1529                  *  signal from the AC97 codec.
1530                  */
1531                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1532                         goto __ok1;
1533                 schedule_timeout_uninterruptible(1);
1534         } while (time_after_eq(end_time, jiffies));
1535
1536         snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1537         return -EIO;
1538
1539       __ok1:
1540         if (chip->dual_codec) {
1541                 end_time = jiffies + HZ;
1542                 do {
1543                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1544                                 goto __codec2_ok;
1545                         schedule_timeout_uninterruptible(1);
1546                 } while (time_after_eq(end_time, jiffies));
1547                 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1548                 chip->dual_codec = 0;
1549         __codec2_ok: ;
1550         }
1551
1552         /*
1553          *  Assert the valid frame signal so that we can start sending commands
1554          *  to the AC97 codec.
1555          */
1556
1557         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1558
1559         /*
1560          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1561          *  the codec is pumping ADC data across the AC-link.
1562          */
1563
1564         end_time = jiffies + HZ;
1565         do {
1566                 /*
1567                  *  Read the input slot valid register and see if input slots 3
1568                  *  4 are valid yet.
1569                  */
1570                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1571                         goto __ok2;
1572                 schedule_timeout_uninterruptible(1);
1573         } while (time_after_eq(end_time, jiffies));
1574
1575         if (--retry_count > 0)
1576                 goto __retry;
1577         snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1578         return -EIO;
1579
1580       __ok2:
1581
1582         /*
1583          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1584          *  commense the transfer of digital audio data to the AC97 codec.
1585          */
1586         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1587
1588         /*
1589          *  Initialize DMA structures
1590          */
1591         for (tmp = 0; tmp < 4; tmp++) {
1592                 struct cs4281_dma *dma = &chip->dma[tmp];
1593                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1594                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1595                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1596                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1597                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1598                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1599                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1600                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1601                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1602                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1603                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1604                                    BA0_FCR_LS(31) |
1605                                    BA0_FCR_RS(31) |
1606                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1607                                    BA0_FCR_OF(dma->fifo_offset));
1608         }
1609
1610         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1611         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1612         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1613         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1614
1615         /* Activate wave playback FIFO for FM playback */
1616         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1617                               BA0_FCR_RS(1) |
1618                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1619                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1620         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1621         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1622                                             (chip->src_right_play_slot << 8) |
1623                                             (chip->src_left_rec_slot << 16) |
1624                                             (chip->src_right_rec_slot << 24));
1625
1626         /* Initialize digital volume */
1627         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1628         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1629
1630         /* Enable IRQs */
1631         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1632         /* Unmask interrupts */
1633         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1634                                         BA0_HISR_MIDI |
1635                                         BA0_HISR_DMAI |
1636                                         BA0_HISR_DMA(0) |
1637                                         BA0_HISR_DMA(1) |
1638                                         BA0_HISR_DMA(2) |
1639                                         BA0_HISR_DMA(3)));
1640         synchronize_irq(chip->irq);
1641
1642         return 0;
1643 }
1644
1645 /*
1646  *  MIDI section
1647  */
1648
1649 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1650 {
1651         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1652         udelay(100);
1653         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1654 }
1655
1656 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1657 {
1658         struct cs4281 *chip = substream->rmidi->private_data;
1659
1660         spin_lock_irq(&chip->reg_lock);
1661         chip->midcr |= BA0_MIDCR_RXE;
1662         chip->midi_input = substream;
1663         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1664                 snd_cs4281_midi_reset(chip);
1665         } else {
1666                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1667         }
1668         spin_unlock_irq(&chip->reg_lock);
1669         return 0;
1670 }
1671
1672 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1673 {
1674         struct cs4281 *chip = substream->rmidi->private_data;
1675
1676         spin_lock_irq(&chip->reg_lock);
1677         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1678         chip->midi_input = NULL;
1679         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1680                 snd_cs4281_midi_reset(chip);
1681         } else {
1682                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1683         }
1684         chip->uartm &= ~CS4281_MODE_INPUT;
1685         spin_unlock_irq(&chip->reg_lock);
1686         return 0;
1687 }
1688
1689 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1690 {
1691         struct cs4281 *chip = substream->rmidi->private_data;
1692
1693         spin_lock_irq(&chip->reg_lock);
1694         chip->uartm |= CS4281_MODE_OUTPUT;
1695         chip->midcr |= BA0_MIDCR_TXE;
1696         chip->midi_output = substream;
1697         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1698                 snd_cs4281_midi_reset(chip);
1699         } else {
1700                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1701         }
1702         spin_unlock_irq(&chip->reg_lock);
1703         return 0;
1704 }
1705
1706 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1707 {
1708         struct cs4281 *chip = substream->rmidi->private_data;
1709
1710         spin_lock_irq(&chip->reg_lock);
1711         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1712         chip->midi_output = NULL;
1713         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1714                 snd_cs4281_midi_reset(chip);
1715         } else {
1716                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1717         }
1718         chip->uartm &= ~CS4281_MODE_OUTPUT;
1719         spin_unlock_irq(&chip->reg_lock);
1720         return 0;
1721 }
1722
1723 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1724 {
1725         unsigned long flags;
1726         struct cs4281 *chip = substream->rmidi->private_data;
1727
1728         spin_lock_irqsave(&chip->reg_lock, flags);
1729         if (up) {
1730                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1731                         chip->midcr |= BA0_MIDCR_RIE;
1732                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1733                 }
1734         } else {
1735                 if (chip->midcr & BA0_MIDCR_RIE) {
1736                         chip->midcr &= ~BA0_MIDCR_RIE;
1737                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1738                 }
1739         }
1740         spin_unlock_irqrestore(&chip->reg_lock, flags);
1741 }
1742
1743 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1744 {
1745         unsigned long flags;
1746         struct cs4281 *chip = substream->rmidi->private_data;
1747         unsigned char byte;
1748
1749         spin_lock_irqsave(&chip->reg_lock, flags);
1750         if (up) {
1751                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1752                         chip->midcr |= BA0_MIDCR_TIE;
1753                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1754                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1755                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1756                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1757                                         chip->midcr &= ~BA0_MIDCR_TIE;
1758                                 } else {
1759                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1760                                 }
1761                         }
1762                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1763                 }
1764         } else {
1765                 if (chip->midcr & BA0_MIDCR_TIE) {
1766                         chip->midcr &= ~BA0_MIDCR_TIE;
1767                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1768                 }
1769         }
1770         spin_unlock_irqrestore(&chip->reg_lock, flags);
1771 }
1772
1773 static struct snd_rawmidi_ops snd_cs4281_midi_output =
1774 {
1775         .open =         snd_cs4281_midi_output_open,
1776         .close =        snd_cs4281_midi_output_close,
1777         .trigger =      snd_cs4281_midi_output_trigger,
1778 };
1779
1780 static struct snd_rawmidi_ops snd_cs4281_midi_input =
1781 {
1782         .open =         snd_cs4281_midi_input_open,
1783         .close =        snd_cs4281_midi_input_close,
1784         .trigger =      snd_cs4281_midi_input_trigger,
1785 };
1786
1787 static int __devinit snd_cs4281_midi(struct cs4281 * chip, int device,
1788                                      struct snd_rawmidi **rrawmidi)
1789 {
1790         struct snd_rawmidi *rmidi;
1791         int err;
1792
1793         if (rrawmidi)
1794                 *rrawmidi = NULL;
1795         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1796                 return err;
1797         strcpy(rmidi->name, "CS4281");
1798         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1799         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1800         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1801         rmidi->private_data = chip;
1802         chip->rmidi = rmidi;
1803         if (rrawmidi)
1804                 *rrawmidi = rmidi;
1805         return 0;
1806 }
1807
1808 /*
1809  *  Interrupt handler
1810  */
1811
1812 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1813 {
1814         struct cs4281 *chip = dev_id;
1815         unsigned int status, dma, val;
1816         struct cs4281_dma *cdma;
1817
1818         if (chip == NULL)
1819                 return IRQ_NONE;
1820         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1821         if ((status & 0x7fffffff) == 0) {
1822                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1823                 return IRQ_NONE;
1824         }
1825
1826         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1827                 for (dma = 0; dma < 4; dma++)
1828                         if (status & BA0_HISR_DMA(dma)) {
1829                                 cdma = &chip->dma[dma];
1830                                 spin_lock(&chip->reg_lock);
1831                                 /* ack DMA IRQ */
1832                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1833                                 /* workaround, sometimes CS4281 acknowledges */
1834                                 /* end or middle transfer position twice */
1835                                 cdma->frag++;
1836                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1837                                         cdma->frag--;
1838                                         chip->spurious_dhtc_irq++;
1839                                         spin_unlock(&chip->reg_lock);
1840                                         continue;
1841                                 }
1842                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1843                                         cdma->frag--;
1844                                         chip->spurious_dtc_irq++;
1845                                         spin_unlock(&chip->reg_lock);
1846                                         continue;
1847                                 }
1848                                 spin_unlock(&chip->reg_lock);
1849                                 snd_pcm_period_elapsed(cdma->substream);
1850                         }
1851         }
1852
1853         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1854                 unsigned char c;
1855
1856                 spin_lock(&chip->reg_lock);
1857                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1858                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1859                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1860                                 continue;
1861                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1862                 }
1863                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1864                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1865                                 break;
1866                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1867                                 chip->midcr &= ~BA0_MIDCR_TIE;
1868                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1869                                 break;
1870                         }
1871                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1872                 }
1873                 spin_unlock(&chip->reg_lock);
1874         }
1875
1876         /* EOI to the PCI part... reenables interrupts */
1877         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1878
1879         return IRQ_HANDLED;
1880 }
1881
1882
1883 /*
1884  * OPL3 command
1885  */
1886 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1887                                     unsigned char val)
1888 {
1889         unsigned long flags;
1890         struct cs4281 *chip = opl3->private_data;
1891         void __iomem *port;
1892
1893         if (cmd & OPL3_RIGHT)
1894                 port = chip->ba0 + BA0_B1AP; /* right port */
1895         else
1896                 port = chip->ba0 + BA0_B0AP; /* left port */
1897
1898         spin_lock_irqsave(&opl3->reg_lock, flags);
1899
1900         writel((unsigned int)cmd, port);
1901         udelay(10);
1902
1903         writel((unsigned int)val, port + 4);
1904         udelay(30);
1905
1906         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1907 }
1908
1909 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1910                                       const struct pci_device_id *pci_id)
1911 {
1912         static int dev;
1913         struct snd_card *card;
1914         struct cs4281 *chip;
1915         struct snd_opl3 *opl3;
1916         int err;
1917
1918         if (dev >= SNDRV_CARDS)
1919                 return -ENODEV;
1920         if (!enable[dev]) {
1921                 dev++;
1922                 return -ENOENT;
1923         }
1924
1925         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1926         if (card == NULL)
1927                 return -ENOMEM;
1928
1929         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1930                 snd_card_free(card);
1931                 return err;
1932         }
1933         card->private_data = chip;
1934
1935         if ((err = snd_cs4281_mixer(chip)) < 0) {
1936                 snd_card_free(card);
1937                 return err;
1938         }
1939         if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1940                 snd_card_free(card);
1941                 return err;
1942         }
1943         if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1944                 snd_card_free(card);
1945                 return err;
1946         }
1947         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1948                 snd_card_free(card);
1949                 return err;
1950         }
1951         opl3->private_data = chip;
1952         opl3->command = snd_cs4281_opl3_command;
1953         snd_opl3_init(opl3);
1954         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1955                 snd_card_free(card);
1956                 return err;
1957         }
1958         snd_cs4281_create_gameport(chip);
1959         strcpy(card->driver, "CS4281");
1960         strcpy(card->shortname, "Cirrus Logic CS4281");
1961         sprintf(card->longname, "%s at 0x%lx, irq %d",
1962                 card->shortname,
1963                 chip->ba0_addr,
1964                 chip->irq);
1965
1966         if ((err = snd_card_register(card)) < 0) {
1967                 snd_card_free(card);
1968                 return err;
1969         }
1970
1971         pci_set_drvdata(pci, card);
1972         dev++;
1973         return 0;
1974 }
1975
1976 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
1977 {
1978         snd_card_free(pci_get_drvdata(pci));
1979         pci_set_drvdata(pci, NULL);
1980 }
1981
1982 /*
1983  * Power Management
1984  */
1985 #ifdef CONFIG_PM
1986
1987 static int saved_regs[SUSPEND_REGISTERS] = {
1988         BA0_JSCTL,
1989         BA0_GPIOR,
1990         BA0_SSCR,
1991         BA0_MIDCR,
1992         BA0_SRCSA,
1993         BA0_PASR,
1994         BA0_CASR,
1995         BA0_DACSR,
1996         BA0_ADCSR,
1997         BA0_FMLVC,
1998         BA0_FMRVC,
1999         BA0_PPLVC,
2000         BA0_PPRVC,
2001 };
2002
2003 #define CLKCR1_CKRA                             0x00010000L
2004
2005 static int cs4281_suspend(struct pci_dev *pci, pm_message_t state)
2006 {
2007         struct snd_card *card = pci_get_drvdata(pci);
2008         struct cs4281 *chip = card->private_data;
2009         u32 ulCLK;
2010         unsigned int i;
2011
2012         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2013         snd_pcm_suspend_all(chip->pcm);
2014
2015         snd_ac97_suspend(chip->ac97);
2016         snd_ac97_suspend(chip->ac97_secondary);
2017
2018         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2019         ulCLK |= CLKCR1_CKRA;
2020         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2021
2022         /* Disable interrupts. */
2023         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2024
2025         /* remember the status registers */
2026         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2027                 if (saved_regs[i])
2028                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2029
2030         /* Turn off the serial ports. */
2031         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2032
2033         /* Power off FM, Joystick, AC link, */
2034         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2035
2036         /* DLL off. */
2037         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2038
2039         /* AC link off. */
2040         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2041
2042         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2043         ulCLK &= ~CLKCR1_CKRA;
2044         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2045
2046         pci_disable_device(pci);
2047         pci_save_state(pci);
2048         pci_set_power_state(pci, pci_choose_state(pci, state));
2049         return 0;
2050 }
2051
2052 static int cs4281_resume(struct pci_dev *pci)
2053 {
2054         struct snd_card *card = pci_get_drvdata(pci);
2055         struct cs4281 *chip = card->private_data;
2056         unsigned int i;
2057         u32 ulCLK;
2058
2059         pci_set_power_state(pci, PCI_D0);
2060         pci_restore_state(pci);
2061         if (pci_enable_device(pci) < 0) {
2062                 printk(KERN_ERR "cs4281: pci_enable_device failed, "
2063                        "disabling device\n");
2064                 snd_card_disconnect(card);
2065                 return -EIO;
2066         }
2067         pci_set_master(pci);
2068
2069         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2070         ulCLK |= CLKCR1_CKRA;
2071         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2072
2073         snd_cs4281_chip_init(chip);
2074
2075         /* restore the status registers */
2076         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2077                 if (saved_regs[i])
2078                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2079
2080         snd_ac97_resume(chip->ac97);
2081         snd_ac97_resume(chip->ac97_secondary);
2082
2083         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2084         ulCLK &= ~CLKCR1_CKRA;
2085         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2086
2087         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2088         return 0;
2089 }
2090 #endif /* CONFIG_PM */
2091
2092 static struct pci_driver driver = {
2093         .name = "CS4281",
2094         .id_table = snd_cs4281_ids,
2095         .probe = snd_cs4281_probe,
2096         .remove = __devexit_p(snd_cs4281_remove),
2097 #ifdef CONFIG_PM
2098         .suspend = cs4281_suspend,
2099         .resume = cs4281_resume,
2100 #endif
2101 };
2102
2103 static int __init alsa_card_cs4281_init(void)
2104 {
2105         return pci_register_driver(&driver);
2106 }
2107
2108 static void __exit alsa_card_cs4281_exit(void)
2109 {
2110         pci_unregister_driver(&driver);
2111 }
2112
2113 module_init(alsa_card_cs4281_init)
2114 module_exit(alsa_card_cs4281_exit)