sound/oss/ad1848.c

   1 /*
   2  * sound/oss/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  *
  17  *
  18  * Copyright (C) by Hannu Savolainen 1993-1997
  19  *
  20  * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
  21  * Version 2 (June 1991). See the "COPYING" file distributed with this software
  22  * for more info.
  23  *
  24  *
  25  * Thomas Sailer        : ioctl code reworked (vmalloc/vfree removed)
  26  *                        general sleep/wakeup clean up.
  27  * Alan Cox             : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
  28  *                        of irqs. Use dev_id.
  29  * Christoph Hellwig    : adapted to module_init/module_exit
  30  * Aki Laukkanen        : added power management support
  31  * Arnaldo C. de Melo   : added missing restore_flags in ad1848_resume
  32  * Miguel Freitas       : added ISA PnP support
  33  * Alan Cox             : Added CS4236->4239 identification
  34  * Daniel T. Cobra      : Alernate config/mixer for later chips
  35  * Alan Cox             : Merged chip idents and config code
  36  *
  37  * TODO
  38  *              APM save restore assist code on IBM thinkpad
  39  *
  40  * Status:
  41  *              Tested. Believed fully functional.
  42  */
  43
  44 #include <linux/init.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/module.h>
  47 #include <linux/stddef.h>
  48 #include <linux/isapnp.h>
  49 #include <linux/pnp.h>
  50 #include <linux/spinlock.h>
  51
  52 #define DEB(x)
  53 #define DEB1(x)
  54 #include "sound_config.h"
  55
  56 #include "ad1848.h"
  57 #include "ad1848_mixer.h"
  58
  59 typedef struct
  60 {
  61         spinlock_t      lock;
  62         int             base;
  63         int             irq;
  64         int             dma1, dma2;
  65         int             dual_dma;       /* 1, when two DMA channels allocated */
  66         int             subtype;
  67         unsigned char   MCE_bit;
  68         unsigned char   saved_regs[64]; /* Includes extended register space */
  69         int             debug_flag;
  70
  71         int             audio_flags;
  72         int             record_dev, playback_dev;
  73
  74         int             xfer_count;
  75         int             audio_mode;
  76         int             open_mode;
  77         int             intr_active;
  78         char           *chip_name, *name;
  79         int             model;
  80 #define MD_1848         1
  81 #define MD_4231         2
  82 #define MD_4231A        3
  83 #define MD_1845         4
  84 #define MD_4232         5
  85 #define MD_C930         6
  86 #define MD_IWAVE        7
  87 #define MD_4235         8 /* Crystal Audio CS4235  */
  88 #define MD_1845_SSCAPE  9 /* Ensoniq Soundscape PNP*/
  89 #define MD_4236         10 /* 4236 and higher */
  90 #define MD_42xB         11 /* CS 42xB */
  91 #define MD_4239         12 /* CS4239 */
  92
  93         /* Mixer parameters */
  94         int             recmask;
  95         int             supported_devices, orig_devices;
  96         int             supported_rec_devices, orig_rec_devices;
  97         int            *levels;
  98         short           mixer_reroute[32];
  99         int             dev_no;
 100         volatile unsigned long timer_ticks;
 101         int             timer_running;
 102         int             irq_ok;
 103         mixer_ents     *mix_devices;
 104         int             mixer_output_port;
 105 } ad1848_info;
 106
 107 typedef struct ad1848_port_info
 108 {
 109         int             open_mode;
 110         int             speed;
 111         unsigned char   speed_bits;
 112         int             channels;
 113         int             audio_format;
 114         unsigned char   format_bits;
 115 }
 116 ad1848_port_info;
 117
 118 static struct address_info cfg;
 119 static int nr_ad1848_devs;
 120
 121 static int deskpro_xl;
 122 static int deskpro_m;
 123 static int soundpro;
 124
 125 static volatile signed char irq2dev[17] = {
 126         -1, -1, -1, -1, -1, -1, -1, -1,
 127         -1, -1, -1, -1, -1, -1, -1, -1, -1
 128 };
 129
 130 #ifndef EXCLUDE_TIMERS
 131 static int timer_installed = -1;
 132 #endif
 133
 134 static int loaded;
 135
 136 static int ad_format_mask[13 /*devc->model */ ] =
 137 {
 138         0,
 139         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 140         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 141         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 142         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,       /* AD1845 */
 143         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 144         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 145         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 146         AFMT_U8 | AFMT_S16_LE /* CS4235 */,
 147         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW        /* Ensoniq Soundscape*/,
 148         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 149         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 150         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
 151 };
 152
 153 static ad1848_info adev_info[MAX_AUDIO_DEV];
 154
 155 #define io_Index_Addr(d)        ((d)->base)
 156 #define io_Indexed_Data(d)      ((d)->base+1)
 157 #define io_Status(d)            ((d)->base+2)
 158 #define io_Polled_IO(d)         ((d)->base+3)
 159
 160 static struct {
 161      unsigned char flags;
 162 #define CAP_F_TIMER 0x01
 163 } capabilities [10 /*devc->model */ ] = {
 164      {0}
 165     ,{0}           /* MD_1848  */
 166     ,{CAP_F_TIMER} /* MD_4231  */
 167     ,{CAP_F_TIMER} /* MD_4231A */
 168     ,{CAP_F_TIMER} /* MD_1845  */
 169     ,{CAP_F_TIMER} /* MD_4232  */
 170     ,{0}           /* MD_C930  */
 171     ,{CAP_F_TIMER} /* MD_IWAVE */
 172     ,{0}           /* MD_4235  */
 173     ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
 174 };
 175
 176 #ifdef CONFIG_PNP
 177 static int isapnp       = 1;
 178 static int isapnpjump;
 179 static int reverse;
 180
 181 static int audio_activated;
 182 #else
 183 static int isapnp;
 184 #endif
 185
 186
 187
 188 static int      ad1848_open(int dev, int mode);
 189 static void     ad1848_close(int dev);
 190 static void     ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
 191 static void     ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
 192 static int      ad1848_prepare_for_output(int dev, int bsize, int bcount);
 193 static int      ad1848_prepare_for_input(int dev, int bsize, int bcount);
 194 static void     ad1848_halt(int dev);
 195 static void     ad1848_halt_input(int dev);
 196 static void     ad1848_halt_output(int dev);
 197 static void     ad1848_trigger(int dev, int bits);
 198
 199 #ifndef EXCLUDE_TIMERS
 200 static int ad1848_tmr_install(int dev);
 201 static void ad1848_tmr_reprogram(int dev);
 202 #endif
 203
 204 static int ad_read(ad1848_info * devc, int reg)
 205 {
 206         int x;
 207         int timeout = 900000;
 208
 209         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 210                 timeout--;
 211
 212         if(reg < 32)
 213         {
 214                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 215                 x = inb(io_Indexed_Data(devc));
 216         }
 217         else
 218         {
 219                 int xreg, xra;
 220
 221                 xreg = (reg & 0xff) - 32;
 222                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 223                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 224                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 225                 x = inb(io_Indexed_Data(devc));
 226         }
 227
 228         return x;
 229 }
 230
 231 static void ad_write(ad1848_info * devc, int reg, int data)
 232 {
 233         int timeout = 900000;
 234
 235         while (timeout > 0 && inb(devc->base) == 0x80)  /* Are we initializing */
 236                 timeout--;
 237
 238         if(reg < 32)
 239         {
 240                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 241                 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
 242         }
 243         else
 244         {
 245                 int xreg, xra;
 246
 247                 xreg = (reg & 0xff) - 32;
 248                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 249                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 250                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 251                 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
 252         }
 253 }
 254
 255 static void wait_for_calibration(ad1848_info * devc)
 256 {
 257         int timeout = 0;
 258
 259         /*
 260          * Wait until the auto calibration process has finished.
 261          *
 262          * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 263          * 2)       Wait until the ACI bit of I11 gets on and then off.
 264          */
 265
 266         timeout = 100000;
 267         while (timeout > 0 && inb(devc->base) == 0x80)
 268                 timeout--;
 269         if (inb(devc->base) & 0x80)
 270                 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
 271
 272         timeout = 100;
 273         while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
 274                 timeout--;
 275         if (!(ad_read(devc, 11) & 0x20))
 276                 return;
 277
 278         timeout = 80000;
 279         while (timeout > 0 && (ad_read(devc, 11) & 0x20))
 280                 timeout--;
 281         if (ad_read(devc, 11) & 0x20)
 282                 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
 283                         printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
 284 }
 285
 286 static void ad_mute(ad1848_info * devc)
 287 {
 288         int i;
 289         unsigned char prev;
 290
 291         /*
 292          * Save old register settings and mute output channels
 293          */
 294
 295         for (i = 6; i < 8; i++)
 296         {
 297                 prev = devc->saved_regs[i] = ad_read(devc, i);
 298         }
 299
 300 }
 301
 302 static void ad_unmute(ad1848_info * devc)
 303 {
 304 }
 305
 306 static void ad_enter_MCE(ad1848_info * devc)
 307 {
 308         int timeout = 1000;
 309         unsigned short prev;
 310
 311         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 312                 timeout--;
 313
 314         devc->MCE_bit = 0x40;
 315         prev = inb(io_Index_Addr(devc));
 316         if (prev & 0x40)
 317         {
 318                 return;
 319         }
 320         outb((devc->MCE_bit), io_Index_Addr(devc));
 321 }
 322
 323 static void ad_leave_MCE(ad1848_info * devc)
 324 {
 325         unsigned char prev, acal;
 326         int timeout = 1000;
 327
 328         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 329                 timeout--;
 330
 331         acal = ad_read(devc, 9);
 332
 333         devc->MCE_bit = 0x00;
 334         prev = inb(io_Index_Addr(devc));
 335         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 336
 337         if ((prev & 0x40) == 0) /* Not in MCE mode */
 338         {
 339                 return;
 340         }
 341         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 342         if (acal & 0x08)        /* Auto calibration is enabled */
 343                 wait_for_calibration(devc);
 344 }
 345
 346 static int ad1848_set_recmask(ad1848_info * devc, int mask)
 347 {
 348         unsigned char   recdev;
 349         int             i, n;
 350         unsigned long flags;
 351
 352         mask &= devc->supported_rec_devices;
 353
 354         /* Rename the mixer bits if necessary */
 355         for (i = 0; i < 32; i++)
 356         {
 357                 if (devc->mixer_reroute[i] != i)
 358                 {
 359                         if (mask & (1 << i))
 360                         {
 361                                 mask &= ~(1 << i);
 362                                 mask |= (1 << devc->mixer_reroute[i]);
 363                         }
 364                 }
 365         }
 366
 367         n = 0;
 368         for (i = 0; i < 32; i++)        /* Count selected device bits */
 369                 if (mask & (1 << i))
 370                         n++;
 371
 372         spin_lock_irqsave(&devc->lock,flags);
 373         if (!soundpro) {
 374                 if (n == 0)
 375                         mask = SOUND_MASK_MIC;
 376                 else if (n != 1) {      /* Too many devices selected */
 377                         mask &= ~devc->recmask; /* Filter out active settings */
 378
 379                         n = 0;
 380                         for (i = 0; i < 32; i++)        /* Count selected device bits */
 381                                 if (mask & (1 << i))
 382                                         n++;
 383
 384                         if (n != 1)
 385                                 mask = SOUND_MASK_MIC;
 386                 }
 387                 switch (mask) {
 388                 case SOUND_MASK_MIC:
 389                         recdev = 2;
 390                         break;
 391
 392                 case SOUND_MASK_LINE:
 393                 case SOUND_MASK_LINE3:
 394                         recdev = 0;
 395                         break;
 396
 397                 case SOUND_MASK_CD:
 398                 case SOUND_MASK_LINE1:
 399                         recdev = 1;
 400                         break;
 401
 402                 case SOUND_MASK_IMIX:
 403                         recdev = 3;
 404                         break;
 405
 406                 default:
 407                         mask = SOUND_MASK_MIC;
 408                         recdev = 2;
 409                 }
 410
 411                 recdev <<= 6;
 412                 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
 413                 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
 414         } else { /* soundpro */
 415                 unsigned char val;
 416                 int set_rec_bit;
 417                 int j;
 418
 419                 for (i = 0; i < 32; i++) {      /* For each bit */
 420                         if ((devc->supported_rec_devices & (1 << i)) == 0)
 421                                 continue;       /* Device not supported */
 422
 423                         for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
 424                                 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
 425                                         continue;
 426
 427                                 /*
 428                                  * This is tricky:
 429                                  * set_rec_bit becomes 1 if the corresponding bit in mask is set
 430                                  * then it gets flipped if the polarity is inverse
 431                                  */
 432                                 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
 433
 434                                 val = ad_read(devc, devc->mix_devices[i][j].recreg);
 435                                 val &= ~(1 << devc->mix_devices[i][j].recpos);
 436                                 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
 437                                 ad_write(devc, devc->mix_devices[i][j].recreg, val);
 438                         }
 439                 }
 440         }
 441         spin_unlock_irqrestore(&devc->lock,flags);
 442
 443         /* Rename the mixer bits back if necessary */
 444         for (i = 0; i < 32; i++)
 445         {
 446                 if (devc->mixer_reroute[i] != i)
 447                 {
 448                         if (mask & (1 << devc->mixer_reroute[i]))
 449                         {
 450                                 mask &= ~(1 << devc->mixer_reroute[i]);
 451                                 mask |= (1 << i);
 452                         }
 453                 }
 454         }
 455         devc->recmask = mask;
 456         return mask;
 457 }
 458
 459 static void change_bits(ad1848_info * devc, unsigned char *regval,
 460                         unsigned char *muteval, int dev, int chn, int newval)
 461 {
 462         unsigned char mask;
 463         int shift;
 464         int mute;
 465         int mutemask;
 466         int set_mute_bit;
 467
 468         set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
 469
 470         if (devc->mix_devices[dev][chn].polarity == 1)  /* Reverse */
 471                 newval = 100 - newval;
 472
 473         mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
 474         shift = devc->mix_devices[dev][chn].bitpos;
 475
 476         if (devc->mix_devices[dev][chn].mutepos == 8)
 477         {                       /* if there is no mute bit */
 478                 mute = 0;       /* No mute bit; do nothing special */
 479                 mutemask = ~0;  /* No mute bit; do nothing special */
 480         }
 481         else
 482         {
 483                 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
 484                 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
 485         }
 486
 487         newval = (int) ((newval * mask) + 50) / 100;    /* Scale it */
 488         *regval &= ~(mask << shift);                    /* Clear bits */
 489         *regval |= (newval & mask) << shift;            /* Set new value */
 490
 491         *muteval &= mutemask;
 492         *muteval |= mute;
 493 }
 494
 495 static int ad1848_mixer_get(ad1848_info * devc, int dev)
 496 {
 497         if (!((1 << dev) & devc->supported_devices))
 498                 return -EINVAL;
 499
 500         dev = devc->mixer_reroute[dev];
 501
 502         return devc->levels[dev];
 503 }
 504
 505 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
 506 {
 507         int regoffs, muteregoffs;
 508         unsigned char val, muteval;
 509         unsigned long flags;
 510
 511         regoffs = devc->mix_devices[dev][channel].regno;
 512         muteregoffs = devc->mix_devices[dev][channel].mutereg;
 513         val = ad_read(devc, regoffs);
 514
 515         if (muteregoffs != regoffs) {
 516                 muteval = ad_read(devc, muteregoffs);
 517                 change_bits(devc, &val, &muteval, dev, channel, value);
 518         }
 519         else
 520                 change_bits(devc, &val, &val, dev, channel, value);
 521
 522         spin_lock_irqsave(&devc->lock,flags);
 523         ad_write(devc, regoffs, val);
 524         devc->saved_regs[regoffs] = val;
 525         if (muteregoffs != regoffs) {
 526                 ad_write(devc, muteregoffs, muteval);
 527                 devc->saved_regs[muteregoffs] = muteval;
 528         }
 529         spin_unlock_irqrestore(&devc->lock,flags);
 530 }
 531
 532 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
 533 {
 534         int left = value & 0x000000ff;
 535         int right = (value & 0x0000ff00) >> 8;
 536         int retvol;
 537
 538         if (dev > 31)
 539                 return -EINVAL;
 540
 541         if (!(devc->supported_devices & (1 << dev)))
 542                 return -EINVAL;
 543
 544         dev = devc->mixer_reroute[dev];
 545
 546         if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
 547                 return -EINVAL;
 548
 549         if (left > 100)
 550                 left = 100;
 551         if (right > 100)
 552                 right = 100;
 553
 554         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)       /* Mono control */
 555                 right = left;
 556
 557         retvol = left | (right << 8);
 558
 559         /* Scale volumes */
 560         left = mix_cvt[left];
 561         right = mix_cvt[right];
 562
 563         devc->levels[dev] = retvol;
 564
 565         /*
 566          * Set the left channel
 567          */
 568         ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
 569
 570         /*
 571          * Set the right channel
 572          */
 573         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
 574                 goto out;
 575         ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
 576
 577  out:
 578         return retvol;
 579 }
 580
 581 static void ad1848_mixer_reset(ad1848_info * devc)
 582 {
 583         int i;
 584         char name[32];
 585         unsigned long flags;
 586
 587         devc->mix_devices = &(ad1848_mix_devices[0]);
 588
 589         sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
 590
 591         for (i = 0; i < 32; i++)
 592                 devc->mixer_reroute[i] = i;
 593
 594         devc->supported_rec_devices = MODE1_REC_DEVICES;
 595
 596         switch (devc->model)
 597         {
 598                 case MD_4231:
 599                 case MD_4231A:
 600                 case MD_1845:
 601                 case MD_1845_SSCAPE:
 602                         devc->supported_devices = MODE2_MIXER_DEVICES;
 603                         break;
 604
 605                 case MD_C930:
 606                         devc->supported_devices = C930_MIXER_DEVICES;
 607                         devc->mix_devices = &(c930_mix_devices[0]);
 608                         break;
 609
 610                 case MD_IWAVE:
 611                         devc->supported_devices = MODE3_MIXER_DEVICES;
 612                         devc->mix_devices = &(iwave_mix_devices[0]);
 613                         break;
 614
 615                 case MD_42xB:
 616                 case MD_4239:
 617                         devc->mix_devices = &(cs42xb_mix_devices[0]);
 618                         devc->supported_devices = MODE3_MIXER_DEVICES;
 619                         break;
 620                 case MD_4232:
 621                 case MD_4235:
 622                 case MD_4236:
 623                         devc->supported_devices = MODE3_MIXER_DEVICES;
 624                         break;
 625
 626                 case MD_1848:
 627                         if (soundpro) {
 628                                 devc->supported_devices = SPRO_MIXER_DEVICES;
 629                                 devc->supported_rec_devices = SPRO_REC_DEVICES;
 630                                 devc->mix_devices = &(spro_mix_devices[0]);
 631                                 break;
 632                         }
 633
 634                 default:
 635                         devc->supported_devices = MODE1_MIXER_DEVICES;
 636         }
 637
 638         devc->orig_devices = devc->supported_devices;
 639         devc->orig_rec_devices = devc->supported_rec_devices;
 640
 641         devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
 642
 643         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 644         {
 645                 if (devc->supported_devices & (1 << i))
 646                         ad1848_mixer_set(devc, i, devc->levels[i]);
 647         }
 648
 649         ad1848_set_recmask(devc, SOUND_MASK_MIC);
 650
 651         devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
 652
 653         spin_lock_irqsave(&devc->lock,flags);
 654         if (!soundpro) {
 655                 if (devc->mixer_output_port & AUDIO_SPEAKER)
 656                         ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 657                 else
 658                         ad_write(devc, 26, ad_read(devc, 26) | 0x40);   /* Mute mono out */
 659         } else {
 660                 /*
 661                  * From the "wouldn't it be nice if the mixer API had (better)
 662                  * support for custom stuff" category
 663                  */
 664                 /* Enable surround mode and SB16 mixer */
 665                 ad_write(devc, 16, 0x60);
 666         }
 667         spin_unlock_irqrestore(&devc->lock,flags);
 668 }
 669
 670 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
 671 {
 672         ad1848_info *devc = mixer_devs[dev]->devc;
 673         int val;
 674
 675         if (cmd == SOUND_MIXER_PRIVATE1)
 676         {
 677                 if (get_user(val, (int __user *)arg))
 678                         return -EFAULT;
 679
 680                 if (val != 0xffff)
 681                 {
 682                         unsigned long flags;
 683                         val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
 684                         devc->mixer_output_port = val;
 685                         val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT;        /* Always on */
 686                         devc->mixer_output_port = val;
 687                         spin_lock_irqsave(&devc->lock,flags);
 688                         if (val & AUDIO_SPEAKER)
 689                                 ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 690                         else
 691                                 ad_write(devc, 26, ad_read(devc, 26) | 0x40);           /* Mute mono out */
 692                         spin_unlock_irqrestore(&devc->lock,flags);
 693                 }
 694                 val = devc->mixer_output_port;
 695                 return put_user(val, (int __user *)arg);
 696         }
 697         if (cmd == SOUND_MIXER_PRIVATE2)
 698         {
 699                 if (get_user(val, (int __user *)arg))
 700                         return -EFAULT;
 701                 return(ad1848_control(AD1848_MIXER_REROUTE, val));
 702         }
 703         if (((cmd >> 8) & 0xff) == 'M')
 704         {
 705                 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
 706                 {
 707                         switch (cmd & 0xff)
 708                         {
 709                                 case SOUND_MIXER_RECSRC:
 710                                         if (get_user(val, (int __user *)arg))
 711                                                 return -EFAULT;
 712                                         val = ad1848_set_recmask(devc, val);
 713                                         break;
 714
 715                                 default:
 716                                         if (get_user(val, (int __user *)arg))
 717                                         return -EFAULT;
 718                                         val = ad1848_mixer_set(devc, cmd & 0xff, val);
 719                                         break;
 720                         }
 721                         return put_user(val, (int __user *)arg);
 722                 }
 723                 else
 724                 {
 725                         switch (cmd & 0xff)
 726                         {
 727                                 /*
 728                                  * Return parameters
 729                                  */
 730
 731                                 case SOUND_MIXER_RECSRC:
 732                                         val = devc->recmask;
 733                                         break;
 734
 735                                 case SOUND_MIXER_DEVMASK:
 736                                         val = devc->supported_devices;
 737                                         break;
 738
 739                                 case SOUND_MIXER_STEREODEVS:
 740                                         val = devc->supported_devices;
 741                                         if (devc->model != MD_C930)
 742                                                 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
 743                                         break;
 744
 745                                 case SOUND_MIXER_RECMASK:
 746                                         val = devc->supported_rec_devices;
 747                                         break;
 748
 749                                 case SOUND_MIXER_CAPS:
 750                                         val=SOUND_CAP_EXCL_INPUT;
 751                                         break;
 752
 753                                 default:
 754                                         val = ad1848_mixer_get(devc, cmd & 0xff);
 755                                         break;
 756                         }
 757                         return put_user(val, (int __user *)arg);
 758                 }
 759         }
 760         else
 761                 return -EINVAL;
 762 }
 763
 764 static int ad1848_set_speed(int dev, int arg)
 765 {
 766         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
 767         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 768
 769         /*
 770          * The sampling speed is encoded in the least significant nibble of I8. The
 771          * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
 772          * three bits select the divisor (indirectly):
 773          *
 774          * The available speeds are in the following table. Keep the speeds in
 775          * the increasing order.
 776          */
 777         typedef struct
 778         {
 779                 int             speed;
 780                 unsigned char   bits;
 781         }
 782         speed_struct;
 783
 784         static speed_struct speed_table[] =
 785         {
 786                 {5510, (0 << 1) | 1},
 787                 {5510, (0 << 1) | 1},
 788                 {6620, (7 << 1) | 1},
 789                 {8000, (0 << 1) | 0},
 790                 {9600, (7 << 1) | 0},
 791                 {11025, (1 << 1) | 1},
 792                 {16000, (1 << 1) | 0},
 793                 {18900, (2 << 1) | 1},
 794                 {22050, (3 << 1) | 1},
 795                 {27420, (2 << 1) | 0},
 796                 {32000, (3 << 1) | 0},
 797                 {33075, (6 << 1) | 1},
 798                 {37800, (4 << 1) | 1},
 799                 {44100, (5 << 1) | 1},
 800                 {48000, (6 << 1) | 0}
 801         };
 802
 803         int i, n, selected = -1;
 804
 805         n = sizeof(speed_table) / sizeof(speed_struct);
 806
 807         if (arg <= 0)
 808                 return portc->speed;
 809
 810         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)    /* AD1845 has different timer than others */
 811         {
 812                 if (arg < 4000)
 813                         arg = 4000;
 814                 if (arg > 50000)
 815                         arg = 50000;
 816
 817                 portc->speed = arg;
 818                 portc->speed_bits = speed_table[3].bits;
 819                 return portc->speed;
 820         }
 821         if (arg < speed_table[0].speed)
 822                 selected = 0;
 823         if (arg > speed_table[n - 1].speed)
 824                 selected = n - 1;
 825
 826         for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 827         {
 828                 if (speed_table[i].speed == arg)
 829                         selected = i;
 830                 else if (speed_table[i].speed > arg)
 831                 {
 832                         int diff1, diff2;
 833
 834                         diff1 = arg - speed_table[i - 1].speed;
 835                         diff2 = speed_table[i].speed - arg;
 836
 837                         if (diff1 < diff2)
 838                                 selected = i - 1;
 839                         else
 840                                 selected = i;
 841                 }
 842         }
 843         if (selected == -1)
 844         {
 845                 printk(KERN_WARNING "ad1848: Can't find speed???\n");
 846                 selected = 3;
 847         }
 848         portc->speed = speed_table[selected].speed;
 849         portc->speed_bits = speed_table[selected].bits;
 850         return portc->speed;
 851 }
 852
 853 static short ad1848_set_channels(int dev, short arg)
 854 {
 855         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 856
 857         if (arg != 1 && arg != 2)
 858                 return portc->channels;
 859
 860         portc->channels = arg;
 861         return arg;
 862 }
 863
 864 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
 865 {
 866         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 867         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 868
 869         static struct format_tbl
 870         {
 871                   int             format;
 872                   unsigned char   bits;
 873         }
 874         format2bits[] =
 875         {
 876                 {
 877                         0, 0
 878                 }
 879                 ,
 880                 {
 881                         AFMT_MU_LAW, 1
 882                 }
 883                 ,
 884                 {
 885                         AFMT_A_LAW, 3
 886                 }
 887                 ,
 888                 {
 889                         AFMT_IMA_ADPCM, 5
 890                 }
 891                 ,
 892                 {
 893                         AFMT_U8, 0
 894                 }
 895                 ,
 896                 {
 897                         AFMT_S16_LE, 2
 898                 }
 899                 ,
 900                 {
 901                         AFMT_S16_BE, 6
 902                 }
 903                 ,
 904                 {
 905                         AFMT_S8, 0
 906                 }
 907                 ,
 908                 {
 909                         AFMT_U16_LE, 0
 910                 }
 911                 ,
 912                 {
 913                         AFMT_U16_BE, 0
 914                 }
 915         };
 916         int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
 917
 918         if (arg == 0)
 919                 return portc->audio_format;
 920
 921         if (!(arg & ad_format_mask[devc->model]))
 922                 arg = AFMT_U8;
 923
 924         portc->audio_format = arg;
 925
 926         for (i = 0; i < n; i++)
 927                 if (format2bits[i].format == arg)
 928                 {
 929                         if ((portc->format_bits = format2bits[i].bits) == 0)
 930                                 return portc->audio_format = AFMT_U8;           /* Was not supported */
 931
 932                         return arg;
 933                 }
 934         /* Still hanging here. Something must be terribly wrong */
 935         portc->format_bits = 0;
 936         return portc->audio_format = AFMT_U8;
 937 }
 938
 939 static struct audio_driver ad1848_audio_driver =
 940 {
 941         .owner                  = THIS_MODULE,
 942         .open                   = ad1848_open,
 943         .close                  = ad1848_close,
 944         .output_block           = ad1848_output_block,
 945         .start_input            = ad1848_start_input,
 946         .prepare_for_input      = ad1848_prepare_for_input,
 947         .prepare_for_output     = ad1848_prepare_for_output,
 948         .halt_io                = ad1848_halt,
 949         .halt_input             = ad1848_halt_input,
 950         .halt_output            = ad1848_halt_output,
 951         .trigger                = ad1848_trigger,
 952         .set_speed              = ad1848_set_speed,
 953         .set_bits               = ad1848_set_bits,
 954         .set_channels           = ad1848_set_channels
 955 };
 956
 957 static struct mixer_operations ad1848_mixer_operations =
 958 {
 959         .owner  = THIS_MODULE,
 960         .id     = "SOUNDPORT",
 961         .name   = "AD1848/CS4248/CS4231",
 962         .ioctl  = ad1848_mixer_ioctl
 963 };
 964
 965 static int ad1848_open(int dev, int mode)
 966 {
 967         ad1848_info    *devc;
 968         ad1848_port_info *portc;
 969         unsigned long   flags;
 970
 971         if (dev < 0 || dev >= num_audiodevs)
 972                 return -ENXIO;
 973
 974         devc = (ad1848_info *) audio_devs[dev]->devc;
 975         portc = (ad1848_port_info *) audio_devs[dev]->portc;
 976
 977         /* here we don't have to protect against intr */
 978         spin_lock(&devc->lock);
 979         if (portc->open_mode || (devc->open_mode & mode))
 980         {
 981                 spin_unlock(&devc->lock);
 982                 return -EBUSY;
 983         }
 984         devc->dual_dma = 0;
 985
 986         if (audio_devs[dev]->flags & DMA_DUPLEX)
 987         {
 988                 devc->dual_dma = 1;
 989         }
 990         devc->intr_active = 0;
 991         devc->audio_mode = 0;
 992         devc->open_mode |= mode;
 993         portc->open_mode = mode;
 994         spin_unlock(&devc->lock);
 995         ad1848_trigger(dev, 0);
 996
 997         if (mode & OPEN_READ)
 998                 devc->record_dev = dev;
 999         if (mode & OPEN_WRITE)
1000                 devc->playback_dev = dev;
1001 /*
1002  * Mute output until the playback really starts. This decreases clicking (hope so).
1003  */
1004         spin_lock_irqsave(&devc->lock,flags);
1005         ad_mute(devc);
1006         spin_unlock_irqrestore(&devc->lock,flags);
1007
1008         return 0;
1009 }
1010
1011 static void ad1848_close(int dev)
1012 {
1013         unsigned long   flags;
1014         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1015         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1016
1017         DEB(printk("ad1848_close(void)\n"));
1018
1019         devc->intr_active = 0;
1020         ad1848_halt(dev);
1021
1022         spin_lock_irqsave(&devc->lock,flags);
1023
1024         devc->audio_mode = 0;
1025         devc->open_mode &= ~portc->open_mode;
1026         portc->open_mode = 0;
1027
1028         ad_unmute(devc);
1029         spin_unlock_irqrestore(&devc->lock,flags);
1030 }
1031
1032 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1033 {
1034         unsigned long   flags, cnt;
1035         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1036         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1037
1038         cnt = count;
1039
1040         if (portc->audio_format == AFMT_IMA_ADPCM)
1041         {
1042                 cnt /= 4;
1043         }
1044         else
1045         {
1046                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1047                         cnt >>= 1;
1048         }
1049         if (portc->channels > 1)
1050                 cnt >>= 1;
1051         cnt--;
1052
1053         if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1054             intrflag &&
1055             cnt == devc->xfer_count)
1056         {
1057                 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1058                 devc->intr_active = 1;
1059                 return; /*
1060                          * Auto DMA mode on. No need to react
1061                          */
1062         }
1063         spin_lock_irqsave(&devc->lock,flags);
1064
1065         ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1066         ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1067
1068         devc->xfer_count = cnt;
1069         devc->audio_mode |= PCM_ENABLE_OUTPUT;
1070         devc->intr_active = 1;
1071         spin_unlock_irqrestore(&devc->lock,flags);
1072 }
1073
1074 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1075 {
1076         unsigned long   flags, cnt;
1077         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1078         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1079
1080         cnt = count;
1081         if (portc->audio_format == AFMT_IMA_ADPCM)
1082         {
1083                 cnt /= 4;
1084         }
1085         else
1086         {
1087                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1088                         cnt >>= 1;
1089         }
1090         if (portc->channels > 1)
1091                 cnt >>= 1;
1092         cnt--;
1093
1094         if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1095                 intrflag &&
1096                 cnt == devc->xfer_count)
1097         {
1098                 devc->audio_mode |= PCM_ENABLE_INPUT;
1099                 devc->intr_active = 1;
1100                 return; /*
1101                          * Auto DMA mode on. No need to react
1102                          */
1103         }
1104         spin_lock_irqsave(&devc->lock,flags);
1105
1106         if (devc->model == MD_1848)
1107         {
1108                   ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1109                   ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1110         }
1111         else
1112         {
1113                   ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1114                   ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1115         }
1116
1117         ad_unmute(devc);
1118
1119         devc->xfer_count = cnt;
1120         devc->audio_mode |= PCM_ENABLE_INPUT;
1121         devc->intr_active = 1;
1122         spin_unlock_irqrestore(&devc->lock,flags);
1123 }
1124
1125 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1126 {
1127         int             timeout;
1128         unsigned char   fs, old_fs, tmp = 0;
1129         unsigned long   flags;
1130         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1131         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1132
1133         ad_mute(devc);
1134
1135         spin_lock_irqsave(&devc->lock,flags);
1136         fs = portc->speed_bits | (portc->format_bits << 5);
1137
1138         if (portc->channels > 1)
1139                 fs |= 0x10;
1140
1141         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1142
1143         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1144         {
1145                 fs &= 0xf0;     /* Mask off the rate select bits */
1146
1147                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1148                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1149         }
1150         old_fs = ad_read(devc, 8);
1151
1152         if (devc->model == MD_4232 || devc->model >= MD_4236)
1153         {
1154                 tmp = ad_read(devc, 16);
1155                 ad_write(devc, 16, tmp | 0x30);
1156         }
1157         if (devc->model == MD_IWAVE)
1158                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1159
1160         ad_write(devc, 8, fs);
1161
1162         /*
1163          * Write to I8 starts resynchronization. Wait until it completes.
1164          */
1165
1166         timeout = 0;
1167         while (timeout < 100 && inb(devc->base) != 0x80)
1168                 timeout++;
1169         timeout = 0;
1170         while (timeout < 10000 && inb(devc->base) == 0x80)
1171                 timeout++;
1172
1173         if (devc->model >= MD_4232)
1174                 ad_write(devc, 16, tmp & ~0x30);
1175
1176         ad_leave_MCE(devc);     /*
1177                                  * Starts the calibration process.
1178                                  */
1179         spin_unlock_irqrestore(&devc->lock,flags);
1180         devc->xfer_count = 0;
1181
1182 #ifndef EXCLUDE_TIMERS
1183         if (dev == timer_installed && devc->timer_running)
1184                 if ((fs & 0x01) != (old_fs & 0x01))
1185                 {
1186                         ad1848_tmr_reprogram(dev);
1187                 }
1188 #endif
1189         ad1848_halt_output(dev);
1190         return 0;
1191 }
1192
1193 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1194 {
1195         int timeout;
1196         unsigned char fs, old_fs, tmp = 0;
1197         unsigned long flags;
1198         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1199         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1200
1201         if (devc->audio_mode)
1202                 return 0;
1203
1204         spin_lock_irqsave(&devc->lock,flags);
1205         fs = portc->speed_bits | (portc->format_bits << 5);
1206
1207         if (portc->channels > 1)
1208                 fs |= 0x10;
1209
1210         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1211
1212         if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE))        /* Use alternate speed select registers */
1213         {
1214                 fs &= 0xf0;     /* Mask off the rate select bits */
1215
1216                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1217                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1218         }
1219         if (devc->model == MD_4232)
1220         {
1221                 tmp = ad_read(devc, 16);
1222                 ad_write(devc, 16, tmp | 0x30);
1223         }
1224         if (devc->model == MD_IWAVE)
1225                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1226
1227         /*
1228          * If mode >= 2 (CS4231), set I28. It's the capture format register.
1229          */
1230
1231         if (devc->model != MD_1848)
1232         {
1233                 old_fs = ad_read(devc, 28);
1234                 ad_write(devc, 28, fs);
1235
1236                 /*
1237                  * Write to I28 starts resynchronization. Wait until it completes.
1238                  */
1239
1240                 timeout = 0;
1241                 while (timeout < 100 && inb(devc->base) != 0x80)
1242                         timeout++;
1243
1244                 timeout = 0;
1245                 while (timeout < 10000 && inb(devc->base) == 0x80)
1246                         timeout++;
1247
1248                 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1249                 {
1250                         /*
1251                          * CS4231 compatible devices don't have separate sampling rate selection
1252                          * register for recording an playback. The I8 register is shared so we have to
1253                          * set the speed encoding bits of it too.
1254                          */
1255                         unsigned char   tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1256
1257                         ad_write(devc, 8, tmp);
1258                         /*
1259                          * Write to I8 starts resynchronization. Wait until it completes.
1260                          */
1261                         timeout = 0;
1262                         while (timeout < 100 && inb(devc->base) != 0x80)
1263                                 timeout++;
1264
1265                         timeout = 0;
1266                         while (timeout < 10000 && inb(devc->base) == 0x80)
1267                                 timeout++;
1268                 }
1269         }
1270         else
1271         {                       /* For AD1848 set I8. */
1272
1273                 old_fs = ad_read(devc, 8);
1274                 ad_write(devc, 8, fs);
1275                 /*
1276                  * Write to I8 starts resynchronization. Wait until it completes.
1277                  */
1278                 timeout = 0;
1279                 while (timeout < 100 && inb(devc->base) != 0x80)
1280                         timeout++;
1281                 timeout = 0;
1282                 while (timeout < 10000 && inb(devc->base) == 0x80)
1283                         timeout++;
1284         }
1285
1286         if (devc->model == MD_4232)
1287                 ad_write(devc, 16, tmp & ~0x30);
1288
1289         ad_leave_MCE(devc);     /*
1290                                  * Starts the calibration process.
1291                                  */
1292         spin_unlock_irqrestore(&devc->lock,flags);
1293         devc->xfer_count = 0;
1294
1295 #ifndef EXCLUDE_TIMERS
1296         if (dev == timer_installed && devc->timer_running)
1297         {
1298                 if ((fs & 0x01) != (old_fs & 0x01))
1299                 {
1300                         ad1848_tmr_reprogram(dev);
1301                 }
1302         }
1303 #endif
1304         ad1848_halt_input(dev);
1305         return 0;
1306 }
1307
1308 static void ad1848_halt(int dev)
1309 {
1310         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1311         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1312
1313         unsigned char   bits = ad_read(devc, 9);
1314
1315         if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1316                 ad1848_halt_output(dev);
1317
1318         if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1319                 ad1848_halt_input(dev);
1320         devc->audio_mode = 0;
1321 }
1322
1323 static void ad1848_halt_input(int dev)
1324 {
1325         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1326         unsigned long   flags;
1327
1328         if (!(ad_read(devc, 9) & 0x02))
1329                 return;         /* Capture not enabled */
1330
1331         spin_lock_irqsave(&devc->lock,flags);
1332
1333         ad_mute(devc);
1334
1335         {
1336                 int             tmout;
1337
1338                 if(!isa_dma_bridge_buggy)
1339                         disable_dma(audio_devs[dev]->dmap_in->dma);
1340
1341                 for (tmout = 0; tmout < 100000; tmout++)
1342                         if (ad_read(devc, 11) & 0x10)
1343                                 break;
1344                 ad_write(devc, 9, ad_read(devc, 9) & ~0x02);    /* Stop capture */
1345
1346                 if(!isa_dma_bridge_buggy)
1347                         enable_dma(audio_devs[dev]->dmap_in->dma);
1348                 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1349         }
1350
1351         outb(0, io_Status(devc));       /* Clear interrupt status */
1352         outb(0, io_Status(devc));       /* Clear interrupt status */
1353
1354         devc->audio_mode &= ~PCM_ENABLE_INPUT;
1355
1356         spin_unlock_irqrestore(&devc->lock,flags);
1357 }
1358
1359 static void ad1848_halt_output(int dev)
1360 {
1361         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1362         unsigned long flags;
1363
1364         if (!(ad_read(devc, 9) & 0x01))
1365                 return;         /* Playback not enabled */
1366
1367         spin_lock_irqsave(&devc->lock,flags);
1368
1369         ad_mute(devc);
1370         {
1371                 int             tmout;
1372
1373                 if(!isa_dma_bridge_buggy)
1374                         disable_dma(audio_devs[dev]->dmap_out->dma);
1375
1376                 for (tmout = 0; tmout < 100000; tmout++)
1377                         if (ad_read(devc, 11) & 0x10)
1378                                 break;
1379                 ad_write(devc, 9, ad_read(devc, 9) & ~0x01);    /* Stop playback */
1380
1381                 if(!isa_dma_bridge_buggy)
1382                        enable_dma(audio_devs[dev]->dmap_out->dma);
1383
1384                 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1385         }
1386
1387         outb((0), io_Status(devc));     /* Clear interrupt status */
1388         outb((0), io_Status(devc));     /* Clear interrupt status */
1389
1390         devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1391
1392         spin_unlock_irqrestore(&devc->lock,flags);
1393 }
1394
1395 static void ad1848_trigger(int dev, int state)
1396 {
1397         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1398         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1399         unsigned long   flags;
1400         unsigned char   tmp, old;
1401
1402         spin_lock_irqsave(&devc->lock,flags);
1403         state &= devc->audio_mode;
1404
1405         tmp = old = ad_read(devc, 9);
1406
1407         if (portc->open_mode & OPEN_READ)
1408         {
1409                   if (state & PCM_ENABLE_INPUT)
1410                           tmp |= 0x02;
1411                   else
1412                           tmp &= ~0x02;
1413         }
1414         if (portc->open_mode & OPEN_WRITE)
1415         {
1416                 if (state & PCM_ENABLE_OUTPUT)
1417                         tmp |= 0x01;
1418                 else
1419                         tmp &= ~0x01;
1420         }
1421         /* ad_mute(devc); */
1422         if (tmp != old)
1423         {
1424                   ad_write(devc, 9, tmp);
1425                   ad_unmute(devc);
1426         }
1427         spin_unlock_irqrestore(&devc->lock,flags);
1428 }
1429
1430 static void ad1848_init_hw(ad1848_info * devc)
1431 {
1432         int i;
1433         int *init_values;
1434
1435         /*
1436          * Initial values for the indirect registers of CS4248/AD1848.
1437          */
1438         static int      init_values_a[] =
1439         {
1440                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1441                 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1442
1443         /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1444                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1445                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1446         };
1447
1448         static int      init_values_b[] =
1449         {
1450                 /*
1451                    Values for the newer chips
1452                    Some of the register initialization values were changed. In
1453                    order to get rid of the click that preceded PCM playback,
1454                    calibration was disabled on the 10th byte. On that same byte,
1455                    dual DMA was enabled; on the 11th byte, ADC dithering was
1456                    enabled, since that is theoretically desirable; on the 13th
1457                    byte, Mode 3 was selected, to enable access to extended
1458                    registers.
1459                  */
1460                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1461                 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1462                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1463                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1464         };
1465
1466         /*
1467          *      Select initialisation data
1468          */
1469
1470         init_values = init_values_a;
1471         if(devc->model >= MD_4236)
1472                 init_values = init_values_b;
1473
1474         for (i = 0; i < 16; i++)
1475                 ad_write(devc, i, init_values[i]);
1476
1477
1478         ad_mute(devc);          /* Initialize some variables */
1479         ad_unmute(devc);        /* Leave it unmuted now */
1480
1481         if (devc->model > MD_1848)
1482         {
1483                 if (devc->model == MD_1845_SSCAPE)
1484                         ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1485                 else
1486                         ad_write(devc, 12, ad_read(devc, 12) | 0x40);           /* Mode2 = enabled */
1487
1488                 if (devc->model == MD_IWAVE)
1489                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1490
1491                 if (devc->model != MD_1845_SSCAPE)
1492                         for (i = 16; i < 32; i++)
1493                                 ad_write(devc, i, init_values[i]);
1494
1495                 if (devc->model == MD_IWAVE)
1496                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1497         }
1498         if (devc->model > MD_1848)
1499         {
1500                 if (devc->audio_flags & DMA_DUPLEX)
1501                         ad_write(devc, 9, ad_read(devc, 9) & ~0x04);    /* Dual DMA mode */
1502                 else
1503                         ad_write(devc, 9, ad_read(devc, 9) | 0x04);     /* Single DMA mode */
1504
1505                 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1506                         ad_write(devc, 27, ad_read(devc, 27) | 0x08);           /* Alternate freq select enabled */
1507
1508                 if (devc->model == MD_IWAVE)
1509                 {               /* Some magic Interwave specific initialization */
1510                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1511                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1512                         ad_write(devc, 17, 0xc2);       /* Alternate feature enable */
1513                 }
1514         }
1515         else
1516         {
1517                   devc->audio_flags &= ~DMA_DUPLEX;
1518                   ad_write(devc, 9, ad_read(devc, 9) | 0x04);   /* Single DMA mode */
1519                   if (soundpro)
1520                           ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1521         }
1522
1523         outb((0), io_Status(devc));     /* Clear pending interrupts */
1524
1525         /*
1526          * Toggle the MCE bit. It completes the initialization phase.
1527          */
1528
1529         ad_enter_MCE(devc);     /* In case the bit was off */
1530         ad_leave_MCE(devc);
1531
1532         ad1848_mixer_reset(devc);
1533 }
1534
1535 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1536 {
1537         unsigned char tmp;
1538         ad1848_info *devc = &adev_info[nr_ad1848_devs];
1539         unsigned char tmp1 = 0xff, tmp2 = 0xff;
1540         int optiC930 = 0;       /* OPTi 82C930 flag */
1541         int interwave = 0;
1542         int ad1847_flag = 0;
1543         int cs4248_flag = 0;
1544         int sscape_flag = 0;
1545         int io_base = ports->start;
1546
1547         int i;
1548
1549         DDB(printk("ad1848_detect(%x)\n", io_base));
1550
1551         if (ad_flags)
1552         {
1553                 if (*ad_flags == 0x12345678)
1554                 {
1555                         interwave = 1;
1556                         *ad_flags = 0;
1557                 }
1558
1559                 if (*ad_flags == 0x87654321)
1560                 {
1561                         sscape_flag = 1;
1562                         *ad_flags = 0;
1563                 }
1564
1565                 if (*ad_flags == 0x12345677)
1566                 {
1567                     cs4248_flag = 1;
1568                     *ad_flags = 0;
1569                 }
1570         }
1571         if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1572         {
1573                 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1574                 return 0;
1575         }
1576         spin_lock_init(&devc->lock);
1577         devc->base = io_base;
1578         devc->irq_ok = 0;
1579         devc->timer_running = 0;
1580         devc->MCE_bit = 0x40;
1581         devc->irq = 0;
1582         devc->open_mode = 0;
1583         devc->chip_name = devc->name = "AD1848";
1584         devc->model = MD_1848;  /* AD1848 or CS4248 */
1585         devc->levels = NULL;
1586         devc->debug_flag = 0;
1587
1588         /*
1589          * Check that the I/O address is in use.
1590          *
1591          * The bit 0x80 of the base I/O port is known to be 0 after the
1592          * chip has performed its power on initialization. Just assume
1593          * this has happened before the OS is starting.
1594          *
1595          * If the I/O address is unused, it typically returns 0xff.
1596          */
1597
1598         if (inb(devc->base) == 0xff)
1599         {
1600                 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1601         }
1602
1603         /*
1604          * Wait for the device to stop initialization
1605          */
1606
1607         DDB(printk("ad1848_detect() - step 0\n"));
1608
1609         for (i = 0; i < 10000000; i++)
1610         {
1611                 unsigned char   x = inb(devc->base);
1612
1613                 if (x == 0xff || !(x & 0x80))
1614                         break;
1615         }
1616
1617         DDB(printk("ad1848_detect() - step A\n"));
1618
1619         if (inb(devc->base) == 0x80)    /* Not ready. Let's wait */
1620                 ad_leave_MCE(devc);
1621
1622         if ((inb(devc->base) & 0x80) != 0x00)   /* Not a AD1848 */
1623         {
1624                 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1625                 return 0;
1626         }
1627
1628         /*
1629          * Test if it's possible to change contents of the indirect registers.
1630          * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1631          * so try to avoid using it.
1632          */
1633
1634         DDB(printk("ad1848_detect() - step B\n"));
1635         ad_write(devc, 0, 0xaa);
1636         ad_write(devc, 1, 0x45);        /* 0x55 with bit 0x10 clear */
1637
1638         if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1639         {
1640                 if (tmp2 == 0x65)       /* AD1847 has couple of bits hardcoded to 1 */
1641                         ad1847_flag = 1;
1642                 else
1643                 {
1644                         DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1645                         return 0;
1646                 }
1647         }
1648         DDB(printk("ad1848_detect() - step C\n"));
1649         ad_write(devc, 0, 0x45);
1650         ad_write(devc, 1, 0xaa);
1651
1652         if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1653         {
1654                 if (tmp2 == 0x8a)       /* AD1847 has few bits hardcoded to 1 */
1655                         ad1847_flag = 1;
1656                 else
1657                 {
1658                         DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1659                         return 0;
1660                 }
1661         }
1662
1663         /*
1664          * The indirect register I12 has some read only bits. Let's
1665          * try to change them.
1666          */
1667
1668         DDB(printk("ad1848_detect() - step D\n"));
1669         tmp = ad_read(devc, 12);
1670         ad_write(devc, 12, (~tmp) & 0x0f);
1671
1672         if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1673         {
1674                 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1675                 return 0;
1676         }
1677
1678         /*
1679          * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1680          *   0x01=RevB and 0x0A=RevC.
1681          */
1682
1683         /*
1684          * The original AD1848/CS4248 has just 15 indirect registers. This means
1685          * that I0 and I16 should return the same value (etc.).
1686          * However this doesn't work with CS4248. Actually it seems to be impossible
1687          * to detect if the chip is a CS4231 or CS4248.
1688          * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1689          * with CS4231.
1690          */
1691
1692         /*
1693          * OPTi 82C930 has mode2 control bit in another place. This test will fail
1694          * with it. Accept this situation as a possible indication of this chip.
1695          */
1696
1697         DDB(printk("ad1848_detect() - step F\n"));
1698         ad_write(devc, 12, 0);  /* Mode2=disabled */
1699
1700         for (i = 0; i < 16; i++)
1701         {
1702                 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1703                 {
1704                         DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1705                         if (!ad1847_flag)
1706                                 optiC930 = 1;
1707                         break;
1708                 }
1709         }
1710
1711         /*
1712          * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1713          * The bit 0x80 is always 1 in CS4248 and CS4231.
1714          */
1715
1716         DDB(printk("ad1848_detect() - step G\n"));
1717
1718         if (ad_flags && *ad_flags == 400)
1719                 *ad_flags = 0;
1720         else
1721                 ad_write(devc, 12, 0x40);       /* Set mode2, clear 0x80 */
1722
1723
1724         if (ad_flags)
1725                 *ad_flags = 0;
1726
1727         tmp1 = ad_read(devc, 12);
1728         if (tmp1 & 0x80)
1729         {
1730                 if (ad_flags)
1731                         *ad_flags |= AD_F_CS4248;
1732
1733                 devc->chip_name = "CS4248";     /* Our best knowledge just now */
1734         }
1735         if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1736         {
1737                 /*
1738                  *      CS4231 detected - is it?
1739                  *
1740                  *      Verify that setting I0 doesn't change I16.
1741                  */
1742
1743                 DDB(printk("ad1848_detect() - step H\n"));
1744                 ad_write(devc, 16, 0);  /* Set I16 to known value */
1745
1746                 ad_write(devc, 0, 0x45);
1747                 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1748                 {
1749                         ad_write(devc, 0, 0xaa);
1750                         if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1751                         {
1752                                 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1753                                 return 0;
1754                         }
1755
1756                         /*
1757                          * Verify that some bits of I25 are read only.
1758                          */
1759
1760                         DDB(printk("ad1848_detect() - step I\n"));
1761                         tmp1 = ad_read(devc, 25);       /* Original bits */
1762                         ad_write(devc, 25, ~tmp1);      /* Invert all bits */
1763                         if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1764                         {
1765                                 int id;
1766
1767                                 /*
1768                                  *      It's at least CS4231
1769                                  */
1770
1771                                 devc->chip_name = "CS4231";
1772                                 devc->model = MD_4231;
1773
1774                                 /*
1775                                  * It could be an AD1845 or CS4231A as well.
1776                                  * CS4231 and AD1845 report the same revision info in I25
1777                                  * while the CS4231A reports different.
1778                                  */
1779
1780                                 id = ad_read(devc, 25);
1781                                 if ((id & 0xe7) == 0x80)        /* Device busy??? */
1782                                         id = ad_read(devc, 25);
1783                                 if ((id & 0xe7) == 0x80)        /* Device still busy??? */
1784                                         id = ad_read(devc, 25);
1785                                 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1786
1787                                 if ((id & 0xe7) == 0x80) {
1788                                         /*
1789                                          * It must be a CS4231 or AD1845. The register I23 of
1790                                          * CS4231 is undefined and it appears to be read only.
1791                                          * AD1845 uses I23 for setting sample rate. Assume
1792                                          * the chip is AD1845 if I23 is changeable.
1793                                          */
1794
1795                                         unsigned char   tmp = ad_read(devc, 23);
1796                                         ad_write(devc, 23, ~tmp);
1797
1798                                         if (interwave)
1799                                         {
1800                                                 devc->model = MD_IWAVE;
1801                                                 devc->chip_name = "IWave";
1802                                         }
1803                                         else if (ad_read(devc, 23) != tmp)      /* AD1845 ? */
1804                                         {
1805                                                 devc->chip_name = "AD1845";
1806                                                 devc->model = MD_1845;
1807                                         }
1808                                         else if (cs4248_flag)
1809                                         {
1810                                                 if (ad_flags)
1811                                                           *ad_flags |= AD_F_CS4248;
1812                                                 devc->chip_name = "CS4248";
1813                                                 devc->model = MD_1848;
1814                                                 ad_write(devc, 12, ad_read(devc, 12) & ~0x40);  /* Mode2 off */
1815                                         }
1816                                         ad_write(devc, 23, tmp);        /* Restore */
1817                                 }
1818                                 else
1819                                 {
1820                                         switch (id & 0x1f) {
1821                                         case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1822                                                 {
1823                                                         int xid;
1824                                                         ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1825                                                         ad_write(devc, 23, 0x9c); /* select extended register 25 */
1826                                                         xid = inb(io_Indexed_Data(devc));
1827                                                         ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1828                                                         switch (xid & 0x1f)
1829                                                         {
1830                                                                 case 0x00:
1831                                                                         devc->chip_name = "CS4237B(B)";
1832                                                                         devc->model = MD_42xB;
1833                                                                         break;
1834                                                                 case 0x08:
1835                                                                         /* Seems to be a 4238 ?? */
1836                                                                         devc->chip_name = "CS4238";
1837                                                                         devc->model = MD_42xB;
1838                                                                         break;
1839                                                                 case 0x09:
1840                                                                         devc->chip_name = "CS4238B";
1841                                                                         devc->model = MD_42xB;
1842                                                                         break;
1843                                                                 case 0x0b:
1844                                                                         devc->chip_name = "CS4236B";
1845                                                                         devc->model = MD_4236;
1846                                                                         break;
1847                                                                 case 0x10:
1848                                                                         devc->chip_name = "CS4237B";
1849                                                                         devc->model = MD_42xB;
1850                                                                         break;
1851                                                                 case 0x1d:
1852                                                                         devc->chip_name = "CS4235";
1853                                                                         devc->model = MD_4235;
1854                                                                         break;
1855                                                                 case 0x1e:
1856                                                                         devc->chip_name = "CS4239";
1857                                                                         devc->model = MD_4239;
1858                                                                         break;
1859                                                                 default:
1860                                                                         printk("Chip ident is %X.\n", xid&0x1F);
1861                                                                         devc->chip_name = "CS42xx";
1862                                                                         devc->model = MD_4232;
1863                                                                         break;
1864                                                         }
1865                                                 }
1866                                                 break;
1867
1868                                         case 2: /* CS4232/CS4232A */
1869                                                 devc->chip_name = "CS4232";
1870                                                 devc->model = MD_4232;
1871                                                 break;
1872
1873                                         case 0:
1874                                                 if ((id & 0xe0) == 0xa0)
1875                                                 {
1876                                                         devc->chip_name = "CS4231A";
1877                                                         devc->model = MD_4231A;
1878                                                 }
1879                                                 else
1880                                                 {
1881                                                         devc->chip_name = "CS4321";
1882                                                         devc->model = MD_4231;
1883                                                 }
1884                                                 break;
1885
1886                                         default: /* maybe */
1887                                                 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1888                                                 if (optiC930)
1889                                                 {
1890                                                         devc->chip_name = "82C930";
1891                                                         devc->model = MD_C930;
1892                                                 }
1893                                                 else
1894                                                 {
1895                                                         devc->chip_name = "CS4231";
1896                                                         devc->model = MD_4231;
1897                                                 }
1898                                         }
1899                                 }
1900                         }
1901                         ad_write(devc, 25, tmp1);       /* Restore bits */
1902
1903                         DDB(printk("ad1848_detect() - step K\n"));
1904                 }
1905         } else if (tmp1 == 0x0a) {
1906                 /*
1907                  * Is it perhaps a SoundPro CMI8330?
1908                  * If so, then we should be able to change indirect registers
1909                  * greater than I15 after activating MODE2, even though reading
1910                  * back I12 does not show it.
1911                  */
1912
1913                 /*
1914                  * Let's try comparing register values
1915                  */
1916                 for (i = 0; i < 16; i++) {
1917                         if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1918                                 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1919                                 soundpro = 1;
1920                                 devc->chip_name = "SoundPro CMI 8330";
1921                                 break;
1922                         }
1923                 }
1924         }
1925
1926         DDB(printk("ad1848_detect() - step L\n"));
1927         if (ad_flags)
1928         {
1929                   if (devc->model != MD_1848)
1930                           *ad_flags |= AD_F_CS4231;
1931         }
1932         DDB(printk("ad1848_detect() - Detected OK\n"));
1933
1934         if (devc->model == MD_1848 && ad1847_flag)
1935                 devc->chip_name = "AD1847";
1936
1937
1938         if (sscape_flag == 1)
1939                 devc->model = MD_1845_SSCAPE;
1940
1941         return 1;
1942 }
1943
1944 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1945                 int dma_capture, int share_dma, int *osp, struct module *owner)
1946 {
1947         /*
1948          * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1949          *   so that this driver doesn't need to allocate/deallocate it.
1950          *   The actually used IRQ is ABS(irq).
1951          */
1952
1953         int my_dev;
1954         char dev_name[100];
1955         int e;
1956
1957         ad1848_info  *devc = &adev_info[nr_ad1848_devs];
1958
1959         ad1848_port_info *portc = NULL;
1960
1961         devc->irq = (irq > 0) ? irq : 0;
1962         devc->open_mode = 0;
1963         devc->timer_ticks = 0;
1964         devc->dma1 = dma_playback;
1965         devc->dma2 = dma_capture;
1966         devc->subtype = cfg.card_subtype;
1967         devc->audio_flags = DMA_AUTOMODE;
1968         devc->playback_dev = devc->record_dev = 0;
1969         if (name != NULL)
1970                 devc->name = name;
1971
1972         if (name != NULL && name[0] != 0)
1973                 sprintf(dev_name,
1974                         "%s (%s)", name, devc->chip_name);
1975         else
1976                 sprintf(dev_name,
1977                         "Generic audio codec (%s)", devc->chip_name);
1978
1979         rename_region(ports, devc->name);
1980
1981         conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1982
1983         if (devc->model == MD_1848 || devc->model == MD_C930)
1984                 devc->audio_flags |= DMA_HARDSTOP;
1985
1986         if (devc->model > MD_1848)
1987         {
1988                 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1989                         devc->audio_flags &= ~DMA_DUPLEX;
1990                 else
1991                         devc->audio_flags |= DMA_DUPLEX;
1992         }
1993
1994         portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1995         if(portc==NULL) {
1996                 release_region(devc->base, 4);
1997                 return -1;
1998         }
1999
2000         if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2001                                              dev_name,
2002                                              &ad1848_audio_driver,
2003                                              sizeof(struct audio_driver),
2004                                              devc->audio_flags,
2005                                              ad_format_mask[devc->model],
2006                                              devc,
2007                                              dma_playback,
2008                                              dma_capture)) < 0)
2009         {
2010                 release_region(devc->base, 4);
2011                 kfree(portc);
2012                 return -1;
2013         }
2014
2015         audio_devs[my_dev]->portc = portc;
2016         audio_devs[my_dev]->mixer_dev = -1;
2017         if (owner)
2018                 audio_devs[my_dev]->d->owner = owner;
2019         memset((char *) portc, 0, sizeof(*portc));
2020
2021         nr_ad1848_devs++;
2022
2023         ad1848_init_hw(devc);
2024
2025         if (irq > 0)
2026         {
2027                 devc->dev_no = my_dev;
2028                 if (request_irq(devc->irq, adintr, 0, devc->name,
2029                                 (void *)(long)my_dev) < 0)
2030                 {
2031                         printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2032                         /* Don't free it either then.. */
2033                         devc->irq = 0;
2034                 }
2035                 if (capabilities[devc->model].flags & CAP_F_TIMER)
2036                 {
2037 #ifndef CONFIG_SMP
2038                         int x;
2039                         unsigned char tmp = ad_read(devc, 16);
2040 #endif
2041
2042                         devc->timer_ticks = 0;
2043
2044                         ad_write(devc, 21, 0x00);       /* Timer MSB */
2045                         ad_write(devc, 20, 0x10);       /* Timer LSB */
2046 #ifndef CONFIG_SMP
2047                         ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2048                         for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2049                         ad_write(devc, 16, tmp & ~0x40);        /* Disable timer */
2050
2051                         if (devc->timer_ticks == 0)
2052                                 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2053                         else
2054                         {
2055                                 DDB(printk("Interrupt test OK\n"));
2056                                 devc->irq_ok = 1;
2057                         }
2058 #else
2059                         devc->irq_ok = 1;
2060 #endif
2061                 }
2062                 else
2063                         devc->irq_ok = 1;       /* Couldn't test. assume it's OK */
2064         } else if (irq < 0)
2065                 irq2dev[-irq] = devc->dev_no = my_dev;
2066
2067 #ifndef EXCLUDE_TIMERS
2068         if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2069             devc->irq_ok)
2070                 ad1848_tmr_install(my_dev);
2071 #endif
2072
2073         if (!share_dma)
2074         {
2075                 if (sound_alloc_dma(dma_playback, devc->name))
2076                         printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2077
2078                 if (dma_capture != dma_playback)
2079                         if (sound_alloc_dma(dma_capture, devc->name))
2080                                 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2081         }
2082
2083         if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2084                                      dev_name,
2085                                      &ad1848_mixer_operations,
2086                                      sizeof(struct mixer_operations),
2087                                      devc)) >= 0)
2088         {
2089                 audio_devs[my_dev]->mixer_dev = e;
2090                 if (owner)
2091                         mixer_devs[e]->owner = owner;
2092         }
2093         return my_dev;
2094 }
2095
2096 int ad1848_control(int cmd, int arg)
2097 {
2098         ad1848_info *devc;
2099         unsigned long flags;
2100
2101         if (nr_ad1848_devs < 1)
2102                 return -ENODEV;
2103
2104         devc = &adev_info[nr_ad1848_devs - 1];
2105
2106         switch (cmd)
2107         {
2108                 case AD1848_SET_XTAL:   /* Change clock frequency of AD1845 (only ) */
2109                         if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2110                                 return -EINVAL;
2111                         spin_lock_irqsave(&devc->lock,flags);
2112                         ad_enter_MCE(devc);
2113                         ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2114                         ad_leave_MCE(devc);
2115                         spin_unlock_irqrestore(&devc->lock,flags);
2116                         break;
2117
2118                 case AD1848_MIXER_REROUTE:
2119                 {
2120                         int o = (arg >> 8) & 0xff;
2121                         int n = arg & 0xff;
2122
2123                         if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2124                                 return -EINVAL;
2125
2126                         if (!(devc->supported_devices & (1 << o)) &&
2127                             !(devc->supported_rec_devices & (1 << o)))
2128                                 return -EINVAL;
2129
2130                         if (n == SOUND_MIXER_NONE)
2131                         {       /* Just hide this control */
2132                                 ad1848_mixer_set(devc, o, 0);   /* Shut up it */
2133                                 devc->supported_devices &= ~(1 << o);
2134                                 devc->supported_rec_devices &= ~(1 << o);
2135                                 break;
2136                         }
2137
2138                         /* Make the mixer control identified by o to appear as n */
2139                         if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2140                                 return -EINVAL;
2141
2142                         devc->mixer_reroute[n] = o;     /* Rename the control */
2143                         if (devc->supported_devices & (1 << o))
2144                                 devc->supported_devices |= (1 << n);
2145                         if (devc->supported_rec_devices & (1 << o))
2146                                 devc->supported_rec_devices |= (1 << n);
2147
2148                         devc->supported_devices &= ~(1 << o);
2149                         devc->supported_rec_devices &= ~(1 << o);
2150                 }
2151                 break;
2152         }
2153         return 0;
2154 }
2155
2156 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2157 {
2158         int i, mixer, dev = 0;
2159         ad1848_info *devc = NULL;
2160
2161         for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2162         {
2163                 if (adev_info[i].base == io_base)
2164                 {
2165                         devc = &adev_info[i];
2166                         dev = devc->dev_no;
2167                 }
2168         }
2169
2170         if (devc != NULL)
2171         {
2172                 kfree(audio_devs[dev]->portc);
2173                 release_region(devc->base, 4);
2174
2175                 if (!share_dma)
2176                 {
2177                         if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2178                                 free_irq(devc->irq, (void *)(long)devc->dev_no);
2179
2180                         sound_free_dma(dma_playback);
2181
2182                         if (dma_playback != dma_capture)
2183                                 sound_free_dma(dma_capture);
2184
2185                 }
2186                 mixer = audio_devs[devc->dev_no]->mixer_dev;
2187                 if(mixer>=0)
2188                         sound_unload_mixerdev(mixer);
2189
2190                 nr_ad1848_devs--;
2191                 for ( ; i < nr_ad1848_devs ; i++)
2192                         adev_info[i] = adev_info[i+1];
2193         }
2194         else
2195                 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2196 }
2197
2198 irqreturn_t adintr(int irq, void *dev_id, struct pt_regs *dummy)
2199 {
2200         unsigned char status;
2201         ad1848_info *devc;
2202         int dev;
2203         int alt_stat = 0xff;
2204         unsigned char c930_stat = 0;
2205         int cnt = 0;
2206
2207         dev = (long)dev_id;
2208         devc = (ad1848_info *) audio_devs[dev]->devc;
2209
2210 interrupt_again:                /* Jump back here if int status doesn't reset */
2211
2212         status = inb(io_Status(devc));
2213
2214         if (status == 0x80)
2215                 printk(KERN_DEBUG "adintr: Why?\n");
2216         if (devc->model == MD_1848)
2217                 outb((0), io_Status(devc));     /* Clear interrupt status */
2218
2219         if (status & 0x01)
2220         {
2221                 if (devc->model == MD_C930)
2222                 {               /* 82C930 has interrupt status register in MAD16 register MC11 */
2223
2224                         spin_lock(&devc->lock);
2225
2226                         /* 0xe0e is C930 address port
2227                          * 0xe0f is C930 data port
2228                          */
2229                         outb(11, 0xe0e);
2230                         c930_stat = inb(0xe0f);
2231                         outb((~c930_stat), 0xe0f);
2232
2233                         spin_unlock(&devc->lock);
2234
2235                         alt_stat = (c930_stat << 2) & 0x30;
2236                 }
2237                 else if (devc->model != MD_1848)
2238                 {
2239                         spin_lock(&devc->lock);
2240                         alt_stat = ad_read(devc, 24);
2241                         ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat);      /* Selective ack */
2242                         spin_unlock(&devc->lock);
2243                 }
2244
2245                 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2246                 {
2247                         DMAbuf_inputintr(devc->record_dev);
2248                 }
2249                 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2250                       (alt_stat & 0x10))
2251                 {
2252                         DMAbuf_outputintr(devc->playback_dev, 1);
2253                 }
2254                 if (devc->model != MD_1848 && (alt_stat & 0x40))        /* Timer interrupt */
2255                 {
2256                         devc->timer_ticks++;
2257 #ifndef EXCLUDE_TIMERS
2258                         if (timer_installed == dev && devc->timer_running)
2259                                 sound_timer_interrupt();
2260 #endif
2261                 }
2262         }
2263 /*
2264  * Sometimes playback or capture interrupts occur while a timer interrupt
2265  * is being handled. The interrupt will not be retriggered if we don't
2266  * handle it now. Check if an interrupt is still pending and restart
2267  * the handler in this case.
2268  */
2269         if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2270         {
2271                   goto interrupt_again;
2272         }
2273         return IRQ_HANDLED;
2274 }
2275
2276 /*
2277  *      Experimental initialization sequence for the integrated sound system
2278  *      of the Compaq Deskpro M.
2279  */
2280
2281 static int init_deskpro_m(struct address_info *hw_config)
2282 {
2283         unsigned char   tmp;
2284
2285         if ((tmp = inb(0xc44)) == 0xff)
2286         {
2287                 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2288                 return 0;
2289         }
2290
2291         outb(0x10, 0xc44);
2292         outb(0x40, 0xc45);
2293         outb(0x00, 0xc46);
2294         outb(0xe8, 0xc47);
2295         outb(0x14, 0xc44);
2296         outb(0x40, 0xc45);
2297         outb(0x00, 0xc46);
2298         outb(0xe8, 0xc47);
2299         outb(0x10, 0xc44);
2300
2301         return 1;
2302 }
2303
2304 /*
2305  *      Experimental initialization sequence for the integrated sound system
2306  *      of Compaq Deskpro XL.
2307  */
2308
2309 static int init_deskpro(struct address_info *hw_config)
2310 {
2311         unsigned char   tmp;
2312
2313         if ((tmp = inb(0xc44)) == 0xff)
2314         {
2315                 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2316                 return 0;
2317         }
2318         outb((tmp | 0x04), 0xc44);      /* Select bank 1 */
2319         if (inb(0xc44) != 0x04)
2320         {
2321                 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2322                 return 0;
2323         }
2324         /*
2325          * OK. It looks like a Deskpro so let's proceed.
2326          */
2327
2328         /*
2329          * I/O port 0xc44 Audio configuration register.
2330          *
2331          * bits 0xc0:   Audio revision bits
2332          *              0x00 = Compaq Business Audio
2333          *              0x40 = MS Sound System Compatible (reset default)
2334          *              0x80 = Reserved
2335          *              0xc0 = Reserved
2336          * bit 0x20:    No Wait State Enable
2337          *              0x00 = Disabled (reset default, DMA mode)
2338          *              0x20 = Enabled (programmed I/O mode)
2339          * bit 0x10:    MS Sound System Decode Enable
2340          *              0x00 = Decoding disabled (reset default)
2341          *              0x10 = Decoding enabled
2342          * bit 0x08:    FM Synthesis Decode Enable
2343          *              0x00 = Decoding Disabled (reset default)
2344          *              0x08 = Decoding enabled
2345          * bit 0x04     Bank select
2346          *              0x00 = Bank 0
2347          *              0x04 = Bank 1
2348          * bits 0x03    MSS Base address
2349          *              0x00 = 0x530 (reset default)
2350          *              0x01 = 0x604
2351          *              0x02 = 0xf40
2352          *              0x03 = 0xe80
2353          */
2354
2355 #ifdef DEBUGXL
2356         /* Debug printing */
2357         printk("Port 0xc44 (before): ");
2358         outb((tmp & ~0x04), 0xc44);
2359         printk("%02x ", inb(0xc44));
2360         outb((tmp | 0x04), 0xc44);
2361         printk("%02x\n", inb(0xc44));
2362 #endif
2363
2364         /* Set bank 1 of the register */
2365         tmp = 0x58;             /* MSS Mode, MSS&FM decode enabled */
2366
2367         switch (hw_config->io_base)
2368         {
2369                 case 0x530:
2370                         tmp |= 0x00;
2371                         break;
2372                 case 0x604:
2373                         tmp |= 0x01;
2374                         break;
2375                 case 0xf40:
2376                         tmp |= 0x02;
2377                         break;
2378                 case 0xe80:
2379                         tmp |= 0x03;
2380                         break;
2381                 default:
2382                         DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2383                         return 0;
2384         }
2385         outb((tmp & ~0x04), 0xc44);     /* Write to bank=0 */
2386
2387 #ifdef DEBUGXL
2388         /* Debug printing */
2389         printk("Port 0xc44 (after): ");
2390         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2391         printk("%02x ", inb(0xc44));
2392         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2393         printk("%02x\n", inb(0xc44));
2394 #endif
2395
2396         /*
2397          * I/O port 0xc45 FM Address Decode/MSS ID Register.
2398          *
2399          * bank=0, bits 0xfe:   FM synthesis Decode Compare bits 7:1 (default=0x88)
2400          * bank=0, bit 0x01:    SBIC Power Control Bit
2401          *                      0x00 = Powered up
2402          *                      0x01 = Powered down
2403          * bank=1, bits 0xfc:   MSS ID (default=0x40)
2404          */
2405
2406 #ifdef DEBUGXL
2407         /* Debug printing */
2408         printk("Port 0xc45 (before): ");
2409         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2410         printk("%02x ", inb(0xc45));
2411         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2412         printk("%02x\n", inb(0xc45));
2413 #endif
2414
2415         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2416         outb((0x88), 0xc45);    /* FM base 7:0 = 0x88 */
2417         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2418         outb((0x10), 0xc45);    /* MSS ID = 0x10 (MSS port returns 0x04) */
2419
2420 #ifdef DEBUGXL
2421         /* Debug printing */
2422         printk("Port 0xc45 (after): ");
2423         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2424         printk("%02x ", inb(0xc45));
2425         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2426         printk("%02x\n", inb(0xc45));
2427 #endif
2428
2429
2430         /*
2431          * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2432          *
2433          * bank=0, bits 0xff:   FM synthesis Decode Compare bits 15:8 (default=0x03)
2434          * bank=1, bits 0xff:   Audio addressing ASIC id
2435          */
2436
2437 #ifdef DEBUGXL
2438         /* Debug printing */
2439         printk("Port 0xc46 (before): ");
2440         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2441         printk("%02x ", inb(0xc46));
2442         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2443         printk("%02x\n", inb(0xc46));
2444 #endif
2445
2446         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2447         outb((0x03), 0xc46);    /* FM base 15:8 = 0x03 */
2448         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2449         outb((0x11), 0xc46);    /* ASIC ID = 0x11 */
2450
2451 #ifdef DEBUGXL
2452         /* Debug printing */
2453         printk("Port 0xc46 (after): ");
2454         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2455         printk("%02x ", inb(0xc46));
2456         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2457         printk("%02x\n", inb(0xc46));
2458 #endif
2459
2460         /*
2461          * I/O port 0xc47 FM Address Decode Register.
2462          *
2463          * bank=0, bits 0xff:   Decode enable selection for various FM address bits
2464          * bank=1, bits 0xff:   Reserved
2465          */
2466
2467 #ifdef DEBUGXL
2468         /* Debug printing */
2469         printk("Port 0xc47 (before): ");
2470         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2471         printk("%02x ", inb(0xc47));
2472         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2473         printk("%02x\n", inb(0xc47));
2474 #endif
2475
2476         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2477         outb((0x7c), 0xc47);    /* FM decode enable bits = 0x7c */
2478         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2479         outb((0x00), 0xc47);    /* Reserved bank1 = 0x00 */
2480
2481 #ifdef DEBUGXL
2482         /* Debug printing */
2483         printk("Port 0xc47 (after): ");
2484         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2485         printk("%02x ", inb(0xc47));
2486         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2487         printk("%02x\n", inb(0xc47));
2488 #endif
2489
2490         /*
2491          * I/O port 0xc6f = Audio Disable Function Register
2492          */
2493
2494 #ifdef DEBUGXL
2495         printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2496 #endif
2497
2498         outb((0x80), 0xc6f);
2499
2500 #ifdef DEBUGXL
2501         printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2502 #endif
2503
2504         return 1;
2505 }
2506
2507 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2508 {
2509         unsigned char   tmp;
2510
2511         DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2512
2513         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2514         {
2515                 /* check_opl3(0x388, hw_config); */
2516                 return ad1848_detect(ports, NULL, hw_config->osp);
2517         }
2518
2519         if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2520         {
2521                 if (!init_deskpro(hw_config))
2522                         return 0;
2523         }
2524
2525         if (deskpro_m)  /* Compaq Deskpro M */
2526         {
2527                 if (!init_deskpro_m(hw_config))
2528                         return 0;
2529         }
2530
2531         /*
2532            * Check if the IO port returns valid signature. The original MS Sound
2533            * system returns 0x04 while some cards (AudioTrix Pro for example)
2534            * return 0x00 or 0x0f.
2535          */
2536
2537         if ((tmp = inb(hw_config->io_base + 3)) == 0xff)        /* Bus float */
2538         {
2539                   int             ret;
2540
2541                   DDB(printk("I/O address is inactive (%x)\n", tmp));
2542                   if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2543                           return 0;
2544                   return 1;
2545         }
2546         DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2547         if ((tmp & 0x3f) != 0x04 &&
2548             (tmp & 0x3f) != 0x0f &&
2549             (tmp & 0x3f) != 0x00)
2550         {
2551                 int ret;
2552
2553                 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2554                 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2555                 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2556                         return 0;
2557
2558                 hw_config->card_subtype = 1;
2559                 return 1;
2560         }
2561         if ((hw_config->irq != 5)  &&
2562             (hw_config->irq != 7)  &&
2563             (hw_config->irq != 9)  &&
2564             (hw_config->irq != 10) &&
2565             (hw_config->irq != 11) &&
2566             (hw_config->irq != 12))
2567         {
2568                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2569                 return 0;
2570         }
2571         if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2572         {
2573                   printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2574                   return 0;
2575         }
2576         /*
2577          * Check that DMA0 is not in use with a 8 bit board.
2578          */
2579
2580         if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2581         {
2582                 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2583                 return 0;
2584         }
2585         if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2586         {
2587                 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2588                 return 0;
2589         }
2590         return ad1848_detect(ports, NULL, hw_config->osp);
2591 }
2592
2593 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2594 {
2595         static signed char interrupt_bits[12] =
2596         {
2597                 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2598         };
2599         signed char     bits;
2600         char            dma2_bit = 0;
2601
2602         static char     dma_bits[4] =
2603         {
2604                 1, 2, 0, 3
2605         };
2606
2607         int config_port = hw_config->io_base + 0;
2608         int version_port = hw_config->io_base + 3;
2609         int dma = hw_config->dma;
2610         int dma2 = hw_config->dma2;
2611
2612         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2613         {
2614                 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2615                                                     hw_config->irq,
2616                                                     hw_config->dma,
2617                                                     hw_config->dma2, 0,
2618                                                     hw_config->osp,
2619                                                     owner);
2620                 return;
2621         }
2622         /*
2623          * Set the IRQ and DMA addresses.
2624          */
2625
2626         bits = interrupt_bits[hw_config->irq];
2627         if (bits == -1)
2628         {
2629                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2630                 release_region(ports->start, 4);
2631                 release_region(ports->start - 4, 4);
2632                 return;
2633         }
2634         outb((bits | 0x40), config_port);
2635         if ((inb(version_port) & 0x40) == 0)
2636                 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2637
2638 /*
2639  * Handle the capture DMA channel
2640  */
2641
2642         if (dma2 != -1 && dma2 != dma)
2643         {
2644                 if (!((dma == 0 && dma2 == 1) ||
2645                         (dma == 1 && dma2 == 0) ||
2646                         (dma == 3 && dma2 == 0)))
2647                 {       /* Unsupported combination. Try to swap channels */
2648                         int tmp = dma;
2649
2650                         dma = dma2;
2651                         dma2 = tmp;
2652                 }
2653                 if ((dma == 0 && dma2 == 1) ||
2654                         (dma == 1 && dma2 == 0) ||
2655                         (dma == 3 && dma2 == 0))
2656                 {
2657                         dma2_bit = 0x04;        /* Enable capture DMA */
2658                 }
2659                 else
2660                 {
2661                         printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2662                         dma2 = dma;
2663                 }
2664         }
2665         else
2666         {
2667                 dma2 = dma;
2668         }
2669
2670         hw_config->dma = dma;
2671         hw_config->dma2 = dma2;
2672
2673         outb((bits | dma_bits[dma] | dma2_bit), config_port);   /* Write IRQ+DMA setup */
2674
2675         hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2676                                           hw_config->irq,
2677                                           dma, dma2, 0,
2678                                           hw_config->osp,
2679                                           THIS_MODULE);
2680 }
2681
2682 void unload_ms_sound(struct address_info *hw_config)
2683 {
2684         ad1848_unload(hw_config->io_base + 4,
2685                       hw_config->irq,
2686                       hw_config->dma,
2687                       hw_config->dma2, 0);
2688         sound_unload_audiodev(hw_config->slots[0]);
2689         release_region(hw_config->io_base, 4);
2690 }
2691
2692 #ifndef EXCLUDE_TIMERS
2693
2694 /*
2695  * Timer stuff (for /dev/music).
2696  */
2697
2698 static unsigned int current_interval;
2699
2700 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2701 {
2702         unsigned long   flags;
2703         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2704         unsigned long   xtal_nsecs;     /* nanoseconds per xtal oscillator tick */
2705         unsigned long   divider;
2706
2707         spin_lock_irqsave(&devc->lock,flags);
2708
2709         /*
2710          * Length of the timer interval (in nanoseconds) depends on the
2711          * selected crystal oscillator. Check this from bit 0x01 of I8.
2712          *
2713          * AD1845 has just one oscillator which has cycle time of 10.050 us
2714          * (when a 24.576 MHz xtal oscillator is used).
2715          *
2716          * Convert requested interval to nanoseconds before computing
2717          * the timer divider.
2718          */
2719
2720         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2721                 xtal_nsecs = 10050;
2722         else if (ad_read(devc, 8) & 0x01)
2723                 xtal_nsecs = 9920;
2724         else
2725                 xtal_nsecs = 9969;
2726
2727         divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2728
2729         if (divider < 100)      /* Don't allow shorter intervals than about 1ms */
2730                 divider = 100;
2731
2732         if (divider > 65535)    /* Overflow check */
2733                 divider = 65535;
2734
2735         ad_write(devc, 21, (divider >> 8) & 0xff);      /* Set upper bits */
2736         ad_write(devc, 20, divider & 0xff);     /* Set lower bits */
2737         ad_write(devc, 16, ad_read(devc, 16) | 0x40);   /* Start the timer */
2738         devc->timer_running = 1;
2739         spin_unlock_irqrestore(&devc->lock,flags);
2740
2741         return current_interval = (divider * xtal_nsecs + 500) / 1000;
2742 }
2743
2744 static void ad1848_tmr_reprogram(int dev)
2745 {
2746         /*
2747          *    Audio driver has changed sampling rate so that a different xtal
2748          *      oscillator was selected. We have to reprogram the timer rate.
2749          */
2750
2751         ad1848_tmr_start(dev, current_interval);
2752         sound_timer_syncinterval(current_interval);
2753 }
2754
2755 static void ad1848_tmr_disable(int dev)
2756 {
2757         unsigned long   flags;
2758         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2759
2760         spin_lock_irqsave(&devc->lock,flags);
2761         ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2762         devc->timer_running = 0;
2763         spin_unlock_irqrestore(&devc->lock,flags);
2764 }
2765
2766 static void ad1848_tmr_restart(int dev)
2767 {
2768         unsigned long   flags;
2769         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2770
2771         if (current_interval == 0)
2772                 return;
2773
2774         spin_lock_irqsave(&devc->lock,flags);
2775         ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2776         devc->timer_running = 1;
2777         spin_unlock_irqrestore(&devc->lock,flags);
2778 }
2779
2780 static struct sound_lowlev_timer ad1848_tmr =
2781 {
2782         0,
2783         2,
2784         ad1848_tmr_start,
2785         ad1848_tmr_disable,
2786         ad1848_tmr_restart
2787 };
2788
2789 static int ad1848_tmr_install(int dev)
2790 {
2791         if (timer_installed != -1)
2792                 return 0;       /* Don't install another timer */
2793
2794         timer_installed = ad1848_tmr.dev = dev;
2795         sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2796
2797         return 1;
2798 }
2799 #endif /* EXCLUDE_TIMERS */
2800
2801 EXPORT_SYMBOL(ad1848_detect);
2802 EXPORT_SYMBOL(ad1848_init);
2803 EXPORT_SYMBOL(ad1848_unload);
2804 EXPORT_SYMBOL(ad1848_control);
2805 EXPORT_SYMBOL(adintr);
2806 EXPORT_SYMBOL(probe_ms_sound);
2807 EXPORT_SYMBOL(attach_ms_sound);
2808 EXPORT_SYMBOL(unload_ms_sound);
2809
2810 static int __initdata io = -1;
2811 static int __initdata irq = -1;
2812 static int __initdata dma = -1;
2813 static int __initdata dma2 = -1;
2814 static int __initdata type = 0;
2815
2816 module_param(io, int, 0);               /* I/O for a raw AD1848 card */
2817 module_param(irq, int, 0);              /* IRQ to use */
2818 module_param(dma, int, 0);              /* First DMA channel */
2819 module_param(dma2, int, 0);             /* Second DMA channel */
2820 module_param(type, int, 0);             /* Card type */
2821 module_param(deskpro_xl, bool, 0);      /* Special magic for Deskpro XL boxen */
2822 module_param(deskpro_m, bool, 0);       /* Special magic for Deskpro M box */
2823 module_param(soundpro, bool, 0);        /* More special magic for SoundPro chips */
2824
2825 #ifdef CONFIG_PNP
2826 module_param(isapnp, int, 0);
2827 module_param(isapnpjump, int, 0);
2828 module_param(reverse, bool, 0);
2829 MODULE_PARM_DESC(isapnp,        "When set to 0, Plug & Play support will be disabled");
2830 MODULE_PARM_DESC(isapnpjump,    "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2831 MODULE_PARM_DESC(reverse,       "When set to 1, will reverse ISAPnP search order");
2832
2833 static struct pnp_dev   *ad1848_dev  = NULL;
2834
2835 /* Please add new entries at the end of the table */
2836 static struct {
2837         char *name;
2838         unsigned short  card_vendor, card_device,
2839                         vendor, function;
2840         short mss_io, irq, dma, dma2;   /* index into isapnp table */
2841         int type;
2842 } ad1848_isapnp_list[] __initdata = {
2843         {"CMI 8330 SoundPRO",
2844                 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2845                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2846                 0, 0, 0,-1, 0},
2847         {"CS4232 based card",
2848                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2849                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2850                 0, 0, 0, 1, 0},
2851         {"CS4232 based card",
2852                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2853                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2854                 0, 0, 0, 1, 0},
2855         {"OPL3-SA2 WSS mode",
2856                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2857                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2858                 1, 0, 0, 1, 1},
2859         {"Advanced Gravis InterWave Audio",
2860                 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2861                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2862                 0, 0, 0, 1, 0},
2863         {NULL}
2864 };
2865
2866 static struct isapnp_device_id id_table[] __devinitdata = {
2867         {       ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2868                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2869         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2870                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2871         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2872                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2873         /* The main driver for this card is opl3sa2
2874         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2875                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2876         */
2877         {       ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2878                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2879         {0}
2880 };
2881
2882 MODULE_DEVICE_TABLE(isapnp, id_table);
2883
2884 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2885 {
2886         int err;
2887
2888         err = pnp_device_attach(dev);
2889         if (err < 0)
2890                 return(NULL);
2891
2892         if((err = pnp_activate_dev(dev)) < 0) {
2893                 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2894
2895                 pnp_device_detach(dev);
2896
2897                 return(NULL);
2898         }
2899         audio_activated = 1;
2900         return(dev);
2901 }
2902
2903 static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
2904                                 struct address_info *hw_config, int slot)
2905 {
2906
2907         /* Configure Audio device */
2908         if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
2909         {
2910                 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
2911                 {
2912                         hw_config->io_base      = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
2913                         hw_config->irq          = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
2914                         hw_config->dma          = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
2915                         if(ad1848_isapnp_list[slot].dma2 != -1)
2916                                 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
2917                         else
2918                                 hw_config->dma2 = -1;
2919                         hw_config->card_subtype = ad1848_isapnp_list[slot].type;
2920                 } else
2921                         return(NULL);
2922         } else
2923                 return(NULL);
2924
2925         return(ad1848_dev);
2926 }
2927
2928 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
2929 {
2930         char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
2931
2932         /* Initialize this baby. */
2933
2934         if(ad1848_init_generic(bus, hw_config, slot)) {
2935                 /* We got it. */
2936
2937                 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
2938                        busname,
2939                        hw_config->io_base, hw_config->irq, hw_config->dma,
2940                        hw_config->dma2);
2941                 return 1;
2942         }
2943         return 0;
2944 }
2945
2946 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
2947 {
2948         static int first = 1;
2949         int i;
2950
2951         /* Count entries in sb_isapnp_list */
2952         for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
2953         i--;
2954
2955         /* Check and adjust isapnpjump */
2956         if( isapnpjump < 0 || isapnpjump > i) {
2957                 isapnpjump = reverse ? i : 0;
2958                 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
2959         }
2960
2961         if(!first || !reverse)
2962                 i = isapnpjump;
2963         first = 0;
2964         while(ad1848_isapnp_list[i].card_vendor != 0) {
2965                 static struct pnp_card *bus = NULL;
2966
2967                 while ((bus = pnp_find_card(
2968                                 ad1848_isapnp_list[i].card_vendor,
2969                                 ad1848_isapnp_list[i].card_device,
2970                                 bus))) {
2971
2972                         if(ad1848_isapnp_init(hw_config, bus, i)) {
2973                                 isapnpjump = i; /* start next search from here */
2974                                 return 0;
2975                         }
2976                 }
2977                 i += reverse ? -1 : 1;
2978         }
2979
2980         return -ENODEV;
2981 }
2982 #endif
2983
2984
2985 static int __init init_ad1848(void)
2986 {
2987         printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2988
2989 #ifdef CONFIG_PNP
2990         if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
2991                 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
2992                 isapnp = 0;
2993         }
2994 #endif
2995
2996         if(io != -1) {
2997                 struct resource *ports;
2998                 if( isapnp == 0 )
2999                 {
3000                         if(irq == -1 || dma == -1) {
3001                                 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3002                                 return -EINVAL;
3003                         }
3004
3005                         cfg.irq = irq;
3006                         cfg.io_base = io;
3007                         cfg.dma = dma;
3008                         cfg.dma2 = dma2;
3009                         cfg.card_subtype = type;
3010                 }
3011
3012                 ports = request_region(io + 4, 4, "ad1848");
3013
3014                 if (!ports)
3015                         return -EBUSY;
3016
3017                 if (!request_region(io, 4, "WSS config")) {
3018                         release_region(io + 4, 4);
3019                         return -EBUSY;
3020                 }
3021
3022                 if (!probe_ms_sound(&cfg, ports)) {
3023                         release_region(io + 4, 4);
3024                         release_region(io, 4);
3025                         return -ENODEV;
3026                 }
3027                 attach_ms_sound(&cfg, ports, THIS_MODULE);
3028                 loaded = 1;
3029         }
3030         return 0;
3031 }
3032
3033 static void __exit cleanup_ad1848(void)
3034 {
3035         if(loaded)
3036                 unload_ms_sound(&cfg);
3037
3038 #ifdef CONFIG_PNP
3039         if(ad1848_dev){
3040                 if(audio_activated)
3041                         pnp_device_detach(ad1848_dev);
3042         }
3043 #endif
3044 }
3045
3046 module_init(init_ad1848);
3047 module_exit(cleanup_ad1848);
3048
3049 #ifndef MODULE
3050 static int __init setup_ad1848(char *str)
3051 {
3052         /* io, irq, dma, dma2, type */
3053         int ints[6];
3054
3055         str = get_options(str, ARRAY_SIZE(ints), ints);
3056
3057         io      = ints[1];
3058         irq     = ints[2];
3059         dma     = ints[3];
3060         dma2    = ints[4];
3061         type    = ints[5];
3062
3063         return 1;
3064 }
3065
3066 __setup("ad1848=", setup_ad1848);
3067 #endif
3068 MODULE_LICENSE("GPL");