net/mlx4_en: Fix mixed PFC and Global pause user control requests
[pandora-kernel.git] / include / drm / drm_os_linux.h
1 /**
2  * \file drm_os_linux.h
3  * OS abstraction macros.
4  */
5
6 #include <linux/interrupt.h>    /* For task queue support */
7 #include <linux/delay.h>
8
9 #ifndef readq
10 static inline u64 readq(void __iomem *reg)
11 {
12         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
13 }
14
15 static inline void writeq(u64 val, void __iomem *reg)
16 {
17         writel(val & 0xffffffff, reg);
18         writel(val >> 32, reg + 0x4UL);
19 }
20 #endif
21
22 /** Current process ID */
23 #define DRM_CURRENTPID                  task_pid_nr(current)
24 #define DRM_SUSER(p)                    capable(CAP_SYS_ADMIN)
25 #define DRM_UDELAY(d)                   udelay(d)
26 /** Read a byte from a MMIO region */
27 #define DRM_READ8(map, offset)          readb(((void __iomem *)(map)->handle) + (offset))
28 /** Read a word from a MMIO region */
29 #define DRM_READ16(map, offset)         readw(((void __iomem *)(map)->handle) + (offset))
30 /** Read a dword from a MMIO region */
31 #define DRM_READ32(map, offset)         readl(((void __iomem *)(map)->handle) + (offset))
32 /** Write a byte into a MMIO region */
33 #define DRM_WRITE8(map, offset, val)    writeb(val, ((void __iomem *)(map)->handle) + (offset))
34 /** Write a word into a MMIO region */
35 #define DRM_WRITE16(map, offset, val)   writew(val, ((void __iomem *)(map)->handle) + (offset))
36 /** Write a dword into a MMIO region */
37 #define DRM_WRITE32(map, offset, val)   writel(val, ((void __iomem *)(map)->handle) + (offset))
38 /** Read memory barrier */
39
40 /** Read a qword from a MMIO region - be careful using these unless you really understand them */
41 #define DRM_READ64(map, offset)         readq(((void __iomem *)(map)->handle) + (offset))
42 /** Write a qword into a MMIO region */
43 #define DRM_WRITE64(map, offset, val)   writeq(val, ((void __iomem *)(map)->handle) + (offset))
44
45 #define DRM_READMEMORYBARRIER()         rmb()
46 /** Write memory barrier */
47 #define DRM_WRITEMEMORYBARRIER()        wmb()
48 /** Read/write memory barrier */
49 #define DRM_MEMORYBARRIER()             mb()
50
51 /** IRQ handler arguments and return type and values */
52 #define DRM_IRQ_ARGS            int irq, void *arg
53
54 /** AGP types */
55 #if __OS_HAS_AGP
56 #define DRM_AGP_MEM             struct agp_memory
57 #define DRM_AGP_KERN            struct agp_kern_info
58 #else
59 /* define some dummy types for non AGP supporting kernels */
60 struct no_agp_kern {
61         unsigned long aper_base;
62         unsigned long aper_size;
63 };
64 #define DRM_AGP_MEM             int
65 #define DRM_AGP_KERN            struct no_agp_kern
66 #endif
67
68 #if !(__OS_HAS_MTRR)
69 static __inline__ int mtrr_add(unsigned long base, unsigned long size,
70                                unsigned int type, char increment)
71 {
72         return -ENODEV;
73 }
74
75 static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size)
76 {
77         return -ENODEV;
78 }
79
80 #define MTRR_TYPE_WRCOMB     1
81
82 #endif
83
84 /** Other copying of data to kernel space */
85 #define DRM_COPY_FROM_USER(arg1, arg2, arg3)            \
86         copy_from_user(arg1, arg2, arg3)
87 /** Other copying of data from kernel space */
88 #define DRM_COPY_TO_USER(arg1, arg2, arg3)              \
89         copy_to_user(arg1, arg2, arg3)
90 /* Macros for copyfrom user, but checking readability only once */
91 #define DRM_VERIFYAREA_READ( uaddr, size )              \
92         (access_ok( VERIFY_READ, uaddr, size ) ? 0 : -EFAULT)
93 #define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3)  \
94         __copy_from_user(arg1, arg2, arg3)
95 #define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3)    \
96         __copy_to_user(arg1, arg2, arg3)
97 #define DRM_GET_USER_UNCHECKED(val, uaddr)              \
98         __get_user(val, uaddr)
99
100 #define DRM_HZ HZ
101
102 #define DRM_WAIT_ON( ret, queue, timeout, condition )           \
103 do {                                                            \
104         DECLARE_WAITQUEUE(entry, current);                      \
105         unsigned long end = jiffies + (timeout);                \
106         add_wait_queue(&(queue), &entry);                       \
107                                                                 \
108         for (;;) {                                              \
109                 __set_current_state(TASK_INTERRUPTIBLE);        \
110                 if (condition)                                  \
111                         break;                                  \
112                 if (time_after_eq(jiffies, end)) {              \
113                         ret = -EBUSY;                           \
114                         break;                                  \
115                 }                                               \
116                 schedule_timeout((HZ/100 > 1) ? HZ/100 : 1);    \
117                 if (signal_pending(current)) {                  \
118                         ret = -EINTR;                           \
119                         break;                                  \
120                 }                                               \
121         }                                                       \
122         __set_current_state(TASK_RUNNING);                      \
123         remove_wait_queue(&(queue), &entry);                    \
124 } while (0)
125
126 #define DRM_WAKEUP( queue ) wake_up( queue )
127 #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )