include/asm-s390/system.h

   1 /*
   2  *  include/asm-s390/system.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
   7  *
   8  *  Derived from "include/asm-i386/system.h"
   9  */
  10
  11 #ifndef __ASM_SYSTEM_H
  12 #define __ASM_SYSTEM_H
  13
  14 #include <linux/config.h>
  15 #include <linux/kernel.h>
  16 #include <asm/types.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/setup.h>
  19 #include <asm/processor.h>
  20
  21 #ifdef __KERNEL__
  22
  23 struct task_struct;
  24
  25 extern struct task_struct *__switch_to(void *, void *);
  26
  27 #ifdef __s390x__
  28 #define __FLAG_SHIFT 56
  29 #else /* ! __s390x__ */
  30 #define __FLAG_SHIFT 24
  31 #endif /* ! __s390x__ */
  32
  33 static inline void save_fp_regs(s390_fp_regs *fpregs)
  34 {
  35         asm volatile (
  36                 "   std   0,8(%1)\n"
  37                 "   std   2,24(%1)\n"
  38                 "   std   4,40(%1)\n"
  39                 "   std   6,56(%1)"
  40                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  41         if (!MACHINE_HAS_IEEE)
  42                 return;
  43         asm volatile(
  44                 "   stfpc 0(%1)\n"
  45                 "   std   1,16(%1)\n"
  46                 "   std   3,32(%1)\n"
  47                 "   std   5,48(%1)\n"
  48                 "   std   7,64(%1)\n"
  49                 "   std   8,72(%1)\n"
  50                 "   std   9,80(%1)\n"
  51                 "   std   10,88(%1)\n"
  52                 "   std   11,96(%1)\n"
  53                 "   std   12,104(%1)\n"
  54                 "   std   13,112(%1)\n"
  55                 "   std   14,120(%1)\n"
  56                 "   std   15,128(%1)\n"
  57                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  58 }
  59
  60 static inline void restore_fp_regs(s390_fp_regs *fpregs)
  61 {
  62         asm volatile (
  63                 "   ld    0,8(%0)\n"
  64                 "   ld    2,24(%0)\n"
  65                 "   ld    4,40(%0)\n"
  66                 "   ld    6,56(%0)"
  67                 : : "a" (fpregs), "m" (*fpregs) );
  68         if (!MACHINE_HAS_IEEE)
  69                 return;
  70         asm volatile(
  71                 "   lfpc  0(%0)\n"
  72                 "   ld    1,16(%0)\n"
  73                 "   ld    3,32(%0)\n"
  74                 "   ld    5,48(%0)\n"
  75                 "   ld    7,64(%0)\n"
  76                 "   ld    8,72(%0)\n"
  77                 "   ld    9,80(%0)\n"
  78                 "   ld    10,88(%0)\n"
  79                 "   ld    11,96(%0)\n"
  80                 "   ld    12,104(%0)\n"
  81                 "   ld    13,112(%0)\n"
  82                 "   ld    14,120(%0)\n"
  83                 "   ld    15,128(%0)\n"
  84                 : : "a" (fpregs), "m" (*fpregs) );
  85 }
  86
  87 static inline void save_access_regs(unsigned int *acrs)
  88 {
  89         asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
  90 }
  91
  92 static inline void restore_access_regs(unsigned int *acrs)
  93 {
  94         asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
  95 }
  96
  97 #define switch_to(prev,next,last) do {                                       \
  98         if (prev == next)                                                    \
  99                 break;                                                       \
 100         save_fp_regs(&prev->thread.fp_regs);                                 \
 101         restore_fp_regs(&next->thread.fp_regs);                              \
 102         save_access_regs(&prev->thread.acrs[0]);                             \
 103         restore_access_regs(&next->thread.acrs[0]);                          \
 104         prev = __switch_to(prev,next);                                       \
 105 } while (0)
 106
 107 /*
 108  * On SMP systems, when the scheduler does migration-cost autodetection,
 109  * it needs a way to flush as much of the CPU's caches as possible.
 110  *
 111  * TODO: fill this in!
 112  */
 113 static inline void sched_cacheflush(void)
 114 {
 115 }
 116
 117 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 118 extern void account_vtime(struct task_struct *);
 119 extern void account_tick_vtime(struct task_struct *);
 120 extern void account_system_vtime(struct task_struct *);
 121 #endif
 122
 123 #define finish_arch_switch(prev) do {                                        \
 124         set_fs(current->thread.mm_segment);                                  \
 125         account_vtime(prev);                                                 \
 126 } while (0)
 127
 128 #define nop() __asm__ __volatile__ ("nop")
 129
 130 #define xchg(ptr,x) \
 131   ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
 132
 133 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 134 {
 135         unsigned long addr, old;
 136         int shift;
 137
 138         switch (size) {
 139         case 1:
 140                 addr = (unsigned long) ptr;
 141                 shift = (3 ^ (addr & 3)) << 3;
 142                 addr ^= addr & 3;
 143                 asm volatile(
 144                         "    l   %0,0(%4)\n"
 145                         "0:  lr  0,%0\n"
 146                         "    nr  0,%3\n"
 147                         "    or  0,%2\n"
 148                         "    cs  %0,0,0(%4)\n"
 149                         "    jl  0b\n"
 150                         : "=&d" (old), "=m" (*(int *) addr)
 151                         : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
 152                           "m" (*(int *) addr) : "memory", "cc", "0" );
 153                 x = old >> shift;
 154                 break;
 155         case 2:
 156                 addr = (unsigned long) ptr;
 157                 shift = (2 ^ (addr & 2)) << 3;
 158                 addr ^= addr & 2;
 159                 asm volatile(
 160                         "    l   %0,0(%4)\n"
 161                         "0:  lr  0,%0\n"
 162                         "    nr  0,%3\n"
 163                         "    or  0,%2\n"
 164                         "    cs  %0,0,0(%4)\n"
 165                         "    jl  0b\n"
 166                         : "=&d" (old), "=m" (*(int *) addr)
 167                         : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
 168                           "m" (*(int *) addr) : "memory", "cc", "0" );
 169                 x = old >> shift;
 170                 break;
 171         case 4:
 172                 asm volatile (
 173                         "    l   %0,0(%3)\n"
 174                         "0:  cs  %0,%2,0(%3)\n"
 175                         "    jl  0b\n"
 176                         : "=&d" (old), "=m" (*(int *) ptr)
 177                         : "d" (x), "a" (ptr), "m" (*(int *) ptr)
 178                         : "memory", "cc" );
 179                 x = old;
 180                 break;
 181 #ifdef __s390x__
 182         case 8:
 183                 asm volatile (
 184                         "    lg  %0,0(%3)\n"
 185                         "0:  csg %0,%2,0(%3)\n"
 186                         "    jl  0b\n"
 187                         : "=&d" (old), "=m" (*(long *) ptr)
 188                         : "d" (x), "a" (ptr), "m" (*(long *) ptr)
 189                         : "memory", "cc" );
 190                 x = old;
 191                 break;
 192 #endif /* __s390x__ */
 193         }
 194         return x;
 195 }
 196
 197 /*
 198  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 199  * store NEW in MEM.  Return the initial value in MEM.  Success is
 200  * indicated by comparing RETURN with OLD.
 201  */
 202
 203 #define __HAVE_ARCH_CMPXCHG 1
 204
 205 #define cmpxchg(ptr,o,n)\
 206         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 207                                         (unsigned long)(n),sizeof(*(ptr))))
 208
 209 static inline unsigned long
 210 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 211 {
 212         unsigned long addr, prev, tmp;
 213         int shift;
 214
 215         switch (size) {
 216         case 1:
 217                 addr = (unsigned long) ptr;
 218                 shift = (3 ^ (addr & 3)) << 3;
 219                 addr ^= addr & 3;
 220                 asm volatile(
 221                         "    l   %0,0(%4)\n"
 222                         "0:  nr  %0,%5\n"
 223                         "    lr  %1,%0\n"
 224                         "    or  %0,%2\n"
 225                         "    or  %1,%3\n"
 226                         "    cs  %0,%1,0(%4)\n"
 227                         "    jnl 1f\n"
 228                         "    xr  %1,%0\n"
 229                         "    nr  %1,%5\n"
 230                         "    jnz 0b\n"
 231                         "1:"
 232                         : "=&d" (prev), "=&d" (tmp)
 233                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 234                           "d" (~(255 << shift))
 235                         : "memory", "cc" );
 236                 return prev >> shift;
 237         case 2:
 238                 addr = (unsigned long) ptr;
 239                 shift = (2 ^ (addr & 2)) << 3;
 240                 addr ^= addr & 2;
 241                 asm volatile(
 242                         "    l   %0,0(%4)\n"
 243                         "0:  nr  %0,%5\n"
 244                         "    lr  %1,%0\n"
 245                         "    or  %0,%2\n"
 246                         "    or  %1,%3\n"
 247                         "    cs  %0,%1,0(%4)\n"
 248                         "    jnl 1f\n"
 249                         "    xr  %1,%0\n"
 250                         "    nr  %1,%5\n"
 251                         "    jnz 0b\n"
 252                         "1:"
 253                         : "=&d" (prev), "=&d" (tmp)
 254                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 255                           "d" (~(65535 << shift))
 256                         : "memory", "cc" );
 257                 return prev >> shift;
 258         case 4:
 259                 asm volatile (
 260                         "    cs  %0,%2,0(%3)\n"
 261                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 262                         : "memory", "cc" );
 263                 return prev;
 264 #ifdef __s390x__
 265         case 8:
 266                 asm volatile (
 267                         "    csg %0,%2,0(%3)\n"
 268                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 269                         : "memory", "cc" );
 270                 return prev;
 271 #endif /* __s390x__ */
 272         }
 273         return old;
 274 }
 275
 276 /*
 277  * Force strict CPU ordering.
 278  * And yes, this is required on UP too when we're talking
 279  * to devices.
 280  *
 281  * This is very similar to the ppc eieio/sync instruction in that is
 282  * does a checkpoint syncronisation & makes sure that
 283  * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 284  */
 285
 286 #define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
 287 # define SYNC_OTHER_CORES(x)   eieio()
 288 #define mb()    eieio()
 289 #define rmb()   eieio()
 290 #define wmb()   eieio()
 291 #define read_barrier_depends() do { } while(0)
 292 #define smp_mb()       mb()
 293 #define smp_rmb()      rmb()
 294 #define smp_wmb()      wmb()
 295 #define smp_read_barrier_depends()    read_barrier_depends()
 296 #define smp_mb__before_clear_bit()     smp_mb()
 297 #define smp_mb__after_clear_bit()      smp_mb()
 298
 299
 300 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 301 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
 302
 303 /* interrupt control.. */
 304 #define local_irq_enable() ({ \
 305         unsigned long  __dummy; \
 306         __asm__ __volatile__ ( \
 307                 "stosm 0(%1),0x03" \
 308                 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
 309         })
 310
 311 #define local_irq_disable() ({ \
 312         unsigned long __flags; \
 313         __asm__ __volatile__ ( \
 314                 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
 315         __flags; \
 316         })
 317
 318 #define local_save_flags(x) \
 319         __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
 320
 321 #define local_irq_restore(x) \
 322         __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory")
 323
 324 #define irqs_disabled()                 \
 325 ({                                      \
 326         unsigned long flags;            \
 327         local_save_flags(flags);        \
 328         !((flags >> __FLAG_SHIFT) & 3); \
 329 })
 330
 331 #ifdef __s390x__
 332
 333 #define __ctl_load(array, low, high) ({ \
 334         typedef struct { char _[sizeof(array)]; } addrtype; \
 335         __asm__ __volatile__ ( \
 336                 "   bras  1,0f\n" \
 337                 "   lctlg 0,0,0(%0)\n" \
 338                 "0: ex    %1,0(1)" \
 339                 : : "a" (&array), "a" (((low)<<4)+(high)), \
 340                     "m" (*(addrtype *)(array)) : "1" ); \
 341         })
 342
 343 #define __ctl_store(array, low, high) ({ \
 344         typedef struct { char _[sizeof(array)]; } addrtype; \
 345         __asm__ __volatile__ ( \
 346                 "   bras  1,0f\n" \
 347                 "   stctg 0,0,0(%1)\n" \
 348                 "0: ex    %2,0(1)" \
 349                 : "=m" (*(addrtype *)(array)) \
 350                 : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
 351         })
 352
 353 #define __ctl_set_bit(cr, bit) ({ \
 354         __u8 __dummy[24]; \
 355         __asm__ __volatile__ ( \
 356                 "    bras  1,0f\n"       /* skip indirect insns */ \
 357                 "    stctg 0,0,0(%1)\n" \
 358                 "    lctlg 0,0,0(%1)\n" \
 359                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 360                 "    lg    0,0(%1)\n" \
 361                 "    ogr   0,%3\n"       /* set the bit */ \
 362                 "    stg   0,0(%1)\n" \
 363                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 364                 : "=m" (__dummy) \
 365                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 366                   "a" (cr*17), "a" (1L<<(bit)) \
 367                 : "cc", "0", "1" ); \
 368         })
 369
 370 #define __ctl_clear_bit(cr, bit) ({ \
 371         __u8 __dummy[16]; \
 372         __asm__ __volatile__ ( \
 373                 "    bras  1,0f\n"       /* skip indirect insns */ \
 374                 "    stctg 0,0,0(%1)\n" \
 375                 "    lctlg 0,0,0(%1)\n" \
 376                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 377                 "    lg    0,0(%1)\n" \
 378                 "    ngr   0,%3\n"       /* set the bit */ \
 379                 "    stg   0,0(%1)\n" \
 380                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 381                 : "=m" (__dummy) \
 382                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 383                   "a" (cr*17), "a" (~(1L<<(bit))) \
 384                 : "cc", "0", "1" ); \
 385         })
 386
 387 #else /* __s390x__ */
 388
 389 #define __ctl_load(array, low, high) ({ \
 390         typedef struct { char _[sizeof(array)]; } addrtype; \
 391         __asm__ __volatile__ ( \
 392                 "   bras  1,0f\n" \
 393                 "   lctl 0,0,0(%0)\n" \
 394                 "0: ex    %1,0(1)" \
 395                 : : "a" (&array), "a" (((low)<<4)+(high)), \
 396                     "m" (*(addrtype *)(array)) : "1" ); \
 397         })
 398
 399 #define __ctl_store(array, low, high) ({ \
 400         typedef struct { char _[sizeof(array)]; } addrtype; \
 401         __asm__ __volatile__ ( \
 402                 "   bras  1,0f\n" \
 403                 "   stctl 0,0,0(%1)\n" \
 404                 "0: ex    %2,0(1)" \
 405                 : "=m" (*(addrtype *)(array)) \
 406                 : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
 407         })
 408
 409 #define __ctl_set_bit(cr, bit) ({ \
 410         __u8 __dummy[16]; \
 411         __asm__ __volatile__ ( \
 412                 "    bras  1,0f\n"       /* skip indirect insns */ \
 413                 "    stctl 0,0,0(%1)\n" \
 414                 "    lctl  0,0,0(%1)\n" \
 415                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 416                 "    l     0,0(%1)\n" \
 417                 "    or    0,%3\n"       /* set the bit */ \
 418                 "    st    0,0(%1)\n" \
 419                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 420                 : "=m" (__dummy) \
 421                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 422                   "a" (cr*17), "a" (1<<(bit)) \
 423                 : "cc", "0", "1" ); \
 424         })
 425
 426 #define __ctl_clear_bit(cr, bit) ({ \
 427         __u8 __dummy[16]; \
 428         __asm__ __volatile__ ( \
 429                 "    bras  1,0f\n"       /* skip indirect insns */ \
 430                 "    stctl 0,0,0(%1)\n" \
 431                 "    lctl  0,0,0(%1)\n" \
 432                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 433                 "    l     0,0(%1)\n" \
 434                 "    nr    0,%3\n"       /* set the bit */ \
 435                 "    st    0,0(%1)\n" \
 436                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 437                 : "=m" (__dummy) \
 438                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 439                   "a" (cr*17), "a" (~(1<<(bit))) \
 440                 : "cc", "0", "1" ); \
 441         })
 442 #endif /* __s390x__ */
 443
 444 /* For spinlocks etc */
 445 #define local_irq_save(x)       ((x) = local_irq_disable())
 446
 447 /*
 448  * Use to set psw mask except for the first byte which
 449  * won't be changed by this function.
 450  */
 451 static inline void
 452 __set_psw_mask(unsigned long mask)
 453 {
 454         local_save_flags(mask);
 455         __load_psw_mask(mask);
 456 }
 457
 458 #define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
 459 #define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
 460
 461 #ifdef CONFIG_SMP
 462
 463 extern void smp_ctl_set_bit(int cr, int bit);
 464 extern void smp_ctl_clear_bit(int cr, int bit);
 465 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
 466 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
 467
 468 #else
 469
 470 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
 471 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
 472
 473 #endif /* CONFIG_SMP */
 474
 475 extern void (*_machine_restart)(char *command);
 476 extern void (*_machine_halt)(void);
 477 extern void (*_machine_power_off)(void);
 478
 479 #define arch_align_stack(x) (x)
 480
 481 #endif /* __KERNEL__ */
 482
 483 #endif
 484