include/asm-mips/system.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/dsp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/war.h>
  23 #include <asm/interrupt.h>
  24
  25 /*
  26  * read_barrier_depends - Flush all pending reads that subsequents reads
  27  * depend on.
  28  *
  29  * No data-dependent reads from memory-like regions are ever reordered
  30  * over this barrier.  All reads preceding this primitive are guaranteed
  31  * to access memory (but not necessarily other CPUs' caches) before any
  32  * reads following this primitive that depend on the data return by
  33  * any of the preceding reads.  This primitive is much lighter weight than
  34  * rmb() on most CPUs, and is never heavier weight than is
  35  * rmb().
  36  *
  37  * These ordering constraints are respected by both the local CPU
  38  * and the compiler.
  39  *
  40  * Ordering is not guaranteed by anything other than these primitives,
  41  * not even by data dependencies.  See the documentation for
  42  * memory_barrier() for examples and URLs to more information.
  43  *
  44  * For example, the following code would force ordering (the initial
  45  * value of "a" is zero, "b" is one, and "p" is "&a"):
  46  *
  47  * <programlisting>
  48  *      CPU 0                           CPU 1
  49  *
  50  *      b = 2;
  51  *      memory_barrier();
  52  *      p = &b;                         q = p;
  53  *                                      read_barrier_depends();
  54  *                                      d = *q;
  55  * </programlisting>
  56  *
  57  * because the read of "*q" depends on the read of "p" and these
  58  * two reads are separated by a read_barrier_depends().  However,
  59  * the following code, with the same initial values for "a" and "b":
  60  *
  61  * <programlisting>
  62  *      CPU 0                           CPU 1
  63  *
  64  *      a = 2;
  65  *      memory_barrier();
  66  *      b = 3;                          y = b;
  67  *                                      read_barrier_depends();
  68  *                                      x = a;
  69  * </programlisting>
  70  *
  71  * does not enforce ordering, since there is no data dependency between
  72  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
  73  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  74  * in cases like this where there are no data dependencies.
  75  */
  76
  77 #define read_barrier_depends()  do { } while(0)
  78
  79 #ifdef CONFIG_CPU_HAS_SYNC
  80 #define __sync()                                \
  81         __asm__ __volatile__(                   \
  82                 ".set   push\n\t"               \
  83                 ".set   noreorder\n\t"          \
  84                 ".set   mips2\n\t"              \
  85                 "sync\n\t"                      \
  86                 ".set   pop"                    \
  87                 : /* no output */               \
  88                 : /* no input */                \
  89                 : "memory")
  90 #else
  91 #define __sync()        do { } while(0)
  92 #endif
  93
  94 #define __fast_iob()                            \
  95         __asm__ __volatile__(                   \
  96                 ".set   push\n\t"               \
  97                 ".set   noreorder\n\t"          \
  98                 "lw     $0,%0\n\t"              \
  99                 "nop\n\t"                       \
 100                 ".set   pop"                    \
 101                 : /* no output */               \
 102                 : "m" (*(int *)CKSEG1)          \
 103                 : "memory")
 104
 105 #define fast_wmb()      __sync()
 106 #define fast_rmb()      __sync()
 107 #define fast_mb()       __sync()
 108 #define fast_iob()                              \
 109         do {                                    \
 110                 __sync();                       \
 111                 __fast_iob();                   \
 112         } while (0)
 113
 114 #ifdef CONFIG_CPU_HAS_WB
 115
 116 #include <asm/wbflush.h>
 117
 118 #define wmb()           fast_wmb()
 119 #define rmb()           fast_rmb()
 120 #define mb()            wbflush()
 121 #define iob()           wbflush()
 122
 123 #else /* !CONFIG_CPU_HAS_WB */
 124
 125 #define wmb()           fast_wmb()
 126 #define rmb()           fast_rmb()
 127 #define mb()            fast_mb()
 128 #define iob()           fast_iob()
 129
 130 #endif /* !CONFIG_CPU_HAS_WB */
 131
 132 #ifdef CONFIG_SMP
 133 #define smp_mb()        mb()
 134 #define smp_rmb()       rmb()
 135 #define smp_wmb()       wmb()
 136 #define smp_read_barrier_depends()      read_barrier_depends()
 137 #else
 138 #define smp_mb()        barrier()
 139 #define smp_rmb()       barrier()
 140 #define smp_wmb()       barrier()
 141 #define smp_read_barrier_depends()      do { } while(0)
 142 #endif
 143
 144 #define set_mb(var, value) \
 145 do { var = value; mb(); } while (0)
 146
 147 #define set_wmb(var, value) \
 148 do { var = value; wmb(); } while (0)
 149
 150 /*
 151  * switch_to(n) should switch tasks to task nr n, first
 152  * checking that n isn't the current task, in which case it does nothing.
 153  */
 154 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 155
 156 struct task_struct;
 157
 158 #ifdef CONFIG_MIPS_MT_FPAFF
 159
 160 /*
 161  * Handle the scheduler resume end of FPU affinity management.  We do this
 162  * inline to try to keep the overhead down. If we have been forced to run on
 163  * a "CPU" with an FPU because of a previous high level of FP computation,
 164  * but did not actually use the FPU during the most recent time-slice (CU1
 165  * isn't set), we undo the restriction on cpus_allowed.
 166  *
 167  * We're not calling set_cpus_allowed() here, because we have no need to
 168  * force prompt migration - we're already switching the current CPU to a
 169  * different thread.
 170  */
 171
 172 #define switch_to(prev,next,last)                                       \
 173 do {                                                                    \
 174         if (cpu_has_fpu &&                                              \
 175             (prev->thread.mflags & MF_FPUBOUND) &&                      \
 176              (!(KSTK_STATUS(prev) & ST0_CU1))) {                        \
 177                 prev->thread.mflags &= ~MF_FPUBOUND;                    \
 178                 prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
 179         }                                                               \
 180         if (cpu_has_dsp)                                                \
 181                 __save_dsp(prev);                                       \
 182         next->thread.emulated_fp = 0;                                   \
 183         (last) = resume(prev, next, next->thread_info);                 \
 184         if (cpu_has_dsp)                                                \
 185                 __restore_dsp(current);                                 \
 186 } while(0)
 187
 188 #else
 189 #define switch_to(prev,next,last)                                       \
 190 do {                                                                    \
 191         if (cpu_has_dsp)                                                \
 192                 __save_dsp(prev);                                       \
 193         (last) = resume(prev, next, task_thread_info(next));            \
 194         if (cpu_has_dsp)                                                \
 195                 __restore_dsp(current);                                 \
 196 } while(0)
 197 #endif
 198
 199 /*
 200  * On SMP systems, when the scheduler does migration-cost autodetection,
 201  * it needs a way to flush as much of the CPU's caches as possible.
 202  *
 203  * TODO: fill this in!
 204  */
 205 static inline void sched_cacheflush(void)
 206 {
 207 }
 208
 209 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 210 {
 211         __u32 retval;
 212
 213         if (cpu_has_llsc && R10000_LLSC_WAR) {
 214                 unsigned long dummy;
 215
 216                 __asm__ __volatile__(
 217                 "       .set    mips3                                   \n"
 218                 "1:     ll      %0, %3                  # xchg_u32      \n"
 219                 "       .set    mips0                                   \n"
 220                 "       move    %2, %z4                                 \n"
 221                 "       .set    mips3                                   \n"
 222                 "       sc      %2, %1                                  \n"
 223                 "       beqzl   %2, 1b                                  \n"
 224 #ifdef CONFIG_SMP
 225                 "       sync                                            \n"
 226 #endif
 227                 "       .set    mips0                                   \n"
 228                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 229                 : "R" (*m), "Jr" (val)
 230                 : "memory");
 231         } else if (cpu_has_llsc) {
 232                 unsigned long dummy;
 233
 234                 __asm__ __volatile__(
 235                 "       .set    mips3                                   \n"
 236                 "1:     ll      %0, %3                  # xchg_u32      \n"
 237                 "       .set    mips0                                   \n"
 238                 "       move    %2, %z4                                 \n"
 239                 "       .set    mips3                                   \n"
 240                 "       sc      %2, %1                                  \n"
 241                 "       beqz    %2, 1b                                  \n"
 242 #ifdef CONFIG_SMP
 243                 "       sync                                            \n"
 244 #endif
 245                 "       .set    mips0                                   \n"
 246                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 247                 : "R" (*m), "Jr" (val)
 248                 : "memory");
 249         } else {
 250                 unsigned long flags;
 251
 252                 local_irq_save(flags);
 253                 retval = *m;
 254                 *m = val;
 255                 local_irq_restore(flags);       /* implies memory barrier  */
 256         }
 257
 258         return retval;
 259 }
 260
 261 #ifdef CONFIG_64BIT
 262 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 263 {
 264         __u64 retval;
 265
 266         if (cpu_has_llsc && R10000_LLSC_WAR) {
 267                 unsigned long dummy;
 268
 269                 __asm__ __volatile__(
 270                 "       .set    mips3                                   \n"
 271                 "1:     lld     %0, %3                  # xchg_u64      \n"
 272                 "       move    %2, %z4                                 \n"
 273                 "       scd     %2, %1                                  \n"
 274                 "       beqzl   %2, 1b                                  \n"
 275 #ifdef CONFIG_SMP
 276                 "       sync                                            \n"
 277 #endif
 278                 "       .set    mips0                                   \n"
 279                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 280                 : "R" (*m), "Jr" (val)
 281                 : "memory");
 282         } else if (cpu_has_llsc) {
 283                 unsigned long dummy;
 284
 285                 __asm__ __volatile__(
 286                 "       .set    mips3                                   \n"
 287                 "1:     lld     %0, %3                  # xchg_u64      \n"
 288                 "       move    %2, %z4                                 \n"
 289                 "       scd     %2, %1                                  \n"
 290                 "       beqz    %2, 1b                                  \n"
 291 #ifdef CONFIG_SMP
 292                 "       sync                                            \n"
 293 #endif
 294                 "       .set    mips0                                   \n"
 295                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 296                 : "R" (*m), "Jr" (val)
 297                 : "memory");
 298         } else {
 299                 unsigned long flags;
 300
 301                 local_irq_save(flags);
 302                 retval = *m;
 303                 *m = val;
 304                 local_irq_restore(flags);       /* implies memory barrier  */
 305         }
 306
 307         return retval;
 308 }
 309 #else
 310 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 311 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 312 #endif
 313
 314 /* This function doesn't exist, so you'll get a linker error
 315    if something tries to do an invalid xchg().  */
 316 extern void __xchg_called_with_bad_pointer(void);
 317
 318 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 319 {
 320         switch (size) {
 321         case 4:
 322                 return __xchg_u32(ptr, x);
 323         case 8:
 324                 return __xchg_u64(ptr, x);
 325         }
 326         __xchg_called_with_bad_pointer();
 327         return x;
 328 }
 329
 330 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 331 #define tas(ptr) (xchg((ptr),1))
 332
 333 #define __HAVE_ARCH_CMPXCHG 1
 334
 335 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 336         unsigned long new)
 337 {
 338         __u32 retval;
 339
 340         if (cpu_has_llsc && R10000_LLSC_WAR) {
 341                 __asm__ __volatile__(
 342                 "       .set    push                                    \n"
 343                 "       .set    noat                                    \n"
 344                 "       .set    mips3                                   \n"
 345                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 346                 "       bne     %0, %z3, 2f                             \n"
 347                 "       .set    mips0                                   \n"
 348                 "       move    $1, %z4                                 \n"
 349                 "       .set    mips3                                   \n"
 350                 "       sc      $1, %1                                  \n"
 351                 "       beqzl   $1, 1b                                  \n"
 352 #ifdef CONFIG_SMP
 353                 "       sync                                            \n"
 354 #endif
 355                 "2:                                                     \n"
 356                 "       .set    pop                                     \n"
 357                 : "=&r" (retval), "=R" (*m)
 358                 : "R" (*m), "Jr" (old), "Jr" (new)
 359                 : "memory");
 360         } else if (cpu_has_llsc) {
 361                 __asm__ __volatile__(
 362                 "       .set    push                                    \n"
 363                 "       .set    noat                                    \n"
 364                 "       .set    mips3                                   \n"
 365                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 366                 "       bne     %0, %z3, 2f                             \n"
 367                 "       .set    mips0                                   \n"
 368                 "       move    $1, %z4                                 \n"
 369                 "       .set    mips3                                   \n"
 370                 "       sc      $1, %1                                  \n"
 371                 "       beqz    $1, 1b                                  \n"
 372 #ifdef CONFIG_SMP
 373                 "       sync                                            \n"
 374 #endif
 375                 "2:                                                     \n"
 376                 "       .set    pop                                     \n"
 377                 : "=&r" (retval), "=R" (*m)
 378                 : "R" (*m), "Jr" (old), "Jr" (new)
 379                 : "memory");
 380         } else {
 381                 unsigned long flags;
 382
 383                 local_irq_save(flags);
 384                 retval = *m;
 385                 if (retval == old)
 386                         *m = new;
 387                 local_irq_restore(flags);       /* implies memory barrier  */
 388         }
 389
 390         return retval;
 391 }
 392
 393 #ifdef CONFIG_64BIT
 394 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 395         unsigned long new)
 396 {
 397         __u64 retval;
 398
 399         if (cpu_has_llsc) {
 400                 __asm__ __volatile__(
 401                 "       .set    push                                    \n"
 402                 "       .set    noat                                    \n"
 403                 "       .set    mips3                                   \n"
 404                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 405                 "       bne     %0, %z3, 2f                             \n"
 406                 "       move    $1, %z4                                 \n"
 407                 "       scd     $1, %1                                  \n"
 408                 "       beqzl   $1, 1b                                  \n"
 409 #ifdef CONFIG_SMP
 410                 "       sync                                            \n"
 411 #endif
 412                 "2:                                                     \n"
 413                 "       .set    pop                                     \n"
 414                 : "=&r" (retval), "=R" (*m)
 415                 : "R" (*m), "Jr" (old), "Jr" (new)
 416                 : "memory");
 417         } else if (cpu_has_llsc) {
 418                 __asm__ __volatile__(
 419                 "       .set    push                                    \n"
 420                 "       .set    noat                                    \n"
 421                 "       .set    mips3                                   \n"
 422                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 423                 "       bne     %0, %z3, 2f                             \n"
 424                 "       move    $1, %z4                                 \n"
 425                 "       scd     $1, %1                                  \n"
 426                 "       beqz    $1, 1b                                  \n"
 427 #ifdef CONFIG_SMP
 428                 "       sync                                            \n"
 429 #endif
 430                 "2:                                                     \n"
 431                 "       .set    pop                                     \n"
 432                 : "=&r" (retval), "=R" (*m)
 433                 : "R" (*m), "Jr" (old), "Jr" (new)
 434                 : "memory");
 435         } else {
 436                 unsigned long flags;
 437
 438                 local_irq_save(flags);
 439                 retval = *m;
 440                 if (retval == old)
 441                         *m = new;
 442                 local_irq_restore(flags);       /* implies memory barrier  */
 443         }
 444
 445         return retval;
 446 }
 447 #else
 448 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
 449         volatile int * m, unsigned long old, unsigned long new);
 450 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
 451 #endif
 452
 453 /* This function doesn't exist, so you'll get a linker error
 454    if something tries to do an invalid cmpxchg().  */
 455 extern void __cmpxchg_called_with_bad_pointer(void);
 456
 457 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 458         unsigned long new, int size)
 459 {
 460         switch (size) {
 461         case 4:
 462                 return __cmpxchg_u32(ptr, old, new);
 463         case 8:
 464                 return __cmpxchg_u64(ptr, old, new);
 465         }
 466         __cmpxchg_called_with_bad_pointer();
 467         return old;
 468 }
 469
 470 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 471
 472 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
 473 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
 474 extern void *set_vi_handler (int n, void *addr);
 475 extern void *set_except_vector(int n, void *addr);
 476 extern unsigned long ebase;
 477 extern void per_cpu_trap_init(void);
 478
 479 extern NORET_TYPE void die(const char *, struct pt_regs *);
 480
 481 static inline void die_if_kernel(const char *str, struct pt_regs *regs)
 482 {
 483         if (unlikely(!user_mode(regs)))
 484                 die(str, regs);
 485 }
 486
 487 extern int stop_a_enabled;
 488
 489 /*
 490  * See include/asm-ia64/system.h; prevents deadlock on SMP
 491  * systems.
 492  */
 493 #define __ARCH_WANT_UNLOCKED_CTXSW
 494
 495 #define arch_align_stack(x) (x)
 496
 497 #endif /* _ASM_SYSTEM_H */