include/asm-mips/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/addrspace.h>
  20 #include <asm/byteorder.h>
  21 #include <asm/cpu.h>
  22 #include <asm/cpu-features.h>
  23 #include <asm/page.h>
  24 #include <asm/pgtable-bits.h>
  25 #include <asm/processor.h>
  26 #include <asm/string.h>
  27
  28 #include <ioremap.h>
  29 #include <mangle-port.h>
  30
  31 /*
  32  * Slowdown I/O port space accesses for antique hardware.
  33  */
  34 #undef CONF_SLOWDOWN_IO
  35
  36 /*
  37  * Raw operations are never swapped in software.  OTOH values that raw
  38  * operations are working on may or may not have been swapped by the bus
  39  * hardware.  An example use would be for flash memory that's used for
  40  * execute in place.
  41  */
  42 # define __raw_ioswabb(a,x)     (x)
  43 # define __raw_ioswabw(a,x)     (x)
  44 # define __raw_ioswabl(a,x)     (x)
  45 # define __raw_ioswabq(a,x)     (x)
  46 # define ____raw_ioswabq(a,x)   (x)
  47
  48 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  49
  50 #define IO_SPACE_LIMIT 0xffff
  51
  52 /*
  53  * On MIPS I/O ports are memory mapped, so we access them using normal
  54  * load/store instructions. mips_io_port_base is the virtual address to
  55  * which all ports are being mapped.  For sake of efficiency some code
  56  * assumes that this is an address that can be loaded with a single lui
  57  * instruction, so the lower 16 bits must be zero.  Should be true on
  58  * on any sane architecture; generic code does not use this assumption.
  59  */
  60 extern const unsigned long mips_io_port_base;
  61
  62 /*
  63  * Gcc will generate code to load the value of mips_io_port_base after each
  64  * function call which may be fairly wasteful in some cases.  So we don't
  65  * play quite by the book.  We tell gcc mips_io_port_base is a long variable
  66  * which solves the code generation issue.  Now we need to violate the
  67  * aliasing rules a little to make initialization possible and finally we
  68  * will need the barrier() to fight side effects of the aliasing chat.
  69  * This trickery will eventually collapse under gcc's optimizer.  Oh well.
  70  */
  71 static inline void set_io_port_base(unsigned long base)
  72 {
  73         * (unsigned long *) &mips_io_port_base = base;
  74         barrier();
  75 }
  76
  77 /*
  78  * Thanks to James van Artsdalen for a better timing-fix than
  79  * the two short jumps: using outb's to a nonexistent port seems
  80  * to guarantee better timings even on fast machines.
  81  *
  82  * On the other hand, I'd like to be sure of a non-existent port:
  83  * I feel a bit unsafe about using 0x80 (should be safe, though)
  84  *
  85  *              Linus
  86  *
  87  */
  88
  89 #define __SLOW_DOWN_IO \
  90         __asm__ __volatile__( \
  91                 "sb\t$0,0x80(%0)" \
  92                 : : "r" (mips_io_port_base));
  93
  94 #ifdef CONF_SLOWDOWN_IO
  95 #ifdef REALLY_SLOW_IO
  96 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
  97 #else
  98 #define SLOW_DOWN_IO __SLOW_DOWN_IO
  99 #endif
 100 #else
 101 #define SLOW_DOWN_IO
 102 #endif
 103
 104 /*
 105  *     virt_to_phys    -       map virtual addresses to physical
 106  *     @address: address to remap
 107  *
 108  *     The returned physical address is the physical (CPU) mapping for
 109  *     the memory address given. It is only valid to use this function on
 110  *     addresses directly mapped or allocated via kmalloc.
 111  *
 112  *     This function does not give bus mappings for DMA transfers. In
 113  *     almost all conceivable cases a device driver should not be using
 114  *     this function
 115  */
 116 static inline unsigned long virt_to_phys(volatile void * address)
 117 {
 118         return (unsigned long)address - PAGE_OFFSET;
 119 }
 120
 121 /*
 122  *     phys_to_virt    -       map physical address to virtual
 123  *     @address: address to remap
 124  *
 125  *     The returned virtual address is a current CPU mapping for
 126  *     the memory address given. It is only valid to use this function on
 127  *     addresses that have a kernel mapping
 128  *
 129  *     This function does not handle bus mappings for DMA transfers. In
 130  *     almost all conceivable cases a device driver should not be using
 131  *     this function
 132  */
 133 static inline void * phys_to_virt(unsigned long address)
 134 {
 135         return (void *)(address + PAGE_OFFSET);
 136 }
 137
 138 /*
 139  * ISA I/O bus memory addresses are 1:1 with the physical address.
 140  */
 141 static inline unsigned long isa_virt_to_bus(volatile void * address)
 142 {
 143         return (unsigned long)address - PAGE_OFFSET;
 144 }
 145
 146 static inline void * isa_bus_to_virt(unsigned long address)
 147 {
 148         return (void *)(address + PAGE_OFFSET);
 149 }
 150
 151 #define isa_page_to_bus page_to_phys
 152
 153 /*
 154  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 155  * are forbidden in portable PCI drivers.
 156  *
 157  * Allow them for x86 for legacy drivers, though.
 158  */
 159 #define virt_to_bus virt_to_phys
 160 #define bus_to_virt phys_to_virt
 161
 162 /*
 163  * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
 164  * for the processor.  This implies the assumption that there is only
 165  * one of these busses.
 166  */
 167 extern unsigned long isa_slot_offset;
 168
 169 /*
 170  * Change "struct page" to physical address.
 171  */
 172 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 173
 174 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 175 extern void __iounmap(volatile void __iomem *addr);
 176
 177 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 178         unsigned long flags)
 179 {
 180 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
 181
 182         if (cpu_has_64bit_addresses) {
 183                 u64 base = UNCAC_BASE;
 184
 185                 /*
 186                  * R10000 supports a 2 bit uncached attribute therefore
 187                  * UNCAC_BASE may not equal IO_BASE.
 188                  */
 189                 if (flags == _CACHE_UNCACHED)
 190                         base = (u64) IO_BASE;
 191                 return (void __iomem *) (unsigned long) (base + offset);
 192         } else if (__builtin_constant_p(offset) &&
 193                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
 194                 phys_t phys_addr, last_addr;
 195
 196                 phys_addr = fixup_bigphys_addr(offset, size);
 197
 198                 /* Don't allow wraparound or zero size. */
 199                 last_addr = phys_addr + size - 1;
 200                 if (!size || last_addr < phys_addr)
 201                         return NULL;
 202
 203                 /*
 204                  * Map uncached objects in the low 512MB of address
 205                  * space using KSEG1.
 206                  */
 207                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
 208                     flags == _CACHE_UNCACHED)
 209                         return (void __iomem *)CKSEG1ADDR(phys_addr);
 210         }
 211
 212         return __ioremap(offset, size, flags);
 213
 214 #undef __IS_LOW512
 215 }
 216
 217 /*
 218  * ioremap     -   map bus memory into CPU space
 219  * @offset:    bus address of the memory
 220  * @size:      size of the resource to map
 221  *
 222  * ioremap performs a platform specific sequence of operations to
 223  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 224  * writew/writel functions and the other mmio helpers. The returned
 225  * address is not guaranteed to be usable directly as a virtual
 226  * address.
 227  */
 228 #define ioremap(offset, size)                                           \
 229         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 230
 231 /*
 232  * ioremap_nocache     -   map bus memory into CPU space
 233  * @offset:    bus address of the memory
 234  * @size:      size of the resource to map
 235  *
 236  * ioremap_nocache performs a platform specific sequence of operations to
 237  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 238  * writew/writel functions and the other mmio helpers. The returned
 239  * address is not guaranteed to be usable directly as a virtual
 240  * address.
 241  *
 242  * This version of ioremap ensures that the memory is marked uncachable
 243  * on the CPU as well as honouring existing caching rules from things like
 244  * the PCI bus. Note that there are other caches and buffers on many
 245  * busses. In paticular driver authors should read up on PCI writes
 246  *
 247  * It's useful if some control registers are in such an area and
 248  * write combining or read caching is not desirable:
 249  */
 250 #define ioremap_nocache(offset, size)                                   \
 251         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 252
 253 /*
 254  * ioremap_cachable -   map bus memory into CPU space
 255  * @offset:         bus address of the memory
 256  * @size:           size of the resource to map
 257  *
 258  * ioremap_nocache performs a platform specific sequence of operations to
 259  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 260  * writew/writel functions and the other mmio helpers. The returned
 261  * address is not guaranteed to be usable directly as a virtual
 262  * address.
 263  *
 264  * This version of ioremap ensures that the memory is marked cachable by
 265  * the CPU.  Also enables full write-combining.  Useful for some
 266  * memory-like regions on I/O busses.
 267  */
 268 #define ioremap_cachable(offset, size)                                  \
 269         __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
 270
 271 /*
 272  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
 273  * requests a cachable mapping, ioremap_uncached_accelerated requests a
 274  * mapping using the uncached accelerated mode which isn't supported on
 275  * all processors.
 276  */
 277 #define ioremap_cacheable_cow(offset, size)                             \
 278         __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
 279 #define ioremap_uncached_accelerated(offset, size)                      \
 280         __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
 281
 282 static inline void iounmap(volatile void __iomem *addr)
 283 {
 284 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
 285
 286         if (cpu_has_64bit_addresses ||
 287             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
 288                 return;
 289
 290         __iounmap(addr);
 291
 292 #undef __IS_KSEG1
 293 }
 294
 295 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
 296                                                                         \
 297 static inline void pfx##write##bwlq(type val,                           \
 298                                     volatile void __iomem *mem)         \
 299 {                                                                       \
 300         volatile type *__mem;                                           \
 301         type __val;                                                     \
 302                                                                         \
 303         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 304                                                                         \
 305         __val = pfx##ioswab##bwlq(__mem, val);                          \
 306                                                                         \
 307         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 308                 *__mem = __val;                                         \
 309         else if (cpu_has_64bits) {                                      \
 310                 unsigned long __flags;                                  \
 311                 type __tmp;                                             \
 312                                                                         \
 313                 if (irq)                                                \
 314                         local_irq_save(__flags);                        \
 315                 __asm__ __volatile__(                                   \
 316                         ".set   mips3"          "\t\t# __writeq""\n\t"  \
 317                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 318                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 319                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 320                         "or     %L0, %L0, %M0"                  "\n\t"  \
 321                         "sd     %L0, %2"                        "\n\t"  \
 322                         ".set   mips0"                          "\n"    \
 323                         : "=r" (__tmp)                                  \
 324                         : "0" (__val), "m" (*__mem));                   \
 325                 if (irq)                                                \
 326                         local_irq_restore(__flags);                     \
 327         } else                                                          \
 328                 BUG();                                                  \
 329 }                                                                       \
 330                                                                         \
 331 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 332 {                                                                       \
 333         volatile type *__mem;                                           \
 334         type __val;                                                     \
 335                                                                         \
 336         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 337                                                                         \
 338         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 339                 __val = *__mem;                                         \
 340         else if (cpu_has_64bits) {                                      \
 341                 unsigned long __flags;                                  \
 342                                                                         \
 343                 if (irq)                                                \
 344                         local_irq_save(__flags);                        \
 345                 __asm__ __volatile__(                                   \
 346                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
 347                         "ld     %L0, %1"                        "\n\t"  \
 348                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 349                         "sll    %L0, %L0, 0"                    "\n\t"  \
 350                         ".set   mips0"                          "\n"    \
 351                         : "=r" (__val)                                  \
 352                         : "m" (*__mem));                                \
 353                 if (irq)                                                \
 354                         local_irq_restore(__flags);                     \
 355         } else {                                                        \
 356                 __val = 0;                                              \
 357                 BUG();                                                  \
 358         }                                                               \
 359                                                                         \
 360         return pfx##ioswab##bwlq(__mem, __val);                         \
 361 }
 362
 363 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 364                                                                         \
 365 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 366 {                                                                       \
 367         volatile type *__addr;                                          \
 368         type __val;                                                     \
 369                                                                         \
 370         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 371                                                                         \
 372         __val = pfx##ioswab##bwlq(__addr, val);                         \
 373                                                                         \
 374         /* Really, we want this to be atomic */                         \
 375         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 376                                                                         \
 377         *__addr = __val;                                                \
 378         slow;                                                           \
 379 }                                                                       \
 380                                                                         \
 381 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 382 {                                                                       \
 383         volatile type *__addr;                                          \
 384         type __val;                                                     \
 385                                                                         \
 386         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 387                                                                         \
 388         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 389                                                                         \
 390         __val = *__addr;                                                \
 391         slow;                                                           \
 392                                                                         \
 393         return pfx##ioswab##bwlq(__addr, __val);                        \
 394 }
 395
 396 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
 397                                                                         \
 398 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 399
 400 #define BUILDIO_MEM(bwlq, type)                                         \
 401                                                                         \
 402 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
 403 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
 404 __BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
 405
 406 BUILDIO_MEM(b, u8)
 407 BUILDIO_MEM(w, u16)
 408 BUILDIO_MEM(l, u32)
 409 BUILDIO_MEM(q, u64)
 410
 411 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 412         __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
 413         __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 414
 415 #define BUILDIO_IOPORT(bwlq, type)                                      \
 416         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 417         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 418
 419 BUILDIO_IOPORT(b, u8)
 420 BUILDIO_IOPORT(w, u16)
 421 BUILDIO_IOPORT(l, u32)
 422 #ifdef CONFIG_64BIT
 423 BUILDIO_IOPORT(q, u64)
 424 #endif
 425
 426 #define __BUILDIO(bwlq, type)                                           \
 427                                                                         \
 428 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 429
 430 __BUILDIO(q, u64)
 431
 432 #define readb_relaxed                   readb
 433 #define readw_relaxed                   readw
 434 #define readl_relaxed                   readl
 435 #define readq_relaxed                   readq
 436
 437 /*
 438  * Some code tests for these symbols
 439  */
 440 #define readq                           readq
 441 #define writeq                          writeq
 442
 443 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 444                                                                         \
 445 static inline void writes##bwlq(volatile void __iomem *mem,             \
 446                                 const void *addr, unsigned int count)   \
 447 {                                                                       \
 448         const volatile type *__addr = addr;                             \
 449                                                                         \
 450         while (count--) {                                               \
 451                 __mem_write##bwlq(*__addr, mem);                        \
 452                 __addr++;                                               \
 453         }                                                               \
 454 }                                                                       \
 455                                                                         \
 456 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 457                                unsigned int count)                      \
 458 {                                                                       \
 459         volatile type *__addr = addr;                                   \
 460                                                                         \
 461         while (count--) {                                               \
 462                 *__addr = __mem_read##bwlq(mem);                        \
 463                 __addr++;                                               \
 464         }                                                               \
 465 }
 466
 467 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 468                                                                         \
 469 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 470                               unsigned int count)                       \
 471 {                                                                       \
 472         const volatile type *__addr = addr;                             \
 473                                                                         \
 474         while (count--) {                                               \
 475                 __mem_out##bwlq(*__addr, port);                         \
 476                 __addr++;                                               \
 477         }                                                               \
 478 }                                                                       \
 479                                                                         \
 480 static inline void ins##bwlq(unsigned long port, void *addr,            \
 481                              unsigned int count)                        \
 482 {                                                                       \
 483         volatile type *__addr = addr;                                   \
 484                                                                         \
 485         while (count--) {                                               \
 486                 *__addr = __mem_in##bwlq(port);                         \
 487                 __addr++;                                               \
 488         }                                                               \
 489 }
 490
 491 #define BUILDSTRING(bwlq, type)                                         \
 492                                                                         \
 493 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 494 __BUILD_IOPORT_STRING(bwlq, type)
 495
 496 BUILDSTRING(b, u8)
 497 BUILDSTRING(w, u16)
 498 BUILDSTRING(l, u32)
 499 #ifdef CONFIG_64BIT
 500 BUILDSTRING(q, u64)
 501 #endif
 502
 503
 504 /* Depends on MIPS II instruction set */
 505 #define mmiowb() asm volatile ("sync" ::: "memory")
 506
 507 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 508 {
 509         memset((void __force *) addr, val, count);
 510 }
 511 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 512 {
 513         memcpy(dst, (void __force *) src, count);
 514 }
 515 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 516 {
 517         memcpy((void __force *) dst, src, count);
 518 }
 519
 520 /*
 521  * Memory Mapped I/O
 522  */
 523 #define ioread8(addr)           readb(addr)
 524 #define ioread16(addr)          readw(addr)
 525 #define ioread32(addr)          readl(addr)
 526
 527 #define iowrite8(b,addr)        writeb(b,addr)
 528 #define iowrite16(w,addr)       writew(w,addr)
 529 #define iowrite32(l,addr)       writel(l,addr)
 530
 531 #define ioread8_rep(a,b,c)      readsb(a,b,c)
 532 #define ioread16_rep(a,b,c)     readsw(a,b,c)
 533 #define ioread32_rep(a,b,c)     readsl(a,b,c)
 534
 535 #define iowrite8_rep(a,b,c)     writesb(a,b,c)
 536 #define iowrite16_rep(a,b,c)    writesw(a,b,c)
 537 #define iowrite32_rep(a,b,c)    writesl(a,b,c)
 538
 539 /* Create a virtual mapping cookie for an IO port range */
 540 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 541 extern void ioport_unmap(void __iomem *);
 542
 543 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 544 struct pci_dev;
 545 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 546 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 547
 548 /*
 549  * ISA space is 'always mapped' on currently supported MIPS systems, no need
 550  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
 551  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 552  * are physical addresses. The following constant pointer can be
 553  * used as the IO-area pointer (it can be iounmapped as well, so the
 554  * analogy with PCI is quite large):
 555  */
 556 #define __ISA_IO_base ((char *)(isa_slot_offset))
 557
 558 /*
 559  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
 560  * just copy it. The net code will then do the checksum later.
 561  */
 562 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
 563
 564 /*
 565  * The caches on some architectures aren't dma-coherent and have need to
 566  * handle this in software.  There are three types of operations that
 567  * can be applied to dma buffers.
 568  *
 569  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 570  *    writing the content of the caches back to memory, if necessary.
 571  *    The function also invalidates the affected part of the caches as
 572  *    necessary before DMA transfers from outside to memory.
 573  *  - dma_cache_wback(start, size) makes caches and coherent by
 574  *    writing the content of the caches back to memory, if necessary.
 575  *    The function also invalidates the affected part of the caches as
 576  *    necessary before DMA transfers from outside to memory.
 577  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 578  *    caches.  Dirty lines of the caches may be written back or simply
 579  *    be discarded.  This operation is necessary before dma operations
 580  *    to the memory.
 581  */
 582 #ifdef CONFIG_DMA_NONCOHERENT
 583
 584 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 585 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 586 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 587
 588 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start,size)
 589 #define dma_cache_wback(start, size)            _dma_cache_wback(start,size)
 590 #define dma_cache_inv(start, size)              _dma_cache_inv(start,size)
 591
 592 #else /* Sane hardware */
 593
 594 #define dma_cache_wback_inv(start,size) \
 595         do { (void) (start); (void) (size); } while (0)
 596 #define dma_cache_wback(start,size)     \
 597         do { (void) (start); (void) (size); } while (0)
 598 #define dma_cache_inv(start,size)       \
 599         do { (void) (start); (void) (size); } while (0)
 600
 601 #endif /* CONFIG_DMA_NONCOHERENT */
 602
 603 /*
 604  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 605  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 606  * Assume the addresses are 8-byte aligned.
 607  */
 608 #ifdef __MIPSEB__
 609 #define __CSR_32_ADJUST 4
 610 #else
 611 #define __CSR_32_ADJUST 0
 612 #endif
 613
 614 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 615 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 616
 617 /*
 618  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 619  * access
 620  */
 621 #define xlate_dev_mem_ptr(p)    __va(p)
 622
 623 /*
 624  * Convert a virtual cached pointer to an uncached pointer
 625  */
 626 #define xlate_dev_kmem_ptr(p)   p
 627
 628 #endif /* _ASM_IO_H */