include/asm-ia64/processor.h

   1 #ifndef _ASM_IA64_PROCESSOR_H
   2 #define _ASM_IA64_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 1998-2004 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *      Stephane Eranian <eranian@hpl.hp.com>
   8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10  *
  11  * 11/24/98     S.Eranian       added ia64_set_iva()
  12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14  */
  15
  16 #include <linux/config.h>
  17
  18 #include <asm/intrinsics.h>
  19 #include <asm/kregs.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/ustack.h>
  22
  23 #define IA64_NUM_DBG_REGS       8
  24 /*
  25  * Limits for PMC and PMD are set to less than maximum architected values
  26  * but should be sufficient for a while
  27  */
  28 #define IA64_NUM_PMC_REGS       64
  29 #define IA64_NUM_PMD_REGS       64
  30
  31 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
  32 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
  33
  34 /*
  35  * TASK_SIZE really is a mis-named.  It really is the maximum user
  36  * space address (plus one).  On IA-64, there are five regions of 2TB
  37  * each (assuming 8KB page size), for a total of 8TB of user virtual
  38  * address space.
  39  */
  40 #define TASK_SIZE               (current->thread.task_size)
  41
  42 /*
  43  * This decides where the kernel will search for a free chunk of vm
  44  * space during mmap's.
  45  */
  46 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
  47
  48 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
  49 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
  50 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
  51 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
  52 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
  53 #define IA64_THREAD_MIGRATION   (__IA64_UL(1) << 5)     /* require migration
  54                                                            sync at ctx sw */
  55 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
  56 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
  57
  58 #define IA64_THREAD_UAC_SHIFT   3
  59 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
  60 #define IA64_THREAD_FPEMU_SHIFT 6
  61 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
  62
  63
  64 /*
  65  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
  66  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
  67  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
  68  */
  69 #define IA64_NSEC_PER_CYC_SHIFT 30
  70
  71 #ifndef __ASSEMBLY__
  72
  73 #include <linux/cache.h>
  74 #include <linux/compiler.h>
  75 #include <linux/threads.h>
  76 #include <linux/types.h>
  77
  78 #include <asm/fpu.h>
  79 #include <asm/page.h>
  80 #include <asm/percpu.h>
  81 #include <asm/rse.h>
  82 #include <asm/unwind.h>
  83 #include <asm/atomic.h>
  84 #ifdef CONFIG_NUMA
  85 #include <asm/nodedata.h>
  86 #endif
  87
  88 /* like above but expressed as bitfields for more efficient access: */
  89 struct ia64_psr {
  90         __u64 reserved0 : 1;
  91         __u64 be : 1;
  92         __u64 up : 1;
  93         __u64 ac : 1;
  94         __u64 mfl : 1;
  95         __u64 mfh : 1;
  96         __u64 reserved1 : 7;
  97         __u64 ic : 1;
  98         __u64 i : 1;
  99         __u64 pk : 1;
 100         __u64 reserved2 : 1;
 101         __u64 dt : 1;
 102         __u64 dfl : 1;
 103         __u64 dfh : 1;
 104         __u64 sp : 1;
 105         __u64 pp : 1;
 106         __u64 di : 1;
 107         __u64 si : 1;
 108         __u64 db : 1;
 109         __u64 lp : 1;
 110         __u64 tb : 1;
 111         __u64 rt : 1;
 112         __u64 reserved3 : 4;
 113         __u64 cpl : 2;
 114         __u64 is : 1;
 115         __u64 mc : 1;
 116         __u64 it : 1;
 117         __u64 id : 1;
 118         __u64 da : 1;
 119         __u64 dd : 1;
 120         __u64 ss : 1;
 121         __u64 ri : 2;
 122         __u64 ed : 1;
 123         __u64 bn : 1;
 124         __u64 reserved4 : 19;
 125 };
 126
 127 /*
 128  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 129  * state comes earlier:
 130  */
 131 struct cpuinfo_ia64 {
 132         __u32 softirq_pending;
 133         __u64 itm_delta;        /* # of clock cycles between clock ticks */
 134         __u64 itm_next;         /* interval timer mask value to use for next clock tick */
 135         __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
 136         __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 137         __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 138         __u64 itc_freq;         /* frequency of ITC counter */
 139         __u64 proc_freq;        /* frequency of processor */
 140         __u64 cyc_per_usec;     /* itc_freq/1000000 */
 141         __u64 ptce_base;
 142         __u32 ptce_count[2];
 143         __u32 ptce_stride[2];
 144         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 145
 146 #ifdef CONFIG_SMP
 147         __u64 loops_per_jiffy;
 148         int cpu;
 149         __u32 socket_id;        /* physical processor socket id */
 150         __u16 core_id;          /* core id */
 151         __u16 thread_id;        /* thread id */
 152         __u16 num_log;          /* Total number of logical processors on
 153                                  * this socket that were successfully booted */
 154         __u8  cores_per_socket; /* Cores per processor socket */
 155         __u8  threads_per_core; /* Threads per core */
 156 #endif
 157
 158         /* CPUID-derived information: */
 159         __u64 ppn;
 160         __u64 features;
 161         __u8 number;
 162         __u8 revision;
 163         __u8 model;
 164         __u8 family;
 165         __u8 archrev;
 166         char vendor[16];
 167
 168 #ifdef CONFIG_NUMA
 169         struct ia64_node_data *node_data;
 170 #endif
 171 };
 172
 173 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
 174
 175 /*
 176  * The "local" data variable.  It refers to the per-CPU data of the currently executing
 177  * CPU, much like "current" points to the per-task data of the currently executing task.
 178  * Do not use the address of local_cpu_data, since it will be different from
 179  * cpu_data(smp_processor_id())!
 180  */
 181 #define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
 182 #define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
 183
 184 extern void print_cpu_info (struct cpuinfo_ia64 *);
 185
 186 typedef struct {
 187         unsigned long seg;
 188 } mm_segment_t;
 189
 190 #define SET_UNALIGN_CTL(task,value)                                                             \
 191 ({                                                                                              \
 192         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 193                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 194         0;                                                                                      \
 195 })
 196 #define GET_UNALIGN_CTL(task,addr)                                                              \
 197 ({                                                                                              \
 198         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 199                  (int __user *) (addr));                                                        \
 200 })
 201
 202 #define SET_FPEMU_CTL(task,value)                                                               \
 203 ({                                                                                              \
 204         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 205                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 206         0;                                                                                      \
 207 })
 208 #define GET_FPEMU_CTL(task,addr)                                                                \
 209 ({                                                                                              \
 210         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 211                  (int __user *) (addr));                                                        \
 212 })
 213
 214 #ifdef CONFIG_IA32_SUPPORT
 215 struct desc_struct {
 216         unsigned int a, b;
 217 };
 218
 219 #define desc_empty(desc)                (!((desc)->a + (desc)->b))
 220 #define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
 221
 222 #define GDT_ENTRY_TLS_ENTRIES   3
 223 #define GDT_ENTRY_TLS_MIN       6
 224 #define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
 225
 226 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
 227
 228 struct partial_page_list;
 229 #endif
 230
 231 struct thread_struct {
 232         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
 233         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
 234         __u8 on_ustack;                 /* executing on user-stacks? */
 235         __u8 pad[3];
 236         __u64 ksp;                      /* kernel stack pointer */
 237         __u64 map_base;                 /* base address for get_unmapped_area() */
 238         __u64 task_size;                /* limit for task size */
 239         __u64 rbs_bot;                  /* the base address for the RBS */
 240         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 241
 242 #ifdef CONFIG_IA32_SUPPORT
 243         __u64 eflag;                    /* IA32 EFLAGS reg */
 244         __u64 fsr;                      /* IA32 floating pt status reg */
 245         __u64 fcr;                      /* IA32 floating pt control reg */
 246         __u64 fir;                      /* IA32 fp except. instr. reg */
 247         __u64 fdr;                      /* IA32 fp except. data reg */
 248         __u64 old_k1;                   /* old value of ar.k1 */
 249         __u64 old_iob;                  /* old IOBase value */
 250         struct partial_page_list *ppl;  /* partial page list for 4K page size issue */
 251         /* cached TLS descriptors. */
 252         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 253
 254 # define INIT_THREAD_IA32       .eflag =        0,                      \
 255                                 .fsr =          0,                      \
 256                                 .fcr =          0x17800000037fULL,      \
 257                                 .fir =          0,                      \
 258                                 .fdr =          0,                      \
 259                                 .old_k1 =       0,                      \
 260                                 .old_iob =      0,                      \
 261                                 .ppl =          NULL,
 262 #else
 263 # define INIT_THREAD_IA32
 264 #endif /* CONFIG_IA32_SUPPORT */
 265 #ifdef CONFIG_PERFMON
 266         __u64 pmcs[IA64_NUM_PMC_REGS];
 267         __u64 pmds[IA64_NUM_PMD_REGS];
 268         void *pfm_context;                   /* pointer to detailed PMU context */
 269         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
 270 # define INIT_THREAD_PM         .pmcs =                 {0UL, },  \
 271                                 .pmds =                 {0UL, },  \
 272                                 .pfm_context =          NULL,     \
 273                                 .pfm_needs_checking =   0UL,
 274 #else
 275 # define INIT_THREAD_PM
 276 #endif
 277         __u64 dbr[IA64_NUM_DBG_REGS];
 278         __u64 ibr[IA64_NUM_DBG_REGS];
 279         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 280 };
 281
 282 #define INIT_THREAD {                                           \
 283         .flags =        0,                                      \
 284         .on_ustack =    0,                                      \
 285         .ksp =          0,                                      \
 286         .map_base =     DEFAULT_MAP_BASE,                       \
 287         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
 288         .task_size =    DEFAULT_TASK_SIZE,                      \
 289         .last_fph_cpu =  -1,                                    \
 290         INIT_THREAD_IA32                                        \
 291         INIT_THREAD_PM                                          \
 292         .dbr =          {0, },                                  \
 293         .ibr =          {0, },                                  \
 294         .fph =          {{{{0}}}, }                             \
 295 }
 296
 297 #define start_thread(regs,new_ip,new_sp) do {                                                   \
 298         set_fs(USER_DS);                                                                        \
 299         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
 300                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
 301         regs->cr_iip = new_ip;                                                                  \
 302         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 303         regs->ar_rnat = 0;                                                                      \
 304         regs->ar_bspstore = current->thread.rbs_bot;                                            \
 305         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 306         regs->loadrs = 0;                                                                       \
 307         regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
 308         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 309         if (unlikely(!current->mm->dumpable)) {                                                 \
 310                 /*                                                                              \
 311                  * Zap scratch regs to avoid leaking bits between processes with different      \
 312                  * uid/privileges.                                                              \
 313                  */                                                                             \
 314                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
 315                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
 316         }                                                                                       \
 317 } while (0)
 318
 319 /* Forward declarations, a strange C thing... */
 320 struct mm_struct;
 321 struct task_struct;
 322
 323 /*
 324  * Free all resources held by a thread. This is called after the
 325  * parent of DEAD_TASK has collected the exit status of the task via
 326  * wait().
 327  */
 328 #define release_thread(dead_task)
 329
 330 /* Prepare to copy thread state - unlazy all lazy status */
 331 #define prepare_to_copy(tsk)    do { } while (0)
 332
 333 /*
 334  * This is the mechanism for creating a new kernel thread.
 335  *
 336  * NOTE 1: Only a kernel-only process (ie the swapper or direct
 337  * descendants who haven't done an "execve()") should use this: it
 338  * will work within a system call from a "real" process, but the
 339  * process memory space will not be free'd until both the parent and
 340  * the child have exited.
 341  *
 342  * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
 343  * into trouble in init/main.c when the child thread returns to
 344  * do_basic_setup() and the timing is such that free_initmem() has
 345  * been called already.
 346  */
 347 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
 348
 349 /* Get wait channel for task P.  */
 350 extern unsigned long get_wchan (struct task_struct *p);
 351
 352 /* Return instruction pointer of blocked task TSK.  */
 353 #define KSTK_EIP(tsk)                                   \
 354   ({                                                    \
 355         struct pt_regs *_regs = task_pt_regs(tsk);      \
 356         _regs->cr_iip + ia64_psr(_regs)->ri;            \
 357   })
 358
 359 /* Return stack pointer of blocked task TSK.  */
 360 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 361
 362 extern void ia64_getreg_unknown_kr (void);
 363 extern void ia64_setreg_unknown_kr (void);
 364
 365 #define ia64_get_kr(regnum)                                     \
 366 ({                                                              \
 367         unsigned long r = 0;                                    \
 368                                                                 \
 369         switch (regnum) {                                       \
 370             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
 371             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
 372             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
 373             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
 374             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
 375             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
 376             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
 377             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
 378             default: ia64_getreg_unknown_kr(); break;           \
 379         }                                                       \
 380         r;                                                      \
 381 })
 382
 383 #define ia64_set_kr(regnum, r)                                  \
 384 ({                                                              \
 385         switch (regnum) {                                       \
 386             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
 387             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
 388             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
 389             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
 390             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
 391             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
 392             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
 393             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
 394             default: ia64_setreg_unknown_kr(); break;           \
 395         }                                                       \
 396 })
 397
 398 /*
 399  * The following three macros can't be inline functions because we don't have struct
 400  * task_struct at this point.
 401  */
 402
 403 /*
 404  * Return TRUE if task T owns the fph partition of the CPU we're running on.
 405  * Must be called from code that has preemption disabled.
 406  */
 407 #define ia64_is_local_fpu_owner(t)                                                              \
 408 ({                                                                                              \
 409         struct task_struct *__ia64_islfo_task = (t);                                            \
 410         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
 411          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 412 })
 413
 414 /*
 415  * Mark task T as owning the fph partition of the CPU we're running on.
 416  * Must be called from code that has preemption disabled.
 417  */
 418 #define ia64_set_local_fpu_owner(t) do {                                                \
 419         struct task_struct *__ia64_slfo_task = (t);                                     \
 420         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
 421         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
 422 } while (0)
 423
 424 /* Mark the fph partition of task T as being invalid on all CPUs.  */
 425 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
 426
 427 extern void __ia64_init_fpu (void);
 428 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 429 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 430 extern void ia64_save_debug_regs (unsigned long *save_area);
 431 extern void ia64_load_debug_regs (unsigned long *save_area);
 432
 433 #ifdef CONFIG_IA32_SUPPORT
 434 extern void ia32_save_state (struct task_struct *task);
 435 extern void ia32_load_state (struct task_struct *task);
 436 #endif
 437
 438 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 439 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 440
 441 /* load fp 0.0 into fph */
 442 static inline void
 443 ia64_init_fpu (void) {
 444         ia64_fph_enable();
 445         __ia64_init_fpu();
 446         ia64_fph_disable();
 447 }
 448
 449 /* save f32-f127 at FPH */
 450 static inline void
 451 ia64_save_fpu (struct ia64_fpreg *fph) {
 452         ia64_fph_enable();
 453         __ia64_save_fpu(fph);
 454         ia64_fph_disable();
 455 }
 456
 457 /* load f32-f127 from FPH */
 458 static inline void
 459 ia64_load_fpu (struct ia64_fpreg *fph) {
 460         ia64_fph_enable();
 461         __ia64_load_fpu(fph);
 462         ia64_fph_disable();
 463 }
 464
 465 static inline __u64
 466 ia64_clear_ic (void)
 467 {
 468         __u64 psr;
 469         psr = ia64_getreg(_IA64_REG_PSR);
 470         ia64_stop();
 471         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
 472         ia64_srlz_i();
 473         return psr;
 474 }
 475
 476 /*
 477  * Restore the psr.
 478  */
 479 static inline void
 480 ia64_set_psr (__u64 psr)
 481 {
 482         ia64_stop();
 483         ia64_setreg(_IA64_REG_PSR_L, psr);
 484         ia64_srlz_d();
 485 }
 486
 487 /*
 488  * Insert a translation into an instruction and/or data translation
 489  * register.
 490  */
 491 static inline void
 492 ia64_itr (__u64 target_mask, __u64 tr_num,
 493           __u64 vmaddr, __u64 pte,
 494           __u64 log_page_size)
 495 {
 496         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 497         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 498         ia64_stop();
 499         if (target_mask & 0x1)
 500                 ia64_itri(tr_num, pte);
 501         if (target_mask & 0x2)
 502                 ia64_itrd(tr_num, pte);
 503 }
 504
 505 /*
 506  * Insert a translation into the instruction and/or data translation
 507  * cache.
 508  */
 509 static inline void
 510 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 511           __u64 log_page_size)
 512 {
 513         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 514         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 515         ia64_stop();
 516         /* as per EAS2.6, itc must be the last instruction in an instruction group */
 517         if (target_mask & 0x1)
 518                 ia64_itci(pte);
 519         if (target_mask & 0x2)
 520                 ia64_itcd(pte);
 521 }
 522
 523 /*
 524  * Purge a range of addresses from instruction and/or data translation
 525  * register(s).
 526  */
 527 static inline void
 528 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 529 {
 530         if (target_mask & 0x1)
 531                 ia64_ptri(vmaddr, (log_size << 2));
 532         if (target_mask & 0x2)
 533                 ia64_ptrd(vmaddr, (log_size << 2));
 534 }
 535
 536 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 537 static inline void
 538 ia64_set_iva (void *ivt_addr)
 539 {
 540         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
 541         ia64_srlz_i();
 542 }
 543
 544 /* Set the page table address and control bits.  */
 545 static inline void
 546 ia64_set_pta (__u64 pta)
 547 {
 548         /* Note: srlz.i implies srlz.d */
 549         ia64_setreg(_IA64_REG_CR_PTA, pta);
 550         ia64_srlz_i();
 551 }
 552
 553 static inline void
 554 ia64_eoi (void)
 555 {
 556         ia64_setreg(_IA64_REG_CR_EOI, 0);
 557         ia64_srlz_d();
 558 }
 559
 560 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 561
 562 static inline int
 563 ia64_get_irr(unsigned int vector)
 564 {
 565         unsigned int reg = vector / 64;
 566         unsigned int bit = vector % 64;
 567         u64 irr;
 568
 569         switch (reg) {
 570         case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
 571         case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
 572         case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
 573         case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
 574         }
 575
 576         return test_bit(bit, &irr);
 577 }
 578
 579 static inline void
 580 ia64_set_lrr0 (unsigned long val)
 581 {
 582         ia64_setreg(_IA64_REG_CR_LRR0, val);
 583         ia64_srlz_d();
 584 }
 585
 586 static inline void
 587 ia64_set_lrr1 (unsigned long val)
 588 {
 589         ia64_setreg(_IA64_REG_CR_LRR1, val);
 590         ia64_srlz_d();
 591 }
 592
 593
 594 /*
 595  * Given the address to which a spill occurred, return the unat bit
 596  * number that corresponds to this address.
 597  */
 598 static inline __u64
 599 ia64_unat_pos (void *spill_addr)
 600 {
 601         return ((__u64) spill_addr >> 3) & 0x3f;
 602 }
 603
 604 /*
 605  * Set the NaT bit of an integer register which was spilled at address
 606  * SPILL_ADDR.  UNAT is the mask to be updated.
 607  */
 608 static inline void
 609 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 610 {
 611         __u64 bit = ia64_unat_pos(spill_addr);
 612         __u64 mask = 1UL << bit;
 613
 614         *unat = (*unat & ~mask) | (nat << bit);
 615 }
 616
 617 /*
 618  * Return saved PC of a blocked thread.
 619  * Note that the only way T can block is through a call to schedule() -> switch_to().
 620  */
 621 static inline unsigned long
 622 thread_saved_pc (struct task_struct *t)
 623 {
 624         struct unw_frame_info info;
 625         unsigned long ip;
 626
 627         unw_init_from_blocked_task(&info, t);
 628         if (unw_unwind(&info) < 0)
 629                 return 0;
 630         unw_get_ip(&info, &ip);
 631         return ip;
 632 }
 633
 634 /*
 635  * Get the current instruction/program counter value.
 636  */
 637 #define current_text_addr() \
 638         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
 639
 640 static inline __u64
 641 ia64_get_ivr (void)
 642 {
 643         __u64 r;
 644         ia64_srlz_d();
 645         r = ia64_getreg(_IA64_REG_CR_IVR);
 646         ia64_srlz_d();
 647         return r;
 648 }
 649
 650 static inline void
 651 ia64_set_dbr (__u64 regnum, __u64 value)
 652 {
 653         __ia64_set_dbr(regnum, value);
 654 #ifdef CONFIG_ITANIUM
 655         ia64_srlz_d();
 656 #endif
 657 }
 658
 659 static inline __u64
 660 ia64_get_dbr (__u64 regnum)
 661 {
 662         __u64 retval;
 663
 664         retval = __ia64_get_dbr(regnum);
 665 #ifdef CONFIG_ITANIUM
 666         ia64_srlz_d();
 667 #endif
 668         return retval;
 669 }
 670
 671 static inline __u64
 672 ia64_rotr (__u64 w, __u64 n)
 673 {
 674         return (w >> n) | (w << (64 - n));
 675 }
 676
 677 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
 678
 679 /*
 680  * Take a mapped kernel address and return the equivalent address
 681  * in the region 7 identity mapped virtual area.
 682  */
 683 static inline void *
 684 ia64_imva (void *addr)
 685 {
 686         void *result;
 687         result = (void *) ia64_tpa(addr);
 688         return __va(result);
 689 }
 690
 691 #define ARCH_HAS_PREFETCH
 692 #define ARCH_HAS_PREFETCHW
 693 #define ARCH_HAS_SPINLOCK_PREFETCH
 694 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
 695
 696 static inline void
 697 prefetch (const void *x)
 698 {
 699          ia64_lfetch(ia64_lfhint_none, x);
 700 }
 701
 702 static inline void
 703 prefetchw (const void *x)
 704 {
 705         ia64_lfetch_excl(ia64_lfhint_none, x);
 706 }
 707
 708 #define spin_lock_prefetch(x)   prefetchw(x)
 709
 710 extern unsigned long boot_option_idle_override;
 711
 712 #endif /* !__ASSEMBLY__ */
 713
 714 #endif /* _ASM_IA64_PROCESSOR_H */