include/asm-ia64/processor.h

   1 #ifndef _ASM_IA64_PROCESSOR_H
   2 #define _ASM_IA64_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 1998-2004 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *      Stephane Eranian <eranian@hpl.hp.com>
   8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10  *
  11  * 11/24/98     S.Eranian       added ia64_set_iva()
  12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14  */
  15
  16
  17 #include <asm/intrinsics.h>
  18 #include <asm/kregs.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/ustack.h>
  21
  22 #define IA64_NUM_PHYS_STACK_REG 96
  23 #define IA64_NUM_DBG_REGS       8
  24
  25 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
  26 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
  27
  28 /*
  29  * TASK_SIZE really is a mis-named.  It really is the maximum user
  30  * space address (plus one).  On IA-64, there are five regions of 2TB
  31  * each (assuming 8KB page size), for a total of 8TB of user virtual
  32  * address space.
  33  */
  34 #define TASK_SIZE               (current->thread.task_size)
  35
  36 /*
  37  * This decides where the kernel will search for a free chunk of vm
  38  * space during mmap's.
  39  */
  40 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
  41
  42 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
  43 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
  44 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
  45 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
  46 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
  47 #define IA64_THREAD_MIGRATION   (__IA64_UL(1) << 5)     /* require migration
  48                                                            sync at ctx sw */
  49 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
  50 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
  51
  52 #define IA64_THREAD_UAC_SHIFT   3
  53 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
  54 #define IA64_THREAD_FPEMU_SHIFT 6
  55 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
  56
  57
  58 /*
  59  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
  60  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
  61  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
  62  */
  63 #define IA64_NSEC_PER_CYC_SHIFT 30
  64
  65 #ifndef __ASSEMBLY__
  66
  67 #include <linux/cache.h>
  68 #include <linux/compiler.h>
  69 #include <linux/threads.h>
  70 #include <linux/types.h>
  71
  72 #include <asm/fpu.h>
  73 #include <asm/page.h>
  74 #include <asm/percpu.h>
  75 #include <asm/rse.h>
  76 #include <asm/unwind.h>
  77 #include <asm/atomic.h>
  78 #ifdef CONFIG_NUMA
  79 #include <asm/nodedata.h>
  80 #endif
  81
  82 /* like above but expressed as bitfields for more efficient access: */
  83 struct ia64_psr {
  84         __u64 reserved0 : 1;
  85         __u64 be : 1;
  86         __u64 up : 1;
  87         __u64 ac : 1;
  88         __u64 mfl : 1;
  89         __u64 mfh : 1;
  90         __u64 reserved1 : 7;
  91         __u64 ic : 1;
  92         __u64 i : 1;
  93         __u64 pk : 1;
  94         __u64 reserved2 : 1;
  95         __u64 dt : 1;
  96         __u64 dfl : 1;
  97         __u64 dfh : 1;
  98         __u64 sp : 1;
  99         __u64 pp : 1;
 100         __u64 di : 1;
 101         __u64 si : 1;
 102         __u64 db : 1;
 103         __u64 lp : 1;
 104         __u64 tb : 1;
 105         __u64 rt : 1;
 106         __u64 reserved3 : 4;
 107         __u64 cpl : 2;
 108         __u64 is : 1;
 109         __u64 mc : 1;
 110         __u64 it : 1;
 111         __u64 id : 1;
 112         __u64 da : 1;
 113         __u64 dd : 1;
 114         __u64 ss : 1;
 115         __u64 ri : 2;
 116         __u64 ed : 1;
 117         __u64 bn : 1;
 118         __u64 reserved4 : 19;
 119 };
 120
 121 /*
 122  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 123  * state comes earlier:
 124  */
 125 struct cpuinfo_ia64 {
 126         __u32 softirq_pending;
 127         __u64 itm_delta;        /* # of clock cycles between clock ticks */
 128         __u64 itm_next;         /* interval timer mask value to use for next clock tick */
 129         __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
 130         __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 131         __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 132         __u64 itc_freq;         /* frequency of ITC counter */
 133         __u64 proc_freq;        /* frequency of processor */
 134         __u64 cyc_per_usec;     /* itc_freq/1000000 */
 135         __u64 ptce_base;
 136         __u32 ptce_count[2];
 137         __u32 ptce_stride[2];
 138         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 139
 140 #ifdef CONFIG_SMP
 141         __u64 loops_per_jiffy;
 142         int cpu;
 143         __u32 socket_id;        /* physical processor socket id */
 144         __u16 core_id;          /* core id */
 145         __u16 thread_id;        /* thread id */
 146         __u16 num_log;          /* Total number of logical processors on
 147                                  * this socket that were successfully booted */
 148         __u8  cores_per_socket; /* Cores per processor socket */
 149         __u8  threads_per_core; /* Threads per core */
 150 #endif
 151
 152         /* CPUID-derived information: */
 153         __u64 ppn;
 154         __u64 features;
 155         __u8 number;
 156         __u8 revision;
 157         __u8 model;
 158         __u8 family;
 159         __u8 archrev;
 160         char vendor[16];
 161         char *model_name;
 162
 163 #ifdef CONFIG_NUMA
 164         struct ia64_node_data *node_data;
 165 #endif
 166 };
 167
 168 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
 169
 170 /*
 171  * The "local" data variable.  It refers to the per-CPU data of the currently executing
 172  * CPU, much like "current" points to the per-task data of the currently executing task.
 173  * Do not use the address of local_cpu_data, since it will be different from
 174  * cpu_data(smp_processor_id())!
 175  */
 176 #define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
 177 #define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
 178
 179 extern void print_cpu_info (struct cpuinfo_ia64 *);
 180
 181 typedef struct {
 182         unsigned long seg;
 183 } mm_segment_t;
 184
 185 #define SET_UNALIGN_CTL(task,value)                                                             \
 186 ({                                                                                              \
 187         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 188                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 189         0;                                                                                      \
 190 })
 191 #define GET_UNALIGN_CTL(task,addr)                                                              \
 192 ({                                                                                              \
 193         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 194                  (int __user *) (addr));                                                        \
 195 })
 196
 197 #define SET_FPEMU_CTL(task,value)                                                               \
 198 ({                                                                                              \
 199         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 200                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 201         0;                                                                                      \
 202 })
 203 #define GET_FPEMU_CTL(task,addr)                                                                \
 204 ({                                                                                              \
 205         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 206                  (int __user *) (addr));                                                        \
 207 })
 208
 209 #ifdef CONFIG_IA32_SUPPORT
 210 struct desc_struct {
 211         unsigned int a, b;
 212 };
 213
 214 #define desc_empty(desc)                (!((desc)->a + (desc)->b))
 215 #define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
 216
 217 #define GDT_ENTRY_TLS_ENTRIES   3
 218 #define GDT_ENTRY_TLS_MIN       6
 219 #define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
 220
 221 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
 222
 223 struct partial_page_list;
 224 #endif
 225
 226 struct thread_struct {
 227         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
 228         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
 229         __u8 on_ustack;                 /* executing on user-stacks? */
 230         __u8 pad[3];
 231         __u64 ksp;                      /* kernel stack pointer */
 232         __u64 map_base;                 /* base address for get_unmapped_area() */
 233         __u64 task_size;                /* limit for task size */
 234         __u64 rbs_bot;                  /* the base address for the RBS */
 235         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 236
 237 #ifdef CONFIG_IA32_SUPPORT
 238         __u64 eflag;                    /* IA32 EFLAGS reg */
 239         __u64 fsr;                      /* IA32 floating pt status reg */
 240         __u64 fcr;                      /* IA32 floating pt control reg */
 241         __u64 fir;                      /* IA32 fp except. instr. reg */
 242         __u64 fdr;                      /* IA32 fp except. data reg */
 243         __u64 old_k1;                   /* old value of ar.k1 */
 244         __u64 old_iob;                  /* old IOBase value */
 245         struct partial_page_list *ppl;  /* partial page list for 4K page size issue */
 246         /* cached TLS descriptors. */
 247         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 248
 249 # define INIT_THREAD_IA32       .eflag =        0,                      \
 250                                 .fsr =          0,                      \
 251                                 .fcr =          0x17800000037fULL,      \
 252                                 .fir =          0,                      \
 253                                 .fdr =          0,                      \
 254                                 .old_k1 =       0,                      \
 255                                 .old_iob =      0,                      \
 256                                 .ppl =          NULL,
 257 #else
 258 # define INIT_THREAD_IA32
 259 #endif /* CONFIG_IA32_SUPPORT */
 260 #ifdef CONFIG_PERFMON
 261         void *pfm_context;                   /* pointer to detailed PMU context */
 262         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
 263 # define INIT_THREAD_PM         .pfm_context =          NULL,     \
 264                                 .pfm_needs_checking =   0UL,
 265 #else
 266 # define INIT_THREAD_PM
 267 #endif
 268         __u64 dbr[IA64_NUM_DBG_REGS];
 269         __u64 ibr[IA64_NUM_DBG_REGS];
 270         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 271 };
 272
 273 #define INIT_THREAD {                                           \
 274         .flags =        0,                                      \
 275         .on_ustack =    0,                                      \
 276         .ksp =          0,                                      \
 277         .map_base =     DEFAULT_MAP_BASE,                       \
 278         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
 279         .task_size =    DEFAULT_TASK_SIZE,                      \
 280         .last_fph_cpu =  -1,                                    \
 281         INIT_THREAD_IA32                                        \
 282         INIT_THREAD_PM                                          \
 283         .dbr =          {0, },                                  \
 284         .ibr =          {0, },                                  \
 285         .fph =          {{{{0}}}, }                             \
 286 }
 287
 288 #define start_thread(regs,new_ip,new_sp) do {                                                   \
 289         set_fs(USER_DS);                                                                        \
 290         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
 291                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
 292         regs->cr_iip = new_ip;                                                                  \
 293         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 294         regs->ar_rnat = 0;                                                                      \
 295         regs->ar_bspstore = current->thread.rbs_bot;                                            \
 296         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 297         regs->loadrs = 0;                                                                       \
 298         regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
 299         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 300         if (unlikely(!current->mm->dumpable)) {                                                 \
 301                 /*                                                                              \
 302                  * Zap scratch regs to avoid leaking bits between processes with different      \
 303                  * uid/privileges.                                                              \
 304                  */                                                                             \
 305                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
 306                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
 307         }                                                                                       \
 308 } while (0)
 309
 310 /* Forward declarations, a strange C thing... */
 311 struct mm_struct;
 312 struct task_struct;
 313
 314 /*
 315  * Free all resources held by a thread. This is called after the
 316  * parent of DEAD_TASK has collected the exit status of the task via
 317  * wait().
 318  */
 319 #define release_thread(dead_task)
 320
 321 /* Prepare to copy thread state - unlazy all lazy status */
 322 #define prepare_to_copy(tsk)    do { } while (0)
 323
 324 /*
 325  * This is the mechanism for creating a new kernel thread.
 326  *
 327  * NOTE 1: Only a kernel-only process (ie the swapper or direct
 328  * descendants who haven't done an "execve()") should use this: it
 329  * will work within a system call from a "real" process, but the
 330  * process memory space will not be free'd until both the parent and
 331  * the child have exited.
 332  *
 333  * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
 334  * into trouble in init/main.c when the child thread returns to
 335  * do_basic_setup() and the timing is such that free_initmem() has
 336  * been called already.
 337  */
 338 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
 339
 340 /* Get wait channel for task P.  */
 341 extern unsigned long get_wchan (struct task_struct *p);
 342
 343 /* Return instruction pointer of blocked task TSK.  */
 344 #define KSTK_EIP(tsk)                                   \
 345   ({                                                    \
 346         struct pt_regs *_regs = task_pt_regs(tsk);      \
 347         _regs->cr_iip + ia64_psr(_regs)->ri;            \
 348   })
 349
 350 /* Return stack pointer of blocked task TSK.  */
 351 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 352
 353 extern void ia64_getreg_unknown_kr (void);
 354 extern void ia64_setreg_unknown_kr (void);
 355
 356 #define ia64_get_kr(regnum)                                     \
 357 ({                                                              \
 358         unsigned long r = 0;                                    \
 359                                                                 \
 360         switch (regnum) {                                       \
 361             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
 362             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
 363             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
 364             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
 365             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
 366             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
 367             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
 368             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
 369             default: ia64_getreg_unknown_kr(); break;           \
 370         }                                                       \
 371         r;                                                      \
 372 })
 373
 374 #define ia64_set_kr(regnum, r)                                  \
 375 ({                                                              \
 376         switch (regnum) {                                       \
 377             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
 378             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
 379             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
 380             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
 381             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
 382             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
 383             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
 384             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
 385             default: ia64_setreg_unknown_kr(); break;           \
 386         }                                                       \
 387 })
 388
 389 /*
 390  * The following three macros can't be inline functions because we don't have struct
 391  * task_struct at this point.
 392  */
 393
 394 /*
 395  * Return TRUE if task T owns the fph partition of the CPU we're running on.
 396  * Must be called from code that has preemption disabled.
 397  */
 398 #define ia64_is_local_fpu_owner(t)                                                              \
 399 ({                                                                                              \
 400         struct task_struct *__ia64_islfo_task = (t);                                            \
 401         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
 402          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 403 })
 404
 405 /*
 406  * Mark task T as owning the fph partition of the CPU we're running on.
 407  * Must be called from code that has preemption disabled.
 408  */
 409 #define ia64_set_local_fpu_owner(t) do {                                                \
 410         struct task_struct *__ia64_slfo_task = (t);                                     \
 411         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
 412         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
 413 } while (0)
 414
 415 /* Mark the fph partition of task T as being invalid on all CPUs.  */
 416 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
 417
 418 extern void __ia64_init_fpu (void);
 419 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 420 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 421 extern void ia64_save_debug_regs (unsigned long *save_area);
 422 extern void ia64_load_debug_regs (unsigned long *save_area);
 423
 424 #ifdef CONFIG_IA32_SUPPORT
 425 extern void ia32_save_state (struct task_struct *task);
 426 extern void ia32_load_state (struct task_struct *task);
 427 #endif
 428
 429 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 430 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 431
 432 /* load fp 0.0 into fph */
 433 static inline void
 434 ia64_init_fpu (void) {
 435         ia64_fph_enable();
 436         __ia64_init_fpu();
 437         ia64_fph_disable();
 438 }
 439
 440 /* save f32-f127 at FPH */
 441 static inline void
 442 ia64_save_fpu (struct ia64_fpreg *fph) {
 443         ia64_fph_enable();
 444         __ia64_save_fpu(fph);
 445         ia64_fph_disable();
 446 }
 447
 448 /* load f32-f127 from FPH */
 449 static inline void
 450 ia64_load_fpu (struct ia64_fpreg *fph) {
 451         ia64_fph_enable();
 452         __ia64_load_fpu(fph);
 453         ia64_fph_disable();
 454 }
 455
 456 static inline __u64
 457 ia64_clear_ic (void)
 458 {
 459         __u64 psr;
 460         psr = ia64_getreg(_IA64_REG_PSR);
 461         ia64_stop();
 462         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
 463         ia64_srlz_i();
 464         return psr;
 465 }
 466
 467 /*
 468  * Restore the psr.
 469  */
 470 static inline void
 471 ia64_set_psr (__u64 psr)
 472 {
 473         ia64_stop();
 474         ia64_setreg(_IA64_REG_PSR_L, psr);
 475         ia64_srlz_d();
 476 }
 477
 478 /*
 479  * Insert a translation into an instruction and/or data translation
 480  * register.
 481  */
 482 static inline void
 483 ia64_itr (__u64 target_mask, __u64 tr_num,
 484           __u64 vmaddr, __u64 pte,
 485           __u64 log_page_size)
 486 {
 487         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 488         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 489         ia64_stop();
 490         if (target_mask & 0x1)
 491                 ia64_itri(tr_num, pte);
 492         if (target_mask & 0x2)
 493                 ia64_itrd(tr_num, pte);
 494 }
 495
 496 /*
 497  * Insert a translation into the instruction and/or data translation
 498  * cache.
 499  */
 500 static inline void
 501 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 502           __u64 log_page_size)
 503 {
 504         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 505         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 506         ia64_stop();
 507         /* as per EAS2.6, itc must be the last instruction in an instruction group */
 508         if (target_mask & 0x1)
 509                 ia64_itci(pte);
 510         if (target_mask & 0x2)
 511                 ia64_itcd(pte);
 512 }
 513
 514 /*
 515  * Purge a range of addresses from instruction and/or data translation
 516  * register(s).
 517  */
 518 static inline void
 519 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 520 {
 521         if (target_mask & 0x1)
 522                 ia64_ptri(vmaddr, (log_size << 2));
 523         if (target_mask & 0x2)
 524                 ia64_ptrd(vmaddr, (log_size << 2));
 525 }
 526
 527 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 528 static inline void
 529 ia64_set_iva (void *ivt_addr)
 530 {
 531         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
 532         ia64_srlz_i();
 533 }
 534
 535 /* Set the page table address and control bits.  */
 536 static inline void
 537 ia64_set_pta (__u64 pta)
 538 {
 539         /* Note: srlz.i implies srlz.d */
 540         ia64_setreg(_IA64_REG_CR_PTA, pta);
 541         ia64_srlz_i();
 542 }
 543
 544 static inline void
 545 ia64_eoi (void)
 546 {
 547         ia64_setreg(_IA64_REG_CR_EOI, 0);
 548         ia64_srlz_d();
 549 }
 550
 551 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 552
 553 static inline int
 554 ia64_get_irr(unsigned int vector)
 555 {
 556         unsigned int reg = vector / 64;
 557         unsigned int bit = vector % 64;
 558         u64 irr;
 559
 560         switch (reg) {
 561         case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
 562         case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
 563         case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
 564         case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
 565         }
 566
 567         return test_bit(bit, &irr);
 568 }
 569
 570 static inline void
 571 ia64_set_lrr0 (unsigned long val)
 572 {
 573         ia64_setreg(_IA64_REG_CR_LRR0, val);
 574         ia64_srlz_d();
 575 }
 576
 577 static inline void
 578 ia64_set_lrr1 (unsigned long val)
 579 {
 580         ia64_setreg(_IA64_REG_CR_LRR1, val);
 581         ia64_srlz_d();
 582 }
 583
 584
 585 /*
 586  * Given the address to which a spill occurred, return the unat bit
 587  * number that corresponds to this address.
 588  */
 589 static inline __u64
 590 ia64_unat_pos (void *spill_addr)
 591 {
 592         return ((__u64) spill_addr >> 3) & 0x3f;
 593 }
 594
 595 /*
 596  * Set the NaT bit of an integer register which was spilled at address
 597  * SPILL_ADDR.  UNAT is the mask to be updated.
 598  */
 599 static inline void
 600 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 601 {
 602         __u64 bit = ia64_unat_pos(spill_addr);
 603         __u64 mask = 1UL << bit;
 604
 605         *unat = (*unat & ~mask) | (nat << bit);
 606 }
 607
 608 /*
 609  * Return saved PC of a blocked thread.
 610  * Note that the only way T can block is through a call to schedule() -> switch_to().
 611  */
 612 static inline unsigned long
 613 thread_saved_pc (struct task_struct *t)
 614 {
 615         struct unw_frame_info info;
 616         unsigned long ip;
 617
 618         unw_init_from_blocked_task(&info, t);
 619         if (unw_unwind(&info) < 0)
 620                 return 0;
 621         unw_get_ip(&info, &ip);
 622         return ip;
 623 }
 624
 625 /*
 626  * Get the current instruction/program counter value.
 627  */
 628 #define current_text_addr() \
 629         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
 630
 631 static inline __u64
 632 ia64_get_ivr (void)
 633 {
 634         __u64 r;
 635         ia64_srlz_d();
 636         r = ia64_getreg(_IA64_REG_CR_IVR);
 637         ia64_srlz_d();
 638         return r;
 639 }
 640
 641 static inline void
 642 ia64_set_dbr (__u64 regnum, __u64 value)
 643 {
 644         __ia64_set_dbr(regnum, value);
 645 #ifdef CONFIG_ITANIUM
 646         ia64_srlz_d();
 647 #endif
 648 }
 649
 650 static inline __u64
 651 ia64_get_dbr (__u64 regnum)
 652 {
 653         __u64 retval;
 654
 655         retval = __ia64_get_dbr(regnum);
 656 #ifdef CONFIG_ITANIUM
 657         ia64_srlz_d();
 658 #endif
 659         return retval;
 660 }
 661
 662 static inline __u64
 663 ia64_rotr (__u64 w, __u64 n)
 664 {
 665         return (w >> n) | (w << (64 - n));
 666 }
 667
 668 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
 669
 670 /*
 671  * Take a mapped kernel address and return the equivalent address
 672  * in the region 7 identity mapped virtual area.
 673  */
 674 static inline void *
 675 ia64_imva (void *addr)
 676 {
 677         void *result;
 678         result = (void *) ia64_tpa(addr);
 679         return __va(result);
 680 }
 681
 682 #define ARCH_HAS_PREFETCH
 683 #define ARCH_HAS_PREFETCHW
 684 #define ARCH_HAS_SPINLOCK_PREFETCH
 685 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
 686
 687 static inline void
 688 prefetch (const void *x)
 689 {
 690          ia64_lfetch(ia64_lfhint_none, x);
 691 }
 692
 693 static inline void
 694 prefetchw (const void *x)
 695 {
 696         ia64_lfetch_excl(ia64_lfhint_none, x);
 697 }
 698
 699 #define spin_lock_prefetch(x)   prefetchw(x)
 700
 701 extern unsigned long boot_option_idle_override;
 702
 703 #endif /* !__ASSEMBLY__ */
 704
 705 #endif /* _ASM_IA64_PROCESSOR_H */