include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h

   1 #ifndef __irq_nmi_defs_asm_h
   2 #define __irq_nmi_defs_asm_h
   3
   4 /*
   5  * This file is autogenerated from
   6  *   file:           ../../mod/irq_nmi.r
   7  *     id:           <not found>
   8  *     last modfied: Thu Jan 22 09:22:43 2004
   9  *
  10  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
  11  *      id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
  12  * Any changes here will be lost.
  13  *
  14  * -*- buffer-read-only: t -*-
  15  */
  16
  17 #ifndef REG_FIELD
  18 #define REG_FIELD( scope, reg, field, value ) \
  19   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  20 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  21 #endif
  22
  23 #ifndef REG_STATE
  24 #define REG_STATE( scope, reg, field, symbolic_value ) \
  25   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  26 #define REG_STATE_X_( k, shift ) (k << shift)
  27 #endif
  28
  29 #ifndef REG_MASK
  30 #define REG_MASK( scope, reg, field ) \
  31   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  33 #endif
  34
  35 #ifndef REG_LSB
  36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  37 #endif
  38
  39 #ifndef REG_BIT
  40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  41 #endif
  42
  43 #ifndef REG_ADDR
  44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  46 #endif
  47
  48 #ifndef REG_ADDR_VECT
  49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  50          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  51                          STRIDE_##scope##_##reg )
  52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  53                           ((inst) + offs + (index) * stride)
  54 #endif
  55
  56 /* Register rw_cmd, scope irq_nmi, type rw */
  57 #define reg_irq_nmi_rw_cmd___delay___lsb 0
  58 #define reg_irq_nmi_rw_cmd___delay___width 16
  59 #define reg_irq_nmi_rw_cmd___op___lsb 16
  60 #define reg_irq_nmi_rw_cmd___op___width 2
  61 #define reg_irq_nmi_rw_cmd_offset 0
  62
  63
  64 /* Constants */
  65 #define regk_irq_nmi_ack_irq                      0x00000002
  66 #define regk_irq_nmi_ack_nmi                      0x00000003
  67 #define regk_irq_nmi_irq                          0x00000000
  68 #define regk_irq_nmi_nmi                          0x00000001
  69 #endif /* __irq_nmi_defs_asm_h */