mm: thp: set the accessed flag for old pages on access fault
[pandora-kernel.git] / drivers / watchdog / ibmasr.c
1 /*
2  * IBM Automatic Server Restart driver.
3  *
4  * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
5  *
6  * Based on driver written by Pete Reynolds.
7  * Copyright (c) IBM Corporation, 1998-2004.
8  *
9  * This software may be used and distributed according to the terms
10  * of the GNU Public License, incorporated herein by reference.
11  */
12
13 #include <linux/fs.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/timer.h>
18 #include <linux/miscdevice.h>
19 #include <linux/watchdog.h>
20 #include <linux/dmi.h>
21 #include <linux/io.h>
22 #include <linux/uaccess.h>
23
24
25 enum {
26         ASMTYPE_UNKNOWN,
27         ASMTYPE_TOPAZ,
28         ASMTYPE_JASPER,
29         ASMTYPE_PEARL,
30         ASMTYPE_JUNIPER,
31         ASMTYPE_SPRUCE,
32 };
33
34 #define PFX "ibmasr: "
35
36 #define TOPAZ_ASR_REG_OFFSET    4
37 #define TOPAZ_ASR_TOGGLE        0x40
38 #define TOPAZ_ASR_DISABLE       0x80
39
40 /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
41 #define PEARL_BASE      0xe04
42 #define PEARL_WRITE     0xe06
43 #define PEARL_READ      0xe07
44
45 #define PEARL_ASR_DISABLE_MASK  0x80    /* bit 7: disable = 1, enable = 0 */
46 #define PEARL_ASR_TOGGLE_MASK   0x40    /* bit 6: 0, then 1, then 0 */
47
48 /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
49 #define JASPER_ASR_REG_OFFSET   0x38
50
51 #define JASPER_ASR_DISABLE_MASK 0x01    /* bit 0: disable = 1, enable = 0 */
52 #define JASPER_ASR_TOGGLE_MASK  0x02    /* bit 1: 0, then 1, then 0 */
53
54 #define JUNIPER_BASE_ADDRESS    0x54b   /* Base address of Juniper ASR */
55 #define JUNIPER_ASR_DISABLE_MASK 0x01   /* bit 0: disable = 1 enable = 0 */
56 #define JUNIPER_ASR_TOGGLE_MASK 0x02    /* bit 1: 0, then 1, then 0 */
57
58 #define SPRUCE_BASE_ADDRESS     0x118e  /* Base address of Spruce ASR */
59 #define SPRUCE_ASR_DISABLE_MASK 0x01    /* bit 1: disable = 1 enable = 0 */
60 #define SPRUCE_ASR_TOGGLE_MASK  0x02    /* bit 0: 0, then 1, then 0 */
61
62
63 static int nowayout = WATCHDOG_NOWAYOUT;
64
65 static unsigned long asr_is_open;
66 static char asr_expect_close;
67
68 static unsigned int asr_type, asr_base, asr_length;
69 static unsigned int asr_read_addr, asr_write_addr;
70 static unsigned char asr_toggle_mask, asr_disable_mask;
71 static spinlock_t asr_lock;
72
73 static void __asr_toggle(void)
74 {
75         unsigned char reg;
76
77         reg = inb(asr_read_addr);
78
79         outb(reg & ~asr_toggle_mask, asr_write_addr);
80         reg = inb(asr_read_addr);
81
82         outb(reg | asr_toggle_mask, asr_write_addr);
83         reg = inb(asr_read_addr);
84
85         outb(reg & ~asr_toggle_mask, asr_write_addr);
86         reg = inb(asr_read_addr);
87 }
88
89 static void asr_toggle(void)
90 {
91         spin_lock(&asr_lock);
92         __asr_toggle();
93         spin_unlock(&asr_lock);
94 }
95
96 static void asr_enable(void)
97 {
98         unsigned char reg;
99
100         spin_lock(&asr_lock);
101         if (asr_type == ASMTYPE_TOPAZ) {
102                 /* asr_write_addr == asr_read_addr */
103                 reg = inb(asr_read_addr);
104                 outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
105                      asr_read_addr);
106         } else {
107                 /*
108                  * First make sure the hardware timer is reset by toggling
109                  * ASR hardware timer line.
110                  */
111                 __asr_toggle();
112
113                 reg = inb(asr_read_addr);
114                 outb(reg & ~asr_disable_mask, asr_write_addr);
115         }
116         reg = inb(asr_read_addr);
117         spin_unlock(&asr_lock);
118 }
119
120 static void asr_disable(void)
121 {
122         unsigned char reg;
123
124         spin_lock(&asr_lock);
125         reg = inb(asr_read_addr);
126
127         if (asr_type == ASMTYPE_TOPAZ)
128                 /* asr_write_addr == asr_read_addr */
129                 outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
130                      asr_read_addr);
131         else {
132                 outb(reg | asr_toggle_mask, asr_write_addr);
133                 reg = inb(asr_read_addr);
134
135                 outb(reg | asr_disable_mask, asr_write_addr);
136         }
137         reg = inb(asr_read_addr);
138         spin_unlock(&asr_lock);
139 }
140
141 static int __init asr_get_base_address(void)
142 {
143         unsigned char low, high;
144         const char *type = "";
145
146         asr_length = 1;
147
148         switch (asr_type) {
149         case ASMTYPE_TOPAZ:
150                 /* SELECT SuperIO CHIP FOR QUERYING
151                    (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
152                 outb(0x07, 0x2e);
153                 outb(0x07, 0x2f);
154
155                 /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
156                 outb(0x60, 0x2e);
157                 high = inb(0x2f);
158
159                 /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
160                 outb(0x61, 0x2e);
161                 low = inb(0x2f);
162
163                 asr_base = (high << 16) | low;
164                 asr_read_addr = asr_write_addr =
165                         asr_base + TOPAZ_ASR_REG_OFFSET;
166                 asr_length = 5;
167
168                 break;
169
170         case ASMTYPE_JASPER:
171                 type = "Jaspers ";
172 #if 0
173                 u32 r;
174                 /* Suggested fix */
175                 pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
176                 if (pdev == NULL)
177                         return -ENODEV;
178                 pci_read_config_dword(pdev, 0x58, &r);
179                 asr_base = r & 0xFFFE;
180                 pci_dev_put(pdev);
181 #else
182                 /* FIXME: need to use pci_config_lock here,
183                    but it's not exported */
184
185 /*              spin_lock_irqsave(&pci_config_lock, flags);*/
186
187                 /* Select the SuperIO chip in the PCI I/O port register */
188                 outl(0x8000f858, 0xcf8);
189
190                 /* BUS 0, Slot 1F, fnc 0, offset 58 */
191
192                 /*
193                  * Read the base address for the SuperIO chip.
194                  * Only the lower 16 bits are valid, but the address is word
195                  * aligned so the last bit must be masked off.
196                  */
197                 asr_base = inl(0xcfc) & 0xfffe;
198
199 /*              spin_unlock_irqrestore(&pci_config_lock, flags);*/
200 #endif
201                 asr_read_addr = asr_write_addr =
202                         asr_base + JASPER_ASR_REG_OFFSET;
203                 asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
204                 asr_disable_mask = JASPER_ASR_DISABLE_MASK;
205                 asr_length = JASPER_ASR_REG_OFFSET + 1;
206
207                 break;
208
209         case ASMTYPE_PEARL:
210                 type = "Pearls ";
211                 asr_base = PEARL_BASE;
212                 asr_read_addr = PEARL_READ;
213                 asr_write_addr = PEARL_WRITE;
214                 asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
215                 asr_disable_mask = PEARL_ASR_DISABLE_MASK;
216                 asr_length = 4;
217                 break;
218
219         case ASMTYPE_JUNIPER:
220                 type = "Junipers ";
221                 asr_base = JUNIPER_BASE_ADDRESS;
222                 asr_read_addr = asr_write_addr = asr_base;
223                 asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
224                 asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
225                 break;
226
227         case ASMTYPE_SPRUCE:
228                 type = "Spruce's ";
229                 asr_base = SPRUCE_BASE_ADDRESS;
230                 asr_read_addr = asr_write_addr = asr_base;
231                 asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
232                 asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
233                 break;
234         }
235
236         if (!request_region(asr_base, asr_length, "ibmasr")) {
237                 printk(KERN_ERR PFX "address %#x already in use\n",
238                         asr_base);
239                 return -EBUSY;
240         }
241
242         printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base);
243
244         return 0;
245 }
246
247
248 static ssize_t asr_write(struct file *file, const char __user *buf,
249                          size_t count, loff_t *ppos)
250 {
251         if (count) {
252                 if (!nowayout) {
253                         size_t i;
254
255                         /* In case it was set long ago */
256                         asr_expect_close = 0;
257
258                         for (i = 0; i != count; i++) {
259                                 char c;
260                                 if (get_user(c, buf + i))
261                                         return -EFAULT;
262                                 if (c == 'V')
263                                         asr_expect_close = 42;
264                         }
265                 }
266                 asr_toggle();
267         }
268         return count;
269 }
270
271 static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
272 {
273         static const struct watchdog_info ident = {
274                 .options =      WDIOF_KEEPALIVEPING |
275                                 WDIOF_MAGICCLOSE,
276                 .identity =     "IBM ASR",
277         };
278         void __user *argp = (void __user *)arg;
279         int __user *p = argp;
280         int heartbeat;
281
282         switch (cmd) {
283         case WDIOC_GETSUPPORT:
284                 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
285         case WDIOC_GETSTATUS:
286         case WDIOC_GETBOOTSTATUS:
287                 return put_user(0, p);
288         case WDIOC_SETOPTIONS:
289         {
290                 int new_options, retval = -EINVAL;
291                 if (get_user(new_options, p))
292                         return -EFAULT;
293                 if (new_options & WDIOS_DISABLECARD) {
294                         asr_disable();
295                         retval = 0;
296                 }
297                 if (new_options & WDIOS_ENABLECARD) {
298                         asr_enable();
299                         asr_toggle();
300                         retval = 0;
301                 }
302                 return retval;
303         }
304         case WDIOC_KEEPALIVE:
305                 asr_toggle();
306                 return 0;
307         /*
308          * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
309          * and WDIOC_GETTIMEOUT always returns 256.
310          */
311         case WDIOC_GETTIMEOUT:
312                 heartbeat = 256;
313                 return put_user(heartbeat, p);
314         default:
315                 return -ENOTTY;
316         }
317 }
318
319 static int asr_open(struct inode *inode, struct file *file)
320 {
321         if (test_and_set_bit(0, &asr_is_open))
322                 return -EBUSY;
323
324         asr_toggle();
325         asr_enable();
326
327         return nonseekable_open(inode, file);
328 }
329
330 static int asr_release(struct inode *inode, struct file *file)
331 {
332         if (asr_expect_close == 42)
333                 asr_disable();
334         else {
335                 printk(KERN_CRIT PFX
336                                 "unexpected close, not stopping watchdog!\n");
337                 asr_toggle();
338         }
339         clear_bit(0, &asr_is_open);
340         asr_expect_close = 0;
341         return 0;
342 }
343
344 static const struct file_operations asr_fops = {
345         .owner =                THIS_MODULE,
346         .llseek =               no_llseek,
347         .write =                asr_write,
348         .unlocked_ioctl =       asr_ioctl,
349         .open =                 asr_open,
350         .release =              asr_release,
351 };
352
353 static struct miscdevice asr_miscdev = {
354         .minor =        WATCHDOG_MINOR,
355         .name =         "watchdog",
356         .fops =         &asr_fops,
357 };
358
359
360 struct ibmasr_id {
361         const char *desc;
362         int type;
363 };
364
365 static struct ibmasr_id __initdata ibmasr_id_table[] = {
366         { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
367         { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
368         { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
369         { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
370         { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
371         { NULL }
372 };
373
374 static int __init ibmasr_init(void)
375 {
376         struct ibmasr_id *id;
377         int rc;
378
379         for (id = ibmasr_id_table; id->desc; id++) {
380                 if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
381                         asr_type = id->type;
382                         break;
383                 }
384         }
385
386         if (!asr_type)
387                 return -ENODEV;
388
389         spin_lock_init(&asr_lock);
390
391         rc = asr_get_base_address();
392         if (rc)
393                 return rc;
394
395         rc = misc_register(&asr_miscdev);
396         if (rc < 0) {
397                 release_region(asr_base, asr_length);
398                 printk(KERN_ERR PFX "failed to register misc device\n");
399                 return rc;
400         }
401
402         return 0;
403 }
404
405 static void __exit ibmasr_exit(void)
406 {
407         if (!nowayout)
408                 asr_disable();
409
410         misc_deregister(&asr_miscdev);
411
412         release_region(asr_base, asr_length);
413 }
414
415 module_init(ibmasr_init);
416 module_exit(ibmasr_exit);
417
418 module_param(nowayout, int, 0);
419 MODULE_PARM_DESC(nowayout,
420         "Watchdog cannot be stopped once started (default="
421                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
422
423 MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
424 MODULE_AUTHOR("Andrey Panin");
425 MODULE_LICENSE("GPL");
426 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);