drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27
  28 #include <video/sh_mobile_hdmi.h>
  29 #include <video/sh_mobile_lcdc.h>
  30
  31 #include "sh_mobile_lcdcfb.h"
  32
  33 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  34 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  35                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  36 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  39                                                         bits 19..16 of Internal CTS */
  40 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  42 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  43 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  45 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  46 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  47 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  48 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  49 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  50 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  51 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  52 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  54 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  55 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  56 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  57 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  58 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  59
  60 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  61 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  62
  63 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  64 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  65 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  66 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  68 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  70 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  72 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  74 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  75 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  76 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  77 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  78 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  79 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  80 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  81 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  82 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  83 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  84 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  86 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  97 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 129 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 130 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 132 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 133 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 134 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 135 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 136 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 137 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 138 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 139 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 140 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 141 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 142 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 143 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 144 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 145 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 146 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 147 #define HDMI_SHA0                               0xB9 /* sha0 */
 148 #define HDMI_SHA1                               0xBA /* sha1 */
 149 #define HDMI_SHA2                               0xBB /* sha2 */
 150 #define HDMI_SHA3                               0xBC /* sha3 */
 151 #define HDMI_SHA4                               0xBD /* sha4 */
 152 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 153 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 154 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 155 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 156 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 157 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 158 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 159 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 160 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 161 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 162 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 163 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 164 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 165 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 166 #define HDMI_AN_SEED                            0xCC /* An seed */
 167 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 168 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 170 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 171 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 172 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 173 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 174 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 175 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 176 #define HDMI_PJ                                 0xD7 /* Pj */
 177 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 178 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 179 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 180 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 181 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 182 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 183 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 184 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 185 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 186 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 187 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 188 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 189 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 190 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 191 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 192 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 193 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 194 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 195 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 196 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 197 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 198 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 199 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 200 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 201 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 202
 203 enum hotplug_state {
 204         HDMI_HOTPLUG_DISCONNECTED,
 205         HDMI_HOTPLUG_CONNECTED,
 206         HDMI_HOTPLUG_EDID_DONE,
 207 };
 208
 209 struct sh_hdmi {
 210         void __iomem *base;
 211         enum hotplug_state hp_state;    /* hot-plug status */
 212         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 213                                            the external mode */
 214         struct clk *hdmi_clk;
 215         struct device *dev;
 216         struct fb_info *info;
 217         struct mutex mutex;             /* Protect the info pointer */
 218         struct delayed_work edid_work;
 219         struct fb_var_screeninfo var;
 220         struct fb_monspecs monspec;
 221 };
 222
 223 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 224 {
 225         iowrite8(data, hdmi->base + reg);
 226 }
 227
 228 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 229 {
 230         return ioread8(hdmi->base + reg);
 231 }
 232
 233 /*
 234  *      HDMI sound
 235  */
 236 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 237                                      unsigned int reg)
 238 {
 239         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 240
 241         return hdmi_read(hdmi, reg);
 242 }
 243
 244 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 245                              unsigned int reg,
 246                              unsigned int value)
 247 {
 248         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 249
 250         hdmi_write(hdmi, value, reg);
 251         return 0;
 252 }
 253
 254 static struct snd_soc_dai_driver sh_hdmi_dai = {
 255         .name = "sh_mobile_hdmi-hifi",
 256         .playback = {
 257                 .stream_name = "Playback",
 258                 .channels_min = 2,
 259                 .channels_max = 8,
 260                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 261                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 262                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 263                          SNDRV_PCM_RATE_192000,
 264                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 265         },
 266 };
 267
 268 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 269 {
 270         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 271
 272         return 0;
 273 }
 274
 275 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 276         .probe          = sh_hdmi_snd_probe,
 277         .read           = sh_hdmi_snd_read,
 278         .write          = sh_hdmi_snd_write,
 279 };
 280
 281 /*
 282  *      HDMI video
 283  */
 284
 285 /* External video parameter settings */
 286 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 287 {
 288         struct fb_var_screeninfo *var = &hdmi->var;
 289         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 290         u8 sync = 0;
 291
 292         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 293
 294         hdelay = var->hsync_len + var->left_margin;
 295         hblank = var->right_margin + hdelay;
 296
 297         /*
 298          * Vertical timing looks a bit different in Figure 18,
 299          * but let's try the same first by setting offset = 0
 300          */
 301         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 302
 303         vdelay = var->vsync_len + var->upper_margin;
 304         vblank = var->lower_margin + vdelay;
 305         voffset = min(var->upper_margin / 2, 6U);
 306
 307         /*
 308          * [3]: VSYNC polarity: Positive
 309          * [2]: HSYNC polarity: Positive
 310          * [1]: Interlace/Progressive: Progressive
 311          * [0]: External video settings enable: used.
 312          */
 313         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 314                 sync |= 4;
 315         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 316                 sync |= 8;
 317
 318         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 319                 htotal, hblank, hdelay, var->hsync_len,
 320                 vtotal, vblank, vdelay, var->vsync_len, sync);
 321
 322         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 323
 324         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 325         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 326
 327         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 328         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 329
 330         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 331         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 332
 333         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 334         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 335
 336         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 337         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 338
 339         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 340
 341         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 342
 343         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 344
 345         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 346         if (!hdmi->preprogrammed_vic)
 347                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 348                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 349 }
 350
 351 /**
 352  * sh_hdmi_video_config()
 353  */
 354 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 355 {
 356         /*
 357          * [7:4]: Audio sampling frequency: 48kHz
 358          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 359          * [0]: Internal/External DE select: internal
 360          */
 361         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 362
 363         /*
 364          * [7:6]: Video output format: RGB 4:4:4
 365          * [5:4]: Input video data width: 8 bit
 366          * [3:1]: EAV/SAV location: channel 1
 367          * [0]: Video input color space: RGB
 368          */
 369         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 370
 371         /*
 372          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 373          * left at 0 by default, this configures 24bpp and sets the Color Depth
 374          * (CD) field in the General Control Packet
 375          */
 376         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 377 }
 378
 379 /**
 380  * sh_hdmi_audio_config()
 381  */
 382 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 383 {
 384         u8 data;
 385         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 386
 387         /*
 388          * [7:4] L/R data swap control
 389          * [3:0] appropriate N[19:16]
 390          */
 391         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 392         /* appropriate N[15:8] */
 393         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 394         /* appropriate N[7:0] */
 395         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 396
 397         /* [7:4] 48 kHz SPDIF not used */
 398         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 399
 400         /*
 401          * [6:5] set required down sampling rate if required
 402          * [4:3] set required audio source
 403          */
 404         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 405         default:
 406                 /* fall through */
 407         case HDMI_SND_SRC_I2S:
 408                 data = 0x0 << 3;
 409                 break;
 410         case HDMI_SND_SRC_SPDIF:
 411                 data = 0x1 << 3;
 412                 break;
 413         case HDMI_SND_SRC_DSD:
 414                 data = 0x2 << 3;
 415                 break;
 416         case HDMI_SND_SRC_HBR:
 417                 data = 0x3 << 3;
 418                 break;
 419         }
 420         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 421
 422         /* [3:0] set sending channel number for channel status */
 423         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 424
 425         /*
 426          * [5:2] set valid I2S source input pin
 427          * [1:0] set input I2S source mode
 428          */
 429         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 430
 431         /* [7:4] set valid DSD source input pin */
 432         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 433
 434         /* [7:0] set appropriate I2S input pin swap settings if required */
 435         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 436
 437         /*
 438          * [7] set validity bit for channel status
 439          * [3:0] set original sample frequency for channel status
 440          */
 441         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 442
 443         /*
 444          * [7] set value for channel status
 445          * [6] set value for channel status
 446          * [5] set copyright bit for channel status
 447          * [4:2] set additional information for channel status
 448          * [1:0] set clock accuracy for channel status
 449          */
 450         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 451
 452         /* [7:0] set category code for channel status */
 453         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 454
 455         /*
 456          * [7:4] set source number for channel status
 457          * [3:0] set word length for channel status
 458          */
 459         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 460
 461         /* [7:4] set sample frequency for channel status */
 462         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 463 }
 464
 465 /**
 466  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 467  */
 468 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 469 {
 470         if (hdmi->var.pixclock < 10000) {
 471                 /* for 1080p8bit 148MHz */
 472                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 473                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 474                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 475                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 476                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 477                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 478                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 479                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 480                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 481         } else if (hdmi->var.pixclock < 30000) {
 482                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 483                 /*
 484                  * [1:0]        Speed_A
 485                  * [3:2]        Speed_B
 486                  * [4]          PLLA_Bypass
 487                  * [6]          DRV_TEST_EN
 488                  * [7]          DRV_TEST_IN
 489                  */
 490                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 491                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 492                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 493                 /*
 494                  * [2:0]        BGR_I_OFFSET
 495                  * [6:4]        BGR_V_OFFSET
 496                  */
 497                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 498                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 499                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 500                 /*
 501                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 502                  * LPF capacitance, LPF resistance[1]
 503                  */
 504                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 505                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 506                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 507                 /*
 508                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 509                  * LPF capacitance, LPF resistance[1]
 510                  */
 511                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 512                 /* DRV_CONFIG, PE_CONFIG */
 513                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 514                 /*
 515                  * [2:0]        AMON_SEL (4 == LPF voltage)
 516                  * [4]          PLLA_CONFIG[16]
 517                  * [5]          PLLB_CONFIG[16]
 518                  */
 519                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 520         } else {
 521                 /* for 480p8bit 27MHz */
 522                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 523                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 524                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 525                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 526                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 527                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 528                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 529                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 530                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 531         }
 532 }
 533
 534 /**
 535  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 536  */
 537 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 538 {
 539         struct fb_var_screeninfo *var = &hdmi->var;
 540         u8 vic;
 541
 542         /* AVI InfoFrame */
 543         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 544
 545         /* Packet Type = 0x82 */
 546         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 547
 548         /* Version = 0x02 */
 549         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 550
 551         /* Length = 13 (0x0D) */
 552         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 553
 554         /* N. A. Checksum */
 555         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 556
 557         /*
 558          * Y = RGB
 559          * A0 = No Data
 560          * B = Bar Data not valid
 561          * S = No Data
 562          */
 563         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 564
 565         /*
 566          * [7:6] C = Colorimetry: no data
 567          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 568          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 569          */
 570         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 571
 572         /*
 573          * ITC = No Data
 574          * EC = xvYCC601
 575          * Q = Default (depends on video format)
 576          * SC = No Known non_uniform Scaling
 577          */
 578         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 579
 580         /*
 581          * VIC should be ignored if external config is used, so, we could just use 0,
 582          * but play safe and use a valid value in any case just in case
 583          */
 584         if (hdmi->preprogrammed_vic)
 585                 vic = hdmi->preprogrammed_vic;
 586         else
 587                 vic = 4;
 588         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 589
 590         /* PR = No Repetition */
 591         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 592
 593         /* Line Number of End of Top Bar (lower 8 bits) */
 594         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 595
 596         /* Line Number of End of Top Bar (upper 8 bits) */
 597         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 598
 599         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 600         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 601
 602         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 603         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 604
 605         /* Pixel Number of End of Left Bar (lower 8 bits) */
 606         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 607
 608         /* Pixel Number of End of Left Bar (upper 8 bits) */
 609         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 610
 611         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 612         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 613
 614         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 615         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 616 }
 617
 618 /**
 619  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 620  */
 621 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 622 {
 623         /* Audio InfoFrame */
 624         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 625
 626         /* Packet Type = 0x84 */
 627         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 628
 629         /* Version Number = 0x01 */
 630         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 631
 632         /* 0 Length = 10 (0x0A) */
 633         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 634
 635         /* n. a. Checksum */
 636         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 637
 638         /* Audio Channel Count = Refer to Stream Header */
 639         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 640
 641         /* Refer to Stream Header */
 642         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 643
 644         /* Format depends on coding type (i.e. CT0...CT3) */
 645         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 646
 647         /* Speaker Channel Allocation = Front Right + Front Left */
 648         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 649
 650         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 651         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 652
 653         /* Reserved (0) */
 654         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 655         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 656         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 658         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 659 }
 660
 661 /**
 662  * sh_hdmi_configure() - Initialise HDMI for output
 663  */
 664 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 665 {
 666         /* Configure video format */
 667         sh_hdmi_video_config(hdmi);
 668
 669         /* Configure audio format */
 670         sh_hdmi_audio_config(hdmi);
 671
 672         /* Configure PHY */
 673         sh_hdmi_phy_config(hdmi);
 674
 675         /* Auxiliary Video Information (AVI) InfoFrame */
 676         sh_hdmi_avi_infoframe_setup(hdmi);
 677
 678         /* Audio InfoFrame */
 679         sh_hdmi_audio_infoframe_setup(hdmi);
 680
 681         /*
 682          * Control packet auto send with VSYNC control: auto send
 683          * General control, Gamut metadata, ISRC, and ACP packets
 684          */
 685         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 686
 687         /* FIXME */
 688         msleep(10);
 689
 690         /* PS mode b->d, reset PLLA and PLLB */
 691         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 692
 693         udelay(10);
 694
 695         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 696 }
 697
 698 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 699                 const struct fb_videomode *mode,
 700                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 701 {
 702         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 703         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 704
 705         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 706         if ((long)*hdmi_rate < 0)
 707                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 708
 709         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 710         if (rate_error && pdata->clk_optimize_parent)
 711                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 712         else if (clk_get_parent(hdmi->hdmi_clk))
 713                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 714
 715         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 716                 mode->left_margin, mode->xres,
 717                 mode->right_margin, mode->hsync_len,
 718                 mode->upper_margin, mode->yres,
 719                 mode->lower_margin, mode->vsync_len);
 720
 721         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 722                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 723                 mode->refresh, *parent_rate);
 724
 725         return rate_error;
 726 }
 727
 728 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 729                              unsigned long *parent_rate)
 730 {
 731         struct fb_var_screeninfo tmpvar;
 732         struct fb_var_screeninfo *var = &tmpvar;
 733         const struct fb_videomode *mode, *found = NULL;
 734         struct fb_info *info = hdmi->info;
 735         struct fb_modelist *modelist = NULL;
 736         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 737         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 738         bool exact_match = false;
 739         u8 edid[128];
 740         char *forced;
 741         int i;
 742
 743         /* Read EDID */
 744         dev_dbg(hdmi->dev, "Read back EDID code:");
 745         for (i = 0; i < 128; i++) {
 746                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 747 #ifdef DEBUG
 748                 if ((i % 16) == 0) {
 749                         printk(KERN_CONT "\n");
 750                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 751                 } else {
 752                         printk(KERN_CONT " %02X", edid[i]);
 753                 }
 754 #endif
 755         }
 756 #ifdef DEBUG
 757         printk(KERN_CONT "\n");
 758 #endif
 759
 760         fb_edid_to_monspecs(edid, &hdmi->monspec);
 761
 762         fb_get_options("sh_mobile_lcdc", &forced);
 763         if (forced && *forced) {
 764                 /* Only primitive parsing so far */
 765                 i = sscanf(forced, "%ux%u@%u",
 766                            &f_width, &f_height, &f_refresh);
 767                 if (i < 2) {
 768                         f_width = 0;
 769                         f_height = 0;
 770                 }
 771                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 772                         f_width, f_height, f_refresh);
 773         }
 774
 775         /* Walk monitor modes to find the best or the exact match */
 776         for (i = 0, mode = hdmi->monspec.modedb;
 777              f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
 778              i++, mode++) {
 779                 unsigned long rate_error;
 780
 781                 /* No interest in unmatching modes */
 782                 if (f_width != mode->xres || f_height != mode->yres)
 783                         continue;
 784
 785                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 786
 787                 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 788                         /*
 789                          * Exact match if either the refresh rate matches or it
 790                          * hasn't been specified and we've found a mode, for
 791                          * which we can configure the clock precisely
 792                          */
 793                         exact_match = true;
 794                 else if (found && found_rate_error <= rate_error)
 795                         /*
 796                          * We otherwise search for the closest matching clock
 797                          * rate - either if no refresh rate has been specified
 798                          * or we cannot find an exactly matching one
 799                          */
 800                         continue;
 801
 802                 /* Check if supported: sufficient fb memory, supported clock-rate */
 803                 fb_videomode_to_var(var, mode);
 804
 805                 if (info && info->fbops->fb_check_var &&
 806                     info->fbops->fb_check_var(var, info)) {
 807                         exact_match = false;
 808                         continue;
 809                 }
 810
 811                 found = mode;
 812                 found_rate_error = rate_error;
 813         }
 814
 815         /*
 816          * TODO 1: if no ->info is present, postpone running the config until
 817          * after ->info first gets registered.
 818          * TODO 2: consider registering the HDMI platform device from the LCDC
 819          * driver, and passing ->info with HDMI platform data.
 820          */
 821         if (info && !found) {
 822                 modelist = hdmi->info->modelist.next &&
 823                         !list_empty(&hdmi->info->modelist) ?
 824                         list_entry(hdmi->info->modelist.next,
 825                                    struct fb_modelist, list) :
 826                         NULL;
 827
 828                 if (modelist) {
 829                         found = &modelist->mode;
 830                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
 831                 }
 832         }
 833
 834         /* No cookie today */
 835         if (!found)
 836                 return -ENXIO;
 837
 838         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 839                 hdmi->preprogrammed_vic = 1;
 840         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
 841                 hdmi->preprogrammed_vic = 2;
 842         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
 843                 hdmi->preprogrammed_vic = 17;
 844         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
 845                 hdmi->preprogrammed_vic = 4;
 846         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
 847                 hdmi->preprogrammed_vic = 32;
 848         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
 849                 hdmi->preprogrammed_vic = 31;
 850         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
 851                 hdmi->preprogrammed_vic = 16;
 852         else
 853                 hdmi->preprogrammed_vic = 0;
 854
 855         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
 856                 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
 857                 found->xres, found->yres, found->refresh,
 858                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
 859
 860         fb_videomode_to_var(&hdmi->var, found);
 861         sh_hdmi_external_video_param(hdmi);
 862
 863         return 0;
 864 }
 865
 866 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 867 {
 868         struct sh_hdmi *hdmi = dev_id;
 869         u8 status1, status2, mask1, mask2;
 870
 871         /* mode_b and PLLA and PLLB reset */
 872         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 873
 874         /* How long shall reset be held? */
 875         udelay(10);
 876
 877         /* mode_b and PLLA and PLLB reset release */
 878         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 879
 880         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 881         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 882
 883         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 884         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 885
 886         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 887         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 888         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 889
 890         if (printk_ratelimit())
 891                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 892                         irq, status1, mask1, status2, mask2);
 893
 894         if (!((status1 & mask1) | (status2 & mask2))) {
 895                 return IRQ_NONE;
 896         } else if (status1 & 0xc0) {
 897                 u8 msens;
 898
 899                 /* Datasheet specifies 10ms... */
 900                 udelay(500);
 901
 902                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 903                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 904                 /* Check, if hot plug & MSENS pin status are both high */
 905                 if ((msens & 0xC0) == 0xC0) {
 906                         /* Display plug in */
 907                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 908
 909                         /* Set EDID word address  */
 910                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 911                         /* Set EDID segment pointer */
 912                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 913                         /* Enable EDID interrupt */
 914                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 915                 } else if (!(status1 & 0x80)) {
 916                         /* Display unplug, beware multiple interrupts */
 917                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
 918                                 schedule_delayed_work(&hdmi->edid_work, 0);
 919
 920                         hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 921                         /* display_off will switch back to mode_a */
 922                 }
 923         } else if (status1 & 2) {
 924                 /* EDID error interrupt: retry */
 925                 /* Set EDID word address  */
 926                 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 927                 /* Set EDID segment pointer */
 928                 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 929         } else if (status1 & 4) {
 930                 /* Disable EDID interrupt */
 931                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 932                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
 933                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 934         }
 935
 936         return IRQ_HANDLED;
 937 }
 938
 939 /* locking:     called with info->lock held, or before register_framebuffer() */
 940 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
 941 {
 942         /*
 943          * info is guaranteed to be valid, when we are called, because our
 944          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
 945          */
 946         struct sh_hdmi *hdmi = arg;
 947         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 948         struct sh_mobile_lcdc_chan *ch = info->par;
 949
 950         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
 951                 pdata->lcd_dev, info->state);
 952
 953         /* No need to lock */
 954         hdmi->info = info;
 955
 956         /*
 957          * hp_state can be set to
 958          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
 959          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
 960          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
 961          */
 962         switch (hdmi->hp_state) {
 963         case HDMI_HOTPLUG_EDID_DONE:
 964                 /* PS mode d->e. All functions are active */
 965                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
 966                 dev_dbg(hdmi->dev, "HDMI running\n");
 967                 break;
 968         case HDMI_HOTPLUG_DISCONNECTED:
 969                 info->state = FBINFO_STATE_SUSPENDED;
 970         default:
 971                 hdmi->var = ch->display_var;
 972         }
 973 }
 974
 975 /* locking: called with info->lock held */
 976 static void sh_hdmi_display_off(void *arg)
 977 {
 978         struct sh_hdmi *hdmi = arg;
 979         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 980
 981         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
 982         /* PS mode e->a */
 983         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
 984 }
 985
 986 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
 987 {
 988         struct fb_info *info = hdmi->info;
 989         struct sh_mobile_lcdc_chan *ch = info->par;
 990         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
 991         struct fb_videomode mode1, mode2;
 992
 993         fb_var_to_videomode(&mode1, old_var);
 994         fb_var_to_videomode(&mode2, new_var);
 995
 996         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
 997                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
 998
 999         if (fb_mode_is_equal(&mode1, &mode2))
1000                 return false;
1001
1002         dev_dbg(info->dev, "Switching %u -> %u lines\n",
1003                 mode1.yres, mode2.yres);
1004         *old_var = *new_var;
1005
1006         return true;
1007 }
1008
1009 /**
1010  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1011  * @hdmi:               driver context
1012  * @hdmi_rate:          HDMI clock frequency in Hz
1013  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1014  * return:              configured positive rate if successful
1015  *                      0 if couldn't set the rate, but managed to enable the
1016  *                      clock, negative error, if couldn't enable the clock
1017  */
1018 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1019                                   unsigned long parent_rate)
1020 {
1021         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1022         int ret;
1023
1024         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1025                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1026                 if (ret < 0) {
1027                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1028                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1029                 } else {
1030                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1031                 }
1032         }
1033
1034         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1035         if (ret < 0) {
1036                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1037                 hdmi_rate = 0;
1038         } else {
1039                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1040         }
1041
1042         return hdmi_rate;
1043 }
1044
1045 /* Hotplug interrupt occurred, read EDID */
1046 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1047 {
1048         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1049         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1050         struct sh_mobile_lcdc_chan *ch;
1051         int ret;
1052
1053         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1054                 pdata->lcd_dev, hdmi->hp_state);
1055
1056         if (!pdata->lcd_dev)
1057                 return;
1058
1059         mutex_lock(&hdmi->mutex);
1060
1061         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1062                 unsigned long parent_rate = 0, hdmi_rate;
1063
1064                 /* A device has been plugged in */
1065                 pm_runtime_get_sync(hdmi->dev);
1066
1067                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1068                 if (ret < 0)
1069                         goto out;
1070
1071                 /* Reconfigure the clock */
1072                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1073                 if (ret < 0)
1074                         goto out;
1075
1076                 msleep(10);
1077                 sh_hdmi_configure(hdmi);
1078                 /* Switched to another (d) power-save mode */
1079                 msleep(10);
1080
1081                 if (!hdmi->info)
1082                         goto out;
1083
1084                 ch = hdmi->info->par;
1085
1086                 acquire_console_sem();
1087
1088                 /* HDMI plug in */
1089                 if (!sh_hdmi_must_reconfigure(hdmi) &&
1090                     hdmi->info->state == FBINFO_STATE_RUNNING) {
1091                         /*
1092                          * First activation with the default monitor - just turn
1093                          * on, if we run a resume here, the logo disappears
1094                          */
1095                         if (lock_fb_info(hdmi->info)) {
1096                                 sh_hdmi_display_on(hdmi, hdmi->info);
1097                                 unlock_fb_info(hdmi->info);
1098                         }
1099                 } else {
1100                         /* New monitor or have to wake up */
1101                         fb_set_suspend(hdmi->info, 0);
1102                 }
1103
1104                 release_console_sem();
1105         } else {
1106                 ret = 0;
1107                 if (!hdmi->info)
1108                         goto out;
1109
1110                 hdmi->monspec.modedb_len = 0;
1111                 fb_destroy_modedb(hdmi->monspec.modedb);
1112                 hdmi->monspec.modedb = NULL;
1113
1114                 acquire_console_sem();
1115
1116                 /* HDMI disconnect */
1117                 fb_set_suspend(hdmi->info, 1);
1118
1119                 release_console_sem();
1120                 pm_runtime_put(hdmi->dev);
1121         }
1122
1123 out:
1124         if (ret < 0)
1125                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1126         mutex_unlock(&hdmi->mutex);
1127
1128         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1129 }
1130
1131 static int sh_hdmi_notify(struct notifier_block *nb,
1132                           unsigned long action, void *data);
1133
1134 static struct notifier_block sh_hdmi_notifier = {
1135         .notifier_call = sh_hdmi_notify,
1136 };
1137
1138 static int sh_hdmi_notify(struct notifier_block *nb,
1139                           unsigned long action, void *data)
1140 {
1141         struct fb_event *event = data;
1142         struct fb_info *info = event->info;
1143         struct sh_mobile_lcdc_chan *ch = info->par;
1144         struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1145         struct sh_hdmi *hdmi = board_cfg->board_data;
1146
1147         if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1148                 return NOTIFY_DONE;
1149
1150         switch(action) {
1151         case FB_EVENT_FB_REGISTERED:
1152                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1153                 break;
1154         case FB_EVENT_FB_UNREGISTERED:
1155                 /*
1156                  * We are called from unregister_framebuffer() with the
1157                  * info->lock held. This is bad for us, because we can race with
1158                  * the scheduled work, which has to call fb_set_suspend(), which
1159                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1160                  * cannot take and hold info->lock for the whole function
1161                  * duration. Using an additional lock creates a classical AB-BA
1162                  * lock up. Therefore, we have to release the info->lock
1163                  * temporarily, synchronise with the work queue and re-acquire
1164                  * the info->lock.
1165                  */
1166                 unlock_fb_info(hdmi->info);
1167                 mutex_lock(&hdmi->mutex);
1168                 hdmi->info = NULL;
1169                 mutex_unlock(&hdmi->mutex);
1170                 lock_fb_info(hdmi->info);
1171                 return NOTIFY_OK;
1172         }
1173         return NOTIFY_DONE;
1174 }
1175
1176 static int __init sh_hdmi_probe(struct platform_device *pdev)
1177 {
1178         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1179         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180         struct sh_mobile_lcdc_board_cfg *board_cfg;
1181         int irq = platform_get_irq(pdev, 0), ret;
1182         struct sh_hdmi *hdmi;
1183         long rate;
1184
1185         if (!res || !pdata || irq < 0)
1186                 return -ENODEV;
1187
1188         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1189         if (!hdmi) {
1190                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1191                 return -ENOMEM;
1192         }
1193
1194         mutex_init(&hdmi->mutex);
1195
1196         hdmi->dev = &pdev->dev;
1197
1198         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1199         if (IS_ERR(hdmi->hdmi_clk)) {
1200                 ret = PTR_ERR(hdmi->hdmi_clk);
1201                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1202                 goto egetclk;
1203         }
1204
1205         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1206         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1207         if (rate > 0)
1208                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1209
1210         if (rate < 0) {
1211                 ret = rate;
1212                 goto erate;
1213         }
1214
1215         ret = clk_enable(hdmi->hdmi_clk);
1216         if (ret < 0) {
1217                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1218                 goto erate;
1219         }
1220
1221         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1222
1223         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1224                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1225                 ret = -EBUSY;
1226                 goto ereqreg;
1227         }
1228
1229         hdmi->base = ioremap(res->start, resource_size(res));
1230         if (!hdmi->base) {
1231                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1232                 ret = -ENOMEM;
1233                 goto emap;
1234         }
1235
1236         platform_set_drvdata(pdev, hdmi);
1237
1238         /* Set up LCDC callbacks */
1239         board_cfg = &pdata->lcd_chan->board_cfg;
1240         board_cfg->owner = THIS_MODULE;
1241         board_cfg->board_data = hdmi;
1242         board_cfg->display_on = sh_hdmi_display_on;
1243         board_cfg->display_off = sh_hdmi_display_off;
1244
1245         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1246
1247         pm_runtime_enable(&pdev->dev);
1248         pm_runtime_resume(&pdev->dev);
1249
1250         /* Product and revision IDs are 0 in sh-mobile version */
1251         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1252                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1253
1254         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1255                           dev_name(&pdev->dev), hdmi);
1256         if (ret < 0) {
1257                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1258                 goto ereqirq;
1259         }
1260
1261         ret = snd_soc_register_codec(&pdev->dev,
1262                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1263         if (ret < 0) {
1264                 dev_err(&pdev->dev, "codec registration failed\n");
1265                 goto ecodec;
1266         }
1267
1268         return 0;
1269
1270 ecodec:
1271         free_irq(irq, hdmi);
1272 ereqirq:
1273         pm_runtime_disable(&pdev->dev);
1274         iounmap(hdmi->base);
1275 emap:
1276         release_mem_region(res->start, resource_size(res));
1277 ereqreg:
1278         clk_disable(hdmi->hdmi_clk);
1279 erate:
1280         clk_put(hdmi->hdmi_clk);
1281 egetclk:
1282         mutex_destroy(&hdmi->mutex);
1283         kfree(hdmi);
1284
1285         return ret;
1286 }
1287
1288 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1289 {
1290         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1291         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1292         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293         struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1294         int irq = platform_get_irq(pdev, 0);
1295
1296         snd_soc_unregister_codec(&pdev->dev);
1297
1298         board_cfg->display_on = NULL;
1299         board_cfg->display_off = NULL;
1300         board_cfg->board_data = NULL;
1301         board_cfg->owner = NULL;
1302
1303         /* No new work will be scheduled, wait for running ISR */
1304         free_irq(irq, hdmi);
1305         /* Wait for already scheduled work */
1306         cancel_delayed_work_sync(&hdmi->edid_work);
1307         pm_runtime_disable(&pdev->dev);
1308         clk_disable(hdmi->hdmi_clk);
1309         clk_put(hdmi->hdmi_clk);
1310         iounmap(hdmi->base);
1311         release_mem_region(res->start, resource_size(res));
1312         mutex_destroy(&hdmi->mutex);
1313         kfree(hdmi);
1314
1315         return 0;
1316 }
1317
1318 static struct platform_driver sh_hdmi_driver = {
1319         .remove         = __exit_p(sh_hdmi_remove),
1320         .driver = {
1321                 .name   = "sh-mobile-hdmi",
1322         },
1323 };
1324
1325 static int __init sh_hdmi_init(void)
1326 {
1327         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1328 }
1329 module_init(sh_hdmi_init);
1330
1331 static void __exit sh_hdmi_exit(void)
1332 {
1333         platform_driver_unregister(&sh_hdmi_driver);
1334 }
1335 module_exit(sh_hdmi_exit);
1336
1337 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1338 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1339 MODULE_LICENSE("GPL v2");