drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27
  28 #include <video/sh_mobile_hdmi.h>
  29 #include <video/sh_mobile_lcdc.h>
  30
  31 #include "sh_mobile_lcdcfb.h"
  32
  33 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  34 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  35                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  36 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  39                                                         bits 19..16 of Internal CTS */
  40 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  42 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  43 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  45 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  46 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  47 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  48 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  49 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  50 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  51 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  52 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  54 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  55 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  56 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  57 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  58 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  59
  60 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  61 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  62
  63 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  64 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  65 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  66 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  68 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  70 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  72 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  74 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  75 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  76 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  77 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  78 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  79 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  80 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  81 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  82 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  83 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  84 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  86 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  97 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 129 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 130 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 132 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 133 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 134 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 135 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 136 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 137 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 138 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 139 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 140 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 141 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 142 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 143 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 144 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 145 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 146 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 147 #define HDMI_SHA0                               0xB9 /* sha0 */
 148 #define HDMI_SHA1                               0xBA /* sha1 */
 149 #define HDMI_SHA2                               0xBB /* sha2 */
 150 #define HDMI_SHA3                               0xBC /* sha3 */
 151 #define HDMI_SHA4                               0xBD /* sha4 */
 152 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 153 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 154 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 155 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 156 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 157 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 158 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 159 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 160 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 161 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 162 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 163 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 164 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 165 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 166 #define HDMI_AN_SEED                            0xCC /* An seed */
 167 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 168 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 170 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 171 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 172 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 173 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 174 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 175 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 176 #define HDMI_PJ                                 0xD7 /* Pj */
 177 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 178 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 179 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 180 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 181 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 182 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 183 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 184 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 185 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 186 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 187 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 188 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 189 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 190 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 191 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 192 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 193 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 194 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 195 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 196 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 197 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 198 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 199 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 200 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 201 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 202
 203 enum hotplug_state {
 204         HDMI_HOTPLUG_DISCONNECTED,
 205         HDMI_HOTPLUG_CONNECTED,
 206         HDMI_HOTPLUG_EDID_DONE,
 207 };
 208
 209 struct sh_hdmi {
 210         void __iomem *base;
 211         enum hotplug_state hp_state;    /* hot-plug status */
 212         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 213                                            the external mode */
 214         u8 edid_block_addr;
 215         u8 edid_segment_nr;
 216         u8 edid_blocks;
 217         struct clk *hdmi_clk;
 218         struct device *dev;
 219         struct fb_info *info;
 220         struct mutex mutex;             /* Protect the info pointer */
 221         struct delayed_work edid_work;
 222         struct fb_var_screeninfo var;
 223         struct fb_monspecs monspec;
 224 };
 225
 226 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 227 {
 228         iowrite8(data, hdmi->base + reg);
 229 }
 230
 231 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 232 {
 233         return ioread8(hdmi->base + reg);
 234 }
 235
 236 /*
 237  *      HDMI sound
 238  */
 239 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 240                                      unsigned int reg)
 241 {
 242         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 243
 244         return hdmi_read(hdmi, reg);
 245 }
 246
 247 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 248                              unsigned int reg,
 249                              unsigned int value)
 250 {
 251         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 252
 253         hdmi_write(hdmi, value, reg);
 254         return 0;
 255 }
 256
 257 static struct snd_soc_dai_driver sh_hdmi_dai = {
 258         .name = "sh_mobile_hdmi-hifi",
 259         .playback = {
 260                 .stream_name = "Playback",
 261                 .channels_min = 2,
 262                 .channels_max = 8,
 263                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 264                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 265                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 266                          SNDRV_PCM_RATE_192000,
 267                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 268         },
 269 };
 270
 271 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 272 {
 273         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 274
 275         return 0;
 276 }
 277
 278 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 279         .probe          = sh_hdmi_snd_probe,
 280         .read           = sh_hdmi_snd_read,
 281         .write          = sh_hdmi_snd_write,
 282 };
 283
 284 /*
 285  *      HDMI video
 286  */
 287
 288 /* External video parameter settings */
 289 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 290 {
 291         struct fb_var_screeninfo *var = &hdmi->var;
 292         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 293         u8 sync = 0;
 294
 295         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 296
 297         hdelay = var->hsync_len + var->left_margin;
 298         hblank = var->right_margin + hdelay;
 299
 300         /*
 301          * Vertical timing looks a bit different in Figure 18,
 302          * but let's try the same first by setting offset = 0
 303          */
 304         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 305
 306         vdelay = var->vsync_len + var->upper_margin;
 307         vblank = var->lower_margin + vdelay;
 308         voffset = min(var->upper_margin / 2, 6U);
 309
 310         /*
 311          * [3]: VSYNC polarity: Positive
 312          * [2]: HSYNC polarity: Positive
 313          * [1]: Interlace/Progressive: Progressive
 314          * [0]: External video settings enable: used.
 315          */
 316         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 317                 sync |= 4;
 318         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 319                 sync |= 8;
 320
 321         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 322                 htotal, hblank, hdelay, var->hsync_len,
 323                 vtotal, vblank, vdelay, var->vsync_len, sync);
 324
 325         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 326
 327         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 328         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 329
 330         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 331         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 332
 333         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 334         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 335
 336         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 337         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 338
 339         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 340         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 341
 342         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 343
 344         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 345
 346         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 347
 348         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 349         if (!hdmi->preprogrammed_vic)
 350                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 351                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 352 }
 353
 354 /**
 355  * sh_hdmi_video_config()
 356  */
 357 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 358 {
 359         /*
 360          * [7:4]: Audio sampling frequency: 48kHz
 361          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 362          * [0]: Internal/External DE select: internal
 363          */
 364         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 365
 366         /*
 367          * [7:6]: Video output format: RGB 4:4:4
 368          * [5:4]: Input video data width: 8 bit
 369          * [3:1]: EAV/SAV location: channel 1
 370          * [0]: Video input color space: RGB
 371          */
 372         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 373
 374         /*
 375          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 376          * left at 0 by default, this configures 24bpp and sets the Color Depth
 377          * (CD) field in the General Control Packet
 378          */
 379         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 380 }
 381
 382 /**
 383  * sh_hdmi_audio_config()
 384  */
 385 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 386 {
 387         u8 data;
 388         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 389
 390         /*
 391          * [7:4] L/R data swap control
 392          * [3:0] appropriate N[19:16]
 393          */
 394         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 395         /* appropriate N[15:8] */
 396         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 397         /* appropriate N[7:0] */
 398         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 399
 400         /* [7:4] 48 kHz SPDIF not used */
 401         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 402
 403         /*
 404          * [6:5] set required down sampling rate if required
 405          * [4:3] set required audio source
 406          */
 407         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 408         default:
 409                 /* fall through */
 410         case HDMI_SND_SRC_I2S:
 411                 data = 0x0 << 3;
 412                 break;
 413         case HDMI_SND_SRC_SPDIF:
 414                 data = 0x1 << 3;
 415                 break;
 416         case HDMI_SND_SRC_DSD:
 417                 data = 0x2 << 3;
 418                 break;
 419         case HDMI_SND_SRC_HBR:
 420                 data = 0x3 << 3;
 421                 break;
 422         }
 423         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 424
 425         /* [3:0] set sending channel number for channel status */
 426         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 427
 428         /*
 429          * [5:2] set valid I2S source input pin
 430          * [1:0] set input I2S source mode
 431          */
 432         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 433
 434         /* [7:4] set valid DSD source input pin */
 435         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 436
 437         /* [7:0] set appropriate I2S input pin swap settings if required */
 438         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 439
 440         /*
 441          * [7] set validity bit for channel status
 442          * [3:0] set original sample frequency for channel status
 443          */
 444         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 445
 446         /*
 447          * [7] set value for channel status
 448          * [6] set value for channel status
 449          * [5] set copyright bit for channel status
 450          * [4:2] set additional information for channel status
 451          * [1:0] set clock accuracy for channel status
 452          */
 453         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 454
 455         /* [7:0] set category code for channel status */
 456         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 457
 458         /*
 459          * [7:4] set source number for channel status
 460          * [3:0] set word length for channel status
 461          */
 462         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 463
 464         /* [7:4] set sample frequency for channel status */
 465         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 466 }
 467
 468 /**
 469  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 470  */
 471 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 472 {
 473         if (hdmi->var.pixclock < 10000) {
 474                 /* for 1080p8bit 148MHz */
 475                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 476                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 477                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 478                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 479                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 480                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 481                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 482                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 483                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 484         } else if (hdmi->var.pixclock < 30000) {
 485                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 486                 /*
 487                  * [1:0]        Speed_A
 488                  * [3:2]        Speed_B
 489                  * [4]          PLLA_Bypass
 490                  * [6]          DRV_TEST_EN
 491                  * [7]          DRV_TEST_IN
 492                  */
 493                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 494                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 495                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 496                 /*
 497                  * [2:0]        BGR_I_OFFSET
 498                  * [6:4]        BGR_V_OFFSET
 499                  */
 500                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 501                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 502                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 503                 /*
 504                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 505                  * LPF capacitance, LPF resistance[1]
 506                  */
 507                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 508                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 509                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 510                 /*
 511                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 512                  * LPF capacitance, LPF resistance[1]
 513                  */
 514                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 515                 /* DRV_CONFIG, PE_CONFIG */
 516                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 517                 /*
 518                  * [2:0]        AMON_SEL (4 == LPF voltage)
 519                  * [4]          PLLA_CONFIG[16]
 520                  * [5]          PLLB_CONFIG[16]
 521                  */
 522                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 523         } else {
 524                 /* for 480p8bit 27MHz */
 525                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 526                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 527                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 528                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 529                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 530                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 531                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 532                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 533                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 534         }
 535 }
 536
 537 /**
 538  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 539  */
 540 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 541 {
 542         u8 vic;
 543
 544         /* AVI InfoFrame */
 545         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 546
 547         /* Packet Type = 0x82 */
 548         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 549
 550         /* Version = 0x02 */
 551         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 552
 553         /* Length = 13 (0x0D) */
 554         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 555
 556         /* N. A. Checksum */
 557         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 558
 559         /*
 560          * Y = RGB
 561          * A0 = No Data
 562          * B = Bar Data not valid
 563          * S = No Data
 564          */
 565         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 566
 567         /*
 568          * [7:6] C = Colorimetry: no data
 569          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 570          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 571          */
 572         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 573
 574         /*
 575          * ITC = No Data
 576          * EC = xvYCC601
 577          * Q = Default (depends on video format)
 578          * SC = No Known non_uniform Scaling
 579          */
 580         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 581
 582         /*
 583          * VIC should be ignored if external config is used, so, we could just use 0,
 584          * but play safe and use a valid value in any case just in case
 585          */
 586         if (hdmi->preprogrammed_vic)
 587                 vic = hdmi->preprogrammed_vic;
 588         else
 589                 vic = 4;
 590         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 591
 592         /* PR = No Repetition */
 593         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 594
 595         /* Line Number of End of Top Bar (lower 8 bits) */
 596         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 597
 598         /* Line Number of End of Top Bar (upper 8 bits) */
 599         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 600
 601         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 602         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 603
 604         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 605         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 606
 607         /* Pixel Number of End of Left Bar (lower 8 bits) */
 608         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 609
 610         /* Pixel Number of End of Left Bar (upper 8 bits) */
 611         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 612
 613         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 614         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 615
 616         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 617         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 618 }
 619
 620 /**
 621  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 622  */
 623 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 624 {
 625         /* Audio InfoFrame */
 626         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 627
 628         /* Packet Type = 0x84 */
 629         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 630
 631         /* Version Number = 0x01 */
 632         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 633
 634         /* 0 Length = 10 (0x0A) */
 635         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 636
 637         /* n. a. Checksum */
 638         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 639
 640         /* Audio Channel Count = Refer to Stream Header */
 641         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 642
 643         /* Refer to Stream Header */
 644         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 645
 646         /* Format depends on coding type (i.e. CT0...CT3) */
 647         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 648
 649         /* Speaker Channel Allocation = Front Right + Front Left */
 650         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 651
 652         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 653         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 654
 655         /* Reserved (0) */
 656         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 658         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 659         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 660         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 661 }
 662
 663 /**
 664  * sh_hdmi_configure() - Initialise HDMI for output
 665  */
 666 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 667 {
 668         /* Configure video format */
 669         sh_hdmi_video_config(hdmi);
 670
 671         /* Configure audio format */
 672         sh_hdmi_audio_config(hdmi);
 673
 674         /* Configure PHY */
 675         sh_hdmi_phy_config(hdmi);
 676
 677         /* Auxiliary Video Information (AVI) InfoFrame */
 678         sh_hdmi_avi_infoframe_setup(hdmi);
 679
 680         /* Audio InfoFrame */
 681         sh_hdmi_audio_infoframe_setup(hdmi);
 682
 683         /*
 684          * Control packet auto send with VSYNC control: auto send
 685          * General control, Gamut metadata, ISRC, and ACP packets
 686          */
 687         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 688
 689         /* FIXME */
 690         msleep(10);
 691
 692         /* PS mode b->d, reset PLLA and PLLB */
 693         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 694
 695         udelay(10);
 696
 697         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 698 }
 699
 700 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 701                 const struct fb_videomode *mode,
 702                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 703 {
 704         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 705         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 706
 707         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 708         if ((long)*hdmi_rate < 0)
 709                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 710
 711         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 712         if (rate_error && pdata->clk_optimize_parent)
 713                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 714         else if (clk_get_parent(hdmi->hdmi_clk))
 715                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 716
 717         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 718                 mode->left_margin, mode->xres,
 719                 mode->right_margin, mode->hsync_len,
 720                 mode->upper_margin, mode->yres,
 721                 mode->lower_margin, mode->vsync_len);
 722
 723         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 724                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 725                 mode->refresh, *parent_rate);
 726
 727         return rate_error;
 728 }
 729
 730 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 731                              unsigned long *parent_rate)
 732 {
 733         struct fb_var_screeninfo tmpvar;
 734         struct fb_var_screeninfo *var = &tmpvar;
 735         const struct fb_videomode *mode, *found = NULL;
 736         struct fb_info *info = hdmi->info;
 737         struct fb_modelist *modelist = NULL;
 738         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 739         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 740         bool exact_match = false;
 741         u8 edid[128];
 742         char *forced;
 743         int i;
 744
 745         /* Read EDID */
 746         dev_dbg(hdmi->dev, "Read back EDID code:");
 747         for (i = 0; i < 128; i++) {
 748                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 749 #ifdef DEBUG
 750                 if ((i % 16) == 0) {
 751                         printk(KERN_CONT "\n");
 752                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 753                 } else {
 754                         printk(KERN_CONT " %02X", edid[i]);
 755                 }
 756 #endif
 757         }
 758 #ifdef DEBUG
 759         printk(KERN_CONT "\n");
 760 #endif
 761
 762         if (!hdmi->edid_blocks) {
 763                 fb_edid_to_monspecs(edid, &hdmi->monspec);
 764                 hdmi->edid_blocks = edid[126] + 1;
 765
 766                 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
 767                         hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
 768         } else {
 769                 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
 770                         edid[0], edid[2]);
 771                 fb_edid_add_monspecs(edid, &hdmi->monspec);
 772         }
 773
 774         if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
 775             (hdmi->edid_block_addr >> 7) + 1) {
 776                 /* More blocks to read */
 777                 if (hdmi->edid_block_addr) {
 778                         hdmi->edid_block_addr = 0;
 779                         hdmi->edid_segment_nr++;
 780                 } else {
 781                         hdmi->edid_block_addr = 0x80;
 782                 }
 783                 /* Set EDID word address  */
 784                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 785                 /* Enable EDID interrupt */
 786                 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 787                 /* Set EDID segment pointer - starts reading EDID */
 788                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 789                 return -EAGAIN;
 790         }
 791
 792         /* All E-EDID blocks ready */
 793         dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
 794
 795         fb_get_options("sh_mobile_lcdc", &forced);
 796         if (forced && *forced) {
 797                 /* Only primitive parsing so far */
 798                 i = sscanf(forced, "%ux%u@%u",
 799                            &f_width, &f_height, &f_refresh);
 800                 if (i < 2) {
 801                         f_width = 0;
 802                         f_height = 0;
 803                 }
 804                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 805                         f_width, f_height, f_refresh);
 806         }
 807
 808         /* Walk monitor modes to find the best or the exact match */
 809         for (i = 0, mode = hdmi->monspec.modedb;
 810              f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
 811              i++, mode++) {
 812                 unsigned long rate_error;
 813
 814                 /* No interest in unmatching modes */
 815                 if (f_width != mode->xres || f_height != mode->yres)
 816                         continue;
 817
 818                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 819
 820                 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 821                         /*
 822                          * Exact match if either the refresh rate matches or it
 823                          * hasn't been specified and we've found a mode, for
 824                          * which we can configure the clock precisely
 825                          */
 826                         exact_match = true;
 827                 else if (found && found_rate_error <= rate_error)
 828                         /*
 829                          * We otherwise search for the closest matching clock
 830                          * rate - either if no refresh rate has been specified
 831                          * or we cannot find an exactly matching one
 832                          */
 833                         continue;
 834
 835                 /* Check if supported: sufficient fb memory, supported clock-rate */
 836                 fb_videomode_to_var(var, mode);
 837
 838                 if (info && info->fbops->fb_check_var &&
 839                     info->fbops->fb_check_var(var, info)) {
 840                         exact_match = false;
 841                         continue;
 842                 }
 843
 844                 found = mode;
 845                 found_rate_error = rate_error;
 846         }
 847
 848         /*
 849          * TODO 1: if no ->info is present, postpone running the config until
 850          * after ->info first gets registered.
 851          * TODO 2: consider registering the HDMI platform device from the LCDC
 852          * driver, and passing ->info with HDMI platform data.
 853          */
 854         if (info && !found) {
 855                 modelist = hdmi->info->modelist.next &&
 856                         !list_empty(&hdmi->info->modelist) ?
 857                         list_entry(hdmi->info->modelist.next,
 858                                    struct fb_modelist, list) :
 859                         NULL;
 860
 861                 if (modelist) {
 862                         found = &modelist->mode;
 863                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
 864                 }
 865         }
 866
 867         /* No cookie today */
 868         if (!found)
 869                 return -ENXIO;
 870
 871         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 872                 hdmi->preprogrammed_vic = 1;
 873         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
 874                 hdmi->preprogrammed_vic = 2;
 875         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
 876                 hdmi->preprogrammed_vic = 17;
 877         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
 878                 hdmi->preprogrammed_vic = 4;
 879         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
 880                 hdmi->preprogrammed_vic = 32;
 881         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
 882                 hdmi->preprogrammed_vic = 31;
 883         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
 884                 hdmi->preprogrammed_vic = 16;
 885         else
 886                 hdmi->preprogrammed_vic = 0;
 887
 888         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
 889                 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
 890                 found->xres, found->yres, found->refresh,
 891                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
 892
 893         fb_videomode_to_var(&hdmi->var, found);
 894         sh_hdmi_external_video_param(hdmi);
 895
 896         return 0;
 897 }
 898
 899 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 900 {
 901         struct sh_hdmi *hdmi = dev_id;
 902         u8 status1, status2, mask1, mask2;
 903
 904         /* mode_b and PLLA and PLLB reset */
 905         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 906
 907         /* How long shall reset be held? */
 908         udelay(10);
 909
 910         /* mode_b and PLLA and PLLB reset release */
 911         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 912
 913         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 914         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 915
 916         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 917         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 918
 919         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 920         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 921         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 922
 923         if (printk_ratelimit())
 924                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 925                         irq, status1, mask1, status2, mask2);
 926
 927         if (!((status1 & mask1) | (status2 & mask2))) {
 928                 return IRQ_NONE;
 929         } else if (status1 & 0xc0) {
 930                 u8 msens;
 931
 932                 /* Datasheet specifies 10ms... */
 933                 udelay(500);
 934
 935                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 936                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 937                 /* Check, if hot plug & MSENS pin status are both high */
 938                 if ((msens & 0xC0) == 0xC0) {
 939                         /* Display plug in */
 940                         hdmi->edid_segment_nr = 0;
 941                         hdmi->edid_block_addr = 0;
 942                         hdmi->edid_blocks = 0;
 943                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 944
 945                         /* Set EDID word address  */
 946                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 947                         /* Enable EDID interrupt */
 948                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 949                         /* Set EDID segment pointer - starts reading EDID */
 950                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 951                 } else if (!(status1 & 0x80)) {
 952                         /* Display unplug, beware multiple interrupts */
 953                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
 954                                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 955                                 schedule_delayed_work(&hdmi->edid_work, 0);
 956                         }
 957                         /* display_off will switch back to mode_a */
 958                 }
 959         } else if (status1 & 2) {
 960                 /* EDID error interrupt: retry */
 961                 /* Set EDID word address  */
 962                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 963                 /* Set EDID segment pointer */
 964                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 965         } else if (status1 & 4) {
 966                 /* Disable EDID interrupt */
 967                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 968                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 969         }
 970
 971         return IRQ_HANDLED;
 972 }
 973
 974 /* locking:     called with info->lock held, or before register_framebuffer() */
 975 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
 976 {
 977         /*
 978          * info is guaranteed to be valid, when we are called, because our
 979          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
 980          */
 981         struct sh_hdmi *hdmi = arg;
 982         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 983         struct sh_mobile_lcdc_chan *ch = info->par;
 984
 985         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
 986                 pdata->lcd_dev, info->state);
 987
 988         /* No need to lock */
 989         hdmi->info = info;
 990
 991         /*
 992          * hp_state can be set to
 993          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
 994          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
 995          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
 996          */
 997         switch (hdmi->hp_state) {
 998         case HDMI_HOTPLUG_EDID_DONE:
 999                 /* PS mode d->e. All functions are active */
1000                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
1001                 dev_dbg(hdmi->dev, "HDMI running\n");
1002                 break;
1003         case HDMI_HOTPLUG_DISCONNECTED:
1004                 info->state = FBINFO_STATE_SUSPENDED;
1005         default:
1006                 hdmi->var = ch->display_var;
1007         }
1008 }
1009
1010 /* locking: called with info->lock held */
1011 static void sh_hdmi_display_off(void *arg)
1012 {
1013         struct sh_hdmi *hdmi = arg;
1014         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1015
1016         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
1017         /* PS mode e->a */
1018         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1019 }
1020
1021 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1022 {
1023         struct fb_info *info = hdmi->info;
1024         struct sh_mobile_lcdc_chan *ch = info->par;
1025         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1026         struct fb_videomode mode1, mode2;
1027
1028         fb_var_to_videomode(&mode1, old_var);
1029         fb_var_to_videomode(&mode2, new_var);
1030
1031         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1032                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1033
1034         if (fb_mode_is_equal(&mode1, &mode2))
1035                 return false;
1036
1037         dev_dbg(info->dev, "Switching %u -> %u lines\n",
1038                 mode1.yres, mode2.yres);
1039         *old_var = *new_var;
1040
1041         return true;
1042 }
1043
1044 /**
1045  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1046  * @hdmi:               driver context
1047  * @hdmi_rate:          HDMI clock frequency in Hz
1048  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1049  * return:              configured positive rate if successful
1050  *                      0 if couldn't set the rate, but managed to enable the
1051  *                      clock, negative error, if couldn't enable the clock
1052  */
1053 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1054                                   unsigned long parent_rate)
1055 {
1056         int ret;
1057
1058         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1059                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1060                 if (ret < 0) {
1061                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1062                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1063                 } else {
1064                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1065                 }
1066         }
1067
1068         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1069         if (ret < 0) {
1070                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1071                 hdmi_rate = 0;
1072         } else {
1073                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1074         }
1075
1076         return hdmi_rate;
1077 }
1078
1079 /* Hotplug interrupt occurred, read EDID */
1080 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1081 {
1082         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1083         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1084         struct sh_mobile_lcdc_chan *ch;
1085         int ret;
1086
1087         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1088                 pdata->lcd_dev, hdmi->hp_state);
1089
1090         if (!pdata->lcd_dev)
1091                 return;
1092
1093         mutex_lock(&hdmi->mutex);
1094
1095         if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1096                 unsigned long parent_rate = 0, hdmi_rate;
1097
1098                 /* A device has been plugged in */
1099                 pm_runtime_get_sync(hdmi->dev);
1100
1101                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1102                 if (ret < 0)
1103                         goto out;
1104
1105                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1106
1107                 /* Reconfigure the clock */
1108                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1109                 if (ret < 0)
1110                         goto out;
1111
1112                 msleep(10);
1113                 sh_hdmi_configure(hdmi);
1114                 /* Switched to another (d) power-save mode */
1115                 msleep(10);
1116
1117                 if (!hdmi->info)
1118                         goto out;
1119
1120                 ch = hdmi->info->par;
1121
1122                 acquire_console_sem();
1123
1124                 /* HDMI plug in */
1125                 if (!sh_hdmi_must_reconfigure(hdmi) &&
1126                     hdmi->info->state == FBINFO_STATE_RUNNING) {
1127                         /*
1128                          * First activation with the default monitor - just turn
1129                          * on, if we run a resume here, the logo disappears
1130                          */
1131                         if (lock_fb_info(hdmi->info)) {
1132                                 sh_hdmi_display_on(hdmi, hdmi->info);
1133                                 unlock_fb_info(hdmi->info);
1134                         }
1135                 } else {
1136                         /* New monitor or have to wake up */
1137                         fb_set_suspend(hdmi->info, 0);
1138                 }
1139
1140                 release_console_sem();
1141         } else {
1142                 ret = 0;
1143                 if (!hdmi->info)
1144                         goto out;
1145
1146                 hdmi->monspec.modedb_len = 0;
1147                 fb_destroy_modedb(hdmi->monspec.modedb);
1148                 hdmi->monspec.modedb = NULL;
1149
1150                 acquire_console_sem();
1151
1152                 /* HDMI disconnect */
1153                 fb_set_suspend(hdmi->info, 1);
1154
1155                 release_console_sem();
1156                 pm_runtime_put(hdmi->dev);
1157         }
1158
1159 out:
1160         if (ret < 0 && ret != -EAGAIN)
1161                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1162         mutex_unlock(&hdmi->mutex);
1163
1164         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1165 }
1166
1167 static int sh_hdmi_notify(struct notifier_block *nb,
1168                           unsigned long action, void *data);
1169
1170 static struct notifier_block sh_hdmi_notifier = {
1171         .notifier_call = sh_hdmi_notify,
1172 };
1173
1174 static int sh_hdmi_notify(struct notifier_block *nb,
1175                           unsigned long action, void *data)
1176 {
1177         struct fb_event *event = data;
1178         struct fb_info *info = event->info;
1179         struct sh_mobile_lcdc_chan *ch = info->par;
1180         struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1181         struct sh_hdmi *hdmi = board_cfg->board_data;
1182
1183         if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1184                 return NOTIFY_DONE;
1185
1186         switch(action) {
1187         case FB_EVENT_FB_REGISTERED:
1188                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1189                 break;
1190         case FB_EVENT_FB_UNREGISTERED:
1191                 /*
1192                  * We are called from unregister_framebuffer() with the
1193                  * info->lock held. This is bad for us, because we can race with
1194                  * the scheduled work, which has to call fb_set_suspend(), which
1195                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1196                  * cannot take and hold info->lock for the whole function
1197                  * duration. Using an additional lock creates a classical AB-BA
1198                  * lock up. Therefore, we have to release the info->lock
1199                  * temporarily, synchronise with the work queue and re-acquire
1200                  * the info->lock.
1201                  */
1202                 unlock_fb_info(hdmi->info);
1203                 mutex_lock(&hdmi->mutex);
1204                 hdmi->info = NULL;
1205                 mutex_unlock(&hdmi->mutex);
1206                 lock_fb_info(hdmi->info);
1207                 return NOTIFY_OK;
1208         }
1209         return NOTIFY_DONE;
1210 }
1211
1212 static int __init sh_hdmi_probe(struct platform_device *pdev)
1213 {
1214         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1215         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1216         struct sh_mobile_lcdc_board_cfg *board_cfg;
1217         int irq = platform_get_irq(pdev, 0), ret;
1218         struct sh_hdmi *hdmi;
1219         long rate;
1220
1221         if (!res || !pdata || irq < 0)
1222                 return -ENODEV;
1223
1224         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1225         if (!hdmi) {
1226                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1227                 return -ENOMEM;
1228         }
1229
1230         mutex_init(&hdmi->mutex);
1231
1232         hdmi->dev = &pdev->dev;
1233
1234         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1235         if (IS_ERR(hdmi->hdmi_clk)) {
1236                 ret = PTR_ERR(hdmi->hdmi_clk);
1237                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1238                 goto egetclk;
1239         }
1240
1241         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1242         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1243         if (rate > 0)
1244                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1245
1246         if (rate < 0) {
1247                 ret = rate;
1248                 goto erate;
1249         }
1250
1251         ret = clk_enable(hdmi->hdmi_clk);
1252         if (ret < 0) {
1253                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1254                 goto erate;
1255         }
1256
1257         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1258
1259         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1260                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1261                 ret = -EBUSY;
1262                 goto ereqreg;
1263         }
1264
1265         hdmi->base = ioremap(res->start, resource_size(res));
1266         if (!hdmi->base) {
1267                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1268                 ret = -ENOMEM;
1269                 goto emap;
1270         }
1271
1272         platform_set_drvdata(pdev, hdmi);
1273
1274         /* Set up LCDC callbacks */
1275         board_cfg = &pdata->lcd_chan->board_cfg;
1276         board_cfg->owner = THIS_MODULE;
1277         board_cfg->board_data = hdmi;
1278         board_cfg->display_on = sh_hdmi_display_on;
1279         board_cfg->display_off = sh_hdmi_display_off;
1280
1281         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1282
1283         pm_runtime_enable(&pdev->dev);
1284         pm_runtime_resume(&pdev->dev);
1285
1286         /* Product and revision IDs are 0 in sh-mobile version */
1287         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1288                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1289
1290         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1291                           dev_name(&pdev->dev), hdmi);
1292         if (ret < 0) {
1293                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1294                 goto ereqirq;
1295         }
1296
1297         ret = snd_soc_register_codec(&pdev->dev,
1298                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1299         if (ret < 0) {
1300                 dev_err(&pdev->dev, "codec registration failed\n");
1301                 goto ecodec;
1302         }
1303
1304         return 0;
1305
1306 ecodec:
1307         free_irq(irq, hdmi);
1308 ereqirq:
1309         pm_runtime_disable(&pdev->dev);
1310         iounmap(hdmi->base);
1311 emap:
1312         release_mem_region(res->start, resource_size(res));
1313 ereqreg:
1314         clk_disable(hdmi->hdmi_clk);
1315 erate:
1316         clk_put(hdmi->hdmi_clk);
1317 egetclk:
1318         mutex_destroy(&hdmi->mutex);
1319         kfree(hdmi);
1320
1321         return ret;
1322 }
1323
1324 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1325 {
1326         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1327         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1328         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329         struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1330         int irq = platform_get_irq(pdev, 0);
1331
1332         snd_soc_unregister_codec(&pdev->dev);
1333
1334         board_cfg->display_on = NULL;
1335         board_cfg->display_off = NULL;
1336         board_cfg->board_data = NULL;
1337         board_cfg->owner = NULL;
1338
1339         /* No new work will be scheduled, wait for running ISR */
1340         free_irq(irq, hdmi);
1341         /* Wait for already scheduled work */
1342         cancel_delayed_work_sync(&hdmi->edid_work);
1343         pm_runtime_disable(&pdev->dev);
1344         clk_disable(hdmi->hdmi_clk);
1345         clk_put(hdmi->hdmi_clk);
1346         iounmap(hdmi->base);
1347         release_mem_region(res->start, resource_size(res));
1348         mutex_destroy(&hdmi->mutex);
1349         kfree(hdmi);
1350
1351         return 0;
1352 }
1353
1354 static struct platform_driver sh_hdmi_driver = {
1355         .remove         = __exit_p(sh_hdmi_remove),
1356         .driver = {
1357                 .name   = "sh-mobile-hdmi",
1358         },
1359 };
1360
1361 static int __init sh_hdmi_init(void)
1362 {
1363         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1364 }
1365 module_init(sh_hdmi_init);
1366
1367 static void __exit sh_hdmi_exit(void)
1368 {
1369         platform_driver_unregister(&sh_hdmi_driver);
1370 }
1371 module_exit(sh_hdmi_exit);
1372
1373 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1374 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1375 MODULE_LICENSE("GPL v2");