drivers/video/s1d13xxxfb.c

   1 /* drivers/video/s1d13xxxfb.c
   2  *
   3  * (c) 2004 Simtec Electronics
   4  * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
   5  * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
   6  *
   7  * Driver for Epson S1D13xxx series framebuffer chips
   8  *
   9  * Adapted from
  10  *  linux/drivers/video/skeletonfb.c
  11  *  linux/drivers/video/epson1355fb.c
  12  *  linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
  13  *
  14  * TODO: - handle dual screen display (CRT and LCD at the same time).
  15  *       - check_var(), mode change, etc.
  16  *       - probably not SMP safe :)
  17  *       - support all bitblt operations on all cards
  18  *
  19  * This file is subject to the terms and conditions of the GNU General Public
  20  * License. See the file COPYING in the main directory of this archive for
  21  * more details.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include <linux/mm.h>
  30 #include <linux/mman.h>
  31 #include <linux/fb.h>
  32 #include <linux/spinlock_types.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/slab.h>
  35
  36 #include <asm/io.h>
  37
  38 #include <video/s1d13xxxfb.h>
  39
  40 #define PFX     "s1d13xxxfb: "
  41 #define BLIT    "s1d13xxxfb_bitblt: "
  42
  43 /*
  44  * set this to enable debugging on general functions
  45  */
  46 #if 0
  47 #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
  48 #else
  49 #define dbg(fmt, args...) do { } while (0)
  50 #endif
  51
  52 /*
  53  * set this to enable debugging on 2D acceleration
  54  */
  55 #if 0
  56 #define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
  57 #else
  58 #define dbg_blit(fmt, args...) do { } while (0)
  59 #endif
  60
  61 /*
  62  * we make sure only one bitblt operation is running
  63  */
  64 static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
  65
  66 /*
  67  * list of card production ids
  68  */
  69 static const int s1d13xxxfb_prod_ids[] = {
  70         S1D13505_PROD_ID,
  71         S1D13506_PROD_ID,
  72         S1D13806_PROD_ID,
  73 };
  74
  75 /*
  76  * List of card strings
  77  */
  78 static const char *s1d13xxxfb_prod_names[] = {
  79         "S1D13505",
  80         "S1D13506",
  81         "S1D13806",
  82 };
  83
  84 /*
  85  * here we define the default struct fb_fix_screeninfo
  86  */
  87 static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
  88         .id             = S1D_FBID,
  89         .type           = FB_TYPE_PACKED_PIXELS,
  90         .visual         = FB_VISUAL_PSEUDOCOLOR,
  91         .xpanstep       = 0,
  92         .ypanstep       = 1,
  93         .ywrapstep      = 0,
  94         .accel          = FB_ACCEL_NONE,
  95 };
  96
  97 static inline u8
  98 s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
  99 {
 100 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
 101         regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
 102 #endif
 103         return readb(par->regs + regno);
 104 }
 105
 106 static inline void
 107 s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
 108 {
 109 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
 110         regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
 111 #endif
 112         writeb(value, par->regs + regno);
 113 }
 114
 115 static inline void
 116 s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
 117                         const struct s1d13xxxfb_regval *initregs,
 118                         const unsigned int size)
 119 {
 120         int i;
 121
 122         for (i = 0; i < size; i++) {
 123                 if ((initregs[i].addr == S1DREG_DELAYOFF) ||
 124                                 (initregs[i].addr == S1DREG_DELAYON))
 125                         mdelay((int)initregs[i].value);
 126                 else {
 127                         s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
 128                 }
 129         }
 130
 131         /* make sure the hardware can cope with us */
 132         mdelay(1);
 133 }
 134
 135 static inline void
 136 lcd_enable(struct s1d13xxxfb_par *par, int enable)
 137 {
 138         u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
 139
 140         if (enable)
 141                 mode |= 0x01;
 142         else
 143                 mode &= ~0x01;
 144
 145         s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
 146 }
 147
 148 static inline void
 149 crt_enable(struct s1d13xxxfb_par *par, int enable)
 150 {
 151         u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
 152
 153         if (enable)
 154                 mode |= 0x02;
 155         else
 156                 mode &= ~0x02;
 157
 158         s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
 159 }
 160
 161
 162 /*************************************************************
 163  framebuffer control functions
 164  *************************************************************/
 165 static inline void
 166 s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
 167 {
 168         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 169
 170         info->var.red.length = 4;
 171         info->var.green.length = 4;
 172         info->var.blue.length = 4;
 173 }
 174
 175 static inline void
 176 s1d13xxxfb_setup_truecolour(struct fb_info *info)
 177 {
 178         info->fix.visual = FB_VISUAL_TRUECOLOR;
 179         info->var.bits_per_pixel = 16;
 180
 181         info->var.red.length = 5;
 182         info->var.red.offset = 11;
 183
 184         info->var.green.length = 6;
 185         info->var.green.offset = 5;
 186
 187         info->var.blue.length = 5;
 188         info->var.blue.offset = 0;
 189 }
 190
 191 /**
 192  *      s1d13xxxfb_set_par - Alters the hardware state.
 193  *      @info: frame buffer structure
 194  *
 195  *      Using the fb_var_screeninfo in fb_info we set the depth of the
 196  *      framebuffer. This function alters the par AND the
 197  *      fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
 198  *      fb_info since we are using that data. This means we depend on the
 199  *      data in var inside fb_info to be supported by the hardware.
 200  *      xxxfb_check_var is always called before xxxfb_set_par to ensure this.
 201  *
 202  *      XXX TODO: write proper s1d13xxxfb_check_var(), without which that
 203  *      function is quite useless.
 204  */
 205 static int
 206 s1d13xxxfb_set_par(struct fb_info *info)
 207 {
 208         struct s1d13xxxfb_par *s1dfb = info->par;
 209         unsigned int val;
 210
 211         dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
 212
 213         if ((s1dfb->display & 0x01))    /* LCD */
 214                 val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE);   /* read colour control */
 215         else    /* CRT */
 216                 val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE);   /* read colour control */
 217
 218         val &= ~0x07;
 219
 220         switch (info->var.bits_per_pixel) {
 221                 case 4:
 222                         dbg("pseudo colour 4\n");
 223                         s1d13xxxfb_setup_pseudocolour(info);
 224                         val |= 2;
 225                         break;
 226                 case 8:
 227                         dbg("pseudo colour 8\n");
 228                         s1d13xxxfb_setup_pseudocolour(info);
 229                         val |= 3;
 230                         break;
 231                 case 16:
 232                         dbg("true colour\n");
 233                         s1d13xxxfb_setup_truecolour(info);
 234                         val |= 5;
 235                         break;
 236
 237                 default:
 238                         dbg("bpp not supported!\n");
 239                         return -EINVAL;
 240         }
 241
 242         dbg("writing %02x to display mode register\n", val);
 243
 244         if ((s1dfb->display & 0x01))    /* LCD */
 245                 s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
 246         else    /* CRT */
 247                 s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
 248
 249         info->fix.line_length  = info->var.xres * info->var.bits_per_pixel;
 250         info->fix.line_length /= 8;
 251
 252         dbg("setting line_length to %d\n", info->fix.line_length);
 253
 254         dbg("done setup\n");
 255
 256         return 0;
 257 }
 258
 259 /**
 260  *      s1d13xxxfb_setcolreg - sets a color register.
 261  *      @regno: Which register in the CLUT we are programming
 262  *      @red: The red value which can be up to 16 bits wide
 263  *      @green: The green value which can be up to 16 bits wide
 264  *      @blue:  The blue value which can be up to 16 bits wide.
 265  *      @transp: If supported the alpha value which can be up to 16 bits wide.
 266  *      @info: frame buffer info structure
 267  *
 268  *      Returns negative errno on error, or zero on success.
 269  */
 270 static int
 271 s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 272                         u_int transp, struct fb_info *info)
 273 {
 274         struct s1d13xxxfb_par *s1dfb = info->par;
 275         unsigned int pseudo_val;
 276
 277         if (regno >= S1D_PALETTE_SIZE)
 278                 return -EINVAL;
 279
 280         dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
 281                     regno, red, green, blue, transp);
 282
 283         if (info->var.grayscale)
 284                 red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
 285
 286         switch (info->fix.visual) {
 287                 case FB_VISUAL_TRUECOLOR:
 288                         if (regno >= 16)
 289                                 return -EINVAL;
 290
 291                         /* deal with creating pseudo-palette entries */
 292
 293                         pseudo_val  = (red   >> 11) << info->var.red.offset;
 294                         pseudo_val |= (green >> 10) << info->var.green.offset;
 295                         pseudo_val |= (blue  >> 11) << info->var.blue.offset;
 296
 297                         dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
 298                                     regno, pseudo_val);
 299
 300 #if defined(CONFIG_PLAT_MAPPI)
 301                         ((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val);
 302 #else
 303                         ((u32 *)info->pseudo_palette)[regno] = pseudo_val;
 304 #endif
 305
 306                         break;
 307                 case FB_VISUAL_PSEUDOCOLOR:
 308                         s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
 309                         s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
 310                         s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
 311                         s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
 312
 313                         break;
 314                 default:
 315                         return -ENOSYS;
 316         }
 317
 318         dbg("s1d13xxxfb_setcolreg: done\n");
 319
 320         return 0;
 321 }
 322
 323 /**
 324  *      s1d13xxxfb_blank - blanks the display.
 325  *      @blank_mode: the blank mode we want.
 326  *      @info: frame buffer structure that represents a single frame buffer
 327  *
 328  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 329  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 330  *      video mode which doesn't support it. Implements VESA suspend
 331  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 332  *      blank_mode == 2: suspend vsync
 333  *      blank_mode == 3: suspend hsync
 334  *      blank_mode == 4: powerdown
 335  *
 336  *      Returns negative errno on error, or zero on success.
 337  */
 338 static int
 339 s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
 340 {
 341         struct s1d13xxxfb_par *par = info->par;
 342
 343         dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
 344
 345         switch (blank_mode) {
 346                 case FB_BLANK_UNBLANK:
 347                 case FB_BLANK_NORMAL:
 348                         if ((par->display & 0x01) != 0)
 349                                 lcd_enable(par, 1);
 350                         if ((par->display & 0x02) != 0)
 351                                 crt_enable(par, 1);
 352                         break;
 353                 case FB_BLANK_VSYNC_SUSPEND:
 354                 case FB_BLANK_HSYNC_SUSPEND:
 355                         break;
 356                 case FB_BLANK_POWERDOWN:
 357                         lcd_enable(par, 0);
 358                         crt_enable(par, 0);
 359                         break;
 360                 default:
 361                         return -EINVAL;
 362         }
 363
 364         /* let fbcon do a soft blank for us */
 365         return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
 366 }
 367
 368 /**
 369  *      s1d13xxxfb_pan_display - Pans the display.
 370  *      @var: frame buffer variable screen structure
 371  *      @info: frame buffer structure that represents a single frame buffer
 372  *
 373  *      Pan (or wrap, depending on the `vmode' field) the display using the
 374  *      `yoffset' field of the `var' structure (`xoffset'  not yet supported).
 375  *      If the values don't fit, return -EINVAL.
 376  *
 377  *      Returns negative errno on error, or zero on success.
 378  */
 379 static int
 380 s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 381 {
 382         struct s1d13xxxfb_par *par = info->par;
 383         u32 start;
 384
 385         if (var->xoffset != 0)  /* not yet ... */
 386                 return -EINVAL;
 387
 388         if (var->yoffset + info->var.yres > info->var.yres_virtual)
 389                 return -EINVAL;
 390
 391         start = (info->fix.line_length >> 1) * var->yoffset;
 392
 393         if ((par->display & 0x01)) {
 394                 /* LCD */
 395                 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
 396                 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
 397                 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
 398         } else {
 399                 /* CRT */
 400                 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
 401                 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
 402                 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
 403         }
 404
 405         return 0;
 406 }
 407
 408 /************************************************************
 409  functions to handle bitblt acceleration
 410  ************************************************************/
 411
 412 /**
 413  *      bltbit_wait_bitset - waits for change in register value
 414  *      @info : framebuffer structure
 415  *      @bit  : value expected in register
 416  *      @timeout : ...
 417  *
 418  *      waits until value changes INTO bit
 419  */
 420 static u8
 421 bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout)
 422 {
 423         while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) {
 424                 udelay(10);
 425                 if (!--timeout) {
 426                         dbg_blit("wait_bitset timeout\n");
 427                         break;
 428                 }
 429         }
 430
 431         return timeout;
 432 }
 433
 434 /**
 435  *      bltbit_wait_bitclear - waits for change in register value
 436  *      @info : frambuffer structure
 437  *      @bit  : value currently in register
 438  *      @timeout : ...
 439  *
 440  *      waits until value changes FROM bit
 441  *
 442  */
 443 static u8
 444 bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
 445 {
 446         while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
 447                 udelay(10);
 448                 if (!--timeout) {
 449                         dbg_blit("wait_bitclear timeout\n");
 450                         break;
 451                 }
 452         }
 453
 454         return timeout;
 455 }
 456
 457 /**
 458  *      bltbit_fifo_status - checks the current status of the fifo
 459  *      @info : framebuffer structure
 460  *
 461  *      returns number of free words in buffer
 462  */
 463 static u8
 464 bltbit_fifo_status(struct fb_info *info)
 465 {
 466         u8 status;
 467
 468         status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0);
 469
 470         /* its empty so room for 16 words */
 471         if (status & BBLT_FIFO_EMPTY)
 472                 return 16;
 473
 474         /* its full so we dont want to add */
 475         if (status & BBLT_FIFO_FULL)
 476                 return 0;
 477
 478         /* its atleast half full but we can add one atleast */
 479         if (status & BBLT_FIFO_NOT_FULL)
 480                 return 1;
 481
 482         return 0;
 483 }
 484
 485 /*
 486  *      s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
 487  *      @info : framebuffer structure
 488  *      @area : fb_copyarea structure
 489  *
 490  *      supports (atleast) S1D13506
 491  *
 492  */
 493 static void
 494 s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
 495 {
 496         u32 dst, src;
 497         u32 stride;
 498         u16 reverse = 0;
 499         u16 sx = area->sx, sy = area->sy;
 500         u16 dx = area->dx, dy = area->dy;
 501         u16 width = area->width, height = area->height;
 502         u16 bpp;
 503
 504         spin_lock(&s1d13xxxfb_bitblt_lock);
 505
 506         /* bytes per xres line */
 507         bpp = (info->var.bits_per_pixel >> 3);
 508         stride = bpp * info->var.xres;
 509
 510         /* reverse, calculate the last pixel in rectangle */
 511         if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
 512                 dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
 513                 src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
 514                 reverse = 1;
 515         /* not reverse, calculate the first pixel in rectangle */
 516         } else { /* (y * xres) + (bpp * x) */
 517                 dst = (dy * stride) + (bpp * dx);
 518                 src = (sy * stride) + (bpp * sx);
 519         }
 520
 521         /* set source address */
 522         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
 523         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
 524         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
 525
 526         /* set destination address */
 527         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
 528         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
 529         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
 530
 531         /* program height and width */
 532         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
 533         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
 534
 535         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
 536         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
 537
 538         /* negative direction ROP */
 539         if (reverse == 1) {
 540                 dbg_blit("(copyarea) negative rop\n");
 541                 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
 542         } else /* positive direction ROP */ {
 543                 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
 544                 dbg_blit("(copyarea) positive rop\n");
 545         }
 546
 547         /* set for rectangel mode and not linear */
 548         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
 549
 550         /* setup the bpp 1 = 16bpp, 0 = 8bpp*/
 551         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
 552
 553         /* set words per xres */
 554         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
 555         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
 556
 557         dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
 558         dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
 559         dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
 560         dbg_blit("(copyarea) stride=%d\n", stride);
 561         dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
 562                 (stride >> 1) & 0xff, stride >> 9);
 563
 564         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
 565
 566         /* initialize the engine */
 567         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
 568
 569         /* wait to complete */
 570         bltbit_wait_bitclear(info, 0x80, 8000);
 571
 572         spin_unlock(&s1d13xxxfb_bitblt_lock);
 573 }
 574
 575 /**
 576  *
 577  *      s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
 578  *      @info : framebuffer structure
 579  *      @rect : fb_fillrect structure
 580  *
 581  *      supports (atleast 13506)
 582  *
 583  **/
 584 static void
 585 s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
 586 {
 587         u32 screen_stride, dest;
 588         u32 fg;
 589         u16 bpp = (info->var.bits_per_pixel >> 3);
 590
 591         /* grab spinlock */
 592         spin_lock(&s1d13xxxfb_bitblt_lock);
 593
 594         /* bytes per x width */
 595         screen_stride = (bpp * info->var.xres);
 596
 597         /* bytes to starting point */
 598         dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
 599
 600         dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
 601                  "(solidfill) : rect_width=%d, rect_height=%d\n",
 602                                 rect->dx, rect->dy, screen_stride, dest,
 603                                 rect->width - 1, rect->height - 1);
 604
 605         dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
 606                                 info->var.xres, info->var.yres,
 607                                 info->var.bits_per_pixel);
 608         dbg_blit("(solidfill) : rop=%d\n", rect->rop);
 609
 610         /* We split the destination into the three registers */
 611         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
 612         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
 613         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
 614
 615         /* give information regarding rectangel width */
 616         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
 617         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
 618
 619         /* give information regarding rectangel height */
 620         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
 621         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
 622
 623         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 624                 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 625                 fg = ((u32 *)info->pseudo_palette)[rect->color];
 626                 dbg_blit("(solidfill) truecolor/directcolor\n");
 627                 dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
 628         } else {
 629                 fg = rect->color;
 630                 dbg_blit("(solidfill) color = %d\n", rect->color);
 631         }
 632
 633         /* set foreground color */
 634         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
 635         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
 636
 637         /* set rectangual region of memory (rectangle and not linear) */
 638         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
 639
 640         /* set operation mode SOLID_FILL */
 641         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
 642
 643         /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
 644         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
 645
 646         /* set the memory offset for the bblt in word sizes */
 647         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
 648         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
 649
 650         /* and away we go.... */
 651         s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
 652
 653         /* wait until its done */
 654         bltbit_wait_bitclear(info, 0x80, 8000);
 655
 656         /* let others play */
 657         spin_unlock(&s1d13xxxfb_bitblt_lock);
 658 }
 659
 660 /* framebuffer information structures */
 661 static struct fb_ops s1d13xxxfb_fbops = {
 662         .owner          = THIS_MODULE,
 663         .fb_set_par     = s1d13xxxfb_set_par,
 664         .fb_setcolreg   = s1d13xxxfb_setcolreg,
 665         .fb_blank       = s1d13xxxfb_blank,
 666
 667         .fb_pan_display = s1d13xxxfb_pan_display,
 668
 669         /* gets replaced at chip detection time */
 670         .fb_fillrect    = cfb_fillrect,
 671         .fb_copyarea    = cfb_copyarea,
 672         .fb_imageblit   = cfb_imageblit,
 673 };
 674
 675 static int s1d13xxxfb_width_tab[2][4] __devinitdata = {
 676         {4, 8, 16, -1},
 677         {9, 12, 18, -1},
 678 };
 679
 680 /**
 681  *      s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
 682  *      hardware setup.
 683  *      @info: frame buffer structure
 684  *
 685  *      We setup the framebuffer structures according to the current
 686  *      hardware setup. On some machines, the BIOS will have filled
 687  *      the chip registers with such info, on others, these values will
 688  *      have been written in some init procedure. In any case, the
 689  *      software values needs to match the hardware ones. This is what
 690  *      this function ensures.
 691  *
 692  *      Note: some of the hardcoded values here might need some love to
 693  *      work on various chips, and might need to no longer be hardcoded.
 694  */
 695 static void __devinit
 696 s1d13xxxfb_fetch_hw_state(struct fb_info *info)
 697 {
 698         struct fb_var_screeninfo *var = &info->var;
 699         struct fb_fix_screeninfo *fix = &info->fix;
 700         struct s1d13xxxfb_par *par = info->par;
 701         u8 panel, display;
 702         u16 offset;
 703         u32 xres, yres;
 704         u32 xres_virtual, yres_virtual;
 705         int bpp, lcd_bpp;
 706         int is_color, is_dual, is_tft;
 707         int lcd_enabled, crt_enabled;
 708
 709         fix->type = FB_TYPE_PACKED_PIXELS;
 710
 711         /* general info */
 712         par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
 713         crt_enabled = (par->display & 0x02) != 0;
 714         lcd_enabled = (par->display & 0x01) != 0;
 715
 716         if (lcd_enabled && crt_enabled)
 717                 printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
 718
 719         if (lcd_enabled)
 720                 display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
 721         else    /* CRT */
 722                 display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
 723
 724         bpp = display & 0x07;
 725
 726         switch (bpp) {
 727                 case 2: /* 4 bpp */
 728                 case 3: /* 8 bpp */
 729                         var->bits_per_pixel = 8;
 730                         var->red.offset = var->green.offset = var->blue.offset = 0;
 731                         var->red.length = var->green.length = var->blue.length = 8;
 732                         break;
 733                 case 5: /* 16 bpp */
 734                         s1d13xxxfb_setup_truecolour(info);
 735                         break;
 736                 default:
 737                         dbg("bpp: %i\n", bpp);
 738         }
 739         fb_alloc_cmap(&info->cmap, 256, 0);
 740
 741         /* LCD info */
 742         panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
 743         is_color = (panel & 0x04) != 0;
 744         is_dual = (panel & 0x02) != 0;
 745         is_tft = (panel & 0x01) != 0;
 746         lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
 747
 748         if (lcd_enabled) {
 749                 xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
 750                 yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
 751                         ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
 752
 753                 offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
 754                         ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
 755         } else { /* crt */
 756                 xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
 757                 yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
 758                         ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
 759
 760                 offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
 761                         ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
 762         }
 763         xres_virtual = offset * 16 / var->bits_per_pixel;
 764         yres_virtual = fix->smem_len / (offset * 2);
 765
 766         var->xres               = xres;
 767         var->yres               = yres;
 768         var->xres_virtual       = xres_virtual;
 769         var->yres_virtual       = yres_virtual;
 770         var->xoffset            = var->yoffset = 0;
 771
 772         fix->line_length        = offset * 2;
 773
 774         var->grayscale          = !is_color;
 775
 776         var->activate           = FB_ACTIVATE_NOW;
 777
 778         dbg(PFX "bpp=%d, lcd_bpp=%d, "
 779                 "crt_enabled=%d, lcd_enabled=%d\n",
 780                 var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
 781         dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
 782                 "is_color=%d, is_dual=%d, is_tft=%d\n",
 783                 xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
 784 }
 785
 786
 787 static int
 788 s1d13xxxfb_remove(struct platform_device *pdev)
 789 {
 790         struct fb_info *info = platform_get_drvdata(pdev);
 791         struct s1d13xxxfb_par *par = NULL;
 792
 793         if (info) {
 794                 par = info->par;
 795                 if (par && par->regs) {
 796                         /* disable output & enable powersave */
 797                         s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
 798                         s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
 799                         iounmap(par->regs);
 800                 }
 801
 802                 fb_dealloc_cmap(&info->cmap);
 803
 804                 if (info->screen_base)
 805                         iounmap(info->screen_base);
 806
 807                 framebuffer_release(info);
 808         }
 809
 810         release_mem_region(pdev->resource[0].start,
 811                         pdev->resource[0].end - pdev->resource[0].start +1);
 812         release_mem_region(pdev->resource[1].start,
 813                         pdev->resource[1].end - pdev->resource[1].start +1);
 814         return 0;
 815 }
 816
 817 static int __devinit
 818 s1d13xxxfb_probe(struct platform_device *pdev)
 819 {
 820         struct s1d13xxxfb_par *default_par;
 821         struct fb_info *info;
 822         struct s1d13xxxfb_pdata *pdata = NULL;
 823         int ret = 0;
 824         int i;
 825         u8 revision, prod_id;
 826
 827         dbg("probe called: device is %p\n", pdev);
 828
 829         printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
 830
 831         /* enable platform-dependent hardware glue, if any */
 832         if (pdev->dev.platform_data)
 833                 pdata = pdev->dev.platform_data;
 834
 835         if (pdata && pdata->platform_init_video)
 836                 pdata->platform_init_video();
 837
 838         if (pdev->num_resources != 2) {
 839                 dev_err(&pdev->dev, "invalid num_resources: %i\n",
 840                        pdev->num_resources);
 841                 ret = -ENODEV;
 842                 goto bail;
 843         }
 844
 845         /* resource[0] is VRAM, resource[1] is registers */
 846         if (pdev->resource[0].flags != IORESOURCE_MEM
 847                         || pdev->resource[1].flags != IORESOURCE_MEM) {
 848                 dev_err(&pdev->dev, "invalid resource type\n");
 849                 ret = -ENODEV;
 850                 goto bail;
 851         }
 852
 853         if (!request_mem_region(pdev->resource[0].start,
 854                 pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) {
 855                 dev_dbg(&pdev->dev, "request_mem_region failed\n");
 856                 ret = -EBUSY;
 857                 goto bail;
 858         }
 859
 860         if (!request_mem_region(pdev->resource[1].start,
 861                 pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) {
 862                 dev_dbg(&pdev->dev, "request_mem_region failed\n");
 863                 ret = -EBUSY;
 864                 goto bail;
 865         }
 866
 867         info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
 868         if (!info) {
 869                 ret = -ENOMEM;
 870                 goto bail;
 871         }
 872
 873         platform_set_drvdata(pdev, info);
 874         default_par = info->par;
 875         default_par->regs = ioremap_nocache(pdev->resource[1].start,
 876                         pdev->resource[1].end - pdev->resource[1].start +1);
 877         if (!default_par->regs) {
 878                 printk(KERN_ERR PFX "unable to map registers\n");
 879                 ret = -ENOMEM;
 880                 goto bail;
 881         }
 882         info->pseudo_palette = default_par->pseudo_palette;
 883
 884         info->screen_base = ioremap_nocache(pdev->resource[0].start,
 885                         pdev->resource[0].end - pdev->resource[0].start +1);
 886
 887         if (!info->screen_base) {
 888                 printk(KERN_ERR PFX "unable to map framebuffer\n");
 889                 ret = -ENOMEM;
 890                 goto bail;
 891         }
 892
 893         /* production id is top 6 bits */
 894         prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
 895         /* revision id is lower 2 bits */
 896         revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;
 897         ret = -ENODEV;
 898
 899         for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) {
 900                 if (prod_id == s1d13xxxfb_prod_ids[i]) {
 901                         /* looks like we got it in our list */
 902                         default_par->prod_id = prod_id;
 903                         default_par->revision = revision;
 904                         ret = 0;
 905                         break;
 906                 }
 907         }
 908
 909         if (!ret) {
 910                 printk(KERN_INFO PFX "chip production id %i = %s\n",
 911                         prod_id, s1d13xxxfb_prod_names[i]);
 912                 printk(KERN_INFO PFX "chip revision %i\n", revision);
 913         } else {
 914                 printk(KERN_INFO PFX
 915                         "unknown chip production id %i, revision %i\n",
 916                         prod_id, revision);
 917                 printk(KERN_INFO PFX "please contant maintainer\n");
 918                 goto bail;
 919         }
 920
 921         info->fix = s1d13xxxfb_fix;
 922         info->fix.mmio_start = pdev->resource[1].start;
 923         info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start + 1;
 924         info->fix.smem_start = pdev->resource[0].start;
 925         info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start + 1;
 926
 927         printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
 928                default_par->regs, info->fix.smem_len / 1024, info->screen_base);
 929
 930         info->par = default_par;
 931         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
 932         info->fbops = &s1d13xxxfb_fbops;
 933
 934         switch(prod_id) {
 935         case S1D13506_PROD_ID:  /* activate acceleration */
 936                 s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
 937                 s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
 938                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
 939                         FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         /* perform "manual" chip initialization, if needed */
 946         if (pdata && pdata->initregs)
 947                 s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
 948
 949         s1d13xxxfb_fetch_hw_state(info);
 950
 951         if (register_framebuffer(info) < 0) {
 952                 ret = -EINVAL;
 953                 goto bail;
 954         }
 955
 956         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 957                info->node, info->fix.id);
 958
 959         return 0;
 960
 961 bail:
 962         s1d13xxxfb_remove(pdev);
 963         return ret;
 964
 965 }
 966
 967 #ifdef CONFIG_PM
 968 static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
 969 {
 970         struct fb_info *info = platform_get_drvdata(dev);
 971         struct s1d13xxxfb_par *s1dfb = info->par;
 972         struct s1d13xxxfb_pdata *pdata = NULL;
 973
 974         /* disable display */
 975         lcd_enable(s1dfb, 0);
 976         crt_enable(s1dfb, 0);
 977
 978         if (dev->dev.platform_data)
 979                 pdata = dev->dev.platform_data;
 980
 981 #if 0
 982         if (!s1dfb->disp_save)
 983                 s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
 984
 985         if (!s1dfb->disp_save) {
 986                 printk(KERN_ERR PFX "no memory to save screen");
 987                 return -ENOMEM;
 988         }
 989
 990         memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
 991 #else
 992         s1dfb->disp_save = NULL;
 993 #endif
 994
 995         if (!s1dfb->regs_save)
 996                 s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
 997
 998         if (!s1dfb->regs_save) {
 999                 printk(KERN_ERR PFX "no memory to save registers");
1000                 return -ENOMEM;
1001         }
1002
1003         /* backup all registers */
1004         memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
1005
1006         /* now activate power save mode */
1007         s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
1008
1009         if (pdata && pdata->platform_suspend_video)
1010                 return pdata->platform_suspend_video();
1011         else
1012                 return 0;
1013 }
1014
1015 static int s1d13xxxfb_resume(struct platform_device *dev)
1016 {
1017         struct fb_info *info = platform_get_drvdata(dev);
1018         struct s1d13xxxfb_par *s1dfb = info->par;
1019         struct s1d13xxxfb_pdata *pdata = NULL;
1020
1021         /* awaken the chip */
1022         s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
1023
1024         /* do not let go until SDRAM "wakes up" */
1025         while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
1026                 udelay(10);
1027
1028         if (dev->dev.platform_data)
1029                 pdata = dev->dev.platform_data;
1030
1031         if (s1dfb->regs_save) {
1032                 /* will write RO regs, *should* get away with it :) */
1033                 memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
1034                 kfree(s1dfb->regs_save);
1035         }
1036
1037         if (s1dfb->disp_save) {
1038                 memcpy_toio(info->screen_base, s1dfb->disp_save,
1039                                 info->fix.smem_len);
1040                 kfree(s1dfb->disp_save);        /* XXX kmalloc()'d when? */
1041         }
1042
1043         if ((s1dfb->display & 0x01) != 0)
1044                 lcd_enable(s1dfb, 1);
1045         if ((s1dfb->display & 0x02) != 0)
1046                 crt_enable(s1dfb, 1);
1047
1048         if (pdata && pdata->platform_resume_video)
1049                 return pdata->platform_resume_video();
1050         else
1051                 return 0;
1052 }
1053 #endif /* CONFIG_PM */
1054
1055 static struct platform_driver s1d13xxxfb_driver = {
1056         .probe          = s1d13xxxfb_probe,
1057         .remove         = s1d13xxxfb_remove,
1058 #ifdef CONFIG_PM
1059         .suspend        = s1d13xxxfb_suspend,
1060         .resume         = s1d13xxxfb_resume,
1061 #endif
1062         .driver         = {
1063                 .name   = S1D_DEVICENAME,
1064         },
1065 };
1066
1067
1068 static int __init
1069 s1d13xxxfb_init(void)
1070 {
1071
1072 #ifndef MODULE
1073         if (fb_get_options("s1d13xxxfb", NULL))
1074                 return -ENODEV;
1075 #endif
1076
1077         return platform_driver_register(&s1d13xxxfb_driver);
1078 }
1079
1080
1081 static void __exit
1082 s1d13xxxfb_exit(void)
1083 {
1084         platform_driver_unregister(&s1d13xxxfb_driver);
1085 }
1086
1087 module_init(s1d13xxxfb_init);
1088 module_exit(s1d13xxxfb_exit);
1089
1090
1091 MODULE_LICENSE("GPL");
1092 MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
1093 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");