drivers/video/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/kernel.h>
  28 #include <linux/sched.h>
  29 #include <linux/errno.h>
  30 #include <linux/string.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/slab.h>
  33 #include <linux/fb.h>
  34 #include <linux/delay.h>
  35 #include <linux/init.h>
  36 #include <linux/ioport.h>
  37 #include <linux/cpufreq.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40
  41 #include <asm/hardware.h>
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/div64.h>
  46 #include <asm/arch/pxa-regs.h>
  47 #include <asm/arch/bitfield.h>
  48 #include <asm/arch/pxafb.h>
  49
  50 /*
  51  * Complain if VAR is out of range.
  52  */
  53 #define DEBUG_VAR 1
  54
  55 #include "pxafb.h"
  56
  57 /* Bits which should not be set in machine configuration structures */
  58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
  59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
  60
  61 static void (*pxafb_backlight_power)(int);
  62 static void (*pxafb_lcd_power)(int);
  63
  64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
  65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  66
  67 #ifdef CONFIG_FB_PXA_PARAMETERS
  68 #define PXAFB_OPTIONS_SIZE 256
  69 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
  70 #endif
  71
  72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  73 {
  74         unsigned long flags;
  75
  76         local_irq_save(flags);
  77         /*
  78          * We need to handle two requests being made at the same time.
  79          * There are two important cases:
  80          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  81          *     We must perform the unblanking, which will do our REENABLE for us.
  82          *  2. When we are blanking, but immediately unblank before we have
  83          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
  84          */
  85         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  86                 state = (u_int) -1;
  87         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  88                 state = C_REENABLE;
  89
  90         if (state != (u_int)-1) {
  91                 fbi->task_state = state;
  92                 schedule_work(&fbi->task);
  93         }
  94         local_irq_restore(flags);
  95 }
  96
  97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  98 {
  99         chan &= 0xffff;
 100         chan >>= 16 - bf->length;
 101         return chan << bf->offset;
 102 }
 103
 104 static int
 105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 106                        u_int trans, struct fb_info *info)
 107 {
 108         struct pxafb_info *fbi = (struct pxafb_info *)info;
 109         u_int val, ret = 1;
 110
 111         if (regno < fbi->palette_size) {
 112                 if (fbi->fb.var.grayscale) {
 113                         val = ((blue >> 8) & 0x00ff);
 114                 } else {
 115                         val  = ((red   >>  0) & 0xf800);
 116                         val |= ((green >>  5) & 0x07e0);
 117                         val |= ((blue  >> 11) & 0x001f);
 118                 }
 119                 fbi->palette_cpu[regno] = val;
 120                 ret = 0;
 121         }
 122         return ret;
 123 }
 124
 125 static int
 126 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 127                    u_int trans, struct fb_info *info)
 128 {
 129         struct pxafb_info *fbi = (struct pxafb_info *)info;
 130         unsigned int val;
 131         int ret = 1;
 132
 133         /*
 134          * If inverse mode was selected, invert all the colours
 135          * rather than the register number.  The register number
 136          * is what you poke into the framebuffer to produce the
 137          * colour you requested.
 138          */
 139         if (fbi->cmap_inverse) {
 140                 red   = 0xffff - red;
 141                 green = 0xffff - green;
 142                 blue  = 0xffff - blue;
 143         }
 144
 145         /*
 146          * If greyscale is true, then we convert the RGB value
 147          * to greyscale no matter what visual we are using.
 148          */
 149         if (fbi->fb.var.grayscale)
 150                 red = green = blue = (19595 * red + 38470 * green +
 151                                         7471 * blue) >> 16;
 152
 153         switch (fbi->fb.fix.visual) {
 154         case FB_VISUAL_TRUECOLOR:
 155                 /*
 156                  * 16-bit True Colour.  We encode the RGB value
 157                  * according to the RGB bitfield information.
 158                  */
 159                 if (regno < 16) {
 160                         u32 *pal = fbi->fb.pseudo_palette;
 161
 162                         val  = chan_to_field(red, &fbi->fb.var.red);
 163                         val |= chan_to_field(green, &fbi->fb.var.green);
 164                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 165
 166                         pal[regno] = val;
 167                         ret = 0;
 168                 }
 169                 break;
 170
 171         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 172         case FB_VISUAL_PSEUDOCOLOR:
 173                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 174                 break;
 175         }
 176
 177         return ret;
 178 }
 179
 180 /*
 181  *  pxafb_bpp_to_lccr3():
 182  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 183  */
 184 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
 185 {
 186         int ret = 0;
 187         switch (var->bits_per_pixel) {
 188         case 1:  ret = LCCR3_1BPP; break;
 189         case 2:  ret = LCCR3_2BPP; break;
 190         case 4:  ret = LCCR3_4BPP; break;
 191         case 8:  ret = LCCR3_8BPP; break;
 192         case 16: ret = LCCR3_16BPP; break;
 193         }
 194         return ret;
 195 }
 196
 197 #ifdef CONFIG_CPU_FREQ
 198 /*
 199  *  pxafb_display_dma_period()
 200  *    Calculate the minimum period (in picoseconds) between two DMA
 201  *    requests for the LCD controller.  If we hit this, it means we're
 202  *    doing nothing but LCD DMA.
 203  */
 204 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 205 {
 206        /*
 207         * Period = pixclock * bits_per_byte * bytes_per_transfer
 208         *              / memory_bits_per_pixel;
 209         */
 210        return var->pixclock * 8 * 16 / var->bits_per_pixel;
 211 }
 212
 213 extern unsigned int get_clk_frequency_khz(int info);
 214 #endif
 215
 216 /*
 217  *  pxafb_check_var():
 218  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 219  *    if it's too big, return -EINVAL.
 220  *
 221  *    Round up in the following order: bits_per_pixel, xres,
 222  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 223  *    bitfields, horizontal timing, vertical timing.
 224  */
 225 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 226 {
 227         struct pxafb_info *fbi = (struct pxafb_info *)info;
 228
 229         if (var->xres < MIN_XRES)
 230                 var->xres = MIN_XRES;
 231         if (var->yres < MIN_YRES)
 232                 var->yres = MIN_YRES;
 233         if (var->xres > fbi->max_xres)
 234                 return -EINVAL;
 235         if (var->yres > fbi->max_yres)
 236                 return -EINVAL;
 237         var->xres_virtual =
 238                 max(var->xres_virtual, var->xres);
 239         var->yres_virtual =
 240                 max(var->yres_virtual, var->yres);
 241
 242         /*
 243          * Setup the RGB parameters for this display.
 244          *
 245          * The pixel packing format is described on page 7-11 of the
 246          * PXA2XX Developer's Manual.
 247          */
 248         if (var->bits_per_pixel == 16) {
 249                 var->red.offset   = 11; var->red.length   = 5;
 250                 var->green.offset = 5;  var->green.length = 6;
 251                 var->blue.offset  = 0;  var->blue.length  = 5;
 252                 var->transp.offset = var->transp.length = 0;
 253         } else {
 254                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
 255                 var->red.length   = 8;
 256                 var->green.length = 8;
 257                 var->blue.length  = 8;
 258                 var->transp.length = 0;
 259         }
 260
 261 #ifdef CONFIG_CPU_FREQ
 262         pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
 263                  pxafb_display_dma_period(var),
 264                  get_clk_frequency_khz(0));
 265 #endif
 266
 267         return 0;
 268 }
 269
 270 static inline void pxafb_set_truecolor(u_int is_true_color)
 271 {
 272         pr_debug("pxafb: true_color = %d\n", is_true_color);
 273         // do your machine-specific setup if needed
 274 }
 275
 276 /*
 277  * pxafb_set_par():
 278  *      Set the user defined part of the display for the specified console
 279  */
 280 static int pxafb_set_par(struct fb_info *info)
 281 {
 282         struct pxafb_info *fbi = (struct pxafb_info *)info;
 283         struct fb_var_screeninfo *var = &info->var;
 284         unsigned long palette_mem_size;
 285
 286         pr_debug("pxafb: set_par\n");
 287
 288         if (var->bits_per_pixel == 16)
 289                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 290         else if (!fbi->cmap_static)
 291                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 292         else {
 293                 /*
 294                  * Some people have weird ideas about wanting static
 295                  * pseudocolor maps.  I suspect their user space
 296                  * applications are broken.
 297                  */
 298                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 299         }
 300
 301         fbi->fb.fix.line_length = var->xres_virtual *
 302                                   var->bits_per_pixel / 8;
 303         if (var->bits_per_pixel == 16)
 304                 fbi->palette_size = 0;
 305         else
 306                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
 307
 308         palette_mem_size = fbi->palette_size * sizeof(u16);
 309
 310         pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
 311
 312         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
 313         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
 314
 315         /*
 316          * Set (any) board control register to handle new color depth
 317          */
 318         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
 319
 320         if (fbi->fb.var.bits_per_pixel == 16)
 321                 fb_dealloc_cmap(&fbi->fb.cmap);
 322         else
 323                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 324
 325         pxafb_activate_var(var, fbi);
 326
 327         return 0;
 328 }
 329
 330 /*
 331  * Formal definition of the VESA spec:
 332  *  On
 333  *      This refers to the state of the display when it is in full operation
 334  *  Stand-By
 335  *      This defines an optional operating state of minimal power reduction with
 336  *      the shortest recovery time
 337  *  Suspend
 338  *      This refers to a level of power management in which substantial power
 339  *      reduction is achieved by the display.  The display can have a longer
 340  *      recovery time from this state than from the Stand-by state
 341  *  Off
 342  *      This indicates that the display is consuming the lowest level of power
 343  *      and is non-operational. Recovery from this state may optionally require
 344  *      the user to manually power on the monitor
 345  *
 346  *  Now, the fbdev driver adds an additional state, (blank), where they
 347  *  turn off the video (maybe by colormap tricks), but don't mess with the
 348  *  video itself: think of it semantically between on and Stand-By.
 349  *
 350  *  So here's what we should do in our fbdev blank routine:
 351  *
 352  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
 353  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
 354  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
 355  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
 356  *
 357  *  This will match the matrox implementation.
 358  */
 359
 360 /*
 361  * pxafb_blank():
 362  *      Blank the display by setting all palette values to zero.  Note, the
 363  *      16 bpp mode does not really use the palette, so this will not
 364  *      blank the display in all modes.
 365  */
 366 static int pxafb_blank(int blank, struct fb_info *info)
 367 {
 368         struct pxafb_info *fbi = (struct pxafb_info *)info;
 369         int i;
 370
 371         pr_debug("pxafb: blank=%d\n", blank);
 372
 373         switch (blank) {
 374         case FB_BLANK_POWERDOWN:
 375         case FB_BLANK_VSYNC_SUSPEND:
 376         case FB_BLANK_HSYNC_SUSPEND:
 377         case FB_BLANK_NORMAL:
 378                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 379                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 380                         for (i = 0; i < fbi->palette_size; i++)
 381                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 382
 383                 pxafb_schedule_work(fbi, C_DISABLE);
 384                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 385                 break;
 386
 387         case FB_BLANK_UNBLANK:
 388                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 389                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 390                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 391                         fb_set_cmap(&fbi->fb.cmap, info);
 392                 pxafb_schedule_work(fbi, C_ENABLE);
 393         }
 394         return 0;
 395 }
 396
 397 static int pxafb_mmap(struct fb_info *info,
 398                       struct vm_area_struct *vma)
 399 {
 400         struct pxafb_info *fbi = (struct pxafb_info *)info;
 401         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
 402
 403         if (off < info->fix.smem_len) {
 404                 vma->vm_pgoff += 1;
 405                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
 406                                              fbi->map_dma, fbi->map_size);
 407         }
 408         return -EINVAL;
 409 }
 410
 411 static struct fb_ops pxafb_ops = {
 412         .owner          = THIS_MODULE,
 413         .fb_check_var   = pxafb_check_var,
 414         .fb_set_par     = pxafb_set_par,
 415         .fb_setcolreg   = pxafb_setcolreg,
 416         .fb_fillrect    = cfb_fillrect,
 417         .fb_copyarea    = cfb_copyarea,
 418         .fb_imageblit   = cfb_imageblit,
 419         .fb_blank       = pxafb_blank,
 420         .fb_mmap        = pxafb_mmap,
 421 };
 422
 423 /*
 424  * Calculate the PCD value from the clock rate (in picoseconds).
 425  * We take account of the PPCR clock setting.
 426  * From PXA Developer's Manual:
 427  *
 428  *   PixelClock =      LCLK
 429  *                -------------
 430  *                2 ( PCD + 1 )
 431  *
 432  *   PCD =      LCLK
 433  *         ------------- - 1
 434  *         2(PixelClock)
 435  *
 436  * Where:
 437  *   LCLK = LCD/Memory Clock
 438  *   PCD = LCCR3[7:0]
 439  *
 440  * PixelClock here is in Hz while the pixclock argument given is the
 441  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 442  *
 443  * The function get_lclk_frequency_10khz returns LCLK in units of
 444  * 10khz. Calling the result of this function lclk gives us the
 445  * following
 446  *
 447  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 448  *          -------------------------------------- - 1
 449  *                          2
 450  *
 451  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 452  */
 453 static inline unsigned int get_pcd(unsigned int pixclock)
 454 {
 455         unsigned long long pcd;
 456
 457         /* FIXME: Need to take into account Double Pixel Clock mode
 458          * (DPC) bit? or perhaps set it based on the various clock
 459          * speeds */
 460
 461         pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
 462         do_div(pcd, 100000000 * 2);
 463         /* no need for this, since we should subtract 1 anyway. they cancel */
 464         /* pcd += 1; */ /* make up for integer math truncations */
 465         return (unsigned int)pcd;
 466 }
 467
 468 /*
 469  * Some touchscreens need hsync information from the video driver to
 470  * function correctly. We export it here.
 471  */
 472 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
 473 {
 474         unsigned long long htime;
 475
 476         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
 477                 fbi->hsync_time=0;
 478                 return;
 479         }
 480
 481         htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
 482         do_div(htime, pcd * fbi->fb.var.hsync_len);
 483         fbi->hsync_time = htime;
 484 }
 485
 486 unsigned long pxafb_get_hsync_time(struct device *dev)
 487 {
 488         struct pxafb_info *fbi = dev_get_drvdata(dev);
 489
 490         /* If display is blanked/suspended, hsync isn't active */
 491         if (!fbi || (fbi->state != C_ENABLE))
 492                 return 0;
 493
 494         return fbi->hsync_time;
 495 }
 496 EXPORT_SYMBOL(pxafb_get_hsync_time);
 497
 498 /*
 499  * pxafb_activate_var():
 500  *      Configures LCD Controller based on entries in var parameter.  Settings are
 501  *      only written to the controller if changes were made.
 502  */
 503 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
 504 {
 505         struct pxafb_lcd_reg new_regs;
 506         u_long flags;
 507         u_int lines_per_panel, pcd = get_pcd(var->pixclock);
 508
 509         pr_debug("pxafb: Configuring PXA LCD\n");
 510
 511         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
 512                  var->xres, var->hsync_len,
 513                  var->left_margin, var->right_margin);
 514         pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
 515                  var->yres, var->vsync_len,
 516                  var->upper_margin, var->lower_margin);
 517         pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
 518
 519 #if DEBUG_VAR
 520         if (var->xres < 16        || var->xres > 1024)
 521                 printk(KERN_ERR "%s: invalid xres %d\n",
 522                         fbi->fb.fix.id, var->xres);
 523         switch(var->bits_per_pixel) {
 524         case 1:
 525         case 2:
 526         case 4:
 527         case 8:
 528         case 16:
 529                 break;
 530         default:
 531                 printk(KERN_ERR "%s: invalid bit depth %d\n",
 532                        fbi->fb.fix.id, var->bits_per_pixel);
 533                 break;
 534         }
 535         if (var->hsync_len < 1    || var->hsync_len > 64)
 536                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
 537                         fbi->fb.fix.id, var->hsync_len);
 538         if (var->left_margin < 1  || var->left_margin > 255)
 539                 printk(KERN_ERR "%s: invalid left_margin %d\n",
 540                         fbi->fb.fix.id, var->left_margin);
 541         if (var->right_margin < 1 || var->right_margin > 255)
 542                 printk(KERN_ERR "%s: invalid right_margin %d\n",
 543                         fbi->fb.fix.id, var->right_margin);
 544         if (var->yres < 1         || var->yres > 1024)
 545                 printk(KERN_ERR "%s: invalid yres %d\n",
 546                         fbi->fb.fix.id, var->yres);
 547         if (var->vsync_len < 1    || var->vsync_len > 64)
 548                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
 549                         fbi->fb.fix.id, var->vsync_len);
 550         if (var->upper_margin < 0 || var->upper_margin > 255)
 551                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
 552                         fbi->fb.fix.id, var->upper_margin);
 553         if (var->lower_margin < 0 || var->lower_margin > 255)
 554                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
 555                         fbi->fb.fix.id, var->lower_margin);
 556 #endif
 557
 558         new_regs.lccr0 = fbi->lccr0 |
 559                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
 560                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 561
 562         new_regs.lccr1 =
 563                 LCCR1_DisWdth(var->xres) +
 564                 LCCR1_HorSnchWdth(var->hsync_len) +
 565                 LCCR1_BegLnDel(var->left_margin) +
 566                 LCCR1_EndLnDel(var->right_margin);
 567
 568         /*
 569          * If we have a dual scan LCD, we need to halve
 570          * the YRES parameter.
 571          */
 572         lines_per_panel = var->yres;
 573         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
 574                 lines_per_panel /= 2;
 575
 576         new_regs.lccr2 =
 577                 LCCR2_DisHght(lines_per_panel) +
 578                 LCCR2_VrtSnchWdth(var->vsync_len) +
 579                 LCCR2_BegFrmDel(var->upper_margin) +
 580                 LCCR2_EndFrmDel(var->lower_margin);
 581
 582         new_regs.lccr3 = fbi->lccr3 |
 583                 pxafb_bpp_to_lccr3(var) |
 584                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
 585                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
 586
 587         if (pcd)
 588                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
 589
 590         pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
 591         pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
 592         pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
 593         pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
 594
 595         /* Update shadow copy atomically */
 596         local_irq_save(flags);
 597
 598         /* setup dma descriptors */
 599         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
 600         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
 601         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
 602
 603         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
 604         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
 605         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
 606
 607 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
 608
 609         /* populate descriptors */
 610         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
 611         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
 612         fbi->dmadesc_fblow_cpu->fidr  = 0;
 613         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
 614
 615         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
 616
 617         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
 618         fbi->dmadesc_fbhigh_cpu->fidr = 0;
 619         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
 620
 621         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
 622         fbi->dmadesc_palette_cpu->fidr  = 0;
 623         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 624
 625         if (var->bits_per_pixel == 16) {
 626                 /* palette shouldn't be loaded in true-color mode */
 627                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 628                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
 629                 /* init it to something, even though we won't be using it */
 630                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
 631         } else {
 632                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 633                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
 634                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
 635         }
 636
 637 #if 0
 638         pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
 639         pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
 640         pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
 641         pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
 642         pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
 643         pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
 644
 645         pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
 646         pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
 647         pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
 648
 649         pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
 650         pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
 651         pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
 652
 653         pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
 654         pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
 655         pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
 656 #endif
 657
 658         fbi->reg_lccr0 = new_regs.lccr0;
 659         fbi->reg_lccr1 = new_regs.lccr1;
 660         fbi->reg_lccr2 = new_regs.lccr2;
 661         fbi->reg_lccr3 = new_regs.lccr3;
 662         set_hsync_time(fbi, pcd);
 663         local_irq_restore(flags);
 664
 665         /*
 666          * Only update the registers if the controller is enabled
 667          * and something has changed.
 668          */
 669         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
 670             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
 671             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
 672                 pxafb_schedule_work(fbi, C_REENABLE);
 673
 674         return 0;
 675 }
 676
 677 /*
 678  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
 679  * Do not call them directly; set_ctrlr_state does the correct serialisation
 680  * to ensure that things happen in the right way 100% of time time.
 681  *      -- rmk
 682  */
 683 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
 684 {
 685         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
 686
 687         if (pxafb_backlight_power)
 688                 pxafb_backlight_power(on);
 689 }
 690
 691 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
 692 {
 693         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
 694
 695         if (pxafb_lcd_power)
 696                 pxafb_lcd_power(on);
 697 }
 698
 699 static void pxafb_setup_gpio(struct pxafb_info *fbi)
 700 {
 701         int gpio, ldd_bits;
 702         unsigned int lccr0 = fbi->lccr0;
 703
 704         /*
 705          * setup is based on type of panel supported
 706         */
 707
 708         /* 4 bit interface */
 709         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 710             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
 711             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
 712                 ldd_bits = 4;
 713
 714         /* 8 bit interface */
 715         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 716                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
 717                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 718                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
 719                 ldd_bits = 8;
 720
 721         /* 16 bit interface */
 722         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 723                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
 724                 ldd_bits = 16;
 725
 726         else {
 727                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
 728                 return;
 729         }
 730
 731         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
 732                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
 733         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
 734         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
 735         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
 736         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
 737 }
 738
 739 static void pxafb_enable_controller(struct pxafb_info *fbi)
 740 {
 741         pr_debug("pxafb: Enabling LCD controller\n");
 742         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
 743         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
 744         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
 745         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
 746         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
 747         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
 748
 749         /* enable LCD controller clock */
 750         pxa_set_cken(CKEN16_LCD, 1);
 751
 752         /* Sequence from 11.7.10 */
 753         LCCR3 = fbi->reg_lccr3;
 754         LCCR2 = fbi->reg_lccr2;
 755         LCCR1 = fbi->reg_lccr1;
 756         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
 757
 758         FDADR0 = fbi->fdadr0;
 759         FDADR1 = fbi->fdadr1;
 760         LCCR0 |= LCCR0_ENB;
 761
 762         pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
 763         pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
 764         pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
 765         pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
 766         pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
 767         pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
 768 }
 769
 770 static void pxafb_disable_controller(struct pxafb_info *fbi)
 771 {
 772         DECLARE_WAITQUEUE(wait, current);
 773
 774         pr_debug("pxafb: disabling LCD controller\n");
 775
 776         set_current_state(TASK_UNINTERRUPTIBLE);
 777         add_wait_queue(&fbi->ctrlr_wait, &wait);
 778
 779         LCSR = 0xffffffff;      /* Clear LCD Status Register */
 780         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 781         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 782
 783         schedule_timeout(200 * HZ / 1000);
 784         remove_wait_queue(&fbi->ctrlr_wait, &wait);
 785
 786         /* disable LCD controller clock */
 787         pxa_set_cken(CKEN16_LCD, 0);
 788 }
 789
 790 /*
 791  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
 792  */
 793 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
 794 {
 795         struct pxafb_info *fbi = dev_id;
 796         unsigned int lcsr = LCSR;
 797
 798         if (lcsr & LCSR_LDD) {
 799                 LCCR0 |= LCCR0_LDM;
 800                 wake_up(&fbi->ctrlr_wait);
 801         }
 802
 803         LCSR = lcsr;
 804         return IRQ_HANDLED;
 805 }
 806
 807 /*
 808  * This function must be called from task context only, since it will
 809  * sleep when disabling the LCD controller, or if we get two contending
 810  * processes trying to alter state.
 811  */
 812 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
 813 {
 814         u_int old_state;
 815
 816         down(&fbi->ctrlr_sem);
 817
 818         old_state = fbi->state;
 819
 820         /*
 821          * Hack around fbcon initialisation.
 822          */
 823         if (old_state == C_STARTUP && state == C_REENABLE)
 824                 state = C_ENABLE;
 825
 826         switch (state) {
 827         case C_DISABLE_CLKCHANGE:
 828                 /*
 829                  * Disable controller for clock change.  If the
 830                  * controller is already disabled, then do nothing.
 831                  */
 832                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
 833                         fbi->state = state;
 834                         //TODO __pxafb_lcd_power(fbi, 0);
 835                         pxafb_disable_controller(fbi);
 836                 }
 837                 break;
 838
 839         case C_DISABLE_PM:
 840         case C_DISABLE:
 841                 /*
 842                  * Disable controller
 843                  */
 844                 if (old_state != C_DISABLE) {
 845                         fbi->state = state;
 846                         __pxafb_backlight_power(fbi, 0);
 847                         __pxafb_lcd_power(fbi, 0);
 848                         if (old_state != C_DISABLE_CLKCHANGE)
 849                                 pxafb_disable_controller(fbi);
 850                 }
 851                 break;
 852
 853         case C_ENABLE_CLKCHANGE:
 854                 /*
 855                  * Enable the controller after clock change.  Only
 856                  * do this if we were disabled for the clock change.
 857                  */
 858                 if (old_state == C_DISABLE_CLKCHANGE) {
 859                         fbi->state = C_ENABLE;
 860                         pxafb_enable_controller(fbi);
 861                         //TODO __pxafb_lcd_power(fbi, 1);
 862                 }
 863                 break;
 864
 865         case C_REENABLE:
 866                 /*
 867                  * Re-enable the controller only if it was already
 868                  * enabled.  This is so we reprogram the control
 869                  * registers.
 870                  */
 871                 if (old_state == C_ENABLE) {
 872                         pxafb_disable_controller(fbi);
 873                         pxafb_setup_gpio(fbi);
 874                         pxafb_enable_controller(fbi);
 875                 }
 876                 break;
 877
 878         case C_ENABLE_PM:
 879                 /*
 880                  * Re-enable the controller after PM.  This is not
 881                  * perfect - think about the case where we were doing
 882                  * a clock change, and we suspended half-way through.
 883                  */
 884                 if (old_state != C_DISABLE_PM)
 885                         break;
 886                 /* fall through */
 887
 888         case C_ENABLE:
 889                 /*
 890                  * Power up the LCD screen, enable controller, and
 891                  * turn on the backlight.
 892                  */
 893                 if (old_state != C_ENABLE) {
 894                         fbi->state = C_ENABLE;
 895                         pxafb_setup_gpio(fbi);
 896                         pxafb_enable_controller(fbi);
 897                         __pxafb_lcd_power(fbi, 1);
 898                         __pxafb_backlight_power(fbi, 1);
 899                 }
 900                 break;
 901         }
 902         up(&fbi->ctrlr_sem);
 903 }
 904
 905 /*
 906  * Our LCD controller task (which is called when we blank or unblank)
 907  * via keventd.
 908  */
 909 static void pxafb_task(void *dummy)
 910 {
 911         struct pxafb_info *fbi = dummy;
 912         u_int state = xchg(&fbi->task_state, -1);
 913
 914         set_ctrlr_state(fbi, state);
 915 }
 916
 917 #ifdef CONFIG_CPU_FREQ
 918 /*
 919  * CPU clock speed change handler.  We need to adjust the LCD timing
 920  * parameters when the CPU clock is adjusted by the power management
 921  * subsystem.
 922  *
 923  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
 924  */
 925 static int
 926 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
 927 {
 928         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
 929         //TODO struct cpufreq_freqs *f = data;
 930         u_int pcd;
 931
 932         switch (val) {
 933         case CPUFREQ_PRECHANGE:
 934                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
 935                 break;
 936
 937         case CPUFREQ_POSTCHANGE:
 938                 pcd = get_pcd(fbi->fb.var.pixclock);
 939                 set_hsync_time(fbi, pcd);
 940                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
 941                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
 942                 break;
 943         }
 944         return 0;
 945 }
 946
 947 static int
 948 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
 949 {
 950         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
 951         struct fb_var_screeninfo *var = &fbi->fb.var;
 952         struct cpufreq_policy *policy = data;
 953
 954         switch (val) {
 955         case CPUFREQ_ADJUST:
 956         case CPUFREQ_INCOMPATIBLE:
 957                 printk(KERN_DEBUG "min dma period: %d ps, "
 958                         "new clock %d kHz\n", pxafb_display_dma_period(var),
 959                         policy->max);
 960                 // TODO: fill in min/max values
 961                 break;
 962 #if 0
 963         case CPUFREQ_NOTIFY:
 964                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
 965                 do {} while(0);
 966                 /* todo: panic if min/max values aren't fulfilled
 967                  * [can't really happen unless there's a bug in the
 968                  * CPU policy verification process *
 969                  */
 970                 break;
 971 #endif
 972         }
 973         return 0;
 974 }
 975 #endif
 976
 977 #ifdef CONFIG_PM
 978 /*
 979  * Power management hooks.  Note that we won't be called from IRQ context,
 980  * unlike the blank functions above, so we may sleep.
 981  */
 982 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
 983 {
 984         struct pxafb_info *fbi = platform_get_drvdata(dev);
 985
 986         set_ctrlr_state(fbi, C_DISABLE_PM);
 987         return 0;
 988 }
 989
 990 static int pxafb_resume(struct platform_device *dev)
 991 {
 992         struct pxafb_info *fbi = platform_get_drvdata(dev);
 993
 994         set_ctrlr_state(fbi, C_ENABLE_PM);
 995         return 0;
 996 }
 997 #else
 998 #define pxafb_suspend   NULL
 999 #define pxafb_resume    NULL
1000 #endif
1001
1002 /*
1003  * pxafb_map_video_memory():
1004  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1005  *      remapped into a non-cached, non-buffered, memory region to
1006  *      allow palette and pixel writes to occur without flushing the
1007  *      cache.  Once this area is remapped, all virtual memory
1008  *      access to the video memory should occur at the new region.
1009  */
1010 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1011 {
1012         u_long palette_mem_size;
1013
1014         /*
1015          * We reserve one page for the palette, plus the size
1016          * of the framebuffer.
1017          */
1018         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1019         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1020                                               &fbi->map_dma, GFP_KERNEL);
1021
1022         if (fbi->map_cpu) {
1023                 /* prevent initial garbage on screen */
1024                 memset(fbi->map_cpu, 0, fbi->map_size);
1025                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1026                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1027                 /*
1028                  * FIXME: this is actually the wrong thing to place in
1029                  * smem_start.  But fbdev suffers from the problem that
1030                  * it needs an API which doesn't exist (in this case,
1031                  * dma_writecombine_mmap)
1032                  */
1033                 fbi->fb.fix.smem_start = fbi->screen_dma;
1034
1035                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1036
1037                 palette_mem_size = fbi->palette_size * sizeof(u16);
1038                 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1039
1040                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1041                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1042         }
1043
1044         return fbi->map_cpu ? 0 : -ENOMEM;
1045 }
1046
1047 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1048 {
1049         struct pxafb_info *fbi;
1050         void *addr;
1051         struct pxafb_mach_info *inf = dev->platform_data;
1052
1053         /* Alloc the pxafb_info and pseudo_palette in one step */
1054         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1055         if (!fbi)
1056                 return NULL;
1057
1058         memset(fbi, 0, sizeof(struct pxafb_info));
1059         fbi->dev = dev;
1060
1061         strcpy(fbi->fb.fix.id, PXA_NAME);
1062
1063         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1064         fbi->fb.fix.type_aux    = 0;
1065         fbi->fb.fix.xpanstep    = 0;
1066         fbi->fb.fix.ypanstep    = 0;
1067         fbi->fb.fix.ywrapstep   = 0;
1068         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1069
1070         fbi->fb.var.nonstd      = 0;
1071         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1072         fbi->fb.var.height      = -1;
1073         fbi->fb.var.width       = -1;
1074         fbi->fb.var.accel_flags = 0;
1075         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1076
1077         fbi->fb.fbops           = &pxafb_ops;
1078         fbi->fb.flags           = FBINFO_DEFAULT;
1079         fbi->fb.node            = -1;
1080
1081         addr = fbi;
1082         addr = addr + sizeof(struct pxafb_info);
1083         fbi->fb.pseudo_palette  = addr;
1084
1085         fbi->max_xres                   = inf->xres;
1086         fbi->fb.var.xres                = inf->xres;
1087         fbi->fb.var.xres_virtual        = inf->xres;
1088         fbi->max_yres                   = inf->yres;
1089         fbi->fb.var.yres                = inf->yres;
1090         fbi->fb.var.yres_virtual        = inf->yres;
1091         fbi->max_bpp                    = inf->bpp;
1092         fbi->fb.var.bits_per_pixel      = inf->bpp;
1093         fbi->fb.var.pixclock            = inf->pixclock;
1094         fbi->fb.var.hsync_len           = inf->hsync_len;
1095         fbi->fb.var.left_margin         = inf->left_margin;
1096         fbi->fb.var.right_margin        = inf->right_margin;
1097         fbi->fb.var.vsync_len           = inf->vsync_len;
1098         fbi->fb.var.upper_margin        = inf->upper_margin;
1099         fbi->fb.var.lower_margin        = inf->lower_margin;
1100         fbi->fb.var.sync                = inf->sync;
1101         fbi->fb.var.grayscale           = inf->cmap_greyscale;
1102         fbi->cmap_inverse               = inf->cmap_inverse;
1103         fbi->cmap_static                = inf->cmap_static;
1104         fbi->lccr0                      = inf->lccr0;
1105         fbi->lccr3                      = inf->lccr3;
1106         fbi->state                      = C_STARTUP;
1107         fbi->task_state                 = (u_char)-1;
1108         fbi->fb.fix.smem_len            = fbi->max_xres * fbi->max_yres *
1109                                           fbi->max_bpp / 8;
1110
1111         init_waitqueue_head(&fbi->ctrlr_wait);
1112         INIT_WORK(&fbi->task, pxafb_task, fbi);
1113         init_MUTEX(&fbi->ctrlr_sem);
1114
1115         return fbi;
1116 }
1117
1118 #ifdef CONFIG_FB_PXA_PARAMETERS
1119 static int __init pxafb_parse_options(struct device *dev, char *options)
1120 {
1121         struct pxafb_mach_info *inf = dev->platform_data;
1122         char *this_opt;
1123
1124         if (!options || !*options)
1125                 return 0;
1126
1127         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1128
1129         /* could be made table driven or similar?... */
1130         while ((this_opt = strsep(&options, ",")) != NULL) {
1131                 if (!strncmp(this_opt, "mode:", 5)) {
1132                         const char *name = this_opt+5;
1133                         unsigned int namelen = strlen(name);
1134                         int res_specified = 0, bpp_specified = 0;
1135                         unsigned int xres = 0, yres = 0, bpp = 0;
1136                         int yres_specified = 0;
1137                         int i;
1138                         for (i = namelen-1; i >= 0; i--) {
1139                                 switch (name[i]) {
1140                                 case '-':
1141                                         namelen = i;
1142                                         if (!bpp_specified && !yres_specified) {
1143                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1144                                                 bpp_specified = 1;
1145                                         } else
1146                                                 goto done;
1147                                         break;
1148                                 case 'x':
1149                                         if (!yres_specified) {
1150                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1151                                                 yres_specified = 1;
1152                                         } else
1153                                                 goto done;
1154                                         break;
1155                                 case '0'...'9':
1156                                         break;
1157                                 default:
1158                                         goto done;
1159                                 }
1160                         }
1161                         if (i < 0 && yres_specified) {
1162                                 xres = simple_strtoul(name, NULL, 0);
1163                                 res_specified = 1;
1164                         }
1165                 done:
1166                         if (res_specified) {
1167                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1168                                 inf->xres = xres; inf->yres = yres;
1169                         }
1170                         if (bpp_specified)
1171                                 switch (bpp) {
1172                                 case 1:
1173                                 case 2:
1174                                 case 4:
1175                                 case 8:
1176                                 case 16:
1177                                         inf->bpp = bpp;
1178                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1179                                         break;
1180                                 default:
1181                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1182                                 }
1183                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1184                         inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1185                         dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1186                 } else if (!strncmp(this_opt, "left:", 5)) {
1187                         inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1188                         dev_info(dev, "override left: %u\n", inf->left_margin);
1189                 } else if (!strncmp(this_opt, "right:", 6)) {
1190                         inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1191                         dev_info(dev, "override right: %u\n", inf->right_margin);
1192                 } else if (!strncmp(this_opt, "upper:", 6)) {
1193                         inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1194                         dev_info(dev, "override upper: %u\n", inf->upper_margin);
1195                 } else if (!strncmp(this_opt, "lower:", 6)) {
1196                         inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1197                         dev_info(dev, "override lower: %u\n", inf->lower_margin);
1198                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1199                         inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1200                         dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1201                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1202                         inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1203                         dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1204                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1205                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1206                                 dev_info(dev, "override hsync: Active Low\n");
1207                                 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1208                         } else {
1209                                 dev_info(dev, "override hsync: Active High\n");
1210                                 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1211                         }
1212                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1213                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1214                                 dev_info(dev, "override vsync: Active Low\n");
1215                                 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1216                         } else {
1217                                 dev_info(dev, "override vsync: Active High\n");
1218                                 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1219                         }
1220                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1221                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1222                                 dev_info(dev, "override double pixel clock: false\n");
1223                                 inf->lccr3 &= ~LCCR3_DPC;
1224                         } else {
1225                                 dev_info(dev, "override double pixel clock: true\n");
1226                                 inf->lccr3 |= LCCR3_DPC;
1227                         }
1228                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1229                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1230                                 dev_info(dev, "override output enable: active low\n");
1231                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1232                         } else {
1233                                 dev_info(dev, "override output enable: active high\n");
1234                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1235                         }
1236                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1237                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1238                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1239                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1240                         } else {
1241                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1242                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1243                         }
1244                 } else if (!strncmp(this_opt, "color", 5)) {
1245                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1246                 } else if (!strncmp(this_opt, "mono", 4)) {
1247                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1248                 } else if (!strncmp(this_opt, "active", 6)) {
1249                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1250                 } else if (!strncmp(this_opt, "passive", 7)) {
1251                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1252                 } else if (!strncmp(this_opt, "single", 6)) {
1253                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1254                 } else if (!strncmp(this_opt, "dual", 4)) {
1255                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1256                 } else if (!strncmp(this_opt, "4pix", 4)) {
1257                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1258                 } else if (!strncmp(this_opt, "8pix", 4)) {
1259                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1260                 } else {
1261                         dev_err(dev, "unknown option: %s\n", this_opt);
1262                         return -EINVAL;
1263                 }
1264         }
1265         return 0;
1266
1267 }
1268 #endif
1269
1270 int __init pxafb_probe(struct platform_device *dev)
1271 {
1272         struct pxafb_info *fbi;
1273         struct pxafb_mach_info *inf;
1274         int ret;
1275
1276         dev_dbg(&dev->dev, "pxafb_probe\n");
1277
1278         inf = dev->dev.platform_data;
1279         ret = -ENOMEM;
1280         fbi = NULL;
1281         if (!inf)
1282                 goto failed;
1283
1284 #ifdef CONFIG_FB_PXA_PARAMETERS
1285         ret = pxafb_parse_options(&dev->dev, g_options);
1286         if (ret < 0)
1287                 goto failed;
1288 #endif
1289
1290 #ifdef DEBUG_VAR
1291         /* Check for various illegal bit-combinations. Currently only
1292          * a warning is given. */
1293
1294         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1295                 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1296                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1297         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1298                 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1299                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1300         if (inf->lccr0 & LCCR0_DPD &&
1301             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1302              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1303              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1304                 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1305                          " single panel mode\n");
1306         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1307             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1308                 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1309         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1310              (inf->upper_margin || inf->lower_margin))
1311                 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
1312 #endif
1313
1314         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1315         if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1316                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1317                 ret = -EINVAL;
1318                 goto failed;
1319         }
1320         pxafb_backlight_power = inf->pxafb_backlight_power;
1321         pxafb_lcd_power = inf->pxafb_lcd_power;
1322         fbi = pxafb_init_fbinfo(&dev->dev);
1323         if (!fbi) {
1324                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1325                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1326                 goto failed;
1327         }
1328
1329         /* Initialize video memory */
1330         ret = pxafb_map_video_memory(fbi);
1331         if (ret) {
1332                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1333                 ret = -ENOMEM;
1334                 goto failed;
1335         }
1336
1337         ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1338         if (ret) {
1339                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1340                 ret = -EBUSY;
1341                 goto failed;
1342         }
1343
1344         /*
1345          * This makes sure that our colour bitfield
1346          * descriptors are correctly initialised.
1347          */
1348         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1349         pxafb_set_par(&fbi->fb);
1350
1351         platform_set_drvdata(dev, fbi);
1352
1353         ret = register_framebuffer(&fbi->fb);
1354         if (ret < 0) {
1355                 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
1356                 goto failed;
1357         }
1358
1359 #ifdef CONFIG_PM
1360         // TODO
1361 #endif
1362
1363 #ifdef CONFIG_CPU_FREQ
1364         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1365         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1366         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1367         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1368 #endif
1369
1370         /*
1371          * Ok, now enable the LCD controller
1372          */
1373         set_ctrlr_state(fbi, C_ENABLE);
1374
1375         return 0;
1376
1377 failed:
1378         platform_set_drvdata(dev, NULL);
1379         kfree(fbi);
1380         return ret;
1381 }
1382
1383 static struct platform_driver pxafb_driver = {
1384         .probe          = pxafb_probe,
1385 #ifdef CONFIG_PM
1386         .suspend        = pxafb_suspend,
1387         .resume         = pxafb_resume,
1388 #endif
1389         .driver         = {
1390                 .name   = "pxa2xx-fb",
1391         },
1392 };
1393
1394 #ifndef MODULE
1395 int __devinit pxafb_setup(char *options)
1396 {
1397 # ifdef CONFIG_FB_PXA_PARAMETERS
1398         if (options)
1399                 strlcpy(g_options, options, sizeof(g_options));
1400 # endif
1401         return 0;
1402 }
1403 #else
1404 # ifdef CONFIG_FB_PXA_PARAMETERS
1405 module_param_string(options, g_options, sizeof(g_options), 0);
1406 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1407 # endif
1408 #endif
1409
1410 int __devinit pxafb_init(void)
1411 {
1412 #ifndef MODULE
1413         char *option = NULL;
1414
1415         if (fb_get_options("pxafb", &option))
1416                 return -ENODEV;
1417         pxafb_setup(option);
1418 #endif
1419         return platform_driver_register(&pxafb_driver);
1420 }
1421
1422 module_init(pxafb_init);
1423
1424 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1425 MODULE_LICENSE("GPL");