drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum omap_burst_size {
 101         OMAP_DSS_BURST_4x32 = 0,
 102         OMAP_DSS_BURST_8x32 = 1,
 103         OMAP_DSS_BURST_16x32 = 2,
 104 };
 105
 106 enum omap_parallel_interface_mode {
 107         OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
 108         OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
 109         OMAP_DSS_PARALLELMODE_DSI,
 110 };
 111
 112 enum dss_clock {
 113         DSS_CLK_ICK     = 1 << 0,       /* DSS_L3_ICLK and DSS_L4_ICLK */
 114         DSS_CLK_FCK     = 1 << 1,       /* DSS1_ALWON_FCLK */
 115         DSS_CLK_SYSCK   = 1 << 2,       /* DSS2_ALWON_FCLK */
 116         DSS_CLK_TVFCK   = 1 << 3,       /* DSS_TV_FCLK */
 117         DSS_CLK_VIDFCK  = 1 << 4,       /* DSS_96M_FCLK*/
 118 };
 119
 120 enum dss_hdmi_venc_clk_source_select {
 121         DSS_VENC_TV_CLK = 0,
 122         DSS_HDMI_M_PCLK = 1,
 123 };
 124
 125 struct dss_clock_info {
 126         /* rates that we get with dividers below */
 127         unsigned long fck;
 128
 129         /* dividers */
 130         u16 fck_div;
 131 };
 132
 133 struct dispc_clock_info {
 134         /* rates that we get with dividers below */
 135         unsigned long lck;
 136         unsigned long pck;
 137
 138         /* dividers */
 139         u16 lck_div;
 140         u16 pck_div;
 141 };
 142
 143 struct dsi_clock_info {
 144         /* rates that we get with dividers below */
 145         unsigned long fint;
 146         unsigned long clkin4ddr;
 147         unsigned long clkin;
 148         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 149                                                  * OMAP4: PLLx_CLK1 */
 150         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 151                                                  * OMAP4: PLLx_CLK2 */
 152         unsigned long lp_clk;
 153
 154         /* dividers */
 155         u16 regn;
 156         u16 regm;
 157         u16 regm_dispc; /* OMAP3: REGM3
 158                          * OMAP4: REGM4 */
 159         u16 regm_dsi;   /* OMAP3: REGM4
 160                          * OMAP4: REGM5 */
 161         u16 lp_clk_div;
 162
 163         u8 highfreq;
 164         bool use_sys_clk;
 165 };
 166
 167 /* HDMI PLL structure */
 168 struct hdmi_pll_info {
 169         u16 regn;
 170         u16 regm;
 171         u32 regmf;
 172         u16 regm2;
 173         u16 regsd;
 174         u16 dcofreq;
 175 };
 176
 177 struct seq_file;
 178 struct platform_device;
 179
 180 /* core */
 181 struct bus_type *dss_get_bus(void);
 182 struct regulator *dss_get_vdds_dsi(void);
 183 struct regulator *dss_get_vdds_sdi(void);
 184
 185 /* display */
 186 int dss_suspend_all_devices(void);
 187 int dss_resume_all_devices(void);
 188 void dss_disable_all_devices(void);
 189
 190 void dss_init_device(struct platform_device *pdev,
 191                 struct omap_dss_device *dssdev);
 192 void dss_uninit_device(struct platform_device *pdev,
 193                 struct omap_dss_device *dssdev);
 194 bool dss_use_replication(struct omap_dss_device *dssdev,
 195                 enum omap_color_mode mode);
 196 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 197                 u32 fifo_size, enum omap_burst_size *burst_size,
 198                 u32 *fifo_low, u32 *fifo_high);
 199
 200 /* manager */
 201 int dss_init_overlay_managers(struct platform_device *pdev);
 202 void dss_uninit_overlay_managers(struct platform_device *pdev);
 203 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 204 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 205                                 u16 *x, u16 *y, u16 *w, u16 *h,
 206                                 bool enlarge_update_area);
 207 void dss_start_update(struct omap_dss_device *dssdev);
 208
 209 /* overlay */
 210 void dss_init_overlays(struct platform_device *pdev);
 211 void dss_uninit_overlays(struct platform_device *pdev);
 212 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 213 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 214 #ifdef L4_EXAMPLE
 215 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 216 #endif
 217 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 218
 219 /* DSS */
 220 int dss_init_platform_driver(void);
 221 void dss_uninit_platform_driver(void);
 222
 223 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 224 void dss_save_context(void);
 225 void dss_restore_context(void);
 226 void dss_clk_enable(enum dss_clock clks);
 227 void dss_clk_disable(enum dss_clock clks);
 228 unsigned long dss_clk_get_rate(enum dss_clock clk);
 229 int dss_need_ctx_restore(void);
 230 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 231 void dss_dump_clocks(struct seq_file *s);
 232
 233 void dss_dump_regs(struct seq_file *s);
 234 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 235 void dss_debug_dump_clocks(struct seq_file *s);
 236 #endif
 237
 238 void dss_sdi_init(u8 datapairs);
 239 int dss_sdi_enable(void);
 240 void dss_sdi_disable(void);
 241
 242 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 243 void dss_select_dsi_clk_source(int dsi_module,
 244                 enum omap_dss_clk_source clk_src);
 245 void dss_select_lcd_clk_source(enum omap_channel channel,
 246                 enum omap_dss_clk_source clk_src);
 247 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 248 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 249 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 250
 251 void dss_set_venc_output(enum omap_dss_venc_type type);
 252 void dss_set_dac_pwrdn_bgz(bool enable);
 253
 254 unsigned long dss_get_dpll4_rate(void);
 255 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 256 int dss_set_clock_div(struct dss_clock_info *cinfo);
 257 int dss_get_clock_div(struct dss_clock_info *cinfo);
 258 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 259                 struct dss_clock_info *dss_cinfo,
 260                 struct dispc_clock_info *dispc_cinfo);
 261
 262 /* SDI */
 263 #ifdef CONFIG_OMAP2_DSS_SDI
 264 int sdi_init(void);
 265 void sdi_exit(void);
 266 int sdi_init_display(struct omap_dss_device *display);
 267 #else
 268 static inline int sdi_init(void)
 269 {
 270         return 0;
 271 }
 272 static inline void sdi_exit(void)
 273 {
 274 }
 275 #endif
 276
 277 /* DSI */
 278 #ifdef CONFIG_OMAP2_DSS_DSI
 279
 280 struct dentry;
 281 struct file_operations;
 282
 283 int dsi_init_platform_driver(void);
 284 void dsi_uninit_platform_driver(void);
 285
 286 void dsi_dump_clocks(struct seq_file *s);
 287 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 288                 const struct file_operations *debug_fops);
 289 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 290                 const struct file_operations *debug_fops);
 291
 292 void dsi_save_context(void);
 293 void dsi_restore_context(void);
 294
 295 int dsi_init_display(struct omap_dss_device *display);
 296 void dsi_irq_handler(void);
 297 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 298 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 299                 struct dsi_clock_info *cinfo);
 300 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 301                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 302                 struct dispc_clock_info *dispc_cinfo);
 303 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 304                 bool enable_hsdiv);
 305 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 306 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 307                 u32 fifo_size, enum omap_burst_size *burst_size,
 308                 u32 *fifo_low, u32 *fifo_high);
 309 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 310 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 311 struct platform_device *dsi_get_dsidev_from_id(int module);
 312 #else
 313 static inline int dsi_init_platform_driver(void)
 314 {
 315         return 0;
 316 }
 317 static inline void dsi_uninit_platform_driver(void)
 318 {
 319 }
 320 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 321 {
 322         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 323         return 0;
 324 }
 325 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 326                 struct dsi_clock_info *cinfo)
 327 {
 328         WARN("%s: DSI not compiled in\n", __func__);
 329         return -ENODEV;
 330 }
 331 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 332                 bool is_tft, unsigned long req_pck,
 333                 struct dsi_clock_info *dsi_cinfo,
 334                 struct dispc_clock_info *dispc_cinfo)
 335 {
 336         WARN("%s: DSI not compiled in\n", __func__);
 337         return -ENODEV;
 338 }
 339 static inline int dsi_pll_init(struct platform_device *dsidev,
 340                 bool enable_hsclk, bool enable_hsdiv)
 341 {
 342         WARN("%s: DSI not compiled in\n", __func__);
 343         return -ENODEV;
 344 }
 345 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 346                 bool disconnect_lanes)
 347 {
 348 }
 349 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 350 {
 351 }
 352 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 353 {
 354 }
 355 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 356 {
 357         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 358                         __func__);
 359         return NULL;
 360 }
 361 #endif
 362
 363 /* DPI */
 364 #ifdef CONFIG_OMAP2_DSS_DPI
 365 int dpi_init(void);
 366 void dpi_exit(void);
 367 int dpi_init_display(struct omap_dss_device *dssdev);
 368 #else
 369 static inline int dpi_init(void)
 370 {
 371         return 0;
 372 }
 373 static inline void dpi_exit(void)
 374 {
 375 }
 376 #endif
 377
 378 /* DISPC */
 379 int dispc_init_platform_driver(void);
 380 void dispc_uninit_platform_driver(void);
 381 void dispc_dump_clocks(struct seq_file *s);
 382 void dispc_dump_irqs(struct seq_file *s);
 383 void dispc_dump_regs(struct seq_file *s);
 384 void dispc_irq_handler(void);
 385 void dispc_fake_vsync_irq(void);
 386
 387 void dispc_save_context(void);
 388 void dispc_restore_context(void);
 389
 390 void dispc_enable_sidle(void);
 391 void dispc_disable_sidle(void);
 392
 393 void dispc_lcd_enable_signal_polarity(bool act_high);
 394 void dispc_lcd_enable_signal(bool enable);
 395 void dispc_pck_free_enable(bool enable);
 396 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
 397
 398 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 399 void dispc_set_digit_size(u16 width, u16 height);
 400 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 401 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
 402 void dispc_enable_fifomerge(bool enable);
 403 void dispc_set_burst_size(enum omap_plane plane,
 404                 enum omap_burst_size burst_size);
 405
 406 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 407 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
 408 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 409 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 410 void dispc_set_channel_out(enum omap_plane plane,
 411                 enum omap_channel channel_out);
 412
 413 void dispc_enable_gamma_table(bool enable);
 414 int dispc_setup_plane(enum omap_plane plane,
 415                       u32 paddr, u16 screen_width,
 416                       u16 pos_x, u16 pos_y,
 417                       u16 width, u16 height,
 418                       u16 out_width, u16 out_height,
 419                       enum omap_color_mode color_mode,
 420                       bool ilace,
 421                       enum omap_dss_rotation_type rotation_type,
 422                       u8 rotation, bool mirror,
 423                       u8 global_alpha, u8 pre_mult_alpha,
 424                       enum omap_channel channel,
 425                       u32 puv_addr);
 426
 427 bool dispc_go_busy(enum omap_channel channel);
 428 void dispc_go(enum omap_channel channel);
 429 void dispc_enable_channel(enum omap_channel channel, bool enable);
 430 bool dispc_is_channel_enabled(enum omap_channel channel);
 431 int dispc_enable_plane(enum omap_plane plane, bool enable);
 432 void dispc_enable_replication(enum omap_plane plane, bool enable);
 433
 434 void dispc_set_parallel_interface_mode(enum omap_channel channel,
 435                 enum omap_parallel_interface_mode mode);
 436 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 437 void dispc_set_lcd_display_type(enum omap_channel channel,
 438                 enum omap_lcd_display_type type);
 439 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 440
 441 void dispc_set_default_color(enum omap_channel channel, u32 color);
 442 u32 dispc_get_default_color(enum omap_channel channel);
 443 void dispc_set_trans_key(enum omap_channel ch,
 444                 enum omap_dss_trans_key_type type,
 445                 u32 trans_key);
 446 void dispc_get_trans_key(enum omap_channel ch,
 447                 enum omap_dss_trans_key_type *type,
 448                 u32 *trans_key);
 449 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
 450 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
 451 bool dispc_trans_key_enabled(enum omap_channel ch);
 452 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 453
 454 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 455 void dispc_set_lcd_timings(enum omap_channel channel,
 456                 struct omap_video_timings *timings);
 457 unsigned long dispc_fclk_rate(void);
 458 unsigned long dispc_lclk_rate(enum omap_channel channel);
 459 unsigned long dispc_pclk_rate(enum omap_channel channel);
 460 void dispc_set_pol_freq(enum omap_channel channel,
 461                 enum omap_panel_config config, u8 acbi, u8 acb);
 462 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 463                 struct dispc_clock_info *cinfo);
 464 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 465                 struct dispc_clock_info *cinfo);
 466 int dispc_set_clock_div(enum omap_channel channel,
 467                 struct dispc_clock_info *cinfo);
 468 int dispc_get_clock_div(enum omap_channel channel,
 469                 struct dispc_clock_info *cinfo);
 470
 471
 472 /* VENC */
 473 #ifdef CONFIG_OMAP2_DSS_VENC
 474 int venc_init_platform_driver(void);
 475 void venc_uninit_platform_driver(void);
 476 void venc_dump_regs(struct seq_file *s);
 477 int venc_init_display(struct omap_dss_device *display);
 478 #else
 479 static inline int venc_init_platform_driver(void)
 480 {
 481         return 0;
 482 }
 483 static inline void venc_uninit_platform_driver(void)
 484 {
 485 }
 486 #endif
 487
 488 /* HDMI */
 489 #ifdef CONFIG_OMAP4_DSS_HDMI
 490 int hdmi_init_platform_driver(void);
 491 void hdmi_uninit_platform_driver(void);
 492 int hdmi_init_display(struct omap_dss_device *dssdev);
 493 #else
 494 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 495 {
 496         return 0;
 497 }
 498 static inline int hdmi_init_platform_driver(void)
 499 {
 500         return 0;
 501 }
 502 static inline void hdmi_uninit_platform_driver(void)
 503 {
 504 }
 505 #endif
 506 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 507 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 508 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 509 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 510                                         struct omap_video_timings *timings);
 511 int hdmi_panel_init(void);
 512 void hdmi_panel_exit(void);
 513
 514 /* RFBI */
 515 #ifdef CONFIG_OMAP2_DSS_RFBI
 516 int rfbi_init_platform_driver(void);
 517 void rfbi_uninit_platform_driver(void);
 518 void rfbi_dump_regs(struct seq_file *s);
 519 int rfbi_init_display(struct omap_dss_device *display);
 520 #else
 521 static inline int rfbi_init_platform_driver(void)
 522 {
 523         return 0;
 524 }
 525 static inline void rfbi_uninit_platform_driver(void)
 526 {
 527 }
 528 #endif
 529
 530
 531 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 532 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 533 {
 534         int b;
 535         for (b = 0; b < 32; ++b) {
 536                 if (irqstatus & (1 << b))
 537                         irq_arr[b]++;
 538         }
 539 }
 540 #endif
 541
 542 #endif