drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42 #include "dss_features.h"
  43
  44 /* DISPC */
  45 #define DISPC_BASE                      0x48050400
  46
  47 #define DISPC_SZ_REGS                   SZ_1K
  48
  49 struct dispc_reg { u16 idx; };
  50
  51 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  52
  53 /* DISPC common */
  54 #define DISPC_REVISION                  DISPC_REG(0x0000)
  55 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  56 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  57 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  58 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  59 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  60 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  61 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  62 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  63 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  64 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  65 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  66 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  67 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  68 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  69 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  70 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  71 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  72 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  73 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  74 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  75
  76 /* DISPC GFX plane */
  77 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  78 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  79 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  80 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  81 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  82 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  83 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  84 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  85 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  86 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  87 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  88
  89 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  90 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  91 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  92
  93 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  94 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  95 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  96
  97 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  98
  99 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 100 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 101
 102 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 103 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 104 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 105 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 106 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 107 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 108 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 109 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 110 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 111 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 112 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 113 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 114 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 115
 116 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 117 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 118 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 119 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 120 /* coef index i = {0, 1, 2, 3, 4} */
 121 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 122 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 123 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 124
 125 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 126
 127
 128 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 129                                          DISPC_IRQ_OCP_ERR | \
 130                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 132                                          DISPC_IRQ_SYNC_LOST | \
 133                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 134
 135 #define DISPC_MAX_NR_ISRS               8
 136
 137 struct omap_dispc_isr_data {
 138         omap_dispc_isr_t        isr;
 139         void                    *arg;
 140         u32                     mask;
 141 };
 142
 143 struct dispc_h_coef {
 144         s8 hc4;
 145         s8 hc3;
 146         u8 hc2;
 147         s8 hc1;
 148         s8 hc0;
 149 };
 150
 151 struct dispc_v_coef {
 152         s8 vc22;
 153         s8 vc2;
 154         u8 vc1;
 155         s8 vc0;
 156         s8 vc00;
 157 };
 158
 159 #define REG_GET(idx, start, end) \
 160         FLD_GET(dispc_read_reg(idx), start, end)
 161
 162 #define REG_FLD_MOD(idx, val, start, end)                               \
 163         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 164
 165 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 166         DISPC_VID_ATTRIBUTES(0),
 167         DISPC_VID_ATTRIBUTES(1) };
 168
 169 struct dispc_irq_stats {
 170         unsigned long last_reset;
 171         unsigned irq_count;
 172         unsigned irqs[32];
 173 };
 174
 175 static struct {
 176         void __iomem    *base;
 177
 178         u32     fifo_size[3];
 179
 180         spinlock_t irq_lock;
 181         u32 irq_error_mask;
 182         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 183         u32 error_irqs;
 184         struct work_struct error_work;
 185
 186         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 187
 188 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 189         spinlock_t irq_stats_lock;
 190         struct dispc_irq_stats irq_stats;
 191 #endif
 192 } dispc;
 193
 194 static void _omap_dispc_set_irqs(void);
 195
 196 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 197 {
 198         __raw_writel(val, dispc.base + idx.idx);
 199 }
 200
 201 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 202 {
 203         return __raw_readl(dispc.base + idx.idx);
 204 }
 205
 206 #define SR(reg) \
 207         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 208 #define RR(reg) \
 209         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 210
 211 void dispc_save_context(void)
 212 {
 213         if (cpu_is_omap24xx())
 214                 return;
 215
 216         SR(SYSCONFIG);
 217         SR(IRQENABLE);
 218         SR(CONTROL);
 219         SR(CONFIG);
 220         SR(DEFAULT_COLOR0);
 221         SR(DEFAULT_COLOR1);
 222         SR(TRANS_COLOR0);
 223         SR(TRANS_COLOR1);
 224         SR(LINE_NUMBER);
 225         SR(TIMING_H);
 226         SR(TIMING_V);
 227         SR(POL_FREQ);
 228         SR(DIVISOR);
 229         SR(GLOBAL_ALPHA);
 230         SR(SIZE_DIG);
 231         SR(SIZE_LCD);
 232
 233         SR(GFX_BA0);
 234         SR(GFX_BA1);
 235         SR(GFX_POSITION);
 236         SR(GFX_SIZE);
 237         SR(GFX_ATTRIBUTES);
 238         SR(GFX_FIFO_THRESHOLD);
 239         SR(GFX_ROW_INC);
 240         SR(GFX_PIXEL_INC);
 241         SR(GFX_WINDOW_SKIP);
 242         SR(GFX_TABLE_BA);
 243
 244         SR(DATA_CYCLE1);
 245         SR(DATA_CYCLE2);
 246         SR(DATA_CYCLE3);
 247
 248         SR(CPR_COEF_R);
 249         SR(CPR_COEF_G);
 250         SR(CPR_COEF_B);
 251
 252         SR(GFX_PRELOAD);
 253
 254         /* VID1 */
 255         SR(VID_BA0(0));
 256         SR(VID_BA1(0));
 257         SR(VID_POSITION(0));
 258         SR(VID_SIZE(0));
 259         SR(VID_ATTRIBUTES(0));
 260         SR(VID_FIFO_THRESHOLD(0));
 261         SR(VID_ROW_INC(0));
 262         SR(VID_PIXEL_INC(0));
 263         SR(VID_FIR(0));
 264         SR(VID_PICTURE_SIZE(0));
 265         SR(VID_ACCU0(0));
 266         SR(VID_ACCU1(0));
 267
 268         SR(VID_FIR_COEF_H(0, 0));
 269         SR(VID_FIR_COEF_H(0, 1));
 270         SR(VID_FIR_COEF_H(0, 2));
 271         SR(VID_FIR_COEF_H(0, 3));
 272         SR(VID_FIR_COEF_H(0, 4));
 273         SR(VID_FIR_COEF_H(0, 5));
 274         SR(VID_FIR_COEF_H(0, 6));
 275         SR(VID_FIR_COEF_H(0, 7));
 276
 277         SR(VID_FIR_COEF_HV(0, 0));
 278         SR(VID_FIR_COEF_HV(0, 1));
 279         SR(VID_FIR_COEF_HV(0, 2));
 280         SR(VID_FIR_COEF_HV(0, 3));
 281         SR(VID_FIR_COEF_HV(0, 4));
 282         SR(VID_FIR_COEF_HV(0, 5));
 283         SR(VID_FIR_COEF_HV(0, 6));
 284         SR(VID_FIR_COEF_HV(0, 7));
 285
 286         SR(VID_CONV_COEF(0, 0));
 287         SR(VID_CONV_COEF(0, 1));
 288         SR(VID_CONV_COEF(0, 2));
 289         SR(VID_CONV_COEF(0, 3));
 290         SR(VID_CONV_COEF(0, 4));
 291
 292         SR(VID_FIR_COEF_V(0, 0));
 293         SR(VID_FIR_COEF_V(0, 1));
 294         SR(VID_FIR_COEF_V(0, 2));
 295         SR(VID_FIR_COEF_V(0, 3));
 296         SR(VID_FIR_COEF_V(0, 4));
 297         SR(VID_FIR_COEF_V(0, 5));
 298         SR(VID_FIR_COEF_V(0, 6));
 299         SR(VID_FIR_COEF_V(0, 7));
 300
 301         SR(VID_PRELOAD(0));
 302
 303         /* VID2 */
 304         SR(VID_BA0(1));
 305         SR(VID_BA1(1));
 306         SR(VID_POSITION(1));
 307         SR(VID_SIZE(1));
 308         SR(VID_ATTRIBUTES(1));
 309         SR(VID_FIFO_THRESHOLD(1));
 310         SR(VID_ROW_INC(1));
 311         SR(VID_PIXEL_INC(1));
 312         SR(VID_FIR(1));
 313         SR(VID_PICTURE_SIZE(1));
 314         SR(VID_ACCU0(1));
 315         SR(VID_ACCU1(1));
 316
 317         SR(VID_FIR_COEF_H(1, 0));
 318         SR(VID_FIR_COEF_H(1, 1));
 319         SR(VID_FIR_COEF_H(1, 2));
 320         SR(VID_FIR_COEF_H(1, 3));
 321         SR(VID_FIR_COEF_H(1, 4));
 322         SR(VID_FIR_COEF_H(1, 5));
 323         SR(VID_FIR_COEF_H(1, 6));
 324         SR(VID_FIR_COEF_H(1, 7));
 325
 326         SR(VID_FIR_COEF_HV(1, 0));
 327         SR(VID_FIR_COEF_HV(1, 1));
 328         SR(VID_FIR_COEF_HV(1, 2));
 329         SR(VID_FIR_COEF_HV(1, 3));
 330         SR(VID_FIR_COEF_HV(1, 4));
 331         SR(VID_FIR_COEF_HV(1, 5));
 332         SR(VID_FIR_COEF_HV(1, 6));
 333         SR(VID_FIR_COEF_HV(1, 7));
 334
 335         SR(VID_CONV_COEF(1, 0));
 336         SR(VID_CONV_COEF(1, 1));
 337         SR(VID_CONV_COEF(1, 2));
 338         SR(VID_CONV_COEF(1, 3));
 339         SR(VID_CONV_COEF(1, 4));
 340
 341         SR(VID_FIR_COEF_V(1, 0));
 342         SR(VID_FIR_COEF_V(1, 1));
 343         SR(VID_FIR_COEF_V(1, 2));
 344         SR(VID_FIR_COEF_V(1, 3));
 345         SR(VID_FIR_COEF_V(1, 4));
 346         SR(VID_FIR_COEF_V(1, 5));
 347         SR(VID_FIR_COEF_V(1, 6));
 348         SR(VID_FIR_COEF_V(1, 7));
 349
 350         SR(VID_PRELOAD(1));
 351 }
 352
 353 void dispc_restore_context(void)
 354 {
 355         RR(SYSCONFIG);
 356         /*RR(IRQENABLE);*/
 357         /*RR(CONTROL);*/
 358         RR(CONFIG);
 359         RR(DEFAULT_COLOR0);
 360         RR(DEFAULT_COLOR1);
 361         RR(TRANS_COLOR0);
 362         RR(TRANS_COLOR1);
 363         RR(LINE_NUMBER);
 364         RR(TIMING_H);
 365         RR(TIMING_V);
 366         RR(POL_FREQ);
 367         RR(DIVISOR);
 368         RR(GLOBAL_ALPHA);
 369         RR(SIZE_DIG);
 370         RR(SIZE_LCD);
 371
 372         RR(GFX_BA0);
 373         RR(GFX_BA1);
 374         RR(GFX_POSITION);
 375         RR(GFX_SIZE);
 376         RR(GFX_ATTRIBUTES);
 377         RR(GFX_FIFO_THRESHOLD);
 378         RR(GFX_ROW_INC);
 379         RR(GFX_PIXEL_INC);
 380         RR(GFX_WINDOW_SKIP);
 381         RR(GFX_TABLE_BA);
 382
 383         RR(DATA_CYCLE1);
 384         RR(DATA_CYCLE2);
 385         RR(DATA_CYCLE3);
 386
 387         RR(CPR_COEF_R);
 388         RR(CPR_COEF_G);
 389         RR(CPR_COEF_B);
 390
 391         RR(GFX_PRELOAD);
 392
 393         /* VID1 */
 394         RR(VID_BA0(0));
 395         RR(VID_BA1(0));
 396         RR(VID_POSITION(0));
 397         RR(VID_SIZE(0));
 398         RR(VID_ATTRIBUTES(0));
 399         RR(VID_FIFO_THRESHOLD(0));
 400         RR(VID_ROW_INC(0));
 401         RR(VID_PIXEL_INC(0));
 402         RR(VID_FIR(0));
 403         RR(VID_PICTURE_SIZE(0));
 404         RR(VID_ACCU0(0));
 405         RR(VID_ACCU1(0));
 406
 407         RR(VID_FIR_COEF_H(0, 0));
 408         RR(VID_FIR_COEF_H(0, 1));
 409         RR(VID_FIR_COEF_H(0, 2));
 410         RR(VID_FIR_COEF_H(0, 3));
 411         RR(VID_FIR_COEF_H(0, 4));
 412         RR(VID_FIR_COEF_H(0, 5));
 413         RR(VID_FIR_COEF_H(0, 6));
 414         RR(VID_FIR_COEF_H(0, 7));
 415
 416         RR(VID_FIR_COEF_HV(0, 0));
 417         RR(VID_FIR_COEF_HV(0, 1));
 418         RR(VID_FIR_COEF_HV(0, 2));
 419         RR(VID_FIR_COEF_HV(0, 3));
 420         RR(VID_FIR_COEF_HV(0, 4));
 421         RR(VID_FIR_COEF_HV(0, 5));
 422         RR(VID_FIR_COEF_HV(0, 6));
 423         RR(VID_FIR_COEF_HV(0, 7));
 424
 425         RR(VID_CONV_COEF(0, 0));
 426         RR(VID_CONV_COEF(0, 1));
 427         RR(VID_CONV_COEF(0, 2));
 428         RR(VID_CONV_COEF(0, 3));
 429         RR(VID_CONV_COEF(0, 4));
 430
 431         RR(VID_FIR_COEF_V(0, 0));
 432         RR(VID_FIR_COEF_V(0, 1));
 433         RR(VID_FIR_COEF_V(0, 2));
 434         RR(VID_FIR_COEF_V(0, 3));
 435         RR(VID_FIR_COEF_V(0, 4));
 436         RR(VID_FIR_COEF_V(0, 5));
 437         RR(VID_FIR_COEF_V(0, 6));
 438         RR(VID_FIR_COEF_V(0, 7));
 439
 440         RR(VID_PRELOAD(0));
 441
 442         /* VID2 */
 443         RR(VID_BA0(1));
 444         RR(VID_BA1(1));
 445         RR(VID_POSITION(1));
 446         RR(VID_SIZE(1));
 447         RR(VID_ATTRIBUTES(1));
 448         RR(VID_FIFO_THRESHOLD(1));
 449         RR(VID_ROW_INC(1));
 450         RR(VID_PIXEL_INC(1));
 451         RR(VID_FIR(1));
 452         RR(VID_PICTURE_SIZE(1));
 453         RR(VID_ACCU0(1));
 454         RR(VID_ACCU1(1));
 455
 456         RR(VID_FIR_COEF_H(1, 0));
 457         RR(VID_FIR_COEF_H(1, 1));
 458         RR(VID_FIR_COEF_H(1, 2));
 459         RR(VID_FIR_COEF_H(1, 3));
 460         RR(VID_FIR_COEF_H(1, 4));
 461         RR(VID_FIR_COEF_H(1, 5));
 462         RR(VID_FIR_COEF_H(1, 6));
 463         RR(VID_FIR_COEF_H(1, 7));
 464
 465         RR(VID_FIR_COEF_HV(1, 0));
 466         RR(VID_FIR_COEF_HV(1, 1));
 467         RR(VID_FIR_COEF_HV(1, 2));
 468         RR(VID_FIR_COEF_HV(1, 3));
 469         RR(VID_FIR_COEF_HV(1, 4));
 470         RR(VID_FIR_COEF_HV(1, 5));
 471         RR(VID_FIR_COEF_HV(1, 6));
 472         RR(VID_FIR_COEF_HV(1, 7));
 473
 474         RR(VID_CONV_COEF(1, 0));
 475         RR(VID_CONV_COEF(1, 1));
 476         RR(VID_CONV_COEF(1, 2));
 477         RR(VID_CONV_COEF(1, 3));
 478         RR(VID_CONV_COEF(1, 4));
 479
 480         RR(VID_FIR_COEF_V(1, 0));
 481         RR(VID_FIR_COEF_V(1, 1));
 482         RR(VID_FIR_COEF_V(1, 2));
 483         RR(VID_FIR_COEF_V(1, 3));
 484         RR(VID_FIR_COEF_V(1, 4));
 485         RR(VID_FIR_COEF_V(1, 5));
 486         RR(VID_FIR_COEF_V(1, 6));
 487         RR(VID_FIR_COEF_V(1, 7));
 488
 489         RR(VID_PRELOAD(1));
 490
 491         /* enable last, because LCD & DIGIT enable are here */
 492         RR(CONTROL);
 493
 494         /* clear spurious SYNC_LOST_DIGIT interrupts */
 495         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 496
 497         /*
 498          * enable last so IRQs won't trigger before
 499          * the context is fully restored
 500          */
 501         RR(IRQENABLE);
 502 }
 503
 504 #undef SR
 505 #undef RR
 506
 507 static inline void enable_clocks(bool enable)
 508 {
 509         if (enable)
 510                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 511         else
 512                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 513 }
 514
 515 bool dispc_go_busy(enum omap_channel channel)
 516 {
 517         int bit;
 518
 519         if (channel == OMAP_DSS_CHANNEL_LCD)
 520                 bit = 5; /* GOLCD */
 521         else
 522                 bit = 6; /* GODIGIT */
 523
 524         return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 525 }
 526
 527 void dispc_go(enum omap_channel channel)
 528 {
 529         int bit;
 530
 531         enable_clocks(1);
 532
 533         if (channel == OMAP_DSS_CHANNEL_LCD)
 534                 bit = 0; /* LCDENABLE */
 535         else
 536                 bit = 1; /* DIGITALENABLE */
 537
 538         /* if the channel is not enabled, we don't need GO */
 539         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 540                 goto end;
 541
 542         if (channel == OMAP_DSS_CHANNEL_LCD)
 543                 bit = 5; /* GOLCD */
 544         else
 545                 bit = 6; /* GODIGIT */
 546
 547         if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 548                 DSSERR("GO bit not down for channel %d\n", channel);
 549                 goto end;
 550         }
 551
 552         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 553
 554         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 555 end:
 556         enable_clocks(0);
 557 }
 558
 559 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 560 {
 561         BUG_ON(plane == OMAP_DSS_GFX);
 562
 563         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 564 }
 565
 566 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 567 {
 568         BUG_ON(plane == OMAP_DSS_GFX);
 569
 570         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 571 }
 572
 573 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 574 {
 575         BUG_ON(plane == OMAP_DSS_GFX);
 576
 577         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 578 }
 579
 580 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 581                 int vscaleup, int five_taps)
 582 {
 583         /* Coefficients for horizontal up-sampling */
 584         static const struct dispc_h_coef coef_hup[8] = {
 585                 {  0,   0, 128,   0,  0 },
 586                 { -1,  13, 124,  -8,  0 },
 587                 { -2,  30, 112, -11, -1 },
 588                 { -5,  51,  95, -11, -2 },
 589                 {  0,  -9,  73,  73, -9 },
 590                 { -2, -11,  95,  51, -5 },
 591                 { -1, -11, 112,  30, -2 },
 592                 {  0,  -8, 124,  13, -1 },
 593         };
 594
 595         /* Coefficients for vertical up-sampling */
 596         static const struct dispc_v_coef coef_vup_3tap[8] = {
 597                 { 0,  0, 128,  0, 0 },
 598                 { 0,  3, 123,  2, 0 },
 599                 { 0, 12, 111,  5, 0 },
 600                 { 0, 32,  89,  7, 0 },
 601                 { 0,  0,  64, 64, 0 },
 602                 { 0,  7,  89, 32, 0 },
 603                 { 0,  5, 111, 12, 0 },
 604                 { 0,  2, 123,  3, 0 },
 605         };
 606
 607         static const struct dispc_v_coef coef_vup_5tap[8] = {
 608                 {  0,   0, 128,   0,  0 },
 609                 { -1,  13, 124,  -8,  0 },
 610                 { -2,  30, 112, -11, -1 },
 611                 { -5,  51,  95, -11, -2 },
 612                 {  0,  -9,  73,  73, -9 },
 613                 { -2, -11,  95,  51, -5 },
 614                 { -1, -11, 112,  30, -2 },
 615                 {  0,  -8, 124,  13, -1 },
 616         };
 617
 618         /* Coefficients for horizontal down-sampling */
 619         static const struct dispc_h_coef coef_hdown[8] = {
 620                 {   0, 36, 56, 36,  0 },
 621                 {   4, 40, 55, 31, -2 },
 622                 {   8, 44, 54, 27, -5 },
 623                 {  12, 48, 53, 22, -7 },
 624                 {  -9, 17, 52, 51, 17 },
 625                 {  -7, 22, 53, 48, 12 },
 626                 {  -5, 27, 54, 44,  8 },
 627                 {  -2, 31, 55, 40,  4 },
 628         };
 629
 630         /* Coefficients for vertical down-sampling */
 631         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 632                 { 0, 36, 56, 36, 0 },
 633                 { 0, 40, 57, 31, 0 },
 634                 { 0, 45, 56, 27, 0 },
 635                 { 0, 50, 55, 23, 0 },
 636                 { 0, 18, 55, 55, 0 },
 637                 { 0, 23, 55, 50, 0 },
 638                 { 0, 27, 56, 45, 0 },
 639                 { 0, 31, 57, 40, 0 },
 640         };
 641
 642         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 643                 {   0, 36, 56, 36,  0 },
 644                 {   4, 40, 55, 31, -2 },
 645                 {   8, 44, 54, 27, -5 },
 646                 {  12, 48, 53, 22, -7 },
 647                 {  -9, 17, 52, 51, 17 },
 648                 {  -7, 22, 53, 48, 12 },
 649                 {  -5, 27, 54, 44,  8 },
 650                 {  -2, 31, 55, 40,  4 },
 651         };
 652
 653         const struct dispc_h_coef *h_coef;
 654         const struct dispc_v_coef *v_coef;
 655         int i;
 656
 657         if (hscaleup)
 658                 h_coef = coef_hup;
 659         else
 660                 h_coef = coef_hdown;
 661
 662         if (vscaleup)
 663                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 664         else
 665                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 666
 667         for (i = 0; i < 8; i++) {
 668                 u32 h, hv;
 669
 670                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 671                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 672                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 673                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 674                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 675                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 676                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 677                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 678
 679                 _dispc_write_firh_reg(plane, i, h);
 680                 _dispc_write_firhv_reg(plane, i, hv);
 681         }
 682
 683         if (five_taps) {
 684                 for (i = 0; i < 8; i++) {
 685                         u32 v;
 686                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 687                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 688                         _dispc_write_firv_reg(plane, i, v);
 689                 }
 690         }
 691 }
 692
 693 static void _dispc_setup_color_conv_coef(void)
 694 {
 695         const struct color_conv_coef {
 696                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 697                 int  full_range;
 698         }  ctbl_bt601_5 = {
 699                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 700         };
 701
 702         const struct color_conv_coef *ct;
 703
 704 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 705
 706         ct = &ctbl_bt601_5;
 707
 708         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 709         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 710         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 711         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 712         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 713
 714         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 718         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 719
 720 #undef CVAL
 721
 722         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 723         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 724 }
 725
 726
 727 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 728 {
 729         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 730                 DISPC_VID_BA0(0),
 731                 DISPC_VID_BA0(1) };
 732
 733         dispc_write_reg(ba0_reg[plane], paddr);
 734 }
 735
 736 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 737 {
 738         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 739                                       DISPC_VID_BA1(0),
 740                                       DISPC_VID_BA1(1) };
 741
 742         dispc_write_reg(ba1_reg[plane], paddr);
 743 }
 744
 745 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 746 {
 747         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 748                                       DISPC_VID_POSITION(0),
 749                                       DISPC_VID_POSITION(1) };
 750
 751         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 752         dispc_write_reg(pos_reg[plane], val);
 753 }
 754
 755 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 756 {
 757         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 758                                       DISPC_VID_PICTURE_SIZE(0),
 759                                       DISPC_VID_PICTURE_SIZE(1) };
 760         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 761         dispc_write_reg(siz_reg[plane], val);
 762 }
 763
 764 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 765 {
 766         u32 val;
 767         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 768                                       DISPC_VID_SIZE(1) };
 769
 770         BUG_ON(plane == OMAP_DSS_GFX);
 771
 772         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 773         dispc_write_reg(vsi_reg[plane-1], val);
 774 }
 775
 776 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 777 {
 778         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 779                 return;
 780
 781         BUG_ON(!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 782                         plane == OMAP_DSS_VIDEO1);
 783
 784         if (plane == OMAP_DSS_GFX)
 785                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 786         else if (plane == OMAP_DSS_VIDEO2)
 787                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 788 }
 789
 790 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 791 {
 792         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 793                                      DISPC_VID_PIXEL_INC(0),
 794                                      DISPC_VID_PIXEL_INC(1) };
 795
 796         dispc_write_reg(ri_reg[plane], inc);
 797 }
 798
 799 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 800 {
 801         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 802                                      DISPC_VID_ROW_INC(0),
 803                                      DISPC_VID_ROW_INC(1) };
 804
 805         dispc_write_reg(ri_reg[plane], inc);
 806 }
 807
 808 static void _dispc_set_color_mode(enum omap_plane plane,
 809                 enum omap_color_mode color_mode)
 810 {
 811         u32 m = 0;
 812
 813         switch (color_mode) {
 814         case OMAP_DSS_COLOR_CLUT1:
 815                 m = 0x0; break;
 816         case OMAP_DSS_COLOR_CLUT2:
 817                 m = 0x1; break;
 818         case OMAP_DSS_COLOR_CLUT4:
 819                 m = 0x2; break;
 820         case OMAP_DSS_COLOR_CLUT8:
 821                 m = 0x3; break;
 822         case OMAP_DSS_COLOR_RGB12U:
 823                 m = 0x4; break;
 824         case OMAP_DSS_COLOR_ARGB16:
 825                 m = 0x5; break;
 826         case OMAP_DSS_COLOR_RGB16:
 827                 m = 0x6; break;
 828         case OMAP_DSS_COLOR_RGB24U:
 829                 m = 0x8; break;
 830         case OMAP_DSS_COLOR_RGB24P:
 831                 m = 0x9; break;
 832         case OMAP_DSS_COLOR_YUV2:
 833                 m = 0xa; break;
 834         case OMAP_DSS_COLOR_UYVY:
 835                 m = 0xb; break;
 836         case OMAP_DSS_COLOR_ARGB32:
 837                 m = 0xc; break;
 838         case OMAP_DSS_COLOR_RGBA32:
 839                 m = 0xd; break;
 840         case OMAP_DSS_COLOR_RGBX32:
 841                 m = 0xe; break;
 842         default:
 843                 BUG(); break;
 844         }
 845
 846         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 847 }
 848
 849 static void _dispc_set_channel_out(enum omap_plane plane,
 850                 enum omap_channel channel)
 851 {
 852         int shift;
 853         u32 val;
 854
 855         switch (plane) {
 856         case OMAP_DSS_GFX:
 857                 shift = 8;
 858                 break;
 859         case OMAP_DSS_VIDEO1:
 860         case OMAP_DSS_VIDEO2:
 861                 shift = 16;
 862                 break;
 863         default:
 864                 BUG();
 865                 return;
 866         }
 867
 868         val = dispc_read_reg(dispc_reg_att[plane]);
 869         val = FLD_MOD(val, channel, shift, shift);
 870         dispc_write_reg(dispc_reg_att[plane], val);
 871 }
 872
 873 void dispc_set_burst_size(enum omap_plane plane,
 874                 enum omap_burst_size burst_size)
 875 {
 876         int shift;
 877         u32 val;
 878
 879         enable_clocks(1);
 880
 881         switch (plane) {
 882         case OMAP_DSS_GFX:
 883                 shift = 6;
 884                 break;
 885         case OMAP_DSS_VIDEO1:
 886         case OMAP_DSS_VIDEO2:
 887                 shift = 14;
 888                 break;
 889         default:
 890                 BUG();
 891                 return;
 892         }
 893
 894         val = dispc_read_reg(dispc_reg_att[plane]);
 895         val = FLD_MOD(val, burst_size, shift+1, shift);
 896         dispc_write_reg(dispc_reg_att[plane], val);
 897
 898         enable_clocks(0);
 899 }
 900
 901 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 902 {
 903         u32 val;
 904
 905         BUG_ON(plane == OMAP_DSS_GFX);
 906
 907         val = dispc_read_reg(dispc_reg_att[plane]);
 908         val = FLD_MOD(val, enable, 9, 9);
 909         dispc_write_reg(dispc_reg_att[plane], val);
 910 }
 911
 912 void dispc_enable_replication(enum omap_plane plane, bool enable)
 913 {
 914         int bit;
 915
 916         if (plane == OMAP_DSS_GFX)
 917                 bit = 5;
 918         else
 919                 bit = 10;
 920
 921         enable_clocks(1);
 922         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
 923         enable_clocks(0);
 924 }
 925
 926 void dispc_set_lcd_size(u16 width, u16 height)
 927 {
 928         u32 val;
 929         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 930         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 931         enable_clocks(1);
 932         dispc_write_reg(DISPC_SIZE_LCD, val);
 933         enable_clocks(0);
 934 }
 935
 936 void dispc_set_digit_size(u16 width, u16 height)
 937 {
 938         u32 val;
 939         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 940         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 941         enable_clocks(1);
 942         dispc_write_reg(DISPC_SIZE_DIG, val);
 943         enable_clocks(0);
 944 }
 945
 946 static void dispc_read_plane_fifo_sizes(void)
 947 {
 948         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 949                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 950                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 951         u32 size;
 952         int plane;
 953         u8 start, end;
 954
 955         enable_clocks(1);
 956
 957         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
 958
 959         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
 960                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
 961                 dispc.fifo_size[plane] = size;
 962         }
 963
 964         enable_clocks(0);
 965 }
 966
 967 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 968 {
 969         return dispc.fifo_size[plane];
 970 }
 971
 972 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 973 {
 974         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 975                                        DISPC_VID_FIFO_THRESHOLD(0),
 976                                        DISPC_VID_FIFO_THRESHOLD(1) };
 977         u8 hi_start, hi_end, lo_start, lo_end;
 978
 979         enable_clocks(1);
 980
 981         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
 982                         plane,
 983                         REG_GET(ftrs_reg[plane], 11, 0),
 984                         REG_GET(ftrs_reg[plane], 27, 16),
 985                         low, high);
 986
 987         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
 988         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
 989
 990         dispc_write_reg(ftrs_reg[plane],
 991                         FLD_VAL(high, hi_start, hi_end) |
 992                         FLD_VAL(low, lo_start, lo_end));
 993
 994         enable_clocks(0);
 995 }
 996
 997 void dispc_enable_fifomerge(bool enable)
 998 {
 999         enable_clocks(1);
1000
1001         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1002         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1003
1004         enable_clocks(0);
1005 }
1006
1007 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1008 {
1009         u32 val;
1010         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1011                                       DISPC_VID_FIR(1) };
1012         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1013
1014         BUG_ON(plane == OMAP_DSS_GFX);
1015
1016         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1017         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1018
1019         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1020                         FLD_VAL(hinc, hinc_start, hinc_end);
1021
1022         dispc_write_reg(fir_reg[plane-1], val);
1023 }
1024
1025 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1026 {
1027         u32 val;
1028         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1029                                       DISPC_VID_ACCU0(1) };
1030
1031         BUG_ON(plane == OMAP_DSS_GFX);
1032
1033         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1034         dispc_write_reg(ac0_reg[plane-1], val);
1035 }
1036
1037 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1038 {
1039         u32 val;
1040         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1041                                       DISPC_VID_ACCU1(1) };
1042
1043         BUG_ON(plane == OMAP_DSS_GFX);
1044
1045         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1046         dispc_write_reg(ac1_reg[plane-1], val);
1047 }
1048
1049
1050 static void _dispc_set_scaling(enum omap_plane plane,
1051                 u16 orig_width, u16 orig_height,
1052                 u16 out_width, u16 out_height,
1053                 bool ilace, bool five_taps,
1054                 bool fieldmode)
1055 {
1056         int fir_hinc;
1057         int fir_vinc;
1058         int hscaleup, vscaleup;
1059         int accu0 = 0;
1060         int accu1 = 0;
1061         u32 l;
1062
1063         BUG_ON(plane == OMAP_DSS_GFX);
1064
1065         hscaleup = orig_width <= out_width;
1066         vscaleup = orig_height <= out_height;
1067
1068         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1069
1070         if (!orig_width || orig_width == out_width)
1071                 fir_hinc = 0;
1072         else
1073                 fir_hinc = 1024 * orig_width / out_width;
1074
1075         if (!orig_height || orig_height == out_height)
1076                 fir_vinc = 0;
1077         else
1078                 fir_vinc = 1024 * orig_height / out_height;
1079
1080         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1081
1082         l = dispc_read_reg(dispc_reg_att[plane]);
1083         l &= ~((0x0f << 5) | (0x3 << 21));
1084
1085         l |= fir_hinc ? (1 << 5) : 0;
1086         l |= fir_vinc ? (1 << 6) : 0;
1087
1088         l |= hscaleup ? 0 : (1 << 7);
1089         l |= vscaleup ? 0 : (1 << 8);
1090
1091         l |= five_taps ? (1 << 21) : 0;
1092         l |= five_taps ? (1 << 22) : 0;
1093
1094         dispc_write_reg(dispc_reg_att[plane], l);
1095
1096         /*
1097          * field 0 = even field = bottom field
1098          * field 1 = odd field = top field
1099          */
1100         if (ilace && !fieldmode) {
1101                 accu1 = 0;
1102                 accu0 = (fir_vinc / 2) & 0x3ff;
1103                 if (accu0 >= 1024/2) {
1104                         accu1 = 1024/2;
1105                         accu0 -= accu1;
1106                 }
1107         }
1108
1109         _dispc_set_vid_accu0(plane, 0, accu0);
1110         _dispc_set_vid_accu1(plane, 0, accu1);
1111 }
1112
1113 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1114                 bool mirroring, enum omap_color_mode color_mode)
1115 {
1116         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1117                         color_mode == OMAP_DSS_COLOR_UYVY) {
1118                 int vidrot = 0;
1119
1120                 if (mirroring) {
1121                         switch (rotation) {
1122                         case OMAP_DSS_ROT_0:
1123                                 vidrot = 2;
1124                                 break;
1125                         case OMAP_DSS_ROT_90:
1126                                 vidrot = 1;
1127                                 break;
1128                         case OMAP_DSS_ROT_180:
1129                                 vidrot = 0;
1130                                 break;
1131                         case OMAP_DSS_ROT_270:
1132                                 vidrot = 3;
1133                                 break;
1134                         }
1135                 } else {
1136                         switch (rotation) {
1137                         case OMAP_DSS_ROT_0:
1138                                 vidrot = 0;
1139                                 break;
1140                         case OMAP_DSS_ROT_90:
1141                                 vidrot = 1;
1142                                 break;
1143                         case OMAP_DSS_ROT_180:
1144                                 vidrot = 2;
1145                                 break;
1146                         case OMAP_DSS_ROT_270:
1147                                 vidrot = 3;
1148                                 break;
1149                         }
1150                 }
1151
1152                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1153
1154                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1155                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1156                 else
1157                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1158         } else {
1159                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1160                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1161         }
1162 }
1163
1164 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1165 {
1166         switch (color_mode) {
1167         case OMAP_DSS_COLOR_CLUT1:
1168                 return 1;
1169         case OMAP_DSS_COLOR_CLUT2:
1170                 return 2;
1171         case OMAP_DSS_COLOR_CLUT4:
1172                 return 4;
1173         case OMAP_DSS_COLOR_CLUT8:
1174                 return 8;
1175         case OMAP_DSS_COLOR_RGB12U:
1176         case OMAP_DSS_COLOR_RGB16:
1177         case OMAP_DSS_COLOR_ARGB16:
1178         case OMAP_DSS_COLOR_YUV2:
1179         case OMAP_DSS_COLOR_UYVY:
1180                 return 16;
1181         case OMAP_DSS_COLOR_RGB24P:
1182                 return 24;
1183         case OMAP_DSS_COLOR_RGB24U:
1184         case OMAP_DSS_COLOR_ARGB32:
1185         case OMAP_DSS_COLOR_RGBA32:
1186         case OMAP_DSS_COLOR_RGBX32:
1187                 return 32;
1188         default:
1189                 BUG();
1190         }
1191 }
1192
1193 static s32 pixinc(int pixels, u8 ps)
1194 {
1195         if (pixels == 1)
1196                 return 1;
1197         else if (pixels > 1)
1198                 return 1 + (pixels - 1) * ps;
1199         else if (pixels < 0)
1200                 return 1 - (-pixels + 1) * ps;
1201         else
1202                 BUG();
1203 }
1204
1205 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1206                 u16 screen_width,
1207                 u16 width, u16 height,
1208                 enum omap_color_mode color_mode, bool fieldmode,
1209                 unsigned int field_offset,
1210                 unsigned *offset0, unsigned *offset1,
1211                 s32 *row_inc, s32 *pix_inc)
1212 {
1213         u8 ps;
1214
1215         /* FIXME CLUT formats */
1216         switch (color_mode) {
1217         case OMAP_DSS_COLOR_CLUT1:
1218         case OMAP_DSS_COLOR_CLUT2:
1219         case OMAP_DSS_COLOR_CLUT4:
1220         case OMAP_DSS_COLOR_CLUT8:
1221                 BUG();
1222                 return;
1223         case OMAP_DSS_COLOR_YUV2:
1224         case OMAP_DSS_COLOR_UYVY:
1225                 ps = 4;
1226                 break;
1227         default:
1228                 ps = color_mode_to_bpp(color_mode) / 8;
1229                 break;
1230         }
1231
1232         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1233                         width, height);
1234
1235         /*
1236          * field 0 = even field = bottom field
1237          * field 1 = odd field = top field
1238          */
1239         switch (rotation + mirror * 4) {
1240         case OMAP_DSS_ROT_0:
1241         case OMAP_DSS_ROT_180:
1242                 /*
1243                  * If the pixel format is YUV or UYVY divide the width
1244                  * of the image by 2 for 0 and 180 degree rotation.
1245                  */
1246                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1247                         color_mode == OMAP_DSS_COLOR_UYVY)
1248                         width = width >> 1;
1249         case OMAP_DSS_ROT_90:
1250         case OMAP_DSS_ROT_270:
1251                 *offset1 = 0;
1252                 if (field_offset)
1253                         *offset0 = field_offset * screen_width * ps;
1254                 else
1255                         *offset0 = 0;
1256
1257                 *row_inc = pixinc(1 + (screen_width - width) +
1258                                 (fieldmode ? screen_width : 0),
1259                                 ps);
1260                 *pix_inc = pixinc(1, ps);
1261                 break;
1262
1263         case OMAP_DSS_ROT_0 + 4:
1264         case OMAP_DSS_ROT_180 + 4:
1265                 /* If the pixel format is YUV or UYVY divide the width
1266                  * of the image by 2  for 0 degree and 180 degree
1267                  */
1268                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1269                         color_mode == OMAP_DSS_COLOR_UYVY)
1270                         width = width >> 1;
1271         case OMAP_DSS_ROT_90 + 4:
1272         case OMAP_DSS_ROT_270 + 4:
1273                 *offset1 = 0;
1274                 if (field_offset)
1275                         *offset0 = field_offset * screen_width * ps;
1276                 else
1277                         *offset0 = 0;
1278                 *row_inc = pixinc(1 - (screen_width + width) -
1279                                 (fieldmode ? screen_width : 0),
1280                                 ps);
1281                 *pix_inc = pixinc(1, ps);
1282                 break;
1283
1284         default:
1285                 BUG();
1286         }
1287 }
1288
1289 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1290                 u16 screen_width,
1291                 u16 width, u16 height,
1292                 enum omap_color_mode color_mode, bool fieldmode,
1293                 unsigned int field_offset,
1294                 unsigned *offset0, unsigned *offset1,
1295                 s32 *row_inc, s32 *pix_inc)
1296 {
1297         u8 ps;
1298         u16 fbw, fbh;
1299
1300         /* FIXME CLUT formats */
1301         switch (color_mode) {
1302         case OMAP_DSS_COLOR_CLUT1:
1303         case OMAP_DSS_COLOR_CLUT2:
1304         case OMAP_DSS_COLOR_CLUT4:
1305         case OMAP_DSS_COLOR_CLUT8:
1306                 BUG();
1307                 return;
1308         default:
1309                 ps = color_mode_to_bpp(color_mode) / 8;
1310                 break;
1311         }
1312
1313         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1314                         width, height);
1315
1316         /* width & height are overlay sizes, convert to fb sizes */
1317
1318         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1319                 fbw = width;
1320                 fbh = height;
1321         } else {
1322                 fbw = height;
1323                 fbh = width;
1324         }
1325
1326         /*
1327          * field 0 = even field = bottom field
1328          * field 1 = odd field = top field
1329          */
1330         switch (rotation + mirror * 4) {
1331         case OMAP_DSS_ROT_0:
1332                 *offset1 = 0;
1333                 if (field_offset)
1334                         *offset0 = *offset1 + field_offset * screen_width * ps;
1335                 else
1336                         *offset0 = *offset1;
1337                 *row_inc = pixinc(1 + (screen_width - fbw) +
1338                                 (fieldmode ? screen_width : 0),
1339                                 ps);
1340                 *pix_inc = pixinc(1, ps);
1341                 break;
1342         case OMAP_DSS_ROT_90:
1343                 *offset1 = screen_width * (fbh - 1) * ps;
1344                 if (field_offset)
1345                         *offset0 = *offset1 + field_offset * ps;
1346                 else
1347                         *offset0 = *offset1;
1348                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1349                                 (fieldmode ? 1 : 0), ps);
1350                 *pix_inc = pixinc(-screen_width, ps);
1351                 break;
1352         case OMAP_DSS_ROT_180:
1353                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1354                 if (field_offset)
1355                         *offset0 = *offset1 - field_offset * screen_width * ps;
1356                 else
1357                         *offset0 = *offset1;
1358                 *row_inc = pixinc(-1 -
1359                                 (screen_width - fbw) -
1360                                 (fieldmode ? screen_width : 0),
1361                                 ps);
1362                 *pix_inc = pixinc(-1, ps);
1363                 break;
1364         case OMAP_DSS_ROT_270:
1365                 *offset1 = (fbw - 1) * ps;
1366                 if (field_offset)
1367                         *offset0 = *offset1 - field_offset * ps;
1368                 else
1369                         *offset0 = *offset1;
1370                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1371                                 (fieldmode ? 1 : 0), ps);
1372                 *pix_inc = pixinc(screen_width, ps);
1373                 break;
1374
1375         /* mirroring */
1376         case OMAP_DSS_ROT_0 + 4:
1377                 *offset1 = (fbw - 1) * ps;
1378                 if (field_offset)
1379                         *offset0 = *offset1 + field_offset * screen_width * ps;
1380                 else
1381                         *offset0 = *offset1;
1382                 *row_inc = pixinc(screen_width * 2 - 1 +
1383                                 (fieldmode ? screen_width : 0),
1384                                 ps);
1385                 *pix_inc = pixinc(-1, ps);
1386                 break;
1387
1388         case OMAP_DSS_ROT_90 + 4:
1389                 *offset1 = 0;
1390                 if (field_offset)
1391                         *offset0 = *offset1 + field_offset * ps;
1392                 else
1393                         *offset0 = *offset1;
1394                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1395                                 (fieldmode ? 1 : 0),
1396                                 ps);
1397                 *pix_inc = pixinc(screen_width, ps);
1398                 break;
1399
1400         case OMAP_DSS_ROT_180 + 4:
1401                 *offset1 = screen_width * (fbh - 1) * ps;
1402                 if (field_offset)
1403                         *offset0 = *offset1 - field_offset * screen_width * ps;
1404                 else
1405                         *offset0 = *offset1;
1406                 *row_inc = pixinc(1 - screen_width * 2 -
1407                                 (fieldmode ? screen_width : 0),
1408                                 ps);
1409                 *pix_inc = pixinc(1, ps);
1410                 break;
1411
1412         case OMAP_DSS_ROT_270 + 4:
1413                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1414                 if (field_offset)
1415                         *offset0 = *offset1 - field_offset * ps;
1416                 else
1417                         *offset0 = *offset1;
1418                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1419                                 (fieldmode ? 1 : 0),
1420                                 ps);
1421                 *pix_inc = pixinc(-screen_width, ps);
1422                 break;
1423
1424         default:
1425                 BUG();
1426         }
1427 }
1428
1429 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1430                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1431 {
1432         u32 fclk = 0;
1433         /* FIXME venc pclk? */
1434         u64 tmp, pclk = dispc_pclk_rate();
1435
1436         if (height > out_height) {
1437                 /* FIXME get real display PPL */
1438                 unsigned int ppl = 800;
1439
1440                 tmp = pclk * height * out_width;
1441                 do_div(tmp, 2 * out_height * ppl);
1442                 fclk = tmp;
1443
1444                 if (height > 2 * out_height) {
1445                         if (ppl == out_width)
1446                                 return 0;
1447
1448                         tmp = pclk * (height - 2 * out_height) * out_width;
1449                         do_div(tmp, 2 * out_height * (ppl - out_width));
1450                         fclk = max(fclk, (u32) tmp);
1451                 }
1452         }
1453
1454         if (width > out_width) {
1455                 tmp = pclk * width;
1456                 do_div(tmp, out_width);
1457                 fclk = max(fclk, (u32) tmp);
1458
1459                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1460                         fclk <<= 1;
1461         }
1462
1463         return fclk;
1464 }
1465
1466 static unsigned long calc_fclk(u16 width, u16 height,
1467                 u16 out_width, u16 out_height)
1468 {
1469         unsigned int hf, vf;
1470
1471         /*
1472          * FIXME how to determine the 'A' factor
1473          * for the no downscaling case ?
1474          */
1475
1476         if (width > 3 * out_width)
1477                 hf = 4;
1478         else if (width > 2 * out_width)
1479                 hf = 3;
1480         else if (width > out_width)
1481                 hf = 2;
1482         else
1483                 hf = 1;
1484
1485         if (height > out_height)
1486                 vf = 2;
1487         else
1488                 vf = 1;
1489
1490         /* FIXME venc pclk? */
1491         return dispc_pclk_rate() * vf * hf;
1492 }
1493
1494 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1495 {
1496         enable_clocks(1);
1497         _dispc_set_channel_out(plane, channel_out);
1498         enable_clocks(0);
1499 }
1500
1501 static int _dispc_setup_plane(enum omap_plane plane,
1502                 u32 paddr, u16 screen_width,
1503                 u16 pos_x, u16 pos_y,
1504                 u16 width, u16 height,
1505                 u16 out_width, u16 out_height,
1506                 enum omap_color_mode color_mode,
1507                 bool ilace,
1508                 enum omap_dss_rotation_type rotation_type,
1509                 u8 rotation, int mirror,
1510                 u8 global_alpha)
1511 {
1512         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1513         bool five_taps = 0;
1514         bool fieldmode = 0;
1515         int cconv = 0;
1516         unsigned offset0, offset1;
1517         s32 row_inc;
1518         s32 pix_inc;
1519         u16 frame_height = height;
1520         unsigned int field_offset = 0;
1521
1522         if (paddr == 0)
1523                 return -EINVAL;
1524
1525         if (ilace && height == out_height)
1526                 fieldmode = 1;
1527
1528         if (ilace) {
1529                 if (fieldmode)
1530                         height /= 2;
1531                 pos_y /= 2;
1532                 out_height /= 2;
1533
1534                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1535                                 "out_height %d\n",
1536                                 height, pos_y, out_height);
1537         }
1538
1539         if (plane == OMAP_DSS_GFX) {
1540                 if (width != out_width || height != out_height)
1541                         return -EINVAL;
1542
1543                 switch (color_mode) {
1544                 case OMAP_DSS_COLOR_ARGB16:
1545                 case OMAP_DSS_COLOR_ARGB32:
1546                 case OMAP_DSS_COLOR_RGBA32:
1547                         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1548                                 return -EINVAL;
1549                 case OMAP_DSS_COLOR_RGBX32:
1550                         if (cpu_is_omap24xx())
1551                                 return -EINVAL;
1552                         /* fall through */
1553                 case OMAP_DSS_COLOR_RGB12U:
1554                 case OMAP_DSS_COLOR_RGB16:
1555                 case OMAP_DSS_COLOR_RGB24P:
1556                 case OMAP_DSS_COLOR_RGB24U:
1557                         break;
1558
1559                 default:
1560                         return -EINVAL;
1561                 }
1562         } else {
1563                 /* video plane */
1564
1565                 unsigned long fclk = 0;
1566
1567                 if (out_width < width / maxdownscale ||
1568                    out_width > width * 8)
1569                         return -EINVAL;
1570
1571                 if (out_height < height / maxdownscale ||
1572                    out_height > height * 8)
1573                         return -EINVAL;
1574
1575                 switch (color_mode) {
1576                 case OMAP_DSS_COLOR_RGBX32:
1577                 case OMAP_DSS_COLOR_RGB12U:
1578                         if (cpu_is_omap24xx())
1579                                 return -EINVAL;
1580                         /* fall through */
1581                 case OMAP_DSS_COLOR_RGB16:
1582                 case OMAP_DSS_COLOR_RGB24P:
1583                 case OMAP_DSS_COLOR_RGB24U:
1584                         break;
1585
1586                 case OMAP_DSS_COLOR_ARGB16:
1587                 case OMAP_DSS_COLOR_ARGB32:
1588                 case OMAP_DSS_COLOR_RGBA32:
1589                         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1590                                 return -EINVAL;
1591                         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
1592                                         plane == OMAP_DSS_VIDEO1)
1593                                 return -EINVAL;
1594                         break;
1595
1596                 case OMAP_DSS_COLOR_YUV2:
1597                 case OMAP_DSS_COLOR_UYVY:
1598                         cconv = 1;
1599                         break;
1600
1601                 default:
1602                         return -EINVAL;
1603                 }
1604
1605                 /* Must use 5-tap filter? */
1606                 five_taps = height > out_height * 2;
1607
1608                 if (!five_taps) {
1609                         fclk = calc_fclk(width, height,
1610                                         out_width, out_height);
1611
1612                         /* Try 5-tap filter if 3-tap fclk is too high */
1613                         if (cpu_is_omap34xx() && height > out_height &&
1614                                         fclk > dispc_fclk_rate())
1615                                 five_taps = true;
1616                 }
1617
1618                 if (width > (2048 >> five_taps)) {
1619                         DSSERR("failed to set up scaling, fclk too low\n");
1620                         return -EINVAL;
1621                 }
1622
1623                 if (five_taps)
1624                         fclk = calc_fclk_five_taps(width, height,
1625                                         out_width, out_height, color_mode);
1626
1627                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1628                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1629
1630                 if (!fclk || fclk > dispc_fclk_rate()) {
1631                         DSSERR("failed to set up scaling, "
1632                                         "required fclk rate = %lu Hz, "
1633                                         "current fclk rate = %lu Hz\n",
1634                                         fclk, dispc_fclk_rate());
1635                         return -EINVAL;
1636                 }
1637         }
1638
1639         if (ilace && !fieldmode) {
1640                 /*
1641                  * when downscaling the bottom field may have to start several
1642                  * source lines below the top field. Unfortunately ACCUI
1643                  * registers will only hold the fractional part of the offset
1644                  * so the integer part must be added to the base address of the
1645                  * bottom field.
1646                  */
1647                 if (!height || height == out_height)
1648                         field_offset = 0;
1649                 else
1650                         field_offset = height / out_height / 2;
1651         }
1652
1653         /* Fields are independent but interleaved in memory. */
1654         if (fieldmode)
1655                 field_offset = 1;
1656
1657         if (rotation_type == OMAP_DSS_ROT_DMA)
1658                 calc_dma_rotation_offset(rotation, mirror,
1659                                 screen_width, width, frame_height, color_mode,
1660                                 fieldmode, field_offset,
1661                                 &offset0, &offset1, &row_inc, &pix_inc);
1662         else
1663                 calc_vrfb_rotation_offset(rotation, mirror,
1664                                 screen_width, width, frame_height, color_mode,
1665                                 fieldmode, field_offset,
1666                                 &offset0, &offset1, &row_inc, &pix_inc);
1667
1668         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1669                         offset0, offset1, row_inc, pix_inc);
1670
1671         _dispc_set_color_mode(plane, color_mode);
1672
1673         _dispc_set_plane_ba0(plane, paddr + offset0);
1674         _dispc_set_plane_ba1(plane, paddr + offset1);
1675
1676         _dispc_set_row_inc(plane, row_inc);
1677         _dispc_set_pix_inc(plane, pix_inc);
1678
1679         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1680                         out_width, out_height);
1681
1682         _dispc_set_plane_pos(plane, pos_x, pos_y);
1683
1684         _dispc_set_pic_size(plane, width, height);
1685
1686         if (plane != OMAP_DSS_GFX) {
1687                 _dispc_set_scaling(plane, width, height,
1688                                    out_width, out_height,
1689                                    ilace, five_taps, fieldmode);
1690                 _dispc_set_vid_size(plane, out_width, out_height);
1691                 _dispc_set_vid_color_conv(plane, cconv);
1692         }
1693
1694         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1695
1696         if (plane != OMAP_DSS_VIDEO1)
1697                 _dispc_setup_global_alpha(plane, global_alpha);
1698
1699         return 0;
1700 }
1701
1702 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1703 {
1704         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1705 }
1706
1707 static void dispc_disable_isr(void *data, u32 mask)
1708 {
1709         struct completion *compl = data;
1710         complete(compl);
1711 }
1712
1713 static void _enable_lcd_out(bool enable)
1714 {
1715         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1716 }
1717
1718 static void dispc_enable_lcd_out(bool enable)
1719 {
1720         struct completion frame_done_completion;
1721         bool is_on;
1722         int r;
1723
1724         enable_clocks(1);
1725
1726         /* When we disable LCD output, we need to wait until frame is done.
1727          * Otherwise the DSS is still working, and turning off the clocks
1728          * prevents DSS from going to OFF mode */
1729         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1730
1731         if (!enable && is_on) {
1732                 init_completion(&frame_done_completion);
1733
1734                 r = omap_dispc_register_isr(dispc_disable_isr,
1735                                 &frame_done_completion,
1736                                 DISPC_IRQ_FRAMEDONE);
1737
1738                 if (r)
1739                         DSSERR("failed to register FRAMEDONE isr\n");
1740         }
1741
1742         _enable_lcd_out(enable);
1743
1744         if (!enable && is_on) {
1745                 if (!wait_for_completion_timeout(&frame_done_completion,
1746                                         msecs_to_jiffies(100)))
1747                         DSSERR("timeout waiting for FRAME DONE\n");
1748
1749                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1750                                 &frame_done_completion,
1751                                 DISPC_IRQ_FRAMEDONE);
1752
1753                 if (r)
1754                         DSSERR("failed to unregister FRAMEDONE isr\n");
1755         }
1756
1757         enable_clocks(0);
1758 }
1759
1760 static void _enable_digit_out(bool enable)
1761 {
1762         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1763 }
1764
1765 static void dispc_enable_digit_out(bool enable)
1766 {
1767         struct completion frame_done_completion;
1768         int r;
1769
1770         enable_clocks(1);
1771
1772         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1773                 enable_clocks(0);
1774                 return;
1775         }
1776
1777         if (enable) {
1778                 unsigned long flags;
1779                 /* When we enable digit output, we'll get an extra digit
1780                  * sync lost interrupt, that we need to ignore */
1781                 spin_lock_irqsave(&dispc.irq_lock, flags);
1782                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1783                 _omap_dispc_set_irqs();
1784                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1785         }
1786
1787         /* When we disable digit output, we need to wait until fields are done.
1788          * Otherwise the DSS is still working, and turning off the clocks
1789          * prevents DSS from going to OFF mode. And when enabling, we need to
1790          * wait for the extra sync losts */
1791         init_completion(&frame_done_completion);
1792
1793         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1794                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1795         if (r)
1796                 DSSERR("failed to register EVSYNC isr\n");
1797
1798         _enable_digit_out(enable);
1799
1800         /* XXX I understand from TRM that we should only wait for the
1801          * current field to complete. But it seems we have to wait
1802          * for both fields */
1803         if (!wait_for_completion_timeout(&frame_done_completion,
1804                                 msecs_to_jiffies(100)))
1805                 DSSERR("timeout waiting for EVSYNC\n");
1806
1807         if (!wait_for_completion_timeout(&frame_done_completion,
1808                                 msecs_to_jiffies(100)))
1809                 DSSERR("timeout waiting for EVSYNC\n");
1810
1811         r = omap_dispc_unregister_isr(dispc_disable_isr,
1812                         &frame_done_completion,
1813                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1814         if (r)
1815                 DSSERR("failed to unregister EVSYNC isr\n");
1816
1817         if (enable) {
1818                 unsigned long flags;
1819                 spin_lock_irqsave(&dispc.irq_lock, flags);
1820                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1821                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1822                 _omap_dispc_set_irqs();
1823                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1824         }
1825
1826         enable_clocks(0);
1827 }
1828
1829 bool dispc_is_channel_enabled(enum omap_channel channel)
1830 {
1831         if (channel == OMAP_DSS_CHANNEL_LCD)
1832                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1833         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1834                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1835         else
1836                 BUG();
1837 }
1838
1839 void dispc_enable_channel(enum omap_channel channel, bool enable)
1840 {
1841         if (channel == OMAP_DSS_CHANNEL_LCD)
1842                 dispc_enable_lcd_out(enable);
1843         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1844                 dispc_enable_digit_out(enable);
1845         else
1846                 BUG();
1847 }
1848
1849 void dispc_lcd_enable_signal_polarity(bool act_high)
1850 {
1851         enable_clocks(1);
1852         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1853         enable_clocks(0);
1854 }
1855
1856 void dispc_lcd_enable_signal(bool enable)
1857 {
1858         enable_clocks(1);
1859         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1860         enable_clocks(0);
1861 }
1862
1863 void dispc_pck_free_enable(bool enable)
1864 {
1865         enable_clocks(1);
1866         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1867         enable_clocks(0);
1868 }
1869
1870 void dispc_enable_fifohandcheck(bool enable)
1871 {
1872         enable_clocks(1);
1873         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1874         enable_clocks(0);
1875 }
1876
1877
1878 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1879 {
1880         int mode;
1881
1882         switch (type) {
1883         case OMAP_DSS_LCD_DISPLAY_STN:
1884                 mode = 0;
1885                 break;
1886
1887         case OMAP_DSS_LCD_DISPLAY_TFT:
1888                 mode = 1;
1889                 break;
1890
1891         default:
1892                 BUG();
1893                 return;
1894         }
1895
1896         enable_clocks(1);
1897         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1898         enable_clocks(0);
1899 }
1900
1901 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1902 {
1903         enable_clocks(1);
1904         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1905         enable_clocks(0);
1906 }
1907
1908
1909 void dispc_set_default_color(enum omap_channel channel, u32 color)
1910 {
1911         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1912                                 DISPC_DEFAULT_COLOR1 };
1913
1914         enable_clocks(1);
1915         dispc_write_reg(def_reg[channel], color);
1916         enable_clocks(0);
1917 }
1918
1919 u32 dispc_get_default_color(enum omap_channel channel)
1920 {
1921         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1922                                 DISPC_DEFAULT_COLOR1 };
1923         u32 l;
1924
1925         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1926                channel != OMAP_DSS_CHANNEL_LCD);
1927
1928         enable_clocks(1);
1929         l = dispc_read_reg(def_reg[channel]);
1930         enable_clocks(0);
1931
1932         return l;
1933 }
1934
1935 void dispc_set_trans_key(enum omap_channel ch,
1936                 enum omap_dss_trans_key_type type,
1937                 u32 trans_key)
1938 {
1939         const struct dispc_reg tr_reg[] = {
1940                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1941
1942         enable_clocks(1);
1943         if (ch == OMAP_DSS_CHANNEL_LCD)
1944                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1945         else /* OMAP_DSS_CHANNEL_DIGIT */
1946                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1947
1948         dispc_write_reg(tr_reg[ch], trans_key);
1949         enable_clocks(0);
1950 }
1951
1952 void dispc_get_trans_key(enum omap_channel ch,
1953                 enum omap_dss_trans_key_type *type,
1954                 u32 *trans_key)
1955 {
1956         const struct dispc_reg tr_reg[] = {
1957                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1958
1959         enable_clocks(1);
1960         if (type) {
1961                 if (ch == OMAP_DSS_CHANNEL_LCD)
1962                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1963                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1964                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1965                 else
1966                         BUG();
1967         }
1968
1969         if (trans_key)
1970                 *trans_key = dispc_read_reg(tr_reg[ch]);
1971         enable_clocks(0);
1972 }
1973
1974 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1975 {
1976         enable_clocks(1);
1977         if (ch == OMAP_DSS_CHANNEL_LCD)
1978                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1979         else /* OMAP_DSS_CHANNEL_DIGIT */
1980                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1981         enable_clocks(0);
1982 }
1983 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1984 {
1985         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1986                 return;
1987
1988         enable_clocks(1);
1989         if (ch == OMAP_DSS_CHANNEL_LCD)
1990                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1991         else /* OMAP_DSS_CHANNEL_DIGIT */
1992                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1993         enable_clocks(0);
1994 }
1995 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1996 {
1997         bool enabled;
1998
1999         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2000                 return false;
2001
2002         enable_clocks(1);
2003         if (ch == OMAP_DSS_CHANNEL_LCD)
2004                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2005         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2006                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2007         else
2008                 BUG();
2009         enable_clocks(0);
2010
2011         return enabled;
2012
2013 }
2014
2015
2016 bool dispc_trans_key_enabled(enum omap_channel ch)
2017 {
2018         bool enabled;
2019
2020         enable_clocks(1);
2021         if (ch == OMAP_DSS_CHANNEL_LCD)
2022                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2023         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2024                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2025         else
2026                 BUG();
2027         enable_clocks(0);
2028
2029         return enabled;
2030 }
2031
2032
2033 void dispc_set_tft_data_lines(u8 data_lines)
2034 {
2035         int code;
2036
2037         switch (data_lines) {
2038         case 12:
2039                 code = 0;
2040                 break;
2041         case 16:
2042                 code = 1;
2043                 break;
2044         case 18:
2045                 code = 2;
2046                 break;
2047         case 24:
2048                 code = 3;
2049                 break;
2050         default:
2051                 BUG();
2052                 return;
2053         }
2054
2055         enable_clocks(1);
2056         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2057         enable_clocks(0);
2058 }
2059
2060 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2061 {
2062         u32 l;
2063         int stallmode;
2064         int gpout0 = 1;
2065         int gpout1;
2066
2067         switch (mode) {
2068         case OMAP_DSS_PARALLELMODE_BYPASS:
2069                 stallmode = 0;
2070                 gpout1 = 1;
2071                 break;
2072
2073         case OMAP_DSS_PARALLELMODE_RFBI:
2074                 stallmode = 1;
2075                 gpout1 = 0;
2076                 break;
2077
2078         case OMAP_DSS_PARALLELMODE_DSI:
2079                 stallmode = 1;
2080                 gpout1 = 1;
2081                 break;
2082
2083         default:
2084                 BUG();
2085                 return;
2086         }
2087
2088         enable_clocks(1);
2089
2090         l = dispc_read_reg(DISPC_CONTROL);
2091
2092         l = FLD_MOD(l, stallmode, 11, 11);
2093         l = FLD_MOD(l, gpout0, 15, 15);
2094         l = FLD_MOD(l, gpout1, 16, 16);
2095
2096         dispc_write_reg(DISPC_CONTROL, l);
2097
2098         enable_clocks(0);
2099 }
2100
2101 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2102                 int vsw, int vfp, int vbp)
2103 {
2104         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2105                 if (hsw < 1 || hsw > 64 ||
2106                                 hfp < 1 || hfp > 256 ||
2107                                 hbp < 1 || hbp > 256 ||
2108                                 vsw < 1 || vsw > 64 ||
2109                                 vfp < 0 || vfp > 255 ||
2110                                 vbp < 0 || vbp > 255)
2111                         return false;
2112         } else {
2113                 if (hsw < 1 || hsw > 256 ||
2114                                 hfp < 1 || hfp > 4096 ||
2115                                 hbp < 1 || hbp > 4096 ||
2116                                 vsw < 1 || vsw > 256 ||
2117                                 vfp < 0 || vfp > 4095 ||
2118                                 vbp < 0 || vbp > 4095)
2119                         return false;
2120         }
2121
2122         return true;
2123 }
2124
2125 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2126 {
2127         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2128                         timings->hbp, timings->vsw,
2129                         timings->vfp, timings->vbp);
2130 }
2131
2132 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2133                                    int vsw, int vfp, int vbp)
2134 {
2135         u32 timing_h, timing_v;
2136
2137         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2138                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2139                         FLD_VAL(hbp-1, 27, 20);
2140
2141                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2142                         FLD_VAL(vbp, 27, 20);
2143         } else {
2144                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2145                         FLD_VAL(hbp-1, 31, 20);
2146
2147                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2148                         FLD_VAL(vbp, 31, 20);
2149         }
2150
2151         enable_clocks(1);
2152         dispc_write_reg(DISPC_TIMING_H, timing_h);
2153         dispc_write_reg(DISPC_TIMING_V, timing_v);
2154         enable_clocks(0);
2155 }
2156
2157 /* change name to mode? */
2158 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2159 {
2160         unsigned xtot, ytot;
2161         unsigned long ht, vt;
2162
2163         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2164                                 timings->hbp, timings->vsw,
2165                                 timings->vfp, timings->vbp))
2166                 BUG();
2167
2168         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2169                         timings->vsw, timings->vfp, timings->vbp);
2170
2171         dispc_set_lcd_size(timings->x_res, timings->y_res);
2172
2173         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2174         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2175
2176         ht = (timings->pixel_clock * 1000) / xtot;
2177         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2178
2179         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2180         DSSDBG("pck %u\n", timings->pixel_clock);
2181         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2182                         timings->hsw, timings->hfp, timings->hbp,
2183                         timings->vsw, timings->vfp, timings->vbp);
2184
2185         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2186 }
2187
2188 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2189 {
2190         BUG_ON(lck_div < 1);
2191         BUG_ON(pck_div < 2);
2192
2193         enable_clocks(1);
2194         dispc_write_reg(DISPC_DIVISOR,
2195                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2196         enable_clocks(0);
2197 }
2198
2199 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2200 {
2201         u32 l;
2202         l = dispc_read_reg(DISPC_DIVISOR);
2203         *lck_div = FLD_GET(l, 23, 16);
2204         *pck_div = FLD_GET(l, 7, 0);
2205 }
2206
2207 unsigned long dispc_fclk_rate(void)
2208 {
2209         unsigned long r = 0;
2210
2211         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2212                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2213         else
2214 #ifdef CONFIG_OMAP2_DSS_DSI
2215                 r = dsi_get_dsi1_pll_rate();
2216 #else
2217         BUG();
2218 #endif
2219         return r;
2220 }
2221
2222 unsigned long dispc_lclk_rate(void)
2223 {
2224         int lcd;
2225         unsigned long r;
2226         u32 l;
2227
2228         l = dispc_read_reg(DISPC_DIVISOR);
2229
2230         lcd = FLD_GET(l, 23, 16);
2231
2232         r = dispc_fclk_rate();
2233
2234         return r / lcd;
2235 }
2236
2237 unsigned long dispc_pclk_rate(void)
2238 {
2239         int lcd, pcd;
2240         unsigned long r;
2241         u32 l;
2242
2243         l = dispc_read_reg(DISPC_DIVISOR);
2244
2245         lcd = FLD_GET(l, 23, 16);
2246         pcd = FLD_GET(l, 7, 0);
2247
2248         r = dispc_fclk_rate();
2249
2250         return r / lcd / pcd;
2251 }
2252
2253 void dispc_dump_clocks(struct seq_file *s)
2254 {
2255         int lcd, pcd;
2256
2257         enable_clocks(1);
2258
2259         dispc_get_lcd_divisor(&lcd, &pcd);
2260
2261         seq_printf(s, "- DISPC -\n");
2262
2263         seq_printf(s, "dispc fclk source = %s\n",
2264                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2265                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2266
2267         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2268         seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2269         seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2270
2271         enable_clocks(0);
2272 }
2273
2274 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2275 void dispc_dump_irqs(struct seq_file *s)
2276 {
2277         unsigned long flags;
2278         struct dispc_irq_stats stats;
2279
2280         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2281
2282         stats = dispc.irq_stats;
2283         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2284         dispc.irq_stats.last_reset = jiffies;
2285
2286         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2287
2288         seq_printf(s, "period %u ms\n",
2289                         jiffies_to_msecs(jiffies - stats.last_reset));
2290
2291         seq_printf(s, "irqs %d\n", stats.irq_count);
2292 #define PIS(x) \
2293         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2294
2295         PIS(FRAMEDONE);
2296         PIS(VSYNC);
2297         PIS(EVSYNC_EVEN);
2298         PIS(EVSYNC_ODD);
2299         PIS(ACBIAS_COUNT_STAT);
2300         PIS(PROG_LINE_NUM);
2301         PIS(GFX_FIFO_UNDERFLOW);
2302         PIS(GFX_END_WIN);
2303         PIS(PAL_GAMMA_MASK);
2304         PIS(OCP_ERR);
2305         PIS(VID1_FIFO_UNDERFLOW);
2306         PIS(VID1_END_WIN);
2307         PIS(VID2_FIFO_UNDERFLOW);
2308         PIS(VID2_END_WIN);
2309         PIS(SYNC_LOST);
2310         PIS(SYNC_LOST_DIGIT);
2311         PIS(WAKEUP);
2312 #undef PIS
2313 }
2314 #endif
2315
2316 void dispc_dump_regs(struct seq_file *s)
2317 {
2318 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2319
2320         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2321
2322         DUMPREG(DISPC_REVISION);
2323         DUMPREG(DISPC_SYSCONFIG);
2324         DUMPREG(DISPC_SYSSTATUS);
2325         DUMPREG(DISPC_IRQSTATUS);
2326         DUMPREG(DISPC_IRQENABLE);
2327         DUMPREG(DISPC_CONTROL);
2328         DUMPREG(DISPC_CONFIG);
2329         DUMPREG(DISPC_CAPABLE);
2330         DUMPREG(DISPC_DEFAULT_COLOR0);
2331         DUMPREG(DISPC_DEFAULT_COLOR1);
2332         DUMPREG(DISPC_TRANS_COLOR0);
2333         DUMPREG(DISPC_TRANS_COLOR1);
2334         DUMPREG(DISPC_LINE_STATUS);
2335         DUMPREG(DISPC_LINE_NUMBER);
2336         DUMPREG(DISPC_TIMING_H);
2337         DUMPREG(DISPC_TIMING_V);
2338         DUMPREG(DISPC_POL_FREQ);
2339         DUMPREG(DISPC_DIVISOR);
2340         DUMPREG(DISPC_GLOBAL_ALPHA);
2341         DUMPREG(DISPC_SIZE_DIG);
2342         DUMPREG(DISPC_SIZE_LCD);
2343
2344         DUMPREG(DISPC_GFX_BA0);
2345         DUMPREG(DISPC_GFX_BA1);
2346         DUMPREG(DISPC_GFX_POSITION);
2347         DUMPREG(DISPC_GFX_SIZE);
2348         DUMPREG(DISPC_GFX_ATTRIBUTES);
2349         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2350         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2351         DUMPREG(DISPC_GFX_ROW_INC);
2352         DUMPREG(DISPC_GFX_PIXEL_INC);
2353         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2354         DUMPREG(DISPC_GFX_TABLE_BA);
2355
2356         DUMPREG(DISPC_DATA_CYCLE1);
2357         DUMPREG(DISPC_DATA_CYCLE2);
2358         DUMPREG(DISPC_DATA_CYCLE3);
2359
2360         DUMPREG(DISPC_CPR_COEF_R);
2361         DUMPREG(DISPC_CPR_COEF_G);
2362         DUMPREG(DISPC_CPR_COEF_B);
2363
2364         DUMPREG(DISPC_GFX_PRELOAD);
2365
2366         DUMPREG(DISPC_VID_BA0(0));
2367         DUMPREG(DISPC_VID_BA1(0));
2368         DUMPREG(DISPC_VID_POSITION(0));
2369         DUMPREG(DISPC_VID_SIZE(0));
2370         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2371         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2372         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2373         DUMPREG(DISPC_VID_ROW_INC(0));
2374         DUMPREG(DISPC_VID_PIXEL_INC(0));
2375         DUMPREG(DISPC_VID_FIR(0));
2376         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2377         DUMPREG(DISPC_VID_ACCU0(0));
2378         DUMPREG(DISPC_VID_ACCU1(0));
2379
2380         DUMPREG(DISPC_VID_BA0(1));
2381         DUMPREG(DISPC_VID_BA1(1));
2382         DUMPREG(DISPC_VID_POSITION(1));
2383         DUMPREG(DISPC_VID_SIZE(1));
2384         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2385         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2386         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2387         DUMPREG(DISPC_VID_ROW_INC(1));
2388         DUMPREG(DISPC_VID_PIXEL_INC(1));
2389         DUMPREG(DISPC_VID_FIR(1));
2390         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2391         DUMPREG(DISPC_VID_ACCU0(1));
2392         DUMPREG(DISPC_VID_ACCU1(1));
2393
2394         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2395         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2396         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2397         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2398         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2399         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2400         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2401         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2402         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2403         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2404         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2405         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2406         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2407         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2408         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2409         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2410         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2411         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2412         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2413         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2414         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2415         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2416         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2417         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2418         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2419         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2420         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2421         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2422         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2423
2424         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2425         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2426         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2427         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2428         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2429         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2430         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2431         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2432         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2433         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2434         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2435         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2436         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2437         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2438         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2439         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2440         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2441         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2442         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2443         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2444         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2445         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2446         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2447         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2448         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2449         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2450         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2451         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2452         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2453
2454         DUMPREG(DISPC_VID_PRELOAD(0));
2455         DUMPREG(DISPC_VID_PRELOAD(1));
2456
2457         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2458 #undef DUMPREG
2459 }
2460
2461 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2462                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2463 {
2464         u32 l = 0;
2465
2466         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2467                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2468
2469         l |= FLD_VAL(onoff, 17, 17);
2470         l |= FLD_VAL(rf, 16, 16);
2471         l |= FLD_VAL(ieo, 15, 15);
2472         l |= FLD_VAL(ipc, 14, 14);
2473         l |= FLD_VAL(ihs, 13, 13);
2474         l |= FLD_VAL(ivs, 12, 12);
2475         l |= FLD_VAL(acbi, 11, 8);
2476         l |= FLD_VAL(acb, 7, 0);
2477
2478         enable_clocks(1);
2479         dispc_write_reg(DISPC_POL_FREQ, l);
2480         enable_clocks(0);
2481 }
2482
2483 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2484 {
2485         _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2486                         (config & OMAP_DSS_LCD_RF) != 0,
2487                         (config & OMAP_DSS_LCD_IEO) != 0,
2488                         (config & OMAP_DSS_LCD_IPC) != 0,
2489                         (config & OMAP_DSS_LCD_IHS) != 0,
2490                         (config & OMAP_DSS_LCD_IVS) != 0,
2491                         acbi, acb);
2492 }
2493
2494 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2495 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2496                 struct dispc_clock_info *cinfo)
2497 {
2498         u16 pcd_min = is_tft ? 2 : 3;
2499         unsigned long best_pck;
2500         u16 best_ld, cur_ld;
2501         u16 best_pd, cur_pd;
2502
2503         best_pck = 0;
2504         best_ld = 0;
2505         best_pd = 0;
2506
2507         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2508                 unsigned long lck = fck / cur_ld;
2509
2510                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2511                         unsigned long pck = lck / cur_pd;
2512                         long old_delta = abs(best_pck - req_pck);
2513                         long new_delta = abs(pck - req_pck);
2514
2515                         if (best_pck == 0 || new_delta < old_delta) {
2516                                 best_pck = pck;
2517                                 best_ld = cur_ld;
2518                                 best_pd = cur_pd;
2519
2520                                 if (pck == req_pck)
2521                                         goto found;
2522                         }
2523
2524                         if (pck < req_pck)
2525                                 break;
2526                 }
2527
2528                 if (lck / pcd_min < req_pck)
2529                         break;
2530         }
2531
2532 found:
2533         cinfo->lck_div = best_ld;
2534         cinfo->pck_div = best_pd;
2535         cinfo->lck = fck / cinfo->lck_div;
2536         cinfo->pck = cinfo->lck / cinfo->pck_div;
2537 }
2538
2539 /* calculate clock rates using dividers in cinfo */
2540 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2541                 struct dispc_clock_info *cinfo)
2542 {
2543         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2544                 return -EINVAL;
2545         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2546                 return -EINVAL;
2547
2548         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2549         cinfo->pck = cinfo->lck / cinfo->pck_div;
2550
2551         return 0;
2552 }
2553
2554 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2555 {
2556         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2557         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2558
2559         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2560
2561         return 0;
2562 }
2563
2564 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2565 {
2566         unsigned long fck;
2567
2568         fck = dispc_fclk_rate();
2569
2570         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2571         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2572
2573         cinfo->lck = fck / cinfo->lck_div;
2574         cinfo->pck = cinfo->lck / cinfo->pck_div;
2575
2576         return 0;
2577 }
2578
2579 /* dispc.irq_lock has to be locked by the caller */
2580 static void _omap_dispc_set_irqs(void)
2581 {
2582         u32 mask;
2583         u32 old_mask;
2584         int i;
2585         struct omap_dispc_isr_data *isr_data;
2586
2587         mask = dispc.irq_error_mask;
2588
2589         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2590                 isr_data = &dispc.registered_isr[i];
2591
2592                 if (isr_data->isr == NULL)
2593                         continue;
2594
2595                 mask |= isr_data->mask;
2596         }
2597
2598         enable_clocks(1);
2599
2600         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2601         /* clear the irqstatus for newly enabled irqs */
2602         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2603
2604         dispc_write_reg(DISPC_IRQENABLE, mask);
2605
2606         enable_clocks(0);
2607 }
2608
2609 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2610 {
2611         int i;
2612         int ret;
2613         unsigned long flags;
2614         struct omap_dispc_isr_data *isr_data;
2615
2616         if (isr == NULL)
2617                 return -EINVAL;
2618
2619         spin_lock_irqsave(&dispc.irq_lock, flags);
2620
2621         /* check for duplicate entry */
2622         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2623                 isr_data = &dispc.registered_isr[i];
2624                 if (isr_data->isr == isr && isr_data->arg == arg &&
2625                                 isr_data->mask == mask) {
2626                         ret = -EINVAL;
2627                         goto err;
2628                 }
2629         }
2630
2631         isr_data = NULL;
2632         ret = -EBUSY;
2633
2634         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2635                 isr_data = &dispc.registered_isr[i];
2636
2637                 if (isr_data->isr != NULL)
2638                         continue;
2639
2640                 isr_data->isr = isr;
2641                 isr_data->arg = arg;
2642                 isr_data->mask = mask;
2643                 ret = 0;
2644
2645                 break;
2646         }
2647
2648         _omap_dispc_set_irqs();
2649
2650         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2651
2652         return 0;
2653 err:
2654         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2655
2656         return ret;
2657 }
2658 EXPORT_SYMBOL(omap_dispc_register_isr);
2659
2660 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2661 {
2662         int i;
2663         unsigned long flags;
2664         int ret = -EINVAL;
2665         struct omap_dispc_isr_data *isr_data;
2666
2667         spin_lock_irqsave(&dispc.irq_lock, flags);
2668
2669         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2670                 isr_data = &dispc.registered_isr[i];
2671                 if (isr_data->isr != isr || isr_data->arg != arg ||
2672                                 isr_data->mask != mask)
2673                         continue;
2674
2675                 /* found the correct isr */
2676
2677                 isr_data->isr = NULL;
2678                 isr_data->arg = NULL;
2679                 isr_data->mask = 0;
2680
2681                 ret = 0;
2682                 break;
2683         }
2684
2685         if (ret == 0)
2686                 _omap_dispc_set_irqs();
2687
2688         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2689
2690         return ret;
2691 }
2692 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2693
2694 #ifdef DEBUG
2695 static void print_irq_status(u32 status)
2696 {
2697         if ((status & dispc.irq_error_mask) == 0)
2698                 return;
2699
2700         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2701
2702 #define PIS(x) \
2703         if (status & DISPC_IRQ_##x) \
2704                 printk(#x " ");
2705         PIS(GFX_FIFO_UNDERFLOW);
2706         PIS(OCP_ERR);
2707         PIS(VID1_FIFO_UNDERFLOW);
2708         PIS(VID2_FIFO_UNDERFLOW);
2709         PIS(SYNC_LOST);
2710         PIS(SYNC_LOST_DIGIT);
2711 #undef PIS
2712
2713         printk("\n");
2714 }
2715 #endif
2716
2717 /* Called from dss.c. Note that we don't touch clocks here,
2718  * but we presume they are on because we got an IRQ. However,
2719  * an irq handler may turn the clocks off, so we may not have
2720  * clock later in the function. */
2721 void dispc_irq_handler(void)
2722 {
2723         int i;
2724         u32 irqstatus;
2725         u32 handledirqs = 0;
2726         u32 unhandled_errors;
2727         struct omap_dispc_isr_data *isr_data;
2728         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2729
2730         spin_lock(&dispc.irq_lock);
2731
2732         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2733
2734 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2735         spin_lock(&dispc.irq_stats_lock);
2736         dispc.irq_stats.irq_count++;
2737         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2738         spin_unlock(&dispc.irq_stats_lock);
2739 #endif
2740
2741 #ifdef DEBUG
2742         if (dss_debug)
2743                 print_irq_status(irqstatus);
2744 #endif
2745         /* Ack the interrupt. Do it here before clocks are possibly turned
2746          * off */
2747         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2748         /* flush posted write */
2749         dispc_read_reg(DISPC_IRQSTATUS);
2750
2751         /* make a copy and unlock, so that isrs can unregister
2752          * themselves */
2753         memcpy(registered_isr, dispc.registered_isr,
2754                         sizeof(registered_isr));
2755
2756         spin_unlock(&dispc.irq_lock);
2757
2758         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2759                 isr_data = &registered_isr[i];
2760
2761                 if (!isr_data->isr)
2762                         continue;
2763
2764                 if (isr_data->mask & irqstatus) {
2765                         isr_data->isr(isr_data->arg, irqstatus);
2766                         handledirqs |= isr_data->mask;
2767                 }
2768         }
2769
2770         spin_lock(&dispc.irq_lock);
2771
2772         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2773
2774         if (unhandled_errors) {
2775                 dispc.error_irqs |= unhandled_errors;
2776
2777                 dispc.irq_error_mask &= ~unhandled_errors;
2778                 _omap_dispc_set_irqs();
2779
2780                 schedule_work(&dispc.error_work);
2781         }
2782
2783         spin_unlock(&dispc.irq_lock);
2784 }
2785
2786 static void dispc_error_worker(struct work_struct *work)
2787 {
2788         int i;
2789         u32 errors;
2790         unsigned long flags;
2791
2792         spin_lock_irqsave(&dispc.irq_lock, flags);
2793         errors = dispc.error_irqs;
2794         dispc.error_irqs = 0;
2795         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2796
2797         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2798                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2799                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2800                         struct omap_overlay *ovl;
2801                         ovl = omap_dss_get_overlay(i);
2802
2803                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2804                                 continue;
2805
2806                         if (ovl->id == 0) {
2807                                 dispc_enable_plane(ovl->id, 0);
2808                                 dispc_go(ovl->manager->id);
2809                                 mdelay(50);
2810                                 break;
2811                         }
2812                 }
2813         }
2814
2815         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2816                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2817                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2818                         struct omap_overlay *ovl;
2819                         ovl = omap_dss_get_overlay(i);
2820
2821                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2822                                 continue;
2823
2824                         if (ovl->id == 1) {
2825                                 dispc_enable_plane(ovl->id, 0);
2826                                 dispc_go(ovl->manager->id);
2827                                 mdelay(50);
2828                                 break;
2829                         }
2830                 }
2831         }
2832
2833         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2834                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2835                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2836                         struct omap_overlay *ovl;
2837                         ovl = omap_dss_get_overlay(i);
2838
2839                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2840                                 continue;
2841
2842                         if (ovl->id == 2) {
2843                                 dispc_enable_plane(ovl->id, 0);
2844                                 dispc_go(ovl->manager->id);
2845                                 mdelay(50);
2846                                 break;
2847                         }
2848                 }
2849         }
2850
2851         if (errors & DISPC_IRQ_SYNC_LOST) {
2852                 struct omap_overlay_manager *manager = NULL;
2853                 bool enable = false;
2854
2855                 DSSERR("SYNC_LOST, disabling LCD\n");
2856
2857                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2858                         struct omap_overlay_manager *mgr;
2859                         mgr = omap_dss_get_overlay_manager(i);
2860
2861                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2862                                 manager = mgr;
2863                                 enable = mgr->device->state ==
2864                                                 OMAP_DSS_DISPLAY_ACTIVE;
2865                                 mgr->device->driver->disable(mgr->device);
2866                                 break;
2867                         }
2868                 }
2869
2870                 if (manager) {
2871                         struct omap_dss_device *dssdev = manager->device;
2872                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2873                                 struct omap_overlay *ovl;
2874                                 ovl = omap_dss_get_overlay(i);
2875
2876                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2877                                         continue;
2878
2879                                 if (ovl->id != 0 && ovl->manager == manager)
2880                                         dispc_enable_plane(ovl->id, 0);
2881                         }
2882
2883                         dispc_go(manager->id);
2884                         mdelay(50);
2885                         if (enable)
2886                                 dssdev->driver->enable(dssdev);
2887                 }
2888         }
2889
2890         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2891                 struct omap_overlay_manager *manager = NULL;
2892                 bool enable = false;
2893
2894                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2895
2896                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2897                         struct omap_overlay_manager *mgr;
2898                         mgr = omap_dss_get_overlay_manager(i);
2899
2900                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2901                                 manager = mgr;
2902                                 enable = mgr->device->state ==
2903                                                 OMAP_DSS_DISPLAY_ACTIVE;
2904                                 mgr->device->driver->disable(mgr->device);
2905                                 break;
2906                         }
2907                 }
2908
2909                 if (manager) {
2910                         struct omap_dss_device *dssdev = manager->device;
2911                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2912                                 struct omap_overlay *ovl;
2913                                 ovl = omap_dss_get_overlay(i);
2914
2915                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2916                                         continue;
2917
2918                                 if (ovl->id != 0 && ovl->manager == manager)
2919                                         dispc_enable_plane(ovl->id, 0);
2920                         }
2921
2922                         dispc_go(manager->id);
2923                         mdelay(50);
2924                         if (enable)
2925                                 dssdev->driver->enable(dssdev);
2926                 }
2927         }
2928
2929         if (errors & DISPC_IRQ_OCP_ERR) {
2930                 DSSERR("OCP_ERR\n");
2931                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2932                         struct omap_overlay_manager *mgr;
2933                         mgr = omap_dss_get_overlay_manager(i);
2934
2935                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2936                                 mgr->device->driver->disable(mgr->device);
2937                 }
2938         }
2939
2940         spin_lock_irqsave(&dispc.irq_lock, flags);
2941         dispc.irq_error_mask |= errors;
2942         _omap_dispc_set_irqs();
2943         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2944 }
2945
2946 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2947 {
2948         void dispc_irq_wait_handler(void *data, u32 mask)
2949         {
2950                 complete((struct completion *)data);
2951         }
2952
2953         int r;
2954         DECLARE_COMPLETION_ONSTACK(completion);
2955
2956         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2957                         irqmask);
2958
2959         if (r)
2960                 return r;
2961
2962         timeout = wait_for_completion_timeout(&completion, timeout);
2963
2964         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2965
2966         if (timeout == 0)
2967                 return -ETIMEDOUT;
2968
2969         if (timeout == -ERESTARTSYS)
2970                 return -ERESTARTSYS;
2971
2972         return 0;
2973 }
2974
2975 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2976                 unsigned long timeout)
2977 {
2978         void dispc_irq_wait_handler(void *data, u32 mask)
2979         {
2980                 complete((struct completion *)data);
2981         }
2982
2983         int r;
2984         DECLARE_COMPLETION_ONSTACK(completion);
2985
2986         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2987                         irqmask);
2988
2989         if (r)
2990                 return r;
2991
2992         timeout = wait_for_completion_interruptible_timeout(&completion,
2993                         timeout);
2994
2995         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2996
2997         if (timeout == 0)
2998                 return -ETIMEDOUT;
2999
3000         if (timeout == -ERESTARTSYS)
3001                 return -ERESTARTSYS;
3002
3003         return 0;
3004 }
3005
3006 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3007 void dispc_fake_vsync_irq(void)
3008 {
3009         u32 irqstatus = DISPC_IRQ_VSYNC;
3010         int i;
3011
3012         WARN_ON(!in_interrupt());
3013
3014         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3015                 struct omap_dispc_isr_data *isr_data;
3016                 isr_data = &dispc.registered_isr[i];
3017
3018                 if (!isr_data->isr)
3019                         continue;
3020
3021                 if (isr_data->mask & irqstatus)
3022                         isr_data->isr(isr_data->arg, irqstatus);
3023         }
3024 }
3025 #endif
3026
3027 static void _omap_dispc_initialize_irq(void)
3028 {
3029         unsigned long flags;
3030
3031         spin_lock_irqsave(&dispc.irq_lock, flags);
3032
3033         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3034
3035         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3036
3037         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3038          * so clear it */
3039         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3040
3041         _omap_dispc_set_irqs();
3042
3043         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3044 }
3045
3046 void dispc_enable_sidle(void)
3047 {
3048         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3049 }
3050
3051 void dispc_disable_sidle(void)
3052 {
3053         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3054 }
3055
3056 static void _omap_dispc_initial_config(void)
3057 {
3058         u32 l;
3059
3060         l = dispc_read_reg(DISPC_SYSCONFIG);
3061         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3062         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3063         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3064         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3065         dispc_write_reg(DISPC_SYSCONFIG, l);
3066
3067         /* FUNCGATED */
3068         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3069
3070         /* L3 firewall setting: enable access to OCM RAM */
3071         /* XXX this should be somewhere in plat-omap */
3072         if (cpu_is_omap24xx())
3073                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3074
3075         _dispc_setup_color_conv_coef();
3076
3077         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3078
3079         dispc_read_plane_fifo_sizes();
3080 }
3081
3082 int dispc_init(void)
3083 {
3084         u32 rev;
3085
3086         spin_lock_init(&dispc.irq_lock);
3087
3088 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3089         spin_lock_init(&dispc.irq_stats_lock);
3090         dispc.irq_stats.last_reset = jiffies;
3091 #endif
3092
3093         INIT_WORK(&dispc.error_work, dispc_error_worker);
3094
3095         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3096         if (!dispc.base) {
3097                 DSSERR("can't ioremap DISPC\n");
3098                 return -ENOMEM;
3099         }
3100
3101         enable_clocks(1);
3102
3103         _omap_dispc_initial_config();
3104
3105         _omap_dispc_initialize_irq();
3106
3107         dispc_save_context();
3108
3109         rev = dispc_read_reg(DISPC_REVISION);
3110         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3111                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3112
3113         enable_clocks(0);
3114
3115         return 0;
3116 }
3117
3118 void dispc_exit(void)
3119 {
3120         iounmap(dispc.base);
3121 }
3122
3123 int dispc_enable_plane(enum omap_plane plane, bool enable)
3124 {
3125         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3126
3127         enable_clocks(1);
3128         _dispc_enable_plane(plane, enable);
3129         enable_clocks(0);
3130
3131         return 0;
3132 }
3133
3134 int dispc_setup_plane(enum omap_plane plane,
3135                        u32 paddr, u16 screen_width,
3136                        u16 pos_x, u16 pos_y,
3137                        u16 width, u16 height,
3138                        u16 out_width, u16 out_height,
3139                        enum omap_color_mode color_mode,
3140                        bool ilace,
3141                        enum omap_dss_rotation_type rotation_type,
3142                        u8 rotation, bool mirror, u8 global_alpha)
3143 {
3144         int r = 0;
3145
3146         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3147                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3148                plane, paddr, screen_width, pos_x, pos_y,
3149                width, height,
3150                out_width, out_height,
3151                ilace, color_mode,
3152                rotation, mirror);
3153
3154         enable_clocks(1);
3155
3156         r = _dispc_setup_plane(plane,
3157                            paddr, screen_width,
3158                            pos_x, pos_y,
3159                            width, height,
3160                            out_width, out_height,
3161                            color_mode, ilace,
3162                            rotation_type,
3163                            rotation, mirror,
3164                            global_alpha);
3165
3166         enable_clocks(0);
3167
3168         return r;
3169 }