2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
40 #include <plat/sram.h>
41 #include <plat/clock.h>
43 #include <video/omapdss.h>
46 #include "dss_features.h"
50 #define DISPC_SZ_REGS SZ_4K
52 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
59 #define DISPC_MAX_NR_ISRS 8
61 #define TABLE_SIZE (256 * 4)
63 struct omap_dispc_isr_data {
85 enum omap_burst_size {
91 #define REG_GET(idx, start, end) \
92 FLD_GET(dispc_read_reg(idx), start, end)
94 #define REG_FLD_MOD(idx, val, start, end) \
95 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
97 struct dispc_irq_stats {
98 unsigned long last_reset;
104 struct platform_device *pdev;
112 u32 fifo_size[MAX_DSS_OVERLAYS];
116 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
118 struct work_struct error_work;
121 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
123 /* palette/gamma table */
125 dma_addr_t table_phys;
127 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
128 spinlock_t irq_stats_lock;
129 struct dispc_irq_stats irq_stats;
133 enum omap_color_component {
134 /* used for all color formats for OMAP3 and earlier
135 * and for RGB and Y color component on OMAP4
137 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
138 /* used for UV component for
139 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
140 * color formats on OMAP4
142 DISPC_COLOR_COMPONENT_UV = 1 << 1,
145 static void _omap_dispc_set_irqs(void);
147 static inline void dispc_write_reg(const u16 idx, u32 val)
149 __raw_writel(val, dispc.base + idx);
152 static inline u32 dispc_read_reg(const u16 idx)
154 return __raw_readl(dispc.base + idx);
157 static int dispc_get_ctx_loss_count(void)
159 struct device *dev = &dispc.pdev->dev;
160 struct omap_display_platform_data *pdata = dev->platform_data;
161 struct omap_dss_board_info *board_data = pdata->board_data;
164 if (!board_data->get_context_loss_count)
167 cnt = board_data->get_context_loss_count(dev);
169 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
175 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
177 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
179 static void dispc_save_context(void)
183 DSSDBG("dispc_save_context\n");
189 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
190 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
192 if (dss_has_feature(FEAT_MGR_LCD2)) {
197 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
198 SR(DEFAULT_COLOR(i));
201 if (i == OMAP_DSS_CHANNEL_DIGIT)
212 if (dss_has_feature(FEAT_CPR)) {
219 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
224 SR(OVL_ATTRIBUTES(i));
225 SR(OVL_FIFO_THRESHOLD(i));
227 SR(OVL_PIXEL_INC(i));
228 if (dss_has_feature(FEAT_PRELOAD))
230 if (i == OMAP_DSS_GFX) {
231 SR(OVL_WINDOW_SKIP(i));
236 SR(OVL_PICTURE_SIZE(i));
240 for (j = 0; j < 8; j++)
241 SR(OVL_FIR_COEF_H(i, j));
243 for (j = 0; j < 8; j++)
244 SR(OVL_FIR_COEF_HV(i, j));
246 for (j = 0; j < 5; j++)
247 SR(OVL_CONV_COEF(i, j));
249 if (dss_has_feature(FEAT_FIR_COEF_V)) {
250 for (j = 0; j < 8; j++)
251 SR(OVL_FIR_COEF_V(i, j));
254 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
261 for (j = 0; j < 8; j++)
262 SR(OVL_FIR_COEF_H2(i, j));
264 for (j = 0; j < 8; j++)
265 SR(OVL_FIR_COEF_HV2(i, j));
267 for (j = 0; j < 8; j++)
268 SR(OVL_FIR_COEF_V2(i, j));
270 if (dss_has_feature(FEAT_ATTR2))
271 SR(OVL_ATTRIBUTES2(i));
274 if (dss_has_feature(FEAT_CORE_CLK_DIV))
277 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
278 dispc.ctx_valid = true;
280 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
283 static void dispc_restore_context(void)
287 DSSDBG("dispc_restore_context\n");
289 if (!dispc.ctx_valid)
292 ctx = dispc_get_ctx_loss_count();
294 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
297 DSSDBG("ctx_loss_count: saved %d, current %d\n",
298 dispc.ctx_loss_cnt, ctx);
304 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
305 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
307 if (dss_has_feature(FEAT_MGR_LCD2))
310 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
311 RR(DEFAULT_COLOR(i));
314 if (i == OMAP_DSS_CHANNEL_DIGIT)
325 if (dss_has_feature(FEAT_CPR)) {
332 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
337 RR(OVL_ATTRIBUTES(i));
338 RR(OVL_FIFO_THRESHOLD(i));
340 RR(OVL_PIXEL_INC(i));
341 if (dss_has_feature(FEAT_PRELOAD))
343 if (i == OMAP_DSS_GFX) {
344 RR(OVL_WINDOW_SKIP(i));
349 RR(OVL_PICTURE_SIZE(i));
353 for (j = 0; j < 8; j++)
354 RR(OVL_FIR_COEF_H(i, j));
356 for (j = 0; j < 8; j++)
357 RR(OVL_FIR_COEF_HV(i, j));
359 for (j = 0; j < 5; j++)
360 RR(OVL_CONV_COEF(i, j));
362 if (dss_has_feature(FEAT_FIR_COEF_V)) {
363 for (j = 0; j < 8; j++)
364 RR(OVL_FIR_COEF_V(i, j));
367 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
374 for (j = 0; j < 8; j++)
375 RR(OVL_FIR_COEF_H2(i, j));
377 for (j = 0; j < 8; j++)
378 RR(OVL_FIR_COEF_HV2(i, j));
380 for (j = 0; j < 8; j++)
381 RR(OVL_FIR_COEF_V2(i, j));
383 if (dss_has_feature(FEAT_ATTR2))
384 RR(OVL_ATTRIBUTES2(i));
387 if (dss_has_feature(FEAT_CORE_CLK_DIV))
390 /* enable last, because LCD & DIGIT enable are here */
392 if (dss_has_feature(FEAT_MGR_LCD2))
394 /* clear spurious SYNC_LOST_DIGIT interrupts */
395 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
398 * enable last so IRQs won't trigger before
399 * the context is fully restored
403 DSSDBG("context restored\n");
409 int dispc_runtime_get(void)
413 DSSDBG("dispc_runtime_get\n");
415 r = pm_runtime_get_sync(&dispc.pdev->dev);
417 return r < 0 ? r : 0;
419 EXPORT_SYMBOL(dispc_runtime_get);
421 void dispc_runtime_put(void)
425 DSSDBG("dispc_runtime_put\n");
427 r = pm_runtime_put_sync(&dispc.pdev->dev);
430 EXPORT_SYMBOL(dispc_runtime_put);
432 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
434 if (channel == OMAP_DSS_CHANNEL_LCD ||
435 channel == OMAP_DSS_CHANNEL_LCD2)
441 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
443 struct omap_overlay_manager *mgr =
444 omap_dss_get_overlay_manager(channel);
446 return mgr ? mgr->device : NULL;
449 bool dispc_mgr_go_busy(enum omap_channel channel)
453 if (dispc_mgr_is_lcd(channel))
456 bit = 6; /* GODIGIT */
458 if (channel == OMAP_DSS_CHANNEL_LCD2)
459 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
461 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
464 void dispc_mgr_go(enum omap_channel channel)
467 bool enable_bit, go_bit;
469 if (dispc_mgr_is_lcd(channel))
470 bit = 0; /* LCDENABLE */
472 bit = 1; /* DIGITALENABLE */
474 /* if the channel is not enabled, we don't need GO */
475 if (channel == OMAP_DSS_CHANNEL_LCD2)
476 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
478 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
483 if (dispc_mgr_is_lcd(channel))
486 bit = 6; /* GODIGIT */
488 if (channel == OMAP_DSS_CHANNEL_LCD2)
489 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
491 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
494 #if 0 /* pandora hack */
495 DSSERR("GO bit not down for channel %d\n", channel);
500 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
501 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
503 if (channel == OMAP_DSS_CHANNEL_LCD2)
504 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
506 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
509 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
511 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
514 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
516 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
519 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
521 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
524 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
526 BUG_ON(plane == OMAP_DSS_GFX);
528 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
531 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
534 BUG_ON(plane == OMAP_DSS_GFX);
536 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
539 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
541 BUG_ON(plane == OMAP_DSS_GFX);
543 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
546 /* Coefficients for horizontal up-sampling */
547 static struct dispc_h_coef coef_hup[8] = {
549 { -1, 13, 124, -8, 0 },
550 { -2, 30, 112, -11, -1 },
551 { -5, 51, 95, -11, -2 },
552 { 0, -9, 73, 73, -9 },
553 { -2, -11, 95, 51, -5 },
554 { -1, -11, 112, 30, -2 },
555 { 0, -8, 124, 13, -1 },
558 /* Coefficients for vertical up-sampling */
559 static struct dispc_v_coef coef_vup_3tap[8] = {
562 { 0, 12, 111, 5, 0 },
566 { 0, 5, 111, 12, 0 },
570 static struct dispc_v_coef coef_vup_5tap[8] = {
572 { -1, 13, 124, -8, 0 },
573 { -2, 30, 112, -11, -1 },
574 { -5, 51, 95, -11, -2 },
575 { 0, -9, 73, 73, -9 },
576 { -2, -11, 95, 51, -5 },
577 { -1, -11, 112, 30, -2 },
578 { 0, -8, 124, 13, -1 },
581 /* Coefficients for horizontal down-sampling */
582 static struct dispc_h_coef coef_hdown[8] = {
583 { 0, 36, 56, 36, 0 },
584 { 4, 40, 55, 31, -2 },
585 { 8, 44, 54, 27, -5 },
586 { 12, 48, 53, 22, -7 },
587 { -9, 17, 52, 51, 17 },
588 { -7, 22, 53, 48, 12 },
589 { -5, 27, 54, 44, 8 },
590 { -2, 31, 55, 40, 4 },
593 /* Coefficients for vertical down-sampling */
594 static struct dispc_v_coef coef_vdown_3tap[8] = {
595 { 0, 36, 56, 36, 0 },
596 { 0, 40, 57, 31, 0 },
597 { 0, 45, 56, 27, 0 },
598 { 0, 50, 55, 23, 0 },
599 { 0, 18, 55, 55, 0 },
600 { 0, 23, 55, 50, 0 },
601 { 0, 27, 56, 45, 0 },
602 { 0, 31, 57, 40, 0 },
605 static struct dispc_v_coef coef_vdown_5tap[8] = {
606 { 0, 36, 56, 36, 0 },
607 { 4, 40, 55, 31, -2 },
608 { 8, 44, 54, 27, -5 },
609 { 12, 48, 53, 22, -7 },
610 { -9, 17, 52, 51, 17 },
611 { -7, 22, 53, 48, 12 },
612 { -5, 27, 54, 44, 8 },
613 { -2, 31, 55, 40, 4 },
616 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
617 int vscaleup, int five_taps,
618 enum omap_color_component color_comp)
620 const struct dispc_h_coef *h_coef;
621 const struct dispc_v_coef *v_coef;
630 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
632 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
634 for (i = 0; i < 8; i++) {
637 h = FLD_VAL(h_coef[i].hc0, 7, 0)
638 | FLD_VAL(h_coef[i].hc1, 15, 8)
639 | FLD_VAL(h_coef[i].hc2, 23, 16)
640 | FLD_VAL(h_coef[i].hc3, 31, 24);
641 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
642 | FLD_VAL(v_coef[i].vc0, 15, 8)
643 | FLD_VAL(v_coef[i].vc1, 23, 16)
644 | FLD_VAL(v_coef[i].vc2, 31, 24);
646 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
647 dispc_ovl_write_firh_reg(plane, i, h);
648 dispc_ovl_write_firhv_reg(plane, i, hv);
650 dispc_ovl_write_firh2_reg(plane, i, h);
651 dispc_ovl_write_firhv2_reg(plane, i, hv);
657 for (i = 0; i < 8; i++) {
659 v = FLD_VAL(v_coef[i].vc00, 7, 0)
660 | FLD_VAL(v_coef[i].vc22, 15, 8);
661 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
662 dispc_ovl_write_firv_reg(plane, i, v);
664 dispc_ovl_write_firv2_reg(plane, i, v);
669 static struct dispc_h_coef *dispc_get_scale_coef_table(enum omap_plane plane,
670 enum omap_filter filter)
673 case OMAP_DSS_FILTER_UP_H:
675 case OMAP_DSS_FILTER_UP_V3:
676 /* XXX: relying on fact that h and v tables have same layout */
677 return (void *)coef_vup_3tap;
678 case OMAP_DSS_FILTER_UP_V5:
679 return (void *)coef_vup_5tap;
680 case OMAP_DSS_FILTER_DOWN_H:
682 case OMAP_DSS_FILTER_DOWN_V3:
683 return (void *)coef_vdown_3tap;
684 case OMAP_DSS_FILTER_DOWN_V5:
685 return (void *)coef_vdown_5tap;
691 void dispc_get_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
692 int phase, int *vals)
694 const struct dispc_h_coef *table;
696 if (phase < 0 || phase >= 8)
699 table = dispc_get_scale_coef_table(plane, filter);
704 vals[0] = table->hc4;
705 vals[1] = table->hc3;
706 vals[2] = table->hc2;
707 vals[3] = table->hc1;
708 vals[4] = table->hc0;
711 void dispc_set_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
712 int phase, const int *vals)
714 struct dispc_h_coef *table;
716 if (phase < 0 || phase >= 8)
719 table = dispc_get_scale_coef_table(plane, filter);
724 table->hc4 = vals[0];
725 table->hc3 = vals[1];
726 table->hc2 = vals[2];
727 table->hc1 = vals[3];
728 table->hc0 = vals[4];
731 static void _dispc_setup_color_conv_coef(void)
734 const struct color_conv_coef {
735 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
738 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
741 const struct color_conv_coef *ct;
743 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
747 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
748 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
749 CVAL(ct->rcr, ct->ry));
750 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
751 CVAL(ct->gy, ct->rcb));
752 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
753 CVAL(ct->gcb, ct->gcr));
754 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
755 CVAL(ct->bcr, ct->by));
756 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
759 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
767 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
769 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
772 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
774 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
777 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
779 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
782 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
784 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
787 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
789 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
791 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
794 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
796 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
798 if (plane == OMAP_DSS_GFX)
799 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
801 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
804 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
808 BUG_ON(plane == OMAP_DSS_GFX);
810 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
812 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
815 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
817 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
819 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
822 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
825 static void dispc_ovl_enable_zorder_planes(void)
829 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
832 for (i = 0; i < dss_feat_get_num_ovls(); i++)
833 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
836 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
838 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
840 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
843 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
846 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
848 static const unsigned shifts[] = { 0, 8, 16, 24, };
850 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
852 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
855 shift = shifts[plane];
856 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
859 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
861 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
864 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
866 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
869 static void dispc_ovl_set_color_mode(enum omap_plane plane,
870 enum omap_color_mode color_mode)
873 if (plane != OMAP_DSS_GFX) {
874 switch (color_mode) {
875 case OMAP_DSS_COLOR_NV12:
877 case OMAP_DSS_COLOR_RGB12U:
879 case OMAP_DSS_COLOR_RGBA16:
881 case OMAP_DSS_COLOR_RGBX16:
883 case OMAP_DSS_COLOR_ARGB16:
885 case OMAP_DSS_COLOR_RGB16:
887 case OMAP_DSS_COLOR_ARGB16_1555:
889 case OMAP_DSS_COLOR_RGB24U:
891 case OMAP_DSS_COLOR_RGB24P:
893 case OMAP_DSS_COLOR_YUV2:
895 case OMAP_DSS_COLOR_UYVY:
897 case OMAP_DSS_COLOR_ARGB32:
899 case OMAP_DSS_COLOR_RGBA32:
901 case OMAP_DSS_COLOR_RGBX32:
903 case OMAP_DSS_COLOR_XRGB16_1555:
909 switch (color_mode) {
910 case OMAP_DSS_COLOR_CLUT1:
912 case OMAP_DSS_COLOR_CLUT2:
914 case OMAP_DSS_COLOR_CLUT4:
916 case OMAP_DSS_COLOR_CLUT8:
918 case OMAP_DSS_COLOR_RGB12U:
920 case OMAP_DSS_COLOR_ARGB16:
922 case OMAP_DSS_COLOR_RGB16:
924 case OMAP_DSS_COLOR_ARGB16_1555:
926 case OMAP_DSS_COLOR_RGB24U:
928 case OMAP_DSS_COLOR_RGB24P:
930 case OMAP_DSS_COLOR_YUV2:
932 case OMAP_DSS_COLOR_UYVY:
934 case OMAP_DSS_COLOR_ARGB32:
936 case OMAP_DSS_COLOR_RGBA32:
938 case OMAP_DSS_COLOR_RGBX32:
940 case OMAP_DSS_COLOR_XRGB16_1555:
947 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
950 static void dispc_ovl_set_channel_out(enum omap_plane plane,
951 enum omap_channel channel)
955 int chan = 0, chan2 = 0;
961 case OMAP_DSS_VIDEO1:
962 case OMAP_DSS_VIDEO2:
963 case OMAP_DSS_VIDEO3:
971 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
972 if (dss_has_feature(FEAT_MGR_LCD2)) {
974 case OMAP_DSS_CHANNEL_LCD:
978 case OMAP_DSS_CHANNEL_DIGIT:
982 case OMAP_DSS_CHANNEL_LCD2:
990 val = FLD_MOD(val, chan, shift, shift);
991 val = FLD_MOD(val, chan2, 31, 30);
993 val = FLD_MOD(val, channel, shift, shift);
995 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
998 static void dispc_ovl_set_burst_size(enum omap_plane plane,
999 enum omap_burst_size burst_size)
1001 static const unsigned shifts[] = { 6, 14, 14, 14, };
1004 shift = shifts[plane];
1005 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1008 static void dispc_configure_burst_sizes(void)
1011 const int burst_size = BURST_SIZE_X8;
1013 /* Configure burst size always to maximum size */
1014 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1015 dispc_ovl_set_burst_size(i, burst_size);
1018 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1020 unsigned unit = dss_feat_get_burst_size_unit();
1021 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1025 void dispc_enable_gamma_table(bool enable)
1028 * This is partially implemented to support only disabling of
1032 DSSWARN("Gamma table enabling for TV not yet supported");
1036 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1039 void dispc_set_gamma_table(void *table, u32 size)
1041 if (table == NULL || size == 0 || size > TABLE_SIZE) {
1042 REG_FLD_MOD(DISPC_CONFIG, 0, 3, 3);
1046 memcpy(dispc.table_virt, table, size);
1048 dispc_write_reg(DISPC_OVL_TABLE_BA(0), dispc.table_phys);
1049 dispc_set_loadmode(OMAP_DSS_LOAD_CLUT_ONCE_FRAME);
1050 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
1053 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1057 if (channel == OMAP_DSS_CHANNEL_LCD)
1059 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1060 reg = DISPC_CONFIG2;
1064 REG_FLD_MOD(reg, enable, 15, 15);
1067 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1068 struct omap_dss_cpr_coefs *coefs)
1070 u32 coef_r, coef_g, coef_b;
1072 if (!dispc_mgr_is_lcd(channel))
1075 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1076 FLD_VAL(coefs->rb, 9, 0);
1077 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1078 FLD_VAL(coefs->gb, 9, 0);
1079 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1080 FLD_VAL(coefs->bb, 9, 0);
1082 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1083 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1084 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1087 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1091 BUG_ON(plane == OMAP_DSS_GFX);
1093 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1094 val = FLD_MOD(val, enable, 9, 9);
1095 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1098 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1100 static const unsigned shifts[] = { 5, 10, 10, 10 };
1103 shift = shifts[plane];
1104 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1107 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1110 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1111 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1112 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1115 void dispc_set_digit_size(u16 width, u16 height)
1118 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1119 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1120 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1123 static void dispc_read_plane_fifo_sizes(void)
1130 unit = dss_feat_get_buffer_size_unit();
1132 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1134 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1135 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1137 dispc.fifo_size[plane] = size;
1141 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1143 return dispc.fifo_size[plane];
1146 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1149 u8 hi_start, hi_end, lo_start, lo_end;
1152 unit = dss_feat_get_buffer_size_unit();
1154 WARN_ON(low % unit != 0);
1155 WARN_ON(high % unit != 0);
1160 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1161 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1163 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1165 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1167 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1171 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1172 FLD_VAL(high, hi_start, hi_end) |
1173 FLD_VAL(low, lo_start, lo_end));
1176 void dispc_enable_fifomerge(bool enable)
1178 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1179 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1182 static void dispc_ovl_set_fir(enum omap_plane plane,
1184 enum omap_color_component color_comp)
1188 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1189 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1191 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1192 &hinc_start, &hinc_end);
1193 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1194 &vinc_start, &vinc_end);
1195 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1196 FLD_VAL(hinc, hinc_start, hinc_end);
1198 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1200 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1201 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1205 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1208 u8 hor_start, hor_end, vert_start, vert_end;
1210 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1211 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1213 val = FLD_VAL(vaccu, vert_start, vert_end) |
1214 FLD_VAL(haccu, hor_start, hor_end);
1216 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1219 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1222 u8 hor_start, hor_end, vert_start, vert_end;
1224 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1225 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1227 val = FLD_VAL(vaccu, vert_start, vert_end) |
1228 FLD_VAL(haccu, hor_start, hor_end);
1230 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1233 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1238 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1239 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1242 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1247 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1248 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1251 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1252 u16 orig_width, u16 orig_height,
1253 u16 out_width, u16 out_height,
1254 bool five_taps, u8 rotation,
1255 enum omap_color_component color_comp)
1257 int fir_hinc, fir_vinc;
1258 int hscaleup, vscaleup;
1260 hscaleup = orig_width <= out_width;
1261 vscaleup = orig_height <= out_height;
1263 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1266 fir_hinc = 1024 * orig_width / out_width;
1267 fir_vinc = 1024 * orig_height / out_height;
1269 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1272 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1273 u16 orig_width, u16 orig_height,
1274 u16 out_width, u16 out_height,
1275 bool ilace, bool five_taps,
1276 bool fieldmode, enum omap_color_mode color_mode,
1283 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1284 out_width, out_height, five_taps,
1285 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1286 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1288 /* RESIZEENABLE and VERTICALTAPS */
1289 l &= ~((0x3 << 5) | (0x1 << 21));
1290 l |= (orig_width != out_width) ? (1 << 5) : 0;
1291 l |= (orig_height != out_height) ? (1 << 6) : 0;
1292 l |= five_taps ? (1 << 21) : 0;
1294 /* VRESIZECONF and HRESIZECONF */
1295 if (dss_has_feature(FEAT_RESIZECONF)) {
1297 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1298 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1301 /* LINEBUFFERSPLIT */
1302 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1304 l |= five_taps ? (1 << 22) : 0;
1307 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1310 * field 0 = even field = bottom field
1311 * field 1 = odd field = top field
1313 if (ilace && !fieldmode) {
1315 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1316 if (accu0 >= 1024/2) {
1322 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1323 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1326 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1327 u16 orig_width, u16 orig_height,
1328 u16 out_width, u16 out_height,
1329 bool ilace, bool five_taps,
1330 bool fieldmode, enum omap_color_mode color_mode,
1333 int scale_x = out_width != orig_width;
1334 int scale_y = out_height != orig_height;
1336 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1338 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1339 color_mode != OMAP_DSS_COLOR_UYVY &&
1340 color_mode != OMAP_DSS_COLOR_NV12)) {
1341 /* reset chroma resampling for RGB formats */
1342 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1345 switch (color_mode) {
1346 case OMAP_DSS_COLOR_NV12:
1347 /* UV is subsampled by 2 vertically*/
1349 /* UV is subsampled by 2 horz.*/
1352 case OMAP_DSS_COLOR_YUV2:
1353 case OMAP_DSS_COLOR_UYVY:
1354 /*For YUV422 with 90/270 rotation,
1355 *we don't upsample chroma
1357 if (rotation == OMAP_DSS_ROT_0 ||
1358 rotation == OMAP_DSS_ROT_180)
1359 /* UV is subsampled by 2 hrz*/
1361 /* must use FIR for YUV422 if rotated */
1362 if (rotation != OMAP_DSS_ROT_0)
1363 scale_x = scale_y = true;
1369 if (out_width != orig_width)
1371 if (out_height != orig_height)
1374 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1375 out_width, out_height, five_taps,
1376 rotation, DISPC_COLOR_COMPONENT_UV);
1378 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1379 (scale_x || scale_y) ? 1 : 0, 8, 8);
1381 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1383 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1385 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1386 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1389 static void dispc_ovl_set_scaling(enum omap_plane plane,
1390 u16 orig_width, u16 orig_height,
1391 u16 out_width, u16 out_height,
1392 bool ilace, bool five_taps,
1393 bool fieldmode, enum omap_color_mode color_mode,
1396 BUG_ON(plane == OMAP_DSS_GFX);
1398 dispc_ovl_set_scaling_common(plane,
1399 orig_width, orig_height,
1400 out_width, out_height,
1402 fieldmode, color_mode,
1405 dispc_ovl_set_scaling_uv(plane,
1406 orig_width, orig_height,
1407 out_width, out_height,
1409 fieldmode, color_mode,
1413 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1414 bool mirroring, enum omap_color_mode color_mode)
1416 bool row_repeat = false;
1419 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1420 color_mode == OMAP_DSS_COLOR_UYVY) {
1424 case OMAP_DSS_ROT_0:
1427 case OMAP_DSS_ROT_90:
1430 case OMAP_DSS_ROT_180:
1433 case OMAP_DSS_ROT_270:
1439 case OMAP_DSS_ROT_0:
1442 case OMAP_DSS_ROT_90:
1445 case OMAP_DSS_ROT_180:
1448 case OMAP_DSS_ROT_270:
1454 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1460 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1461 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1462 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1463 row_repeat ? 1 : 0, 18, 18);
1466 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1468 switch (color_mode) {
1469 case OMAP_DSS_COLOR_CLUT1:
1471 case OMAP_DSS_COLOR_CLUT2:
1473 case OMAP_DSS_COLOR_CLUT4:
1475 case OMAP_DSS_COLOR_CLUT8:
1476 case OMAP_DSS_COLOR_NV12:
1478 case OMAP_DSS_COLOR_RGB12U:
1479 case OMAP_DSS_COLOR_RGB16:
1480 case OMAP_DSS_COLOR_ARGB16:
1481 case OMAP_DSS_COLOR_YUV2:
1482 case OMAP_DSS_COLOR_UYVY:
1483 case OMAP_DSS_COLOR_RGBA16:
1484 case OMAP_DSS_COLOR_RGBX16:
1485 case OMAP_DSS_COLOR_ARGB16_1555:
1486 case OMAP_DSS_COLOR_XRGB16_1555:
1488 case OMAP_DSS_COLOR_RGB24P:
1490 case OMAP_DSS_COLOR_RGB24U:
1491 case OMAP_DSS_COLOR_ARGB32:
1492 case OMAP_DSS_COLOR_RGBA32:
1493 case OMAP_DSS_COLOR_RGBX32:
1500 static s32 pixinc(int pixels, u8 ps)
1504 else if (pixels > 1)
1505 return 1 + (pixels - 1) * ps;
1506 else if (pixels < 0)
1507 return 1 - (-pixels + 1) * ps;
1512 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1514 u16 width, u16 height,
1515 enum omap_color_mode color_mode, bool fieldmode,
1516 unsigned int field_offset,
1517 unsigned *offset0, unsigned *offset1,
1518 s32 *row_inc, s32 *pix_inc)
1522 /* FIXME CLUT formats */
1523 switch (color_mode) {
1524 case OMAP_DSS_COLOR_CLUT1:
1525 case OMAP_DSS_COLOR_CLUT2:
1526 case OMAP_DSS_COLOR_CLUT4:
1527 case OMAP_DSS_COLOR_CLUT8:
1530 case OMAP_DSS_COLOR_YUV2:
1531 case OMAP_DSS_COLOR_UYVY:
1535 ps = color_mode_to_bpp(color_mode) / 8;
1539 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1543 * field 0 = even field = bottom field
1544 * field 1 = odd field = top field
1546 switch (rotation + mirror * 4) {
1547 case OMAP_DSS_ROT_0:
1548 case OMAP_DSS_ROT_180:
1550 * If the pixel format is YUV or UYVY divide the width
1551 * of the image by 2 for 0 and 180 degree rotation.
1553 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1554 color_mode == OMAP_DSS_COLOR_UYVY)
1556 case OMAP_DSS_ROT_90:
1557 case OMAP_DSS_ROT_270:
1560 *offset0 = field_offset * screen_width * ps;
1564 *row_inc = pixinc(1 + (screen_width - width) +
1565 (fieldmode ? screen_width : 0),
1567 *pix_inc = pixinc(1, ps);
1570 case OMAP_DSS_ROT_0 + 4:
1571 case OMAP_DSS_ROT_180 + 4:
1572 /* If the pixel format is YUV or UYVY divide the width
1573 * of the image by 2 for 0 degree and 180 degree
1575 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1576 color_mode == OMAP_DSS_COLOR_UYVY)
1578 case OMAP_DSS_ROT_90 + 4:
1579 case OMAP_DSS_ROT_270 + 4:
1582 *offset0 = field_offset * screen_width * ps;
1585 *row_inc = pixinc(1 - (screen_width + width) -
1586 (fieldmode ? screen_width : 0),
1588 *pix_inc = pixinc(1, ps);
1596 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1598 u16 width, u16 height,
1599 enum omap_color_mode color_mode, bool fieldmode,
1600 unsigned int field_offset,
1601 unsigned *offset0, unsigned *offset1,
1602 s32 *row_inc, s32 *pix_inc)
1607 /* FIXME CLUT formats */
1608 switch (color_mode) {
1609 case OMAP_DSS_COLOR_CLUT1:
1610 case OMAP_DSS_COLOR_CLUT2:
1611 case OMAP_DSS_COLOR_CLUT4:
1612 case OMAP_DSS_COLOR_CLUT8:
1616 ps = color_mode_to_bpp(color_mode) / 8;
1620 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1623 /* width & height are overlay sizes, convert to fb sizes */
1625 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1634 * field 0 = even field = bottom field
1635 * field 1 = odd field = top field
1637 switch (rotation + mirror * 4) {
1638 case OMAP_DSS_ROT_0:
1641 *offset0 = *offset1 + field_offset * screen_width * ps;
1643 *offset0 = *offset1;
1644 *row_inc = pixinc(1 + (screen_width - fbw) +
1645 (fieldmode ? screen_width : 0),
1647 *pix_inc = pixinc(1, ps);
1649 case OMAP_DSS_ROT_90:
1650 *offset1 = screen_width * (fbh - 1) * ps;
1652 *offset0 = *offset1 + field_offset * ps;
1654 *offset0 = *offset1;
1655 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1656 (fieldmode ? 1 : 0), ps);
1657 *pix_inc = pixinc(-screen_width, ps);
1659 case OMAP_DSS_ROT_180:
1660 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1662 *offset0 = *offset1 - field_offset * screen_width * ps;
1664 *offset0 = *offset1;
1665 *row_inc = pixinc(-1 -
1666 (screen_width - fbw) -
1667 (fieldmode ? screen_width : 0),
1669 *pix_inc = pixinc(-1, ps);
1671 case OMAP_DSS_ROT_270:
1672 *offset1 = (fbw - 1) * ps;
1674 *offset0 = *offset1 - field_offset * ps;
1676 *offset0 = *offset1;
1677 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1678 (fieldmode ? 1 : 0), ps);
1679 *pix_inc = pixinc(screen_width, ps);
1683 case OMAP_DSS_ROT_0 + 4:
1684 *offset1 = (fbw - 1) * ps;
1686 *offset0 = *offset1 + field_offset * screen_width * ps;
1688 *offset0 = *offset1;
1689 *row_inc = pixinc(screen_width * 2 - 1 +
1690 (fieldmode ? screen_width : 0),
1692 *pix_inc = pixinc(-1, ps);
1695 case OMAP_DSS_ROT_90 + 4:
1698 *offset0 = *offset1 + field_offset * ps;
1700 *offset0 = *offset1;
1701 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1702 (fieldmode ? 1 : 0),
1704 *pix_inc = pixinc(screen_width, ps);
1707 case OMAP_DSS_ROT_180 + 4:
1708 *offset1 = screen_width * (fbh - 1) * ps;
1710 *offset0 = *offset1 - field_offset * screen_width * ps;
1712 *offset0 = *offset1;
1713 *row_inc = pixinc(1 - screen_width * 2 -
1714 (fieldmode ? screen_width : 0),
1716 *pix_inc = pixinc(1, ps);
1719 case OMAP_DSS_ROT_270 + 4:
1720 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1722 *offset0 = *offset1 - field_offset * ps;
1724 *offset0 = *offset1;
1725 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1726 (fieldmode ? 1 : 0),
1728 *pix_inc = pixinc(-screen_width, ps);
1736 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1737 u16 height, u16 out_width, u16 out_height,
1738 enum omap_color_mode color_mode)
1741 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1743 if (height > out_height) {
1744 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1745 unsigned int ppl = dssdev->panel.timings.x_res;
1747 tmp = pclk * height * out_width;
1748 do_div(tmp, 2 * out_height * ppl);
1751 if (height > 2 * out_height) {
1752 if (ppl == out_width)
1755 tmp = pclk * (height - 2 * out_height) * out_width;
1756 do_div(tmp, 2 * out_height * (ppl - out_width));
1757 fclk = max(fclk, (u32) tmp);
1761 if (width > out_width) {
1763 do_div(tmp, out_width);
1764 fclk = max(fclk, (u32) tmp);
1766 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1773 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1774 u16 height, u16 out_width, u16 out_height)
1776 unsigned int hf, vf;
1779 * FIXME how to determine the 'A' factor
1780 * for the no downscaling case ?
1783 if (width > 3 * out_width)
1785 else if (width > 2 * out_width)
1787 else if (width > out_width)
1792 if (height > out_height)
1797 return dispc_mgr_pclk_rate(channel) * vf * hf;
1800 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1801 enum omap_channel channel, u16 width, u16 height,
1802 u16 out_width, u16 out_height,
1803 enum omap_color_mode color_mode, bool *five_taps)
1805 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1806 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1807 unsigned long fclk = 0;
1809 if (width == out_width && height == out_height)
1812 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1815 if (out_width < width / maxdownscale ||
1816 out_width > width * 8)
1819 if (out_height < height / maxdownscale ||
1820 out_height > height * 8)
1823 /* Must use 5-tap filter? */
1824 *five_taps = height > out_height * 2;
1827 fclk = calc_fclk(channel, width, height, out_width,
1830 /* Try 5-tap filter if 3-tap fclk is too high */
1831 if (cpu_is_omap34xx() && height > out_height &&
1832 fclk > dispc_fclk_rate())
1836 if (width > (2048 >> *five_taps)) {
1837 DSSERR("failed to set up scaling, fclk too low\n");
1842 fclk = calc_fclk_five_taps(channel, width, height,
1843 out_width, out_height, color_mode);
1845 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1846 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1848 if (!fclk || fclk > dispc_fclk_rate()) {
1849 DSSERR("failed to set up scaling, "
1850 "required fclk rate = %lu Hz, "
1851 "current fclk rate = %lu Hz\n",
1852 fclk, dispc_fclk_rate());
1859 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1860 bool ilace, enum omap_channel channel, bool replication,
1861 u32 fifo_low, u32 fifo_high)
1863 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1864 bool five_taps = false;
1867 unsigned offset0, offset1;
1870 u16 frame_height = oi->height;
1871 unsigned int field_offset = 0;
1873 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1874 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1875 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1876 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1877 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1878 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1883 if (ilace && oi->height == oi->out_height)
1890 oi->out_height /= 2;
1892 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1894 oi->height, oi->pos_y, oi->out_height);
1897 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1900 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1901 oi->out_width, oi->out_height, oi->color_mode,
1906 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1907 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1908 oi->color_mode == OMAP_DSS_COLOR_NV12)
1911 if (ilace && !fieldmode) {
1913 * when downscaling the bottom field may have to start several
1914 * source lines below the top field. Unfortunately ACCUI
1915 * registers will only hold the fractional part of the offset
1916 * so the integer part must be added to the base address of the
1919 if (!oi->height || oi->height == oi->out_height)
1922 field_offset = oi->height / oi->out_height / 2;
1925 /* Fields are independent but interleaved in memory. */
1929 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1930 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1931 oi->screen_width, oi->width, frame_height,
1932 oi->color_mode, fieldmode, field_offset,
1933 &offset0, &offset1, &row_inc, &pix_inc);
1935 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1936 oi->screen_width, oi->width, frame_height,
1937 oi->color_mode, fieldmode, field_offset,
1938 &offset0, &offset1, &row_inc, &pix_inc);
1940 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1941 offset0, offset1, row_inc, pix_inc);
1943 dispc_ovl_set_color_mode(plane, oi->color_mode);
1945 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1946 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1948 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1949 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1950 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1954 dispc_ovl_set_row_inc(plane, row_inc);
1955 dispc_ovl_set_pix_inc(plane, pix_inc);
1957 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1958 oi->height, oi->out_width, oi->out_height);
1960 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1962 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1964 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1965 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1966 oi->out_width, oi->out_height,
1967 ilace, five_taps, fieldmode,
1968 oi->color_mode, oi->rotation);
1969 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1970 dispc_ovl_set_vid_color_conv(plane, cconv);
1973 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1976 dispc_ovl_set_zorder(plane, oi->zorder);
1977 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1978 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1980 dispc_ovl_set_channel_out(plane, channel);
1982 dispc_ovl_enable_replication(plane, replication);
1983 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1988 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1990 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1992 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1997 static void dispc_disable_isr(void *data, u32 mask)
1999 struct completion *compl = data;
2003 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2005 if (channel == OMAP_DSS_CHANNEL_LCD2)
2006 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2008 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
2011 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2013 struct completion frame_done_completion;
2018 /* When we disable LCD output, we need to wait until frame is done.
2019 * Otherwise the DSS is still working, and turning off the clocks
2020 * prevents DSS from going to OFF mode */
2021 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2022 REG_GET(DISPC_CONTROL2, 0, 0) :
2023 REG_GET(DISPC_CONTROL, 0, 0);
2025 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2026 DISPC_IRQ_FRAMEDONE;
2028 if (!enable && is_on) {
2029 init_completion(&frame_done_completion);
2031 r = omap_dispc_register_isr(dispc_disable_isr,
2032 &frame_done_completion, irq);
2035 DSSERR("failed to register FRAMEDONE isr\n");
2038 _enable_lcd_out(channel, enable);
2040 if (!enable && is_on) {
2041 if (!wait_for_completion_timeout(&frame_done_completion,
2042 msecs_to_jiffies(100)))
2043 DSSERR("timeout waiting for FRAME DONE\n");
2045 r = omap_dispc_unregister_isr(dispc_disable_isr,
2046 &frame_done_completion, irq);
2049 DSSERR("failed to unregister FRAMEDONE isr\n");
2053 static void _enable_digit_out(bool enable)
2055 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2058 static void dispc_mgr_enable_digit_out(bool enable)
2060 struct completion frame_done_completion;
2061 enum dss_hdmi_venc_clk_source_select src;
2066 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2069 src = dss_get_hdmi_venc_clk_source();
2072 unsigned long flags;
2073 /* When we enable digit output, we'll get an extra digit
2074 * sync lost interrupt, that we need to ignore */
2075 spin_lock_irqsave(&dispc.irq_lock, flags);
2076 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2077 _omap_dispc_set_irqs();
2078 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2081 /* When we disable digit output, we need to wait until fields are done.
2082 * Otherwise the DSS is still working, and turning off the clocks
2083 * prevents DSS from going to OFF mode. And when enabling, we need to
2084 * wait for the extra sync losts */
2085 init_completion(&frame_done_completion);
2087 if (src == DSS_HDMI_M_PCLK && enable == false) {
2088 irq_mask = DISPC_IRQ_FRAMEDONETV;
2091 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2092 /* XXX I understand from TRM that we should only wait for the
2093 * current field to complete. But it seems we have to wait for
2098 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2101 DSSERR("failed to register %x isr\n", irq_mask);
2103 _enable_digit_out(enable);
2105 for (i = 0; i < num_irqs; ++i) {
2106 if (!wait_for_completion_timeout(&frame_done_completion,
2107 msecs_to_jiffies(100)))
2108 DSSERR("timeout waiting for digit out to %s\n",
2109 enable ? "start" : "stop");
2112 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2115 DSSERR("failed to unregister %x isr\n", irq_mask);
2118 unsigned long flags;
2119 spin_lock_irqsave(&dispc.irq_lock, flags);
2120 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2121 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2122 _omap_dispc_set_irqs();
2123 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2127 bool dispc_mgr_is_enabled(enum omap_channel channel)
2129 if (channel == OMAP_DSS_CHANNEL_LCD)
2130 return !!REG_GET(DISPC_CONTROL, 0, 0);
2131 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2132 return !!REG_GET(DISPC_CONTROL, 1, 1);
2133 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2134 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2139 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2141 if (dispc_mgr_is_lcd(channel))
2142 dispc_mgr_enable_lcd_out(channel, enable);
2143 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2144 dispc_mgr_enable_digit_out(enable);
2149 void dispc_lcd_enable_signal_polarity(bool act_high)
2151 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2154 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2157 void dispc_lcd_enable_signal(bool enable)
2159 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2162 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2165 void dispc_pck_free_enable(bool enable)
2167 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2170 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2173 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2175 if (channel == OMAP_DSS_CHANNEL_LCD2)
2176 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2178 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2182 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2183 enum omap_lcd_display_type type)
2188 case OMAP_DSS_LCD_DISPLAY_STN:
2192 case OMAP_DSS_LCD_DISPLAY_TFT:
2201 if (channel == OMAP_DSS_CHANNEL_LCD2)
2202 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2204 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2207 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2209 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2213 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2215 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2218 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2222 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2223 channel != OMAP_DSS_CHANNEL_LCD &&
2224 channel != OMAP_DSS_CHANNEL_LCD2);
2226 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2231 void dispc_mgr_set_trans_key(enum omap_channel ch,
2232 enum omap_dss_trans_key_type type,
2235 if (ch == OMAP_DSS_CHANNEL_LCD)
2236 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2237 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2238 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2239 else /* OMAP_DSS_CHANNEL_LCD2 */
2240 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2242 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2245 void dispc_mgr_get_trans_key(enum omap_channel ch,
2246 enum omap_dss_trans_key_type *type,
2250 if (ch == OMAP_DSS_CHANNEL_LCD)
2251 *type = REG_GET(DISPC_CONFIG, 11, 11);
2252 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2253 *type = REG_GET(DISPC_CONFIG, 13, 13);
2254 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2255 *type = REG_GET(DISPC_CONFIG2, 11, 11);
2261 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2264 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2266 if (ch == OMAP_DSS_CHANNEL_LCD)
2267 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2268 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2269 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2270 else /* OMAP_DSS_CHANNEL_LCD2 */
2271 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2274 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2276 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2279 if (ch == OMAP_DSS_CHANNEL_LCD)
2280 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2281 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2282 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2285 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2289 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2292 if (ch == OMAP_DSS_CHANNEL_LCD)
2293 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2294 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2295 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2302 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2306 if (ch == OMAP_DSS_CHANNEL_LCD)
2307 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2308 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2309 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2310 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2311 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2319 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2323 switch (data_lines) {
2341 if (channel == OMAP_DSS_CHANNEL_LCD2)
2342 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2344 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2347 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2353 case DSS_IO_PAD_MODE_RESET:
2357 case DSS_IO_PAD_MODE_RFBI:
2361 case DSS_IO_PAD_MODE_BYPASS:
2370 l = dispc_read_reg(DISPC_CONTROL);
2371 l = FLD_MOD(l, gpout0, 15, 15);
2372 l = FLD_MOD(l, gpout1, 16, 16);
2373 dispc_write_reg(DISPC_CONTROL, l);
2376 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2378 if (channel == OMAP_DSS_CHANNEL_LCD2)
2379 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2381 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2384 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2385 int vsw, int vfp, int vbp)
2387 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2388 if (hsw < 1 || hsw > 64 ||
2389 hfp < 1 || hfp > 256 ||
2390 hbp < 1 || hbp > 256 ||
2391 vsw < 1 || vsw > 64 ||
2392 vfp < 0 || vfp > 255 ||
2393 vbp < 0 || vbp > 255)
2396 if (hsw < 1 || hsw > 256 ||
2397 hfp < 1 || hfp > 4096 ||
2398 hbp < 1 || hbp > 4096 ||
2399 vsw < 1 || vsw > 256 ||
2400 vfp < 0 || vfp > 4095 ||
2401 vbp < 0 || vbp > 4095)
2408 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2410 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2411 timings->hbp, timings->vsw,
2412 timings->vfp, timings->vbp);
2415 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2416 int hfp, int hbp, int vsw, int vfp, int vbp)
2418 u32 timing_h, timing_v;
2420 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2421 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2422 FLD_VAL(hbp-1, 27, 20);
2424 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2425 FLD_VAL(vbp, 27, 20);
2427 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2428 FLD_VAL(hbp-1, 31, 20);
2430 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2431 FLD_VAL(vbp, 31, 20);
2434 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2435 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2438 /* change name to mode? */
2439 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2440 struct omap_video_timings *timings)
2442 unsigned xtot, ytot;
2443 unsigned long ht, vt;
2445 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2446 timings->hbp, timings->vsw,
2447 timings->vfp, timings->vbp))
2450 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2451 timings->hbp, timings->vsw, timings->vfp,
2454 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2456 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2457 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2459 ht = (timings->pixel_clock * 1000) / xtot;
2460 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2462 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2464 DSSDBG("pck %u\n", timings->pixel_clock);
2465 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2466 timings->hsw, timings->hfp, timings->hbp,
2467 timings->vsw, timings->vfp, timings->vbp);
2469 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2472 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2475 BUG_ON(lck_div < 1);
2476 BUG_ON(pck_div < 1);
2478 dispc_write_reg(DISPC_DIVISORo(channel),
2479 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2482 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2486 l = dispc_read_reg(DISPC_DIVISORo(channel));
2487 *lck_div = FLD_GET(l, 23, 16);
2488 *pck_div = FLD_GET(l, 7, 0);
2491 unsigned long dispc_fclk_rate(void)
2493 struct platform_device *dsidev;
2494 unsigned long r = 0;
2496 switch (dss_get_dispc_clk_source()) {
2497 case OMAP_DSS_CLK_SRC_FCK:
2498 r = clk_get_rate(dispc.dss_clk);
2500 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2501 dsidev = dsi_get_dsidev_from_id(0);
2502 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2504 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2505 dsidev = dsi_get_dsidev_from_id(1);
2506 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2515 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2517 struct platform_device *dsidev;
2522 l = dispc_read_reg(DISPC_DIVISORo(channel));
2524 lcd = FLD_GET(l, 23, 16);
2526 switch (dss_get_lcd_clk_source(channel)) {
2527 case OMAP_DSS_CLK_SRC_FCK:
2528 r = clk_get_rate(dispc.dss_clk);
2530 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2531 dsidev = dsi_get_dsidev_from_id(0);
2532 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2534 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2535 dsidev = dsi_get_dsidev_from_id(1);
2536 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2545 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2549 if (dispc_mgr_is_lcd(channel)) {
2553 l = dispc_read_reg(DISPC_DIVISORo(channel));
2555 pcd = FLD_GET(l, 7, 0);
2557 r = dispc_mgr_lclk_rate(channel);
2561 struct omap_dss_device *dssdev =
2562 dispc_mgr_get_device(channel);
2564 switch (dssdev->type) {
2565 case OMAP_DISPLAY_TYPE_VENC:
2566 return venc_get_pixel_clock();
2567 case OMAP_DISPLAY_TYPE_HDMI:
2568 return hdmi_get_pixel_clock();
2575 void dispc_dump_clocks(struct seq_file *s)
2579 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2580 enum omap_dss_clk_source lcd_clk_src;
2582 if (dispc_runtime_get())
2585 seq_printf(s, "- DISPC -\n");
2587 seq_printf(s, "dispc fclk source = %s (%s)\n",
2588 dss_get_generic_clk_source_name(dispc_clk_src),
2589 dss_feat_get_clk_source_name(dispc_clk_src));
2591 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2593 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2594 seq_printf(s, "- DISPC-CORE-CLK -\n");
2595 l = dispc_read_reg(DISPC_DIVISOR);
2596 lcd = FLD_GET(l, 23, 16);
2598 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2599 (dispc_fclk_rate()/lcd), lcd);
2601 seq_printf(s, "- LCD1 -\n");
2603 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2605 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2606 dss_get_generic_clk_source_name(lcd_clk_src),
2607 dss_feat_get_clk_source_name(lcd_clk_src));
2609 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2611 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2612 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2613 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2614 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2615 if (dss_has_feature(FEAT_MGR_LCD2)) {
2616 seq_printf(s, "- LCD2 -\n");
2618 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2620 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2621 dss_get_generic_clk_source_name(lcd_clk_src),
2622 dss_feat_get_clk_source_name(lcd_clk_src));
2624 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2626 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2627 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2628 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2629 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2632 dispc_runtime_put();
2635 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2636 void dispc_dump_irqs(struct seq_file *s)
2638 unsigned long flags;
2639 struct dispc_irq_stats stats;
2641 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2643 stats = dispc.irq_stats;
2644 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2645 dispc.irq_stats.last_reset = jiffies;
2647 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2649 seq_printf(s, "period %u ms\n",
2650 jiffies_to_msecs(jiffies - stats.last_reset));
2652 seq_printf(s, "irqs %d\n", stats.irq_count);
2654 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2660 PIS(ACBIAS_COUNT_STAT);
2662 PIS(GFX_FIFO_UNDERFLOW);
2664 PIS(PAL_GAMMA_MASK);
2666 PIS(VID1_FIFO_UNDERFLOW);
2668 PIS(VID2_FIFO_UNDERFLOW);
2670 if (dss_feat_get_num_ovls() > 3) {
2671 PIS(VID3_FIFO_UNDERFLOW);
2675 PIS(SYNC_LOST_DIGIT);
2677 if (dss_has_feature(FEAT_MGR_LCD2)) {
2680 PIS(ACBIAS_COUNT_STAT2);
2687 void dispc_dump_regs(struct seq_file *s)
2690 const char *mgr_names[] = {
2691 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2692 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2693 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2695 const char *ovl_names[] = {
2696 [OMAP_DSS_GFX] = "GFX",
2697 [OMAP_DSS_VIDEO1] = "VID1",
2698 [OMAP_DSS_VIDEO2] = "VID2",
2699 [OMAP_DSS_VIDEO3] = "VID3",
2701 const char **p_names;
2703 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2705 if (dispc_runtime_get())
2708 /* DISPC common registers */
2709 DUMPREG(DISPC_REVISION);
2710 DUMPREG(DISPC_SYSCONFIG);
2711 DUMPREG(DISPC_SYSSTATUS);
2712 DUMPREG(DISPC_IRQSTATUS);
2713 DUMPREG(DISPC_IRQENABLE);
2714 DUMPREG(DISPC_CONTROL);
2715 DUMPREG(DISPC_CONFIG);
2716 DUMPREG(DISPC_CAPABLE);
2717 DUMPREG(DISPC_LINE_STATUS);
2718 DUMPREG(DISPC_LINE_NUMBER);
2719 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2720 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2721 DUMPREG(DISPC_GLOBAL_ALPHA);
2722 if (dss_has_feature(FEAT_MGR_LCD2)) {
2723 DUMPREG(DISPC_CONTROL2);
2724 DUMPREG(DISPC_CONFIG2);
2729 #define DISPC_REG(i, name) name(i)
2730 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2731 48 - strlen(#r) - strlen(p_names[i]), " ", \
2732 dispc_read_reg(DISPC_REG(i, r)))
2734 p_names = mgr_names;
2736 /* DISPC channel specific registers */
2737 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2738 DUMPREG(i, DISPC_DEFAULT_COLOR);
2739 DUMPREG(i, DISPC_TRANS_COLOR);
2740 DUMPREG(i, DISPC_SIZE_MGR);
2742 if (i == OMAP_DSS_CHANNEL_DIGIT)
2745 DUMPREG(i, DISPC_DEFAULT_COLOR);
2746 DUMPREG(i, DISPC_TRANS_COLOR);
2747 DUMPREG(i, DISPC_TIMING_H);
2748 DUMPREG(i, DISPC_TIMING_V);
2749 DUMPREG(i, DISPC_POL_FREQ);
2750 DUMPREG(i, DISPC_DIVISORo);
2751 DUMPREG(i, DISPC_SIZE_MGR);
2753 DUMPREG(i, DISPC_DATA_CYCLE1);
2754 DUMPREG(i, DISPC_DATA_CYCLE2);
2755 DUMPREG(i, DISPC_DATA_CYCLE3);
2757 if (dss_has_feature(FEAT_CPR)) {
2758 DUMPREG(i, DISPC_CPR_COEF_R);
2759 DUMPREG(i, DISPC_CPR_COEF_G);
2760 DUMPREG(i, DISPC_CPR_COEF_B);
2764 p_names = ovl_names;
2766 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2767 DUMPREG(i, DISPC_OVL_BA0);
2768 DUMPREG(i, DISPC_OVL_BA1);
2769 DUMPREG(i, DISPC_OVL_POSITION);
2770 DUMPREG(i, DISPC_OVL_SIZE);
2771 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2772 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2773 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2774 DUMPREG(i, DISPC_OVL_ROW_INC);
2775 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2776 if (dss_has_feature(FEAT_PRELOAD))
2777 DUMPREG(i, DISPC_OVL_PRELOAD);
2779 if (i == OMAP_DSS_GFX) {
2780 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2781 DUMPREG(i, DISPC_OVL_TABLE_BA);
2785 DUMPREG(i, DISPC_OVL_FIR);
2786 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2787 DUMPREG(i, DISPC_OVL_ACCU0);
2788 DUMPREG(i, DISPC_OVL_ACCU1);
2789 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2790 DUMPREG(i, DISPC_OVL_BA0_UV);
2791 DUMPREG(i, DISPC_OVL_BA1_UV);
2792 DUMPREG(i, DISPC_OVL_FIR2);
2793 DUMPREG(i, DISPC_OVL_ACCU2_0);
2794 DUMPREG(i, DISPC_OVL_ACCU2_1);
2796 if (dss_has_feature(FEAT_ATTR2))
2797 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2798 if (dss_has_feature(FEAT_PRELOAD))
2799 DUMPREG(i, DISPC_OVL_PRELOAD);
2805 #define DISPC_REG(plane, name, i) name(plane, i)
2806 #define DUMPREG(plane, name, i) \
2807 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2808 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2809 dispc_read_reg(DISPC_REG(plane, name, i)))
2811 /* Video pipeline coefficient registers */
2813 /* start from OMAP_DSS_VIDEO1 */
2814 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2815 for (j = 0; j < 8; j++)
2816 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2818 for (j = 0; j < 8; j++)
2819 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2821 for (j = 0; j < 5; j++)
2822 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2824 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2825 for (j = 0; j < 8; j++)
2826 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2829 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2830 for (j = 0; j < 8; j++)
2831 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2833 for (j = 0; j < 8; j++)
2834 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2836 for (j = 0; j < 8; j++)
2837 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2841 dispc_runtime_put();
2847 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2848 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2853 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2854 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2856 l |= FLD_VAL(onoff, 17, 17);
2857 l |= FLD_VAL(rf, 16, 16);
2858 l |= FLD_VAL(ieo, 15, 15);
2859 l |= FLD_VAL(ipc, 14, 14);
2860 l |= FLD_VAL(ihs, 13, 13);
2861 l |= FLD_VAL(ivs, 12, 12);
2862 l |= FLD_VAL(acbi, 11, 8);
2863 l |= FLD_VAL(acb, 7, 0);
2865 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2868 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2869 enum omap_panel_config config, u8 acbi, u8 acb)
2871 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2872 (config & OMAP_DSS_LCD_RF) != 0,
2873 (config & OMAP_DSS_LCD_IEO) != 0,
2874 (config & OMAP_DSS_LCD_IPC) != 0,
2875 (config & OMAP_DSS_LCD_IHS) != 0,
2876 (config & OMAP_DSS_LCD_IVS) != 0,
2880 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2881 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2882 struct dispc_clock_info *cinfo)
2884 u16 pcd_min, pcd_max;
2885 unsigned long best_pck;
2886 u16 best_ld, cur_ld;
2887 u16 best_pd, cur_pd;
2889 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2890 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2899 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2900 unsigned long lck = fck / cur_ld;
2902 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2903 unsigned long pck = lck / cur_pd;
2904 long old_delta = abs(best_pck - req_pck);
2905 long new_delta = abs(pck - req_pck);
2907 if (best_pck == 0 || new_delta < old_delta) {
2920 if (lck / pcd_min < req_pck)
2925 cinfo->lck_div = best_ld;
2926 cinfo->pck_div = best_pd;
2927 cinfo->lck = fck / cinfo->lck_div;
2928 cinfo->pck = cinfo->lck / cinfo->pck_div;
2931 /* calculate clock rates using dividers in cinfo */
2932 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2933 struct dispc_clock_info *cinfo)
2935 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2937 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2940 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2941 cinfo->pck = cinfo->lck / cinfo->pck_div;
2946 int dispc_mgr_set_clock_div(enum omap_channel channel,
2947 struct dispc_clock_info *cinfo)
2949 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2950 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2952 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2957 int dispc_mgr_get_clock_div(enum omap_channel channel,
2958 struct dispc_clock_info *cinfo)
2962 fck = dispc_fclk_rate();
2964 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2965 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2967 cinfo->lck = fck / cinfo->lck_div;
2968 cinfo->pck = cinfo->lck / cinfo->pck_div;
2973 /* dispc.irq_lock has to be locked by the caller */
2974 static void _omap_dispc_set_irqs(void)
2979 struct omap_dispc_isr_data *isr_data;
2981 mask = dispc.irq_error_mask;
2983 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2984 isr_data = &dispc.registered_isr[i];
2986 if (isr_data->isr == NULL)
2989 mask |= isr_data->mask;
2992 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2993 /* clear the irqstatus for newly enabled irqs */
2994 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2996 dispc_write_reg(DISPC_IRQENABLE, mask);
2999 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3003 unsigned long flags;
3004 struct omap_dispc_isr_data *isr_data;
3009 spin_lock_irqsave(&dispc.irq_lock, flags);
3011 /* check for duplicate entry */
3012 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3013 isr_data = &dispc.registered_isr[i];
3014 if (isr_data->isr == isr && isr_data->arg == arg &&
3015 isr_data->mask == mask) {
3024 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3025 isr_data = &dispc.registered_isr[i];
3027 if (isr_data->isr != NULL)
3030 isr_data->isr = isr;
3031 isr_data->arg = arg;
3032 isr_data->mask = mask;
3041 _omap_dispc_set_irqs();
3043 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3047 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3051 EXPORT_SYMBOL(omap_dispc_register_isr);
3053 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3056 unsigned long flags;
3058 struct omap_dispc_isr_data *isr_data;
3060 spin_lock_irqsave(&dispc.irq_lock, flags);
3062 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3063 isr_data = &dispc.registered_isr[i];
3064 if (isr_data->isr != isr || isr_data->arg != arg ||
3065 isr_data->mask != mask)
3068 /* found the correct isr */
3070 isr_data->isr = NULL;
3071 isr_data->arg = NULL;
3079 _omap_dispc_set_irqs();
3081 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3085 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3088 static void print_irq_status(u32 status)
3090 if ((status & dispc.irq_error_mask) == 0)
3093 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3096 if (status & DISPC_IRQ_##x) \
3098 PIS(GFX_FIFO_UNDERFLOW);
3100 PIS(VID1_FIFO_UNDERFLOW);
3101 PIS(VID2_FIFO_UNDERFLOW);
3102 if (dss_feat_get_num_ovls() > 3)
3103 PIS(VID3_FIFO_UNDERFLOW);
3105 PIS(SYNC_LOST_DIGIT);
3106 if (dss_has_feature(FEAT_MGR_LCD2))
3114 /* Called from dss.c. Note that we don't touch clocks here,
3115 * but we presume they are on because we got an IRQ. However,
3116 * an irq handler may turn the clocks off, so we may not have
3117 * clock later in the function. */
3118 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3121 u32 irqstatus, irqenable;
3122 u32 handledirqs = 0;
3123 u32 unhandled_errors;
3124 struct omap_dispc_isr_data *isr_data;
3125 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3127 spin_lock(&dispc.irq_lock);
3129 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3130 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3132 /* IRQ is not for us */
3133 if (!(irqstatus & irqenable)) {
3134 spin_unlock(&dispc.irq_lock);
3138 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3139 spin_lock(&dispc.irq_stats_lock);
3140 dispc.irq_stats.irq_count++;
3141 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3142 spin_unlock(&dispc.irq_stats_lock);
3147 print_irq_status(irqstatus);
3149 /* Ack the interrupt. Do it here before clocks are possibly turned
3151 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3152 /* flush posted write */
3153 dispc_read_reg(DISPC_IRQSTATUS);
3155 /* make a copy and unlock, so that isrs can unregister
3157 memcpy(registered_isr, dispc.registered_isr,
3158 sizeof(registered_isr));
3160 spin_unlock(&dispc.irq_lock);
3162 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3163 isr_data = ®istered_isr[i];
3168 if (isr_data->mask & irqstatus) {
3169 isr_data->isr(isr_data->arg, irqstatus);
3170 handledirqs |= isr_data->mask;
3174 spin_lock(&dispc.irq_lock);
3176 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3178 if (unhandled_errors) {
3179 dispc.error_irqs |= unhandled_errors;
3181 dispc.irq_error_mask &= ~unhandled_errors;
3182 _omap_dispc_set_irqs();
3184 schedule_work(&dispc.error_work);
3187 spin_unlock(&dispc.irq_lock);
3192 static void dispc_error_worker(struct work_struct *work)
3196 unsigned long flags;
3197 static const unsigned fifo_underflow_bits[] = {
3198 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3199 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3200 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3201 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3204 static const unsigned sync_lost_bits[] = {
3205 DISPC_IRQ_SYNC_LOST,
3206 DISPC_IRQ_SYNC_LOST_DIGIT,
3207 DISPC_IRQ_SYNC_LOST2,
3210 spin_lock_irqsave(&dispc.irq_lock, flags);
3211 errors = dispc.error_irqs;
3212 dispc.error_irqs = 0;
3213 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3215 dispc_runtime_get();
3217 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3218 struct omap_overlay *ovl;
3221 ovl = omap_dss_get_overlay(i);
3222 bit = fifo_underflow_bits[i];
3225 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3227 dispc_ovl_enable(ovl->id, false);
3228 dispc_mgr_go(ovl->manager->id);
3233 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3234 struct omap_overlay_manager *mgr;
3237 mgr = omap_dss_get_overlay_manager(i);
3238 bit = sync_lost_bits[i];
3241 struct omap_dss_device *dssdev = mgr->device;
3244 DSSERR("SYNC_LOST on channel %s, restarting the output "
3245 "with video overlays disabled\n",
3248 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3249 dssdev->driver->disable(dssdev);
3251 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3252 struct omap_overlay *ovl;
3253 ovl = omap_dss_get_overlay(i);
3255 if (ovl->id != OMAP_DSS_GFX &&
3256 ovl->manager == mgr)
3257 dispc_ovl_enable(ovl->id, false);
3260 dispc_mgr_go(mgr->id);
3264 dssdev->driver->enable(dssdev);
3268 if (errors & DISPC_IRQ_OCP_ERR) {
3269 DSSERR("OCP_ERR\n");
3270 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3271 struct omap_overlay_manager *mgr;
3272 mgr = omap_dss_get_overlay_manager(i);
3273 mgr->device->driver->disable(mgr->device);
3277 spin_lock_irqsave(&dispc.irq_lock, flags);
3278 dispc.irq_error_mask |= errors;
3279 _omap_dispc_set_irqs();
3280 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3282 dispc_runtime_put();
3285 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3287 void dispc_irq_wait_handler(void *data, u32 mask)
3289 complete((struct completion *)data);
3293 DECLARE_COMPLETION_ONSTACK(completion);
3295 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3301 timeout = wait_for_completion_timeout(&completion, timeout);
3303 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3308 if (timeout == -ERESTARTSYS)
3309 return -ERESTARTSYS;
3314 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3315 unsigned long timeout)
3317 void dispc_irq_wait_handler(void *data, u32 mask)
3319 complete((struct completion *)data);
3323 DECLARE_COMPLETION_ONSTACK(completion);
3325 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3331 timeout = wait_for_completion_interruptible_timeout(&completion,
3334 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3339 if (timeout == -ERESTARTSYS)
3340 return -ERESTARTSYS;
3345 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3346 void dispc_fake_vsync_irq(void)
3348 u32 irqstatus = DISPC_IRQ_VSYNC;
3351 WARN_ON(!in_interrupt());
3353 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3354 struct omap_dispc_isr_data *isr_data;
3355 isr_data = &dispc.registered_isr[i];
3360 if (isr_data->mask & irqstatus)
3361 isr_data->isr(isr_data->arg, irqstatus);
3366 static void _omap_dispc_initialize_irq(void)
3368 unsigned long flags;
3370 spin_lock_irqsave(&dispc.irq_lock, flags);
3372 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3374 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3375 if (dss_has_feature(FEAT_MGR_LCD2))
3376 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3377 if (dss_feat_get_num_ovls() > 3)
3378 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3380 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3382 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3384 _omap_dispc_set_irqs();
3386 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3389 void dispc_enable_sidle(void)
3391 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3394 void dispc_disable_sidle(void)
3396 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3399 static void _omap_dispc_initial_config(void)
3403 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3404 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3405 l = dispc_read_reg(DISPC_DIVISOR);
3406 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3407 l = FLD_MOD(l, 1, 0, 0);
3408 l = FLD_MOD(l, 1, 23, 16);
3409 dispc_write_reg(DISPC_DIVISOR, l);
3413 if (dss_has_feature(FEAT_FUNCGATED))
3414 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3416 /* L3 firewall setting: enable access to OCM RAM */
3417 /* XXX this should be somewhere in plat-omap */
3418 if (cpu_is_omap24xx())
3419 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3421 _dispc_setup_color_conv_coef();
3423 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3425 dispc_read_plane_fifo_sizes();
3427 dispc_configure_burst_sizes();
3429 dispc_ovl_enable_zorder_planes();
3432 /* DISPC HW IP initialisation */
3433 static int omap_dispchw_probe(struct platform_device *pdev)
3437 struct resource *dispc_mem;
3442 clk = clk_get(&pdev->dev, "fck");
3444 DSSERR("can't get fck\n");
3449 dispc.dss_clk = clk;
3451 spin_lock_init(&dispc.irq_lock);
3453 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3454 spin_lock_init(&dispc.irq_stats_lock);
3455 dispc.irq_stats.last_reset = jiffies;
3458 INIT_WORK(&dispc.error_work, dispc_error_worker);
3460 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3462 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3466 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3468 DSSERR("can't ioremap DISPC\n");
3472 dispc.irq = platform_get_irq(dispc.pdev, 0);
3473 if (dispc.irq < 0) {
3474 DSSERR("platform_get_irq failed\n");
3479 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3480 "OMAP DISPC", dispc.pdev);
3482 DSSERR("request_irq failed\n");
3486 pdev->dev.coherent_dma_mask = ~0;
3487 dispc.table_virt = dma_alloc_writecombine(&pdev->dev,
3488 TABLE_SIZE, &dispc.table_phys, GFP_KERNEL);
3489 if (dispc.table_virt == NULL) {
3490 dev_err(&pdev->dev, "failed to alloc palette memory\n");
3493 memset(dispc.table_virt, 0, TABLE_SIZE);
3495 pm_runtime_enable(&pdev->dev);
3497 r = dispc_runtime_get();
3499 goto err_runtime_get;
3501 _omap_dispc_initial_config();
3503 _omap_dispc_initialize_irq();
3505 rev = dispc_read_reg(DISPC_REVISION);
3506 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3507 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3509 dispc_runtime_put();
3514 pm_runtime_disable(&pdev->dev);
3515 dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3516 dispc.table_virt, dispc.table_phys);
3518 free_irq(dispc.irq, dispc.pdev);
3520 iounmap(dispc.base);
3522 clk_put(dispc.dss_clk);
3527 static int omap_dispchw_remove(struct platform_device *pdev)
3529 pm_runtime_disable(&pdev->dev);
3531 dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3532 dispc.table_virt, dispc.table_phys);
3534 clk_put(dispc.dss_clk);
3536 free_irq(dispc.irq, dispc.pdev);
3537 iounmap(dispc.base);
3541 static int dispc_runtime_suspend(struct device *dev)
3543 dispc_save_context();
3549 static int dispc_runtime_resume(struct device *dev)
3553 r = dss_runtime_get();
3557 dispc_restore_context();
3562 static const struct dev_pm_ops dispc_pm_ops = {
3563 .runtime_suspend = dispc_runtime_suspend,
3564 .runtime_resume = dispc_runtime_resume,
3567 static struct platform_driver omap_dispchw_driver = {
3568 .remove = omap_dispchw_remove,
3570 .name = "omapdss_dispc",
3571 .owner = THIS_MODULE,
3572 .pm = &dispc_pm_ops,
3576 int dispc_init_platform_driver(void)
3578 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3581 void dispc_uninit_platform_driver(void)
3583 return platform_driver_unregister(&omap_dispchw_driver);