drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <plat/sram.h>
  41 #include <plat/clock.h>
  42
  43 #include <video/omapdss.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47 #include "dispc.h"
  48
  49 /* DISPC */
  50 #define DISPC_SZ_REGS                   SZ_4K
  51
  52 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  53                                          DISPC_IRQ_OCP_ERR | \
  54                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  56                                          DISPC_IRQ_SYNC_LOST | \
  57                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  58
  59 #define DISPC_MAX_NR_ISRS               8
  60
  61 #define TABLE_SIZE (256 * 4)
  62
  63 struct omap_dispc_isr_data {
  64         omap_dispc_isr_t        isr;
  65         void                    *arg;
  66         u32                     mask;
  67 };
  68
  69 struct dispc_h_coef {
  70         s8 hc4;
  71         s8 hc3;
  72         u8 hc2;
  73         s8 hc1;
  74         s8 hc0;
  75 };
  76
  77 struct dispc_v_coef {
  78         s8 vc22;
  79         s8 vc2;
  80         u8 vc1;
  81         s8 vc0;
  82         s8 vc00;
  83 };
  84
  85 enum omap_burst_size {
  86         BURST_SIZE_X2 = 0,
  87         BURST_SIZE_X4 = 1,
  88         BURST_SIZE_X8 = 2,
  89 };
  90
  91 #define REG_GET(idx, start, end) \
  92         FLD_GET(dispc_read_reg(idx), start, end)
  93
  94 #define REG_FLD_MOD(idx, val, start, end)                               \
  95         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  96
  97 struct dispc_irq_stats {
  98         unsigned long last_reset;
  99         unsigned irq_count;
 100         unsigned irqs[32];
 101 };
 102
 103 static struct {
 104         struct platform_device *pdev;
 105         void __iomem    *base;
 106
 107         int             ctx_loss_cnt;
 108
 109         int irq;
 110         struct clk *dss_clk;
 111
 112         u32     fifo_size[MAX_DSS_OVERLAYS];
 113
 114         spinlock_t irq_lock;
 115         u32 irq_error_mask;
 116         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 117         u32 error_irqs;
 118         struct work_struct error_work;
 119
 120         u32 frame_counter;
 121         u32 fc_last_use;
 122         bool fc_isr_registered;
 123         struct completion *fc_complete[4];
 124
 125         bool            ctx_valid;
 126         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 127
 128         /* palette/gamma table */
 129         void            *table_virt;
 130         dma_addr_t      table_phys;
 131
 132 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 133         spinlock_t irq_stats_lock;
 134         struct dispc_irq_stats irq_stats;
 135 #endif
 136 } dispc;
 137
 138 enum omap_color_component {
 139         /* used for all color formats for OMAP3 and earlier
 140          * and for RGB and Y color component on OMAP4
 141          */
 142         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 143         /* used for UV component for
 144          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 145          * color formats on OMAP4
 146          */
 147         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 148 };
 149
 150 static void _omap_dispc_set_irqs(void);
 151
 152 static inline void dispc_write_reg(const u16 idx, u32 val)
 153 {
 154         __raw_writel(val, dispc.base + idx);
 155 }
 156
 157 static inline u32 dispc_read_reg(const u16 idx)
 158 {
 159         return __raw_readl(dispc.base + idx);
 160 }
 161
 162 static int dispc_get_ctx_loss_count(void)
 163 {
 164         struct device *dev = &dispc.pdev->dev;
 165         struct omap_display_platform_data *pdata = dev->platform_data;
 166         struct omap_dss_board_info *board_data = pdata->board_data;
 167         int cnt;
 168
 169         if (!board_data->get_context_loss_count)
 170                 return -ENOENT;
 171
 172         cnt = board_data->get_context_loss_count(dev);
 173
 174         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 175
 176         return cnt;
 177 }
 178
 179 #define SR(reg) \
 180         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 181 #define RR(reg) \
 182         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 183
 184 static void dispc_save_context(void)
 185 {
 186         int i, j;
 187
 188         DSSDBG("dispc_save_context\n");
 189
 190         SR(IRQENABLE);
 191         SR(CONTROL);
 192         SR(CONFIG);
 193         SR(LINE_NUMBER);
 194         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 195                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 196                 SR(GLOBAL_ALPHA);
 197         if (dss_has_feature(FEAT_MGR_LCD2)) {
 198                 SR(CONTROL2);
 199                 SR(CONFIG2);
 200         }
 201
 202         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 203                 SR(DEFAULT_COLOR(i));
 204                 SR(TRANS_COLOR(i));
 205                 SR(SIZE_MGR(i));
 206                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 207                         continue;
 208                 SR(TIMING_H(i));
 209                 SR(TIMING_V(i));
 210                 SR(POL_FREQ(i));
 211                 SR(DIVISORo(i));
 212
 213                 SR(DATA_CYCLE1(i));
 214                 SR(DATA_CYCLE2(i));
 215                 SR(DATA_CYCLE3(i));
 216
 217                 if (dss_has_feature(FEAT_CPR)) {
 218                         SR(CPR_COEF_R(i));
 219                         SR(CPR_COEF_G(i));
 220                         SR(CPR_COEF_B(i));
 221                 }
 222         }
 223
 224         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 225                 SR(OVL_BA0(i));
 226                 SR(OVL_BA1(i));
 227                 SR(OVL_POSITION(i));
 228                 SR(OVL_SIZE(i));
 229                 SR(OVL_ATTRIBUTES(i));
 230                 SR(OVL_FIFO_THRESHOLD(i));
 231                 SR(OVL_ROW_INC(i));
 232                 SR(OVL_PIXEL_INC(i));
 233                 if (dss_has_feature(FEAT_PRELOAD))
 234                         SR(OVL_PRELOAD(i));
 235                 if (i == OMAP_DSS_GFX) {
 236                         SR(OVL_WINDOW_SKIP(i));
 237                         SR(OVL_TABLE_BA(i));
 238                         continue;
 239                 }
 240                 SR(OVL_FIR(i));
 241                 SR(OVL_PICTURE_SIZE(i));
 242                 SR(OVL_ACCU0(i));
 243                 SR(OVL_ACCU1(i));
 244
 245                 for (j = 0; j < 8; j++)
 246                         SR(OVL_FIR_COEF_H(i, j));
 247
 248                 for (j = 0; j < 8; j++)
 249                         SR(OVL_FIR_COEF_HV(i, j));
 250
 251                 for (j = 0; j < 5; j++)
 252                         SR(OVL_CONV_COEF(i, j));
 253
 254                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 255                         for (j = 0; j < 8; j++)
 256                                 SR(OVL_FIR_COEF_V(i, j));
 257                 }
 258
 259                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 260                         SR(OVL_BA0_UV(i));
 261                         SR(OVL_BA1_UV(i));
 262                         SR(OVL_FIR2(i));
 263                         SR(OVL_ACCU2_0(i));
 264                         SR(OVL_ACCU2_1(i));
 265
 266                         for (j = 0; j < 8; j++)
 267                                 SR(OVL_FIR_COEF_H2(i, j));
 268
 269                         for (j = 0; j < 8; j++)
 270                                 SR(OVL_FIR_COEF_HV2(i, j));
 271
 272                         for (j = 0; j < 8; j++)
 273                                 SR(OVL_FIR_COEF_V2(i, j));
 274                 }
 275                 if (dss_has_feature(FEAT_ATTR2))
 276                         SR(OVL_ATTRIBUTES2(i));
 277         }
 278
 279         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 280                 SR(DIVISOR);
 281
 282         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 283         dispc.ctx_valid = true;
 284
 285         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 286 }
 287
 288 static void dispc_restore_context(void)
 289 {
 290         int i, j, ctx;
 291
 292         DSSDBG("dispc_restore_context\n");
 293
 294         if (!dispc.ctx_valid)
 295                 return;
 296
 297         ctx = dispc_get_ctx_loss_count();
 298
 299         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 300                 return;
 301
 302         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 303                         dispc.ctx_loss_cnt, ctx);
 304
 305         /*RR(IRQENABLE);*/
 306         /*RR(CONTROL);*/
 307         RR(CONFIG);
 308         RR(LINE_NUMBER);
 309         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 310                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 311                 RR(GLOBAL_ALPHA);
 312         if (dss_has_feature(FEAT_MGR_LCD2))
 313                 RR(CONFIG2);
 314
 315         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 316                 RR(DEFAULT_COLOR(i));
 317                 RR(TRANS_COLOR(i));
 318                 RR(SIZE_MGR(i));
 319                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 320                         continue;
 321                 RR(TIMING_H(i));
 322                 RR(TIMING_V(i));
 323                 RR(POL_FREQ(i));
 324                 RR(DIVISORo(i));
 325
 326                 RR(DATA_CYCLE1(i));
 327                 RR(DATA_CYCLE2(i));
 328                 RR(DATA_CYCLE3(i));
 329
 330                 if (dss_has_feature(FEAT_CPR)) {
 331                         RR(CPR_COEF_R(i));
 332                         RR(CPR_COEF_G(i));
 333                         RR(CPR_COEF_B(i));
 334                 }
 335         }
 336
 337         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 338                 RR(OVL_BA0(i));
 339                 RR(OVL_BA1(i));
 340                 RR(OVL_POSITION(i));
 341                 RR(OVL_SIZE(i));
 342                 RR(OVL_ATTRIBUTES(i));
 343                 RR(OVL_FIFO_THRESHOLD(i));
 344                 RR(OVL_ROW_INC(i));
 345                 RR(OVL_PIXEL_INC(i));
 346                 if (dss_has_feature(FEAT_PRELOAD))
 347                         RR(OVL_PRELOAD(i));
 348                 if (i == OMAP_DSS_GFX) {
 349                         RR(OVL_WINDOW_SKIP(i));
 350                         RR(OVL_TABLE_BA(i));
 351                         continue;
 352                 }
 353                 RR(OVL_FIR(i));
 354                 RR(OVL_PICTURE_SIZE(i));
 355                 RR(OVL_ACCU0(i));
 356                 RR(OVL_ACCU1(i));
 357
 358                 for (j = 0; j < 8; j++)
 359                         RR(OVL_FIR_COEF_H(i, j));
 360
 361                 for (j = 0; j < 8; j++)
 362                         RR(OVL_FIR_COEF_HV(i, j));
 363
 364                 for (j = 0; j < 5; j++)
 365                         RR(OVL_CONV_COEF(i, j));
 366
 367                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_V(i, j));
 370                 }
 371
 372                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 373                         RR(OVL_BA0_UV(i));
 374                         RR(OVL_BA1_UV(i));
 375                         RR(OVL_FIR2(i));
 376                         RR(OVL_ACCU2_0(i));
 377                         RR(OVL_ACCU2_1(i));
 378
 379                         for (j = 0; j < 8; j++)
 380                                 RR(OVL_FIR_COEF_H2(i, j));
 381
 382                         for (j = 0; j < 8; j++)
 383                                 RR(OVL_FIR_COEF_HV2(i, j));
 384
 385                         for (j = 0; j < 8; j++)
 386                                 RR(OVL_FIR_COEF_V2(i, j));
 387                 }
 388                 if (dss_has_feature(FEAT_ATTR2))
 389                         RR(OVL_ATTRIBUTES2(i));
 390         }
 391
 392         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 393                 RR(DIVISOR);
 394
 395         /* enable last, because LCD & DIGIT enable are here */
 396         RR(CONTROL);
 397         if (dss_has_feature(FEAT_MGR_LCD2))
 398                 RR(CONTROL2);
 399         /* clear spurious SYNC_LOST_DIGIT interrupts */
 400         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 401
 402         /*
 403          * enable last so IRQs won't trigger before
 404          * the context is fully restored
 405          */
 406         RR(IRQENABLE);
 407
 408         DSSDBG("context restored\n");
 409 }
 410
 411 #undef SR
 412 #undef RR
 413
 414 int dispc_runtime_get(void)
 415 {
 416         int r;
 417
 418         DSSDBG("dispc_runtime_get\n");
 419
 420         r = pm_runtime_get_sync(&dispc.pdev->dev);
 421         WARN_ON(r < 0);
 422         return r < 0 ? r : 0;
 423 }
 424 EXPORT_SYMBOL(dispc_runtime_get);
 425
 426 void dispc_runtime_put(void)
 427 {
 428         int r;
 429
 430         DSSDBG("dispc_runtime_put\n");
 431
 432         r = pm_runtime_put_sync(&dispc.pdev->dev);
 433         WARN_ON(r < 0);
 434 }
 435 EXPORT_SYMBOL(dispc_runtime_put);
 436
 437 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
 438 {
 439         if (channel == OMAP_DSS_CHANNEL_LCD ||
 440                         channel == OMAP_DSS_CHANNEL_LCD2)
 441                 return true;
 442         else
 443                 return false;
 444 }
 445
 446 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
 447 {
 448         struct omap_overlay_manager *mgr =
 449                 omap_dss_get_overlay_manager(channel);
 450
 451         return mgr ? mgr->device : NULL;
 452 }
 453
 454 bool dispc_mgr_go_busy(enum omap_channel channel)
 455 {
 456         int bit;
 457
 458         if (dispc_mgr_is_lcd(channel))
 459                 bit = 5; /* GOLCD */
 460         else
 461                 bit = 6; /* GODIGIT */
 462
 463         if (channel == OMAP_DSS_CHANNEL_LCD2)
 464                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 465         else
 466                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 467 }
 468
 469 void dispc_mgr_go(enum omap_channel channel)
 470 {
 471         int bit;
 472         bool enable_bit, go_bit;
 473
 474         if (dispc_mgr_is_lcd(channel))
 475                 bit = 0; /* LCDENABLE */
 476         else
 477                 bit = 1; /* DIGITALENABLE */
 478
 479         /* if the channel is not enabled, we don't need GO */
 480         if (channel == OMAP_DSS_CHANNEL_LCD2)
 481                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 482         else
 483                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 484
 485         if (!enable_bit)
 486                 return;
 487
 488         if (dispc_mgr_is_lcd(channel))
 489                 bit = 5; /* GOLCD */
 490         else
 491                 bit = 6; /* GODIGIT */
 492
 493         if (channel == OMAP_DSS_CHANNEL_LCD2)
 494                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 495         else
 496                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 497
 498         if (go_bit) {
 499 #if 0 /* pandora hack */
 500                 DSSERR("GO bit not down for channel %d\n", channel);
 501 #endif
 502                 return;
 503         }
 504
 505         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 506                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 507
 508         if (channel == OMAP_DSS_CHANNEL_LCD2)
 509                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 510         else
 511                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 512 }
 513
 514 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 515 {
 516         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 517 }
 518
 519 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 520 {
 521         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 522 }
 523
 524 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 525 {
 526         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 527 }
 528
 529 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         BUG_ON(plane == OMAP_DSS_GFX);
 532
 533         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 534 }
 535
 536 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 537                 u32 value)
 538 {
 539         BUG_ON(plane == OMAP_DSS_GFX);
 540
 541         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 542 }
 543
 544 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 545 {
 546         BUG_ON(plane == OMAP_DSS_GFX);
 547
 548         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 549 }
 550
 551 /* Coefficients for horizontal up-sampling */
 552 static struct dispc_h_coef coef_hup[8] = {
 553         {  0,   0, 128,   0,  0 },
 554         { -1,  13, 124,  -8,  0 },
 555         { -2,  30, 112, -11, -1 },
 556         { -5,  51,  95, -11, -2 },
 557         {  0,  -9,  73,  73, -9 },
 558         { -2, -11,  95,  51, -5 },
 559         { -1, -11, 112,  30, -2 },
 560         {  0,  -8, 124,  13, -1 },
 561 };
 562
 563 /* Coefficients for vertical up-sampling */
 564 static struct dispc_v_coef coef_vup_3tap[8] = {
 565         { 0,  0, 128,  0, 0 },
 566         { 0,  3, 123,  2, 0 },
 567         { 0, 12, 111,  5, 0 },
 568         { 0, 32,  89,  7, 0 },
 569         { 0,  0,  64, 64, 0 },
 570         { 0,  7,  89, 32, 0 },
 571         { 0,  5, 111, 12, 0 },
 572         { 0,  2, 123,  3, 0 },
 573 };
 574
 575 static struct dispc_v_coef coef_vup_5tap[8] = {
 576         {  0,   0, 128,   0,  0 },
 577         { -1,  13, 124,  -8,  0 },
 578         { -2,  30, 112, -11, -1 },
 579         { -5,  51,  95, -11, -2 },
 580         {  0,  -9,  73,  73, -9 },
 581         { -2, -11,  95,  51, -5 },
 582         { -1, -11, 112,  30, -2 },
 583         {  0,  -8, 124,  13, -1 },
 584 };
 585
 586 /* Coefficients for horizontal down-sampling */
 587 static struct dispc_h_coef coef_hdown[8] = {
 588         {   0, 36, 56, 36,  0 },
 589         {   4, 40, 55, 31, -2 },
 590         {   8, 44, 54, 27, -5 },
 591         {  12, 48, 53, 22, -7 },
 592         {  -9, 17, 52, 51, 17 },
 593         {  -7, 22, 53, 48, 12 },
 594         {  -5, 27, 54, 44,  8 },
 595         {  -2, 31, 55, 40,  4 },
 596 };
 597
 598 /* Coefficients for vertical down-sampling */
 599 static struct dispc_v_coef coef_vdown_3tap[8] = {
 600         { 0, 36, 56, 36, 0 },
 601         { 0, 40, 57, 31, 0 },
 602         { 0, 45, 56, 27, 0 },
 603         { 0, 50, 55, 23, 0 },
 604         { 0, 18, 55, 55, 0 },
 605         { 0, 23, 55, 50, 0 },
 606         { 0, 27, 56, 45, 0 },
 607         { 0, 31, 57, 40, 0 },
 608 };
 609
 610 static struct dispc_v_coef coef_vdown_5tap[8] = {
 611         {   0, 36, 56, 36,  0 },
 612         {   4, 40, 55, 31, -2 },
 613         {   8, 44, 54, 27, -5 },
 614         {  12, 48, 53, 22, -7 },
 615         {  -9, 17, 52, 51, 17 },
 616         {  -7, 22, 53, 48, 12 },
 617         {  -5, 27, 54, 44,  8 },
 618         {  -2, 31, 55, 40,  4 },
 619 };
 620
 621 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
 622                                   int vscaleup, int five_taps,
 623                                   enum omap_color_component color_comp)
 624 {
 625         const struct dispc_h_coef *h_coef;
 626         const struct dispc_v_coef *v_coef;
 627         int i;
 628
 629         if (hscaleup)
 630                 h_coef = coef_hup;
 631         else
 632                 h_coef = coef_hdown;
 633
 634         if (vscaleup)
 635                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 636         else
 637                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 638
 639         for (i = 0; i < 8; i++) {
 640                 u32 h, hv;
 641
 642                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 643                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 644                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 645                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 646                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 647                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 648                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 649                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 650
 651                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 652                         dispc_ovl_write_firh_reg(plane, i, h);
 653                         dispc_ovl_write_firhv_reg(plane, i, hv);
 654                 } else {
 655                         dispc_ovl_write_firh2_reg(plane, i, h);
 656                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 657                 }
 658
 659         }
 660
 661         if (five_taps) {
 662                 for (i = 0; i < 8; i++) {
 663                         u32 v;
 664                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 665                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 666                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 667                                 dispc_ovl_write_firv_reg(plane, i, v);
 668                         else
 669                                 dispc_ovl_write_firv2_reg(plane, i, v);
 670                 }
 671         }
 672 }
 673
 674 static struct dispc_h_coef *dispc_get_scale_coef_table(enum omap_plane plane,
 675                 enum omap_filter filter)
 676 {
 677         switch (filter) {
 678         case OMAP_DSS_FILTER_UP_H:
 679                 return coef_hup;
 680         case OMAP_DSS_FILTER_UP_V3:
 681                 /* XXX: relying on fact that h and v tables have same layout */
 682                 return (void *)coef_vup_3tap;
 683         case OMAP_DSS_FILTER_UP_V5:
 684                 return (void *)coef_vup_5tap;
 685         case OMAP_DSS_FILTER_DOWN_H:
 686                 return coef_hdown;
 687         case OMAP_DSS_FILTER_DOWN_V3:
 688                 return (void *)coef_vdown_3tap;
 689         case OMAP_DSS_FILTER_DOWN_V5:
 690                 return (void *)coef_vdown_5tap;
 691         default:
 692                 return NULL;
 693         }
 694 }
 695
 696 void dispc_get_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
 697                 int phase, int *vals)
 698 {
 699         const struct dispc_h_coef *table;
 700
 701         if (phase < 0 || phase >= 8)
 702                 return;
 703
 704         table = dispc_get_scale_coef_table(plane, filter);
 705         if (table == NULL)
 706                 return;
 707
 708         table += phase;
 709         vals[0] = table->hc4;
 710         vals[1] = table->hc3;
 711         vals[2] = table->hc2;
 712         vals[3] = table->hc1;
 713         vals[4] = table->hc0;
 714 }
 715
 716 void dispc_set_scale_coef_phase(enum omap_plane plane, enum omap_filter filter,
 717                 int phase, const int *vals)
 718 {
 719         struct dispc_h_coef *table;
 720
 721         if (phase < 0 || phase >= 8)
 722                 return;
 723
 724         table = dispc_get_scale_coef_table(plane, filter);
 725         if (table == NULL)
 726                 return;
 727
 728         table += phase;
 729         table->hc4 = vals[0];
 730         table->hc3 = vals[1];
 731         table->hc2 = vals[2];
 732         table->hc1 = vals[3];
 733         table->hc0 = vals[4];
 734 }
 735
 736 static void _dispc_setup_color_conv_coef(void)
 737 {
 738         int i;
 739         const struct color_conv_coef {
 740                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 741                 int  full_range;
 742         }  ctbl_bt601_5 = {
 743                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 744         };
 745
 746         const struct color_conv_coef *ct;
 747
 748 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 749
 750         ct = &ctbl_bt601_5;
 751
 752         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 753                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 754                         CVAL(ct->rcr, ct->ry));
 755                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 756                         CVAL(ct->gy,  ct->rcb));
 757                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 758                         CVAL(ct->gcb, ct->gcr));
 759                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 760                         CVAL(ct->bcr, ct->by));
 761                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 762                         CVAL(0, ct->bcb));
 763
 764                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 765                         11, 11);
 766         }
 767
 768 #undef CVAL
 769 }
 770
 771
 772 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 773 {
 774         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 775 }
 776
 777 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 778 {
 779         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 780 }
 781
 782 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 783 {
 784         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 785 }
 786
 787 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 788 {
 789         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 790 }
 791
 792 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 793 {
 794         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 795
 796         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 797 }
 798
 799 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 800 {
 801         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 802
 803         if (plane == OMAP_DSS_GFX)
 804                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 805         else
 806                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 807 }
 808
 809 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 810 {
 811         u32 val;
 812
 813         BUG_ON(plane == OMAP_DSS_GFX);
 814
 815         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 816
 817         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 818 }
 819
 820 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
 821 {
 822         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 823
 824         if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 825                 return;
 826
 827         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 828 }
 829
 830 static void dispc_ovl_enable_zorder_planes(void)
 831 {
 832         int i;
 833
 834         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 835                 return;
 836
 837         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 838                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 839 }
 840
 841 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 842 {
 843         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 844
 845         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 846                 return;
 847
 848         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 849 }
 850
 851 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 852 {
 853         static const unsigned shifts[] = { 0, 8, 16, 24, };
 854         int shift;
 855         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 856
 857         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 858                 return;
 859
 860         shift = shifts[plane];
 861         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 862 }
 863
 864 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 865 {
 866         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 867 }
 868
 869 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 870 {
 871         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 872 }
 873
 874 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 875                 enum omap_color_mode color_mode)
 876 {
 877         u32 m = 0;
 878         if (plane != OMAP_DSS_GFX) {
 879                 switch (color_mode) {
 880                 case OMAP_DSS_COLOR_NV12:
 881                         m = 0x0; break;
 882                 case OMAP_DSS_COLOR_RGB12U:
 883                         m = 0x1; break;
 884                 case OMAP_DSS_COLOR_RGBA16:
 885                         m = 0x2; break;
 886                 case OMAP_DSS_COLOR_RGBX16:
 887                         m = 0x4; break;
 888                 case OMAP_DSS_COLOR_ARGB16:
 889                         m = 0x5; break;
 890                 case OMAP_DSS_COLOR_RGB16:
 891                         m = 0x6; break;
 892                 case OMAP_DSS_COLOR_ARGB16_1555:
 893                         m = 0x7; break;
 894                 case OMAP_DSS_COLOR_RGB24U:
 895                         m = 0x8; break;
 896                 case OMAP_DSS_COLOR_RGB24P:
 897                         m = 0x9; break;
 898                 case OMAP_DSS_COLOR_YUV2:
 899                         m = 0xa; break;
 900                 case OMAP_DSS_COLOR_UYVY:
 901                         m = 0xb; break;
 902                 case OMAP_DSS_COLOR_ARGB32:
 903                         m = 0xc; break;
 904                 case OMAP_DSS_COLOR_RGBA32:
 905                         m = 0xd; break;
 906                 case OMAP_DSS_COLOR_RGBX32:
 907                         m = 0xe; break;
 908                 case OMAP_DSS_COLOR_XRGB16_1555:
 909                         m = 0xf; break;
 910                 default:
 911                         BUG(); break;
 912                 }
 913         } else {
 914                 switch (color_mode) {
 915                 case OMAP_DSS_COLOR_CLUT1:
 916                         m = 0x0; break;
 917                 case OMAP_DSS_COLOR_CLUT2:
 918                         m = 0x1; break;
 919                 case OMAP_DSS_COLOR_CLUT4:
 920                         m = 0x2; break;
 921                 case OMAP_DSS_COLOR_CLUT8:
 922                         m = 0x3; break;
 923                 case OMAP_DSS_COLOR_RGB12U:
 924                         m = 0x4; break;
 925                 case OMAP_DSS_COLOR_ARGB16:
 926                         m = 0x5; break;
 927                 case OMAP_DSS_COLOR_RGB16:
 928                         m = 0x6; break;
 929                 case OMAP_DSS_COLOR_ARGB16_1555:
 930                         m = 0x7; break;
 931                 case OMAP_DSS_COLOR_RGB24U:
 932                         m = 0x8; break;
 933                 case OMAP_DSS_COLOR_RGB24P:
 934                         m = 0x9; break;
 935                 case OMAP_DSS_COLOR_YUV2:
 936                         m = 0xa; break;
 937                 case OMAP_DSS_COLOR_UYVY:
 938                         m = 0xb; break;
 939                 case OMAP_DSS_COLOR_ARGB32:
 940                         m = 0xc; break;
 941                 case OMAP_DSS_COLOR_RGBA32:
 942                         m = 0xd; break;
 943                 case OMAP_DSS_COLOR_RGBX32:
 944                         m = 0xe; break;
 945                 case OMAP_DSS_COLOR_XRGB16_1555:
 946                         m = 0xf; break;
 947                 default:
 948                         BUG(); break;
 949                 }
 950         }
 951
 952         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 953 }
 954
 955 static void dispc_ovl_set_channel_out(enum omap_plane plane,
 956                 enum omap_channel channel)
 957 {
 958         int shift;
 959         u32 val;
 960         int chan = 0, chan2 = 0;
 961
 962         switch (plane) {
 963         case OMAP_DSS_GFX:
 964                 shift = 8;
 965                 break;
 966         case OMAP_DSS_VIDEO1:
 967         case OMAP_DSS_VIDEO2:
 968         case OMAP_DSS_VIDEO3:
 969                 shift = 16;
 970                 break;
 971         default:
 972                 BUG();
 973                 return;
 974         }
 975
 976         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 977         if (dss_has_feature(FEAT_MGR_LCD2)) {
 978                 switch (channel) {
 979                 case OMAP_DSS_CHANNEL_LCD:
 980                         chan = 0;
 981                         chan2 = 0;
 982                         break;
 983                 case OMAP_DSS_CHANNEL_DIGIT:
 984                         chan = 1;
 985                         chan2 = 0;
 986                         break;
 987                 case OMAP_DSS_CHANNEL_LCD2:
 988                         chan = 0;
 989                         chan2 = 1;
 990                         break;
 991                 default:
 992                         BUG();
 993                 }
 994
 995                 val = FLD_MOD(val, chan, shift, shift);
 996                 val = FLD_MOD(val, chan2, 31, 30);
 997         } else {
 998                 val = FLD_MOD(val, channel, shift, shift);
 999         }
1000         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1001 }
1002
1003 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1004                 enum omap_burst_size burst_size)
1005 {
1006         static const unsigned shifts[] = { 6, 14, 14, 14, };
1007         int shift;
1008
1009         shift = shifts[plane];
1010         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1011 }
1012
1013 static void dispc_configure_burst_sizes(void)
1014 {
1015         int i;
1016         const int burst_size = BURST_SIZE_X8;
1017
1018         /* Configure burst size always to maximum size */
1019         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1020                 dispc_ovl_set_burst_size(i, burst_size);
1021 }
1022
1023 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1024 {
1025         unsigned unit = dss_feat_get_burst_size_unit();
1026         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1027         return unit * 8;
1028 }
1029
1030 void dispc_enable_gamma_table(bool enable)
1031 {
1032         /*
1033          * This is partially implemented to support only disabling of
1034          * the gamma table.
1035          */
1036         if (enable) {
1037                 DSSWARN("Gamma table enabling for TV not yet supported");
1038                 return;
1039         }
1040
1041         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1042 }
1043
1044 void dispc_set_gamma_table(void *table, u32 size)
1045 {
1046         if (table == NULL || size == 0 || size > TABLE_SIZE) {
1047                 REG_FLD_MOD(DISPC_CONFIG, 0, 3, 3);
1048                 return;
1049         }
1050
1051         memcpy(dispc.table_virt, table, size);
1052
1053         dispc_write_reg(DISPC_OVL_TABLE_BA(0), dispc.table_phys);
1054         dispc_set_loadmode(OMAP_DSS_LOAD_CLUT_ONCE_FRAME);
1055         REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
1056 }
1057
1058 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1059 {
1060         u16 reg;
1061
1062         if (channel == OMAP_DSS_CHANNEL_LCD)
1063                 reg = DISPC_CONFIG;
1064         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1065                 reg = DISPC_CONFIG2;
1066         else
1067                 return;
1068
1069         REG_FLD_MOD(reg, enable, 15, 15);
1070 }
1071
1072 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1073                 struct omap_dss_cpr_coefs *coefs)
1074 {
1075         u32 coef_r, coef_g, coef_b;
1076
1077         if (!dispc_mgr_is_lcd(channel))
1078                 return;
1079
1080         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1081                 FLD_VAL(coefs->rb, 9, 0);
1082         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1083                 FLD_VAL(coefs->gb, 9, 0);
1084         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1085                 FLD_VAL(coefs->bb, 9, 0);
1086
1087         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1088         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1089         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1090 }
1091
1092 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1093 {
1094         u32 val;
1095
1096         BUG_ON(plane == OMAP_DSS_GFX);
1097
1098         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1099         val = FLD_MOD(val, enable, 9, 9);
1100         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1101 }
1102
1103 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1104 {
1105         static const unsigned shifts[] = { 5, 10, 10, 10 };
1106         int shift;
1107
1108         shift = shifts[plane];
1109         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1110 }
1111
1112 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1113 {
1114         u32 val;
1115         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1116         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1117         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1118 }
1119
1120 void dispc_set_digit_size(u16 width, u16 height)
1121 {
1122         u32 val;
1123         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1124         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1125         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1126 }
1127
1128 static void dispc_read_plane_fifo_sizes(void)
1129 {
1130         u32 size;
1131         int plane;
1132         u8 start, end;
1133         u32 unit;
1134
1135         unit = dss_feat_get_buffer_size_unit();
1136
1137         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1138
1139         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1140                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1141                 size *= unit;
1142                 dispc.fifo_size[plane] = size;
1143         }
1144 }
1145
1146 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1147 {
1148         return dispc.fifo_size[plane];
1149 }
1150
1151 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1152                 u32 high)
1153 {
1154         u8 hi_start, hi_end, lo_start, lo_end;
1155         u32 unit;
1156
1157         unit = dss_feat_get_buffer_size_unit();
1158
1159         WARN_ON(low % unit != 0);
1160         WARN_ON(high % unit != 0);
1161
1162         low /= unit;
1163         high /= unit;
1164
1165         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1166         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1167
1168         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1169                         plane,
1170                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1171                                 lo_start, lo_end),
1172                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1173                                 hi_start, hi_end),
1174                         low, high);
1175
1176         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1177                         FLD_VAL(high, hi_start, hi_end) |
1178                         FLD_VAL(low, lo_start, lo_end));
1179 }
1180
1181 void dispc_enable_fifomerge(bool enable)
1182 {
1183         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1184         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1185 }
1186
1187 static void dispc_ovl_set_fir(enum omap_plane plane,
1188                                 int hinc, int vinc,
1189                                 enum omap_color_component color_comp)
1190 {
1191         u32 val;
1192
1193         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1194                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1195
1196                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1197                                         &hinc_start, &hinc_end);
1198                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1199                                         &vinc_start, &vinc_end);
1200                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1201                                 FLD_VAL(hinc, hinc_start, hinc_end);
1202
1203                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1204         } else {
1205                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1206                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1207         }
1208 }
1209
1210 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1211 {
1212         u32 val;
1213         u8 hor_start, hor_end, vert_start, vert_end;
1214
1215         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1216         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1217
1218         val = FLD_VAL(vaccu, vert_start, vert_end) |
1219                         FLD_VAL(haccu, hor_start, hor_end);
1220
1221         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1222 }
1223
1224 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1225 {
1226         u32 val;
1227         u8 hor_start, hor_end, vert_start, vert_end;
1228
1229         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1230         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1231
1232         val = FLD_VAL(vaccu, vert_start, vert_end) |
1233                         FLD_VAL(haccu, hor_start, hor_end);
1234
1235         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1236 }
1237
1238 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1239                 int vaccu)
1240 {
1241         u32 val;
1242
1243         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1244         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1245 }
1246
1247 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1248                 int vaccu)
1249 {
1250         u32 val;
1251
1252         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1253         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1254 }
1255
1256 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1257                 u16 orig_width, u16 orig_height,
1258                 u16 out_width, u16 out_height,
1259                 bool five_taps, u8 rotation,
1260                 enum omap_color_component color_comp)
1261 {
1262         int fir_hinc, fir_vinc;
1263         int hscaleup, vscaleup;
1264
1265         hscaleup = orig_width <= out_width;
1266         vscaleup = orig_height <= out_height;
1267
1268         dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1269                         color_comp);
1270
1271         fir_hinc = 1024 * orig_width / out_width;
1272         fir_vinc = 1024 * orig_height / out_height;
1273
1274         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1275 }
1276
1277 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1278                 u16 orig_width, u16 orig_height,
1279                 u16 out_width, u16 out_height,
1280                 bool ilace, bool five_taps,
1281                 bool fieldmode, enum omap_color_mode color_mode,
1282                 u8 rotation)
1283 {
1284         int accu0 = 0;
1285         int accu1 = 0;
1286         u32 l;
1287
1288         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1289                                 out_width, out_height, five_taps,
1290                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1291         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1292
1293         /* RESIZEENABLE and VERTICALTAPS */
1294         l &= ~((0x3 << 5) | (0x1 << 21));
1295         l |= (orig_width != out_width) ? (1 << 5) : 0;
1296         l |= (orig_height != out_height) ? (1 << 6) : 0;
1297         l |= five_taps ? (1 << 21) : 0;
1298
1299         /* VRESIZECONF and HRESIZECONF */
1300         if (dss_has_feature(FEAT_RESIZECONF)) {
1301                 l &= ~(0x3 << 7);
1302                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1303                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1304         }
1305
1306         /* LINEBUFFERSPLIT */
1307         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1308                 l &= ~(0x1 << 22);
1309                 l |= five_taps ? (1 << 22) : 0;
1310         }
1311
1312         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1313
1314         /*
1315          * field 0 = even field = bottom field
1316          * field 1 = odd field = top field
1317          */
1318         if (ilace && !fieldmode) {
1319                 accu1 = 0;
1320                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1321                 if (accu0 >= 1024/2) {
1322                         accu1 = 1024/2;
1323                         accu0 -= accu1;
1324                 }
1325         }
1326
1327         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1328         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1329 }
1330
1331 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1332                 u16 orig_width, u16 orig_height,
1333                 u16 out_width, u16 out_height,
1334                 bool ilace, bool five_taps,
1335                 bool fieldmode, enum omap_color_mode color_mode,
1336                 u8 rotation)
1337 {
1338         int scale_x = out_width != orig_width;
1339         int scale_y = out_height != orig_height;
1340
1341         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1342                 return;
1343         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1344                         color_mode != OMAP_DSS_COLOR_UYVY &&
1345                         color_mode != OMAP_DSS_COLOR_NV12)) {
1346                 /* reset chroma resampling for RGB formats  */
1347                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1348                 return;
1349         }
1350         switch (color_mode) {
1351         case OMAP_DSS_COLOR_NV12:
1352                 /* UV is subsampled by 2 vertically*/
1353                 orig_height >>= 1;
1354                 /* UV is subsampled by 2 horz.*/
1355                 orig_width >>= 1;
1356                 break;
1357         case OMAP_DSS_COLOR_YUV2:
1358         case OMAP_DSS_COLOR_UYVY:
1359                 /*For YUV422 with 90/270 rotation,
1360                  *we don't upsample chroma
1361                  */
1362                 if (rotation == OMAP_DSS_ROT_0 ||
1363                         rotation == OMAP_DSS_ROT_180)
1364                         /* UV is subsampled by 2 hrz*/
1365                         orig_width >>= 1;
1366                 /* must use FIR for YUV422 if rotated */
1367                 if (rotation != OMAP_DSS_ROT_0)
1368                         scale_x = scale_y = true;
1369                 break;
1370         default:
1371                 BUG();
1372         }
1373
1374         if (out_width != orig_width)
1375                 scale_x = true;
1376         if (out_height != orig_height)
1377                 scale_y = true;
1378
1379         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1380                         out_width, out_height, five_taps,
1381                                 rotation, DISPC_COLOR_COMPONENT_UV);
1382
1383         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1384                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1385         /* set H scaling */
1386         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1387         /* set V scaling */
1388         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1389
1390         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1391         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1392 }
1393
1394 static void dispc_ovl_set_scaling(enum omap_plane plane,
1395                 u16 orig_width, u16 orig_height,
1396                 u16 out_width, u16 out_height,
1397                 bool ilace, bool five_taps,
1398                 bool fieldmode, enum omap_color_mode color_mode,
1399                 u8 rotation)
1400 {
1401         BUG_ON(plane == OMAP_DSS_GFX);
1402
1403         dispc_ovl_set_scaling_common(plane,
1404                         orig_width, orig_height,
1405                         out_width, out_height,
1406                         ilace, five_taps,
1407                         fieldmode, color_mode,
1408                         rotation);
1409
1410         dispc_ovl_set_scaling_uv(plane,
1411                 orig_width, orig_height,
1412                 out_width, out_height,
1413                 ilace, five_taps,
1414                 fieldmode, color_mode,
1415                 rotation);
1416 }
1417
1418 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1419                 bool mirroring, enum omap_color_mode color_mode)
1420 {
1421         bool row_repeat = false;
1422         int vidrot = 0;
1423
1424         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1425                         color_mode == OMAP_DSS_COLOR_UYVY) {
1426
1427                 if (mirroring) {
1428                         switch (rotation) {
1429                         case OMAP_DSS_ROT_0:
1430                                 vidrot = 2;
1431                                 break;
1432                         case OMAP_DSS_ROT_90:
1433                                 vidrot = 1;
1434                                 break;
1435                         case OMAP_DSS_ROT_180:
1436                                 vidrot = 0;
1437                                 break;
1438                         case OMAP_DSS_ROT_270:
1439                                 vidrot = 3;
1440                                 break;
1441                         }
1442                 } else {
1443                         switch (rotation) {
1444                         case OMAP_DSS_ROT_0:
1445                                 vidrot = 0;
1446                                 break;
1447                         case OMAP_DSS_ROT_90:
1448                                 vidrot = 1;
1449                                 break;
1450                         case OMAP_DSS_ROT_180:
1451                                 vidrot = 2;
1452                                 break;
1453                         case OMAP_DSS_ROT_270:
1454                                 vidrot = 3;
1455                                 break;
1456                         }
1457                 }
1458
1459                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1460                         row_repeat = true;
1461                 else
1462                         row_repeat = false;
1463         }
1464
1465         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1466         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1467                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1468                         row_repeat ? 1 : 0, 18, 18);
1469 }
1470
1471 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1472 {
1473         switch (color_mode) {
1474         case OMAP_DSS_COLOR_CLUT1:
1475                 return 1;
1476         case OMAP_DSS_COLOR_CLUT2:
1477                 return 2;
1478         case OMAP_DSS_COLOR_CLUT4:
1479                 return 4;
1480         case OMAP_DSS_COLOR_CLUT8:
1481         case OMAP_DSS_COLOR_NV12:
1482                 return 8;
1483         case OMAP_DSS_COLOR_RGB12U:
1484         case OMAP_DSS_COLOR_RGB16:
1485         case OMAP_DSS_COLOR_ARGB16:
1486         case OMAP_DSS_COLOR_YUV2:
1487         case OMAP_DSS_COLOR_UYVY:
1488         case OMAP_DSS_COLOR_RGBA16:
1489         case OMAP_DSS_COLOR_RGBX16:
1490         case OMAP_DSS_COLOR_ARGB16_1555:
1491         case OMAP_DSS_COLOR_XRGB16_1555:
1492                 return 16;
1493         case OMAP_DSS_COLOR_RGB24P:
1494                 return 24;
1495         case OMAP_DSS_COLOR_RGB24U:
1496         case OMAP_DSS_COLOR_ARGB32:
1497         case OMAP_DSS_COLOR_RGBA32:
1498         case OMAP_DSS_COLOR_RGBX32:
1499                 return 32;
1500         default:
1501                 BUG();
1502         }
1503 }
1504
1505 static s32 pixinc(int pixels, u8 ps)
1506 {
1507         if (pixels == 1)
1508                 return 1;
1509         else if (pixels > 1)
1510                 return 1 + (pixels - 1) * ps;
1511         else if (pixels < 0)
1512                 return 1 - (-pixels + 1) * ps;
1513         else
1514                 BUG();
1515 }
1516
1517 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1518                 u16 screen_width,
1519                 u16 width, u16 height,
1520                 enum omap_color_mode color_mode, bool fieldmode,
1521                 unsigned int field_offset,
1522                 unsigned *offset0, unsigned *offset1,
1523                 s32 *row_inc, s32 *pix_inc)
1524 {
1525         u8 ps;
1526
1527         /* FIXME CLUT formats */
1528         switch (color_mode) {
1529         case OMAP_DSS_COLOR_CLUT1:
1530         case OMAP_DSS_COLOR_CLUT2:
1531         case OMAP_DSS_COLOR_CLUT4:
1532         case OMAP_DSS_COLOR_CLUT8:
1533                 BUG();
1534                 return;
1535         case OMAP_DSS_COLOR_YUV2:
1536         case OMAP_DSS_COLOR_UYVY:
1537                 ps = 4;
1538                 break;
1539         default:
1540                 ps = color_mode_to_bpp(color_mode) / 8;
1541                 break;
1542         }
1543
1544         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1545                         width, height);
1546
1547         /*
1548          * field 0 = even field = bottom field
1549          * field 1 = odd field = top field
1550          */
1551         switch (rotation + mirror * 4) {
1552         case OMAP_DSS_ROT_0:
1553         case OMAP_DSS_ROT_180:
1554                 /*
1555                  * If the pixel format is YUV or UYVY divide the width
1556                  * of the image by 2 for 0 and 180 degree rotation.
1557                  */
1558                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1559                         color_mode == OMAP_DSS_COLOR_UYVY)
1560                         width = width >> 1;
1561         case OMAP_DSS_ROT_90:
1562         case OMAP_DSS_ROT_270:
1563                 *offset1 = 0;
1564                 if (field_offset)
1565                         *offset0 = field_offset * screen_width * ps;
1566                 else
1567                         *offset0 = 0;
1568
1569                 *row_inc = pixinc(1 + (screen_width - width) +
1570                                 (fieldmode ? screen_width : 0),
1571                                 ps);
1572                 *pix_inc = pixinc(1, ps);
1573                 break;
1574
1575         case OMAP_DSS_ROT_0 + 4:
1576         case OMAP_DSS_ROT_180 + 4:
1577                 /* If the pixel format is YUV or UYVY divide the width
1578                  * of the image by 2  for 0 degree and 180 degree
1579                  */
1580                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1581                         color_mode == OMAP_DSS_COLOR_UYVY)
1582                         width = width >> 1;
1583         case OMAP_DSS_ROT_90 + 4:
1584         case OMAP_DSS_ROT_270 + 4:
1585                 *offset1 = 0;
1586                 if (field_offset)
1587                         *offset0 = field_offset * screen_width * ps;
1588                 else
1589                         *offset0 = 0;
1590                 *row_inc = pixinc(1 - (screen_width + width) -
1591                                 (fieldmode ? screen_width : 0),
1592                                 ps);
1593                 *pix_inc = pixinc(1, ps);
1594                 break;
1595
1596         default:
1597                 BUG();
1598         }
1599 }
1600
1601 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1602                 u16 screen_width,
1603                 u16 width, u16 height,
1604                 enum omap_color_mode color_mode, bool fieldmode,
1605                 unsigned int field_offset,
1606                 unsigned *offset0, unsigned *offset1,
1607                 s32 *row_inc, s32 *pix_inc)
1608 {
1609         u8 ps;
1610         u16 fbw, fbh;
1611
1612         /* FIXME CLUT formats */
1613         switch (color_mode) {
1614         case OMAP_DSS_COLOR_CLUT1:
1615         case OMAP_DSS_COLOR_CLUT2:
1616         case OMAP_DSS_COLOR_CLUT4:
1617         case OMAP_DSS_COLOR_CLUT8:
1618                 BUG();
1619                 return;
1620         default:
1621                 ps = color_mode_to_bpp(color_mode) / 8;
1622                 break;
1623         }
1624
1625         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1626                         width, height);
1627
1628         /* width & height are overlay sizes, convert to fb sizes */
1629
1630         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1631                 fbw = width;
1632                 fbh = height;
1633         } else {
1634                 fbw = height;
1635                 fbh = width;
1636         }
1637
1638         /*
1639          * field 0 = even field = bottom field
1640          * field 1 = odd field = top field
1641          */
1642         switch (rotation + mirror * 4) {
1643         case OMAP_DSS_ROT_0:
1644                 *offset1 = 0;
1645                 if (field_offset)
1646                         *offset0 = *offset1 + field_offset * screen_width * ps;
1647                 else
1648                         *offset0 = *offset1;
1649                 *row_inc = pixinc(1 + (screen_width - fbw) +
1650                                 (fieldmode ? screen_width : 0),
1651                                 ps);
1652                 *pix_inc = pixinc(1, ps);
1653                 break;
1654         case OMAP_DSS_ROT_90:
1655                 *offset1 = screen_width * (fbh - 1) * ps;
1656                 if (field_offset)
1657                         *offset0 = *offset1 + field_offset * ps;
1658                 else
1659                         *offset0 = *offset1;
1660                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1661                                 (fieldmode ? 1 : 0), ps);
1662                 *pix_inc = pixinc(-screen_width, ps);
1663                 break;
1664         case OMAP_DSS_ROT_180:
1665                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1666                 if (field_offset)
1667                         *offset0 = *offset1 - field_offset * screen_width * ps;
1668                 else
1669                         *offset0 = *offset1;
1670                 *row_inc = pixinc(-1 -
1671                                 (screen_width - fbw) -
1672                                 (fieldmode ? screen_width : 0),
1673                                 ps);
1674                 *pix_inc = pixinc(-1, ps);
1675                 break;
1676         case OMAP_DSS_ROT_270:
1677                 *offset1 = (fbw - 1) * ps;
1678                 if (field_offset)
1679                         *offset0 = *offset1 - field_offset * ps;
1680                 else
1681                         *offset0 = *offset1;
1682                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1683                                 (fieldmode ? 1 : 0), ps);
1684                 *pix_inc = pixinc(screen_width, ps);
1685                 break;
1686
1687         /* mirroring */
1688         case OMAP_DSS_ROT_0 + 4:
1689                 *offset1 = (fbw - 1) * ps;
1690                 if (field_offset)
1691                         *offset0 = *offset1 + field_offset * screen_width * ps;
1692                 else
1693                         *offset0 = *offset1;
1694                 *row_inc = pixinc(screen_width * 2 - 1 +
1695                                 (fieldmode ? screen_width : 0),
1696                                 ps);
1697                 *pix_inc = pixinc(-1, ps);
1698                 break;
1699
1700         case OMAP_DSS_ROT_90 + 4:
1701                 *offset1 = 0;
1702                 if (field_offset)
1703                         *offset0 = *offset1 + field_offset * ps;
1704                 else
1705                         *offset0 = *offset1;
1706                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1707                                 (fieldmode ? 1 : 0),
1708                                 ps);
1709                 *pix_inc = pixinc(screen_width, ps);
1710                 break;
1711
1712         case OMAP_DSS_ROT_180 + 4:
1713                 *offset1 = screen_width * (fbh - 1) * ps;
1714                 if (field_offset)
1715                         *offset0 = *offset1 - field_offset * screen_width * ps;
1716                 else
1717                         *offset0 = *offset1;
1718                 *row_inc = pixinc(1 - screen_width * 2 -
1719                                 (fieldmode ? screen_width : 0),
1720                                 ps);
1721                 *pix_inc = pixinc(1, ps);
1722                 break;
1723
1724         case OMAP_DSS_ROT_270 + 4:
1725                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1726                 if (field_offset)
1727                         *offset0 = *offset1 - field_offset * ps;
1728                 else
1729                         *offset0 = *offset1;
1730                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1731                                 (fieldmode ? 1 : 0),
1732                                 ps);
1733                 *pix_inc = pixinc(-screen_width, ps);
1734                 break;
1735
1736         default:
1737                 BUG();
1738         }
1739 }
1740
1741 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1742                 u16 height, u16 out_width, u16 out_height,
1743                 enum omap_color_mode color_mode)
1744 {
1745         u32 fclk = 0;
1746         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1747
1748         if (height > out_height) {
1749                 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1750                 unsigned int ppl = dssdev->panel.timings.x_res;
1751
1752                 tmp = pclk * height * out_width;
1753                 do_div(tmp, 2 * out_height * ppl);
1754                 fclk = tmp;
1755
1756                 if (height > 2 * out_height) {
1757                         if (ppl == out_width)
1758                                 return 0;
1759
1760                         tmp = pclk * (height - 2 * out_height) * out_width;
1761                         do_div(tmp, 2 * out_height * (ppl - out_width));
1762                         fclk = max(fclk, (u32) tmp);
1763                 }
1764         }
1765
1766         if (width > out_width) {
1767                 tmp = pclk * width;
1768                 do_div(tmp, out_width);
1769                 fclk = max(fclk, (u32) tmp);
1770
1771                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1772                         fclk <<= 1;
1773         }
1774
1775         return fclk;
1776 }
1777
1778 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1779                 u16 height, u16 out_width, u16 out_height)
1780 {
1781         unsigned int hf, vf;
1782
1783         /*
1784          * FIXME how to determine the 'A' factor
1785          * for the no downscaling case ?
1786          */
1787
1788         if (width > 3 * out_width)
1789                 hf = 4;
1790         else if (width > 2 * out_width)
1791                 hf = 3;
1792         else if (width > out_width)
1793                 hf = 2;
1794         else
1795                 hf = 1;
1796
1797         if (height > out_height)
1798                 vf = 2;
1799         else
1800                 vf = 1;
1801
1802         return dispc_mgr_pclk_rate(channel) * vf * hf;
1803 }
1804
1805 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1806                 enum omap_channel channel, u16 width, u16 height,
1807                 u16 out_width, u16 out_height,
1808                 enum omap_color_mode color_mode, bool *five_taps)
1809 {
1810         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1811         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1812         unsigned long fclk = 0;
1813
1814         if (width == out_width && height == out_height)
1815                 return 0;
1816
1817         if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1818                 return -EINVAL;
1819
1820         if (out_width < width / maxdownscale ||
1821                         out_width > width * 8)
1822                 return -EINVAL;
1823
1824         if (out_height < height / maxdownscale ||
1825                         out_height > height * 8)
1826                 return -EINVAL;
1827
1828         /* Must use 5-tap filter? */
1829         *five_taps = height > out_height * 2;
1830
1831         if (!*five_taps) {
1832                 fclk = calc_fclk(channel, width, height, out_width,
1833                                 out_height);
1834
1835                 /* Try 5-tap filter if 3-tap fclk is too high */
1836                 if (cpu_is_omap34xx() && height > out_height &&
1837                                 fclk > dispc_fclk_rate())
1838                         *five_taps = true;
1839         }
1840
1841         if (width > (2048 >> *five_taps)) {
1842                 DSSERR("failed to set up scaling, fclk too low\n");
1843                 return -EINVAL;
1844         }
1845
1846         if (*five_taps)
1847                 fclk = calc_fclk_five_taps(channel, width, height,
1848                                 out_width, out_height, color_mode);
1849
1850         DSSDBG("required fclk rate = %lu Hz\n", fclk);
1851         DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1852
1853         if (!fclk || fclk > dispc_fclk_rate()) {
1854                 DSSERR("failed to set up scaling, "
1855                         "required fclk rate = %lu Hz, "
1856                         "current fclk rate = %lu Hz\n",
1857                         fclk, dispc_fclk_rate());
1858                 return -EINVAL;
1859         }
1860
1861         return 0;
1862 }
1863
1864 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1865                 bool ilace, enum omap_channel channel, bool replication,
1866                 u32 fifo_low, u32 fifo_high)
1867 {
1868         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1869         bool five_taps = false;
1870         bool fieldmode = 0;
1871         int r, cconv = 0;
1872         unsigned offset0, offset1;
1873         s32 row_inc;
1874         s32 pix_inc;
1875         u16 frame_height = oi->height;
1876         unsigned int field_offset = 0;
1877
1878         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1879                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1880                 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1881                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1882                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1883                 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1884
1885         if (oi->paddr == 0)
1886                 return -EINVAL;
1887
1888         if (ilace && oi->height == oi->out_height)
1889                 fieldmode = 1;
1890
1891         if (ilace) {
1892                 if (fieldmode)
1893                         oi->height /= 2;
1894                 oi->pos_y /= 2;
1895                 oi->out_height /= 2;
1896
1897                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1898                                 "out_height %d\n",
1899                                 oi->height, oi->pos_y, oi->out_height);
1900         }
1901
1902         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1903                 return -EINVAL;
1904
1905         r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1906                         oi->out_width, oi->out_height, oi->color_mode,
1907                         &five_taps);
1908         if (r)
1909                 return r;
1910
1911         if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1912                         oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1913                         oi->color_mode == OMAP_DSS_COLOR_NV12)
1914                 cconv = 1;
1915
1916         if (ilace && !fieldmode) {
1917                 /*
1918                  * when downscaling the bottom field may have to start several
1919                  * source lines below the top field. Unfortunately ACCUI
1920                  * registers will only hold the fractional part of the offset
1921                  * so the integer part must be added to the base address of the
1922                  * bottom field.
1923                  */
1924                 if (!oi->height || oi->height == oi->out_height)
1925                         field_offset = 0;
1926                 else
1927                         field_offset = oi->height / oi->out_height / 2;
1928         }
1929
1930         /* Fields are independent but interleaved in memory. */
1931         if (fieldmode)
1932                 field_offset = 1;
1933
1934         if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1935                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1936                                 oi->screen_width, oi->width, frame_height,
1937                                 oi->color_mode, fieldmode, field_offset,
1938                                 &offset0, &offset1, &row_inc, &pix_inc);
1939         else
1940                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1941                                 oi->screen_width, oi->width, frame_height,
1942                                 oi->color_mode, fieldmode, field_offset,
1943                                 &offset0, &offset1, &row_inc, &pix_inc);
1944
1945         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1946                         offset0, offset1, row_inc, pix_inc);
1947
1948         dispc_ovl_set_color_mode(plane, oi->color_mode);
1949
1950         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1951         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1952
1953         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1954                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1955                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1956         }
1957
1958
1959         dispc_ovl_set_row_inc(plane, row_inc);
1960         dispc_ovl_set_pix_inc(plane, pix_inc);
1961
1962         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1963                         oi->height, oi->out_width, oi->out_height);
1964
1965         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1966
1967         dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1968
1969         if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1970                 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1971                                    oi->out_width, oi->out_height,
1972                                    ilace, five_taps, fieldmode,
1973                                    oi->color_mode, oi->rotation);
1974                 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1975                 dispc_ovl_set_vid_color_conv(plane, cconv);
1976         }
1977
1978         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1979                         oi->color_mode);
1980
1981         dispc_ovl_set_zorder(plane, oi->zorder);
1982         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1983         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1984
1985         dispc_ovl_set_channel_out(plane, channel);
1986
1987         dispc_ovl_enable_replication(plane, replication);
1988         dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1989
1990         return 0;
1991 }
1992
1993 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1994 {
1995         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1996
1997         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1998
1999         return 0;
2000 }
2001
2002 static void dispc_disable_isr(void *data, u32 mask)
2003 {
2004         struct completion *compl = data;
2005         complete(compl);
2006 }
2007
2008 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2009 {
2010         if (channel == OMAP_DSS_CHANNEL_LCD2)
2011                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2012         else
2013                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
2014 }
2015
2016 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2017 {
2018         struct completion frame_done_completion;
2019         bool is_on;
2020         int r;
2021         u32 irq;
2022
2023         /* When we disable LCD output, we need to wait until frame is done.
2024          * Otherwise the DSS is still working, and turning off the clocks
2025          * prevents DSS from going to OFF mode */
2026         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2027                         REG_GET(DISPC_CONTROL2, 0, 0) :
2028                         REG_GET(DISPC_CONTROL, 0, 0);
2029
2030         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2031                         DISPC_IRQ_FRAMEDONE;
2032
2033         if (!enable && is_on) {
2034                 init_completion(&frame_done_completion);
2035
2036                 r = omap_dispc_register_isr(dispc_disable_isr,
2037                                 &frame_done_completion, irq);
2038
2039                 if (r)
2040                         DSSERR("failed to register FRAMEDONE isr\n");
2041         }
2042
2043         _enable_lcd_out(channel, enable);
2044
2045         if (!enable && is_on) {
2046                 if (!wait_for_completion_timeout(&frame_done_completion,
2047                                         msecs_to_jiffies(100)))
2048                         DSSERR("timeout waiting for FRAME DONE\n");
2049
2050                 r = omap_dispc_unregister_isr(dispc_disable_isr,
2051                                 &frame_done_completion, irq);
2052
2053                 if (r)
2054                         DSSERR("failed to unregister FRAMEDONE isr\n");
2055         }
2056 }
2057
2058 static void _enable_digit_out(bool enable)
2059 {
2060         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2061 }
2062
2063 static void dispc_mgr_enable_digit_out(bool enable)
2064 {
2065         struct completion frame_done_completion;
2066         enum dss_hdmi_venc_clk_source_select src;
2067         int r, i;
2068         u32 irq_mask;
2069         int num_irqs;
2070
2071         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2072                 return;
2073
2074         src = dss_get_hdmi_venc_clk_source();
2075
2076         if (enable) {
2077                 unsigned long flags;
2078                 /* When we enable digit output, we'll get an extra digit
2079                  * sync lost interrupt, that we need to ignore */
2080                 spin_lock_irqsave(&dispc.irq_lock, flags);
2081                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2082                 _omap_dispc_set_irqs();
2083                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2084         }
2085
2086         /* When we disable digit output, we need to wait until fields are done.
2087          * Otherwise the DSS is still working, and turning off the clocks
2088          * prevents DSS from going to OFF mode. And when enabling, we need to
2089          * wait for the extra sync losts */
2090         init_completion(&frame_done_completion);
2091
2092         if (src == DSS_HDMI_M_PCLK && enable == false) {
2093                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2094                 num_irqs = 1;
2095         } else {
2096                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2097                 /* XXX I understand from TRM that we should only wait for the
2098                  * current field to complete. But it seems we have to wait for
2099                  * both fields */
2100                 num_irqs = 2;
2101         }
2102
2103         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2104                         irq_mask);
2105         if (r)
2106                 DSSERR("failed to register %x isr\n", irq_mask);
2107
2108         _enable_digit_out(enable);
2109
2110         for (i = 0; i < num_irqs; ++i) {
2111                 if (!wait_for_completion_timeout(&frame_done_completion,
2112                                         msecs_to_jiffies(100)))
2113                         DSSERR("timeout waiting for digit out to %s\n",
2114                                         enable ? "start" : "stop");
2115         }
2116
2117         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2118                         irq_mask);
2119         if (r)
2120                 DSSERR("failed to unregister %x isr\n", irq_mask);
2121
2122         if (enable) {
2123                 unsigned long flags;
2124                 spin_lock_irqsave(&dispc.irq_lock, flags);
2125                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2126                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2127                 _omap_dispc_set_irqs();
2128                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2129         }
2130 }
2131
2132 bool dispc_mgr_is_enabled(enum omap_channel channel)
2133 {
2134         if (channel == OMAP_DSS_CHANNEL_LCD)
2135                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2136         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2137                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2138         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2139                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2140         else
2141                 BUG();
2142 }
2143
2144 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2145 {
2146         if (dispc_mgr_is_lcd(channel))
2147                 dispc_mgr_enable_lcd_out(channel, enable);
2148         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2149                 dispc_mgr_enable_digit_out(enable);
2150         else
2151                 BUG();
2152 }
2153
2154 void dispc_lcd_enable_signal_polarity(bool act_high)
2155 {
2156         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2157                 return;
2158
2159         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2160 }
2161
2162 void dispc_lcd_enable_signal(bool enable)
2163 {
2164         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2165                 return;
2166
2167         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2168 }
2169
2170 void dispc_pck_free_enable(bool enable)
2171 {
2172         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2173                 return;
2174
2175         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2176 }
2177
2178 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2179 {
2180         if (channel == OMAP_DSS_CHANNEL_LCD2)
2181                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2182         else
2183                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2184 }
2185
2186
2187 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2188                 enum omap_lcd_display_type type)
2189 {
2190         int mode;
2191
2192         switch (type) {
2193         case OMAP_DSS_LCD_DISPLAY_STN:
2194                 mode = 0;
2195                 break;
2196
2197         case OMAP_DSS_LCD_DISPLAY_TFT:
2198                 mode = 1;
2199                 break;
2200
2201         default:
2202                 BUG();
2203                 return;
2204         }
2205
2206         if (channel == OMAP_DSS_CHANNEL_LCD2)
2207                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2208         else
2209                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2210 }
2211
2212 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2213 {
2214         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2215 }
2216
2217
2218 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2219 {
2220         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2221 }
2222
2223 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2224 {
2225         u32 l;
2226
2227         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2228                 channel != OMAP_DSS_CHANNEL_LCD &&
2229                 channel != OMAP_DSS_CHANNEL_LCD2);
2230
2231         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2232
2233         return l;
2234 }
2235
2236 void dispc_mgr_set_trans_key(enum omap_channel ch,
2237                 enum omap_dss_trans_key_type type,
2238                 u32 trans_key)
2239 {
2240         if (ch == OMAP_DSS_CHANNEL_LCD)
2241                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2242         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2243                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2244         else /* OMAP_DSS_CHANNEL_LCD2 */
2245                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2246
2247         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2248 }
2249
2250 void dispc_mgr_get_trans_key(enum omap_channel ch,
2251                 enum omap_dss_trans_key_type *type,
2252                 u32 *trans_key)
2253 {
2254         if (type) {
2255                 if (ch == OMAP_DSS_CHANNEL_LCD)
2256                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2257                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2258                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2259                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2260                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2261                 else
2262                         BUG();
2263         }
2264
2265         if (trans_key)
2266                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2267 }
2268
2269 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2270 {
2271         if (ch == OMAP_DSS_CHANNEL_LCD)
2272                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2273         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2274                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2275         else /* OMAP_DSS_CHANNEL_LCD2 */
2276                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2277 }
2278
2279 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2280 {
2281         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2282                 return;
2283
2284         if (ch == OMAP_DSS_CHANNEL_LCD)
2285                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2286         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2287                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2288 }
2289
2290 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2291 {
2292         bool enabled;
2293
2294         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2295                 return false;
2296
2297         if (ch == OMAP_DSS_CHANNEL_LCD)
2298                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2299         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2300                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2301         else
2302                 BUG();
2303
2304         return enabled;
2305 }
2306
2307 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2308 {
2309         bool enabled;
2310
2311         if (ch == OMAP_DSS_CHANNEL_LCD)
2312                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2313         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2314                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2315         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2316                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2317         else
2318                 BUG();
2319
2320         return enabled;
2321 }
2322
2323
2324 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2325 {
2326         int code;
2327
2328         switch (data_lines) {
2329         case 12:
2330                 code = 0;
2331                 break;
2332         case 16:
2333                 code = 1;
2334                 break;
2335         case 18:
2336                 code = 2;
2337                 break;
2338         case 24:
2339                 code = 3;
2340                 break;
2341         default:
2342                 BUG();
2343                 return;
2344         }
2345
2346         if (channel == OMAP_DSS_CHANNEL_LCD2)
2347                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2348         else
2349                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2350 }
2351
2352 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2353 {
2354         u32 l;
2355         int gpout0, gpout1;
2356
2357         switch (mode) {
2358         case DSS_IO_PAD_MODE_RESET:
2359                 gpout0 = 0;
2360                 gpout1 = 0;
2361                 break;
2362         case DSS_IO_PAD_MODE_RFBI:
2363                 gpout0 = 1;
2364                 gpout1 = 0;
2365                 break;
2366         case DSS_IO_PAD_MODE_BYPASS:
2367                 gpout0 = 1;
2368                 gpout1 = 1;
2369                 break;
2370         default:
2371                 BUG();
2372                 return;
2373         }
2374
2375         l = dispc_read_reg(DISPC_CONTROL);
2376         l = FLD_MOD(l, gpout0, 15, 15);
2377         l = FLD_MOD(l, gpout1, 16, 16);
2378         dispc_write_reg(DISPC_CONTROL, l);
2379 }
2380
2381 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2382 {
2383         if (channel == OMAP_DSS_CHANNEL_LCD2)
2384                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2385         else
2386                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2387 }
2388
2389 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2390                 int vsw, int vfp, int vbp)
2391 {
2392         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2393                 if (hsw < 1 || hsw > 64 ||
2394                                 hfp < 1 || hfp > 256 ||
2395                                 hbp < 1 || hbp > 256 ||
2396                                 vsw < 1 || vsw > 64 ||
2397                                 vfp < 0 || vfp > 255 ||
2398                                 vbp < 0 || vbp > 255)
2399                         return false;
2400         } else {
2401                 if (hsw < 1 || hsw > 256 ||
2402                                 hfp < 1 || hfp > 4096 ||
2403                                 hbp < 1 || hbp > 4096 ||
2404                                 vsw < 1 || vsw > 256 ||
2405                                 vfp < 0 || vfp > 4095 ||
2406                                 vbp < 0 || vbp > 4095)
2407                         return false;
2408         }
2409
2410         return true;
2411 }
2412
2413 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2414 {
2415         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2416                         timings->hbp, timings->vsw,
2417                         timings->vfp, timings->vbp);
2418 }
2419
2420 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2421                 int hfp, int hbp, int vsw, int vfp, int vbp)
2422 {
2423         u32 timing_h, timing_v;
2424
2425         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2426                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2427                         FLD_VAL(hbp-1, 27, 20);
2428
2429                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2430                         FLD_VAL(vbp, 27, 20);
2431         } else {
2432                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2433                         FLD_VAL(hbp-1, 31, 20);
2434
2435                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2436                         FLD_VAL(vbp, 31, 20);
2437         }
2438
2439         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2440         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2441 }
2442
2443 /* change name to mode? */
2444 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2445                 struct omap_video_timings *timings)
2446 {
2447         unsigned xtot, ytot;
2448         unsigned long ht, vt;
2449
2450         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2451                                 timings->hbp, timings->vsw,
2452                                 timings->vfp, timings->vbp))
2453                 BUG();
2454
2455         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2456                         timings->hbp, timings->vsw, timings->vfp,
2457                         timings->vbp);
2458
2459         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2460
2461         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2462         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2463
2464         ht = (timings->pixel_clock * 1000) / xtot;
2465         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2466
2467         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2468                         timings->y_res);
2469         DSSDBG("pck %u\n", timings->pixel_clock);
2470         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2471                         timings->hsw, timings->hfp, timings->hbp,
2472                         timings->vsw, timings->vfp, timings->vbp);
2473
2474         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2475 }
2476
2477 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2478                 u16 pck_div)
2479 {
2480         BUG_ON(lck_div < 1);
2481         BUG_ON(pck_div < 1);
2482
2483         dispc_write_reg(DISPC_DIVISORo(channel),
2484                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2485 }
2486
2487 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2488                 int *pck_div)
2489 {
2490         u32 l;
2491         l = dispc_read_reg(DISPC_DIVISORo(channel));
2492         *lck_div = FLD_GET(l, 23, 16);
2493         *pck_div = FLD_GET(l, 7, 0);
2494 }
2495
2496 unsigned long dispc_fclk_rate(void)
2497 {
2498         struct platform_device *dsidev;
2499         unsigned long r = 0;
2500
2501         switch (dss_get_dispc_clk_source()) {
2502         case OMAP_DSS_CLK_SRC_FCK:
2503                 r = clk_get_rate(dispc.dss_clk);
2504                 break;
2505         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2506                 dsidev = dsi_get_dsidev_from_id(0);
2507                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2508                 break;
2509         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2510                 dsidev = dsi_get_dsidev_from_id(1);
2511                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2512                 break;
2513         default:
2514                 BUG();
2515         }
2516
2517         return r;
2518 }
2519
2520 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2521 {
2522         struct platform_device *dsidev;
2523         int lcd;
2524         unsigned long r;
2525         u32 l;
2526
2527         l = dispc_read_reg(DISPC_DIVISORo(channel));
2528
2529         lcd = FLD_GET(l, 23, 16);
2530
2531         switch (dss_get_lcd_clk_source(channel)) {
2532         case OMAP_DSS_CLK_SRC_FCK:
2533                 r = clk_get_rate(dispc.dss_clk);
2534                 break;
2535         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2536                 dsidev = dsi_get_dsidev_from_id(0);
2537                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2538                 break;
2539         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2540                 dsidev = dsi_get_dsidev_from_id(1);
2541                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2542                 break;
2543         default:
2544                 BUG();
2545         }
2546
2547         return r / lcd;
2548 }
2549
2550 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2551 {
2552         unsigned long r;
2553
2554         if (dispc_mgr_is_lcd(channel)) {
2555                 int pcd;
2556                 u32 l;
2557
2558                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2559
2560                 pcd = FLD_GET(l, 7, 0);
2561
2562                 r = dispc_mgr_lclk_rate(channel);
2563
2564                 return r / pcd;
2565         } else {
2566                 struct omap_dss_device *dssdev =
2567                         dispc_mgr_get_device(channel);
2568
2569                 switch (dssdev->type) {
2570                 case OMAP_DISPLAY_TYPE_VENC:
2571                         return venc_get_pixel_clock();
2572                 case OMAP_DISPLAY_TYPE_HDMI:
2573                         return hdmi_get_pixel_clock();
2574                 default:
2575                         BUG();
2576                 }
2577         }
2578 }
2579
2580 void dispc_dump_clocks(struct seq_file *s)
2581 {
2582         int lcd, pcd;
2583         u32 l;
2584         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2585         enum omap_dss_clk_source lcd_clk_src;
2586
2587         if (dispc_runtime_get())
2588                 return;
2589
2590         seq_printf(s, "- DISPC -\n");
2591
2592         seq_printf(s, "dispc fclk source = %s (%s)\n",
2593                         dss_get_generic_clk_source_name(dispc_clk_src),
2594                         dss_feat_get_clk_source_name(dispc_clk_src));
2595
2596         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2597
2598         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2599                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2600                 l = dispc_read_reg(DISPC_DIVISOR);
2601                 lcd = FLD_GET(l, 23, 16);
2602
2603                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2604                                 (dispc_fclk_rate()/lcd), lcd);
2605         }
2606         seq_printf(s, "- LCD1 -\n");
2607
2608         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2609
2610         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2611                 dss_get_generic_clk_source_name(lcd_clk_src),
2612                 dss_feat_get_clk_source_name(lcd_clk_src));
2613
2614         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2615
2616         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2617                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2618         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2619                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2620         if (dss_has_feature(FEAT_MGR_LCD2)) {
2621                 seq_printf(s, "- LCD2 -\n");
2622
2623                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2624
2625                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2626                         dss_get_generic_clk_source_name(lcd_clk_src),
2627                         dss_feat_get_clk_source_name(lcd_clk_src));
2628
2629                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2630
2631                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2632                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2633                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2634                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2635         }
2636
2637         dispc_runtime_put();
2638 }
2639
2640 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2641 void dispc_dump_irqs(struct seq_file *s)
2642 {
2643         unsigned long flags;
2644         struct dispc_irq_stats stats;
2645
2646         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2647
2648         stats = dispc.irq_stats;
2649         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2650         dispc.irq_stats.last_reset = jiffies;
2651
2652         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2653
2654         seq_printf(s, "period %u ms\n",
2655                         jiffies_to_msecs(jiffies - stats.last_reset));
2656
2657         seq_printf(s, "irqs %d\n", stats.irq_count);
2658 #define PIS(x) \
2659         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2660
2661         PIS(FRAMEDONE);
2662         PIS(VSYNC);
2663         PIS(EVSYNC_EVEN);
2664         PIS(EVSYNC_ODD);
2665         PIS(ACBIAS_COUNT_STAT);
2666         PIS(PROG_LINE_NUM);
2667         PIS(GFX_FIFO_UNDERFLOW);
2668         PIS(GFX_END_WIN);
2669         PIS(PAL_GAMMA_MASK);
2670         PIS(OCP_ERR);
2671         PIS(VID1_FIFO_UNDERFLOW);
2672         PIS(VID1_END_WIN);
2673         PIS(VID2_FIFO_UNDERFLOW);
2674         PIS(VID2_END_WIN);
2675         if (dss_feat_get_num_ovls() > 3) {
2676                 PIS(VID3_FIFO_UNDERFLOW);
2677                 PIS(VID3_END_WIN);
2678         }
2679         PIS(SYNC_LOST);
2680         PIS(SYNC_LOST_DIGIT);
2681         PIS(WAKEUP);
2682         if (dss_has_feature(FEAT_MGR_LCD2)) {
2683                 PIS(FRAMEDONE2);
2684                 PIS(VSYNC2);
2685                 PIS(ACBIAS_COUNT_STAT2);
2686                 PIS(SYNC_LOST2);
2687         }
2688 #undef PIS
2689 }
2690 #endif
2691
2692 void dispc_dump_regs(struct seq_file *s)
2693 {
2694         int i, j;
2695         const char *mgr_names[] = {
2696                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2697                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2698                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2699         };
2700         const char *ovl_names[] = {
2701                 [OMAP_DSS_GFX]          = "GFX",
2702                 [OMAP_DSS_VIDEO1]       = "VID1",
2703                 [OMAP_DSS_VIDEO2]       = "VID2",
2704                 [OMAP_DSS_VIDEO3]       = "VID3",
2705         };
2706         const char **p_names;
2707
2708 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2709
2710         if (dispc_runtime_get())
2711                 return;
2712
2713         /* DISPC common registers */
2714         DUMPREG(DISPC_REVISION);
2715         DUMPREG(DISPC_SYSCONFIG);
2716         DUMPREG(DISPC_SYSSTATUS);
2717         DUMPREG(DISPC_IRQSTATUS);
2718         DUMPREG(DISPC_IRQENABLE);
2719         DUMPREG(DISPC_CONTROL);
2720         DUMPREG(DISPC_CONFIG);
2721         DUMPREG(DISPC_CAPABLE);
2722         DUMPREG(DISPC_LINE_STATUS);
2723         DUMPREG(DISPC_LINE_NUMBER);
2724         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2725                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2726                 DUMPREG(DISPC_GLOBAL_ALPHA);
2727         if (dss_has_feature(FEAT_MGR_LCD2)) {
2728                 DUMPREG(DISPC_CONTROL2);
2729                 DUMPREG(DISPC_CONFIG2);
2730         }
2731
2732 #undef DUMPREG
2733
2734 #define DISPC_REG(i, name) name(i)
2735 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2736         48 - strlen(#r) - strlen(p_names[i]), " ", \
2737         dispc_read_reg(DISPC_REG(i, r)))
2738
2739         p_names = mgr_names;
2740
2741         /* DISPC channel specific registers */
2742         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2743                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2744                 DUMPREG(i, DISPC_TRANS_COLOR);
2745                 DUMPREG(i, DISPC_SIZE_MGR);
2746
2747                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2748                         continue;
2749
2750                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2751                 DUMPREG(i, DISPC_TRANS_COLOR);
2752                 DUMPREG(i, DISPC_TIMING_H);
2753                 DUMPREG(i, DISPC_TIMING_V);
2754                 DUMPREG(i, DISPC_POL_FREQ);
2755                 DUMPREG(i, DISPC_DIVISORo);
2756                 DUMPREG(i, DISPC_SIZE_MGR);
2757
2758                 DUMPREG(i, DISPC_DATA_CYCLE1);
2759                 DUMPREG(i, DISPC_DATA_CYCLE2);
2760                 DUMPREG(i, DISPC_DATA_CYCLE3);
2761
2762                 if (dss_has_feature(FEAT_CPR)) {
2763                         DUMPREG(i, DISPC_CPR_COEF_R);
2764                         DUMPREG(i, DISPC_CPR_COEF_G);
2765                         DUMPREG(i, DISPC_CPR_COEF_B);
2766                 }
2767         }
2768
2769         p_names = ovl_names;
2770
2771         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2772                 DUMPREG(i, DISPC_OVL_BA0);
2773                 DUMPREG(i, DISPC_OVL_BA1);
2774                 DUMPREG(i, DISPC_OVL_POSITION);
2775                 DUMPREG(i, DISPC_OVL_SIZE);
2776                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2777                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2778                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2779                 DUMPREG(i, DISPC_OVL_ROW_INC);
2780                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2781                 if (dss_has_feature(FEAT_PRELOAD))
2782                         DUMPREG(i, DISPC_OVL_PRELOAD);
2783
2784                 if (i == OMAP_DSS_GFX) {
2785                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2786                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2787                         continue;
2788                 }
2789
2790                 DUMPREG(i, DISPC_OVL_FIR);
2791                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2792                 DUMPREG(i, DISPC_OVL_ACCU0);
2793                 DUMPREG(i, DISPC_OVL_ACCU1);
2794                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2795                         DUMPREG(i, DISPC_OVL_BA0_UV);
2796                         DUMPREG(i, DISPC_OVL_BA1_UV);
2797                         DUMPREG(i, DISPC_OVL_FIR2);
2798                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2799                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2800                 }
2801                 if (dss_has_feature(FEAT_ATTR2))
2802                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2803                 if (dss_has_feature(FEAT_PRELOAD))
2804                         DUMPREG(i, DISPC_OVL_PRELOAD);
2805         }
2806
2807 #undef DISPC_REG
2808 #undef DUMPREG
2809
2810 #define DISPC_REG(plane, name, i) name(plane, i)
2811 #define DUMPREG(plane, name, i) \
2812         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2813         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2814         dispc_read_reg(DISPC_REG(plane, name, i)))
2815
2816         /* Video pipeline coefficient registers */
2817
2818         /* start from OMAP_DSS_VIDEO1 */
2819         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2820                 for (j = 0; j < 8; j++)
2821                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2822
2823                 for (j = 0; j < 8; j++)
2824                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2825
2826                 for (j = 0; j < 5; j++)
2827                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2828
2829                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2830                         for (j = 0; j < 8; j++)
2831                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2832                 }
2833
2834                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2835                         for (j = 0; j < 8; j++)
2836                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2837
2838                         for (j = 0; j < 8; j++)
2839                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2840
2841                         for (j = 0; j < 8; j++)
2842                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2843                 }
2844         }
2845
2846         dispc_runtime_put();
2847
2848 #undef DISPC_REG
2849 #undef DUMPREG
2850 }
2851
2852 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2853                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2854                 u8 acb)
2855 {
2856         u32 l = 0;
2857
2858         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2859                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2860
2861         l |= FLD_VAL(onoff, 17, 17);
2862         l |= FLD_VAL(rf, 16, 16);
2863         l |= FLD_VAL(ieo, 15, 15);
2864         l |= FLD_VAL(ipc, 14, 14);
2865         l |= FLD_VAL(ihs, 13, 13);
2866         l |= FLD_VAL(ivs, 12, 12);
2867         l |= FLD_VAL(acbi, 11, 8);
2868         l |= FLD_VAL(acb, 7, 0);
2869
2870         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2871 }
2872
2873 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2874                 enum omap_panel_config config, u8 acbi, u8 acb)
2875 {
2876         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2877                         (config & OMAP_DSS_LCD_RF) != 0,
2878                         (config & OMAP_DSS_LCD_IEO) != 0,
2879                         (config & OMAP_DSS_LCD_IPC) != 0,
2880                         (config & OMAP_DSS_LCD_IHS) != 0,
2881                         (config & OMAP_DSS_LCD_IVS) != 0,
2882                         acbi, acb);
2883 }
2884
2885 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2886 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2887                 struct dispc_clock_info *cinfo)
2888 {
2889         u16 pcd_min, pcd_max;
2890         unsigned long best_pck;
2891         u16 best_ld, cur_ld;
2892         u16 best_pd, cur_pd;
2893
2894         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2895         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2896
2897         if (!is_tft)
2898                 pcd_min = 3;
2899
2900         best_pck = 0;
2901         best_ld = 0;
2902         best_pd = 0;
2903
2904         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2905                 unsigned long lck = fck / cur_ld;
2906
2907                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2908                         unsigned long pck = lck / cur_pd;
2909                         long old_delta = abs(best_pck - req_pck);
2910                         long new_delta = abs(pck - req_pck);
2911
2912                         if (best_pck == 0 || new_delta < old_delta) {
2913                                 best_pck = pck;
2914                                 best_ld = cur_ld;
2915                                 best_pd = cur_pd;
2916
2917                                 if (pck == req_pck)
2918                                         goto found;
2919                         }
2920
2921                         if (pck < req_pck)
2922                                 break;
2923                 }
2924
2925                 if (lck / pcd_min < req_pck)
2926                         break;
2927         }
2928
2929 found:
2930         cinfo->lck_div = best_ld;
2931         cinfo->pck_div = best_pd;
2932         cinfo->lck = fck / cinfo->lck_div;
2933         cinfo->pck = cinfo->lck / cinfo->pck_div;
2934 }
2935
2936 /* calculate clock rates using dividers in cinfo */
2937 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2938                 struct dispc_clock_info *cinfo)
2939 {
2940         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2941                 return -EINVAL;
2942         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2943                 return -EINVAL;
2944
2945         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2946         cinfo->pck = cinfo->lck / cinfo->pck_div;
2947
2948         return 0;
2949 }
2950
2951 int dispc_mgr_set_clock_div(enum omap_channel channel,
2952                 struct dispc_clock_info *cinfo)
2953 {
2954         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2955         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2956
2957         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2958
2959         return 0;
2960 }
2961
2962 int dispc_mgr_get_clock_div(enum omap_channel channel,
2963                 struct dispc_clock_info *cinfo)
2964 {
2965         unsigned long fck;
2966
2967         fck = dispc_fclk_rate();
2968
2969         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2970         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2971
2972         cinfo->lck = fck / cinfo->lck_div;
2973         cinfo->pck = cinfo->lck / cinfo->pck_div;
2974
2975         return 0;
2976 }
2977
2978 /* dispc.irq_lock has to be locked by the caller */
2979 static void _omap_dispc_set_irqs(void)
2980 {
2981         u32 mask;
2982         u32 old_mask;
2983         int i;
2984         struct omap_dispc_isr_data *isr_data;
2985
2986         mask = dispc.irq_error_mask;
2987
2988         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2989                 isr_data = &dispc.registered_isr[i];
2990
2991                 if (isr_data->isr == NULL)
2992                         continue;
2993
2994                 mask |= isr_data->mask;
2995         }
2996
2997         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2998         /* clear the irqstatus for newly enabled irqs */
2999         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3000
3001         dispc_write_reg(DISPC_IRQENABLE, mask);
3002         /* flush posted write */
3003         dispc_read_reg(DISPC_IRQENABLE);
3004 }
3005
3006 static int omap_dispc_register_isr_unlocked(omap_dispc_isr_t isr,
3007                 void *arg, u32 mask)
3008 {
3009         int i;
3010         int ret;
3011         struct omap_dispc_isr_data *isr_data;
3012
3013         if (isr == NULL)
3014                 return -EINVAL;
3015
3016         /* check for duplicate entry */
3017         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3018                 isr_data = &dispc.registered_isr[i];
3019                 if (isr_data->isr == isr && isr_data->arg == arg &&
3020                                 isr_data->mask == mask) {
3021                         ret = -EINVAL;
3022                         goto err;
3023                 }
3024         }
3025
3026         isr_data = NULL;
3027         ret = -EBUSY;
3028
3029         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3030                 isr_data = &dispc.registered_isr[i];
3031
3032                 if (isr_data->isr != NULL)
3033                         continue;
3034
3035                 isr_data->isr = isr;
3036                 isr_data->arg = arg;
3037                 isr_data->mask = mask;
3038                 ret = 0;
3039
3040                 break;
3041         }
3042
3043         if (ret)
3044                 goto err;
3045
3046         _omap_dispc_set_irqs();
3047
3048 err:
3049         return ret;
3050 }
3051
3052 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3053 {
3054         unsigned long flags;
3055         int ret;
3056
3057         spin_lock_irqsave(&dispc.irq_lock, flags);
3058         ret = omap_dispc_register_isr_unlocked(isr, arg, mask);
3059         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3060
3061         return ret;
3062 }
3063 EXPORT_SYMBOL(omap_dispc_register_isr);
3064
3065 static int omap_dispc_unregister_isr_unlocked(omap_dispc_isr_t isr,
3066                 void *arg, u32 mask)
3067 {
3068         int i;
3069         int ret = -EINVAL;
3070         struct omap_dispc_isr_data *isr_data;
3071
3072         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3073                 isr_data = &dispc.registered_isr[i];
3074                 if (isr_data->isr != isr || isr_data->arg != arg ||
3075                                 isr_data->mask != mask)
3076                         continue;
3077
3078                 /* found the correct isr */
3079
3080                 isr_data->isr = NULL;
3081                 isr_data->arg = NULL;
3082                 isr_data->mask = 0;
3083
3084                 ret = 0;
3085                 break;
3086         }
3087
3088         if (ret == 0)
3089                 _omap_dispc_set_irqs();
3090
3091         return ret;
3092 }
3093
3094 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3095 {
3096         unsigned long flags;
3097         int ret;
3098
3099         spin_lock_irqsave(&dispc.irq_lock, flags);
3100         ret = omap_dispc_unregister_isr_unlocked(isr, arg, mask);
3101         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3102
3103         return ret;
3104 }
3105 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3106
3107 #ifdef DEBUG
3108 static void print_irq_status(u32 status)
3109 {
3110         if ((status & dispc.irq_error_mask) == 0)
3111                 return;
3112
3113         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3114
3115 #define PIS(x) \
3116         if (status & DISPC_IRQ_##x) \
3117                 printk(#x " ");
3118         PIS(GFX_FIFO_UNDERFLOW);
3119         PIS(OCP_ERR);
3120         PIS(VID1_FIFO_UNDERFLOW);
3121         PIS(VID2_FIFO_UNDERFLOW);
3122         if (dss_feat_get_num_ovls() > 3)
3123                 PIS(VID3_FIFO_UNDERFLOW);
3124         PIS(SYNC_LOST);
3125         PIS(SYNC_LOST_DIGIT);
3126         if (dss_has_feature(FEAT_MGR_LCD2))
3127                 PIS(SYNC_LOST2);
3128 #undef PIS
3129
3130         printk("\n");
3131 }
3132 #endif
3133
3134 /* Called from dss.c. Note that we don't touch clocks here,
3135  * but we presume they are on because we got an IRQ. However,
3136  * an irq handler may turn the clocks off, so we may not have
3137  * clock later in the function. */
3138 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3139 {
3140         int i;
3141         u32 irqstatus, irqenable;
3142         u32 handledirqs = 0;
3143         u32 unhandled_errors;
3144         struct omap_dispc_isr_data *isr_data;
3145         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3146
3147         spin_lock(&dispc.irq_lock);
3148
3149         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3150         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3151
3152         /* IRQ is not for us */
3153         if (!(irqstatus & irqenable)) {
3154                 spin_unlock(&dispc.irq_lock);
3155                 return IRQ_NONE;
3156         }
3157
3158 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3159         spin_lock(&dispc.irq_stats_lock);
3160         dispc.irq_stats.irq_count++;
3161         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3162         spin_unlock(&dispc.irq_stats_lock);
3163 #endif
3164
3165 #ifdef DEBUG
3166         if (dss_debug)
3167                 print_irq_status(irqstatus);
3168 #endif
3169         /* Ack the interrupt. Do it here before clocks are possibly turned
3170          * off */
3171         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3172         /* flush posted write */
3173         dispc_read_reg(DISPC_IRQSTATUS);
3174
3175         /* make a copy and unlock, so that isrs can unregister
3176          * themselves */
3177         memcpy(registered_isr, dispc.registered_isr,
3178                         sizeof(registered_isr));
3179
3180         spin_unlock(&dispc.irq_lock);
3181
3182         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3183                 isr_data = &registered_isr[i];
3184
3185                 if (!isr_data->isr)
3186                         continue;
3187
3188                 if (isr_data->mask & irqstatus) {
3189                         isr_data->isr(isr_data->arg, irqstatus);
3190                         handledirqs |= isr_data->mask;
3191                 }
3192         }
3193
3194         spin_lock(&dispc.irq_lock);
3195
3196         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3197
3198         if (unhandled_errors) {
3199                 dispc.error_irqs |= unhandled_errors;
3200
3201                 dispc.irq_error_mask &= ~unhandled_errors;
3202                 _omap_dispc_set_irqs();
3203
3204                 schedule_work(&dispc.error_work);
3205         }
3206
3207         spin_unlock(&dispc.irq_lock);
3208
3209         return IRQ_HANDLED;
3210 }
3211
3212 static void dispc_error_worker(struct work_struct *work)
3213 {
3214         int i;
3215         u32 errors;
3216         unsigned long flags;
3217         static const unsigned fifo_underflow_bits[] = {
3218                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3219                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3220                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3221                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3222         };
3223
3224         static const unsigned sync_lost_bits[] = {
3225                 DISPC_IRQ_SYNC_LOST,
3226                 DISPC_IRQ_SYNC_LOST_DIGIT,
3227                 DISPC_IRQ_SYNC_LOST2,
3228         };
3229
3230         spin_lock_irqsave(&dispc.irq_lock, flags);
3231         errors = dispc.error_irqs;
3232         dispc.error_irqs = 0;
3233         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3234
3235         dispc_runtime_get();
3236
3237         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3238                 struct omap_overlay *ovl;
3239                 unsigned bit;
3240
3241                 ovl = omap_dss_get_overlay(i);
3242                 bit = fifo_underflow_bits[i];
3243
3244                 if (bit & errors) {
3245                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3246                                         ovl->name);
3247                         dispc_ovl_enable(ovl->id, false);
3248                         dispc_mgr_go(ovl->manager->id);
3249                         mdelay(50);
3250                 }
3251         }
3252
3253         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3254                 struct omap_overlay_manager *mgr;
3255                 unsigned bit;
3256
3257                 mgr = omap_dss_get_overlay_manager(i);
3258                 bit = sync_lost_bits[i];
3259
3260                 if (bit & errors) {
3261                         struct omap_dss_device *dssdev = mgr->device;
3262                         bool enable;
3263
3264                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3265                                         "with video overlays disabled\n",
3266                                         mgr->name);
3267
3268                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3269                         dssdev->driver->disable(dssdev);
3270
3271                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3272                                 struct omap_overlay *ovl;
3273                                 ovl = omap_dss_get_overlay(i);
3274
3275                                 if (ovl->id != OMAP_DSS_GFX &&
3276                                                 ovl->manager == mgr)
3277                                         dispc_ovl_enable(ovl->id, false);
3278                         }
3279
3280                         dispc_mgr_go(mgr->id);
3281                         mdelay(50);
3282
3283                         if (enable)
3284                                 dssdev->driver->enable(dssdev);
3285                 }
3286         }
3287
3288         if (errors & DISPC_IRQ_OCP_ERR) {
3289                 DSSERR("OCP_ERR\n");
3290                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3291                         struct omap_overlay_manager *mgr;
3292                         mgr = omap_dss_get_overlay_manager(i);
3293                         mgr->device->driver->disable(mgr->device);
3294                 }
3295         }
3296
3297         spin_lock_irqsave(&dispc.irq_lock, flags);
3298         dispc.irq_error_mask |= errors;
3299         _omap_dispc_set_irqs();
3300         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3301
3302         dispc_runtime_put();
3303 }
3304
3305 static void dispc_irq_wait_handler(void *data, u32 mask)
3306 {
3307         complete((struct completion *)data);
3308 }
3309
3310 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3311 {
3312         int r;
3313         DECLARE_COMPLETION_ONSTACK(completion);
3314
3315         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3316                         irqmask);
3317
3318         if (r)
3319                 return r;
3320
3321         timeout = wait_for_completion_timeout(&completion, timeout);
3322
3323         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3324
3325         if (timeout == 0)
3326                 return -ETIMEDOUT;
3327
3328         if (timeout == -ERESTARTSYS)
3329                 return -ERESTARTSYS;
3330
3331         return 0;
3332 }
3333
3334 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3335                 unsigned long timeout)
3336 {
3337         int r;
3338         DECLARE_COMPLETION_ONSTACK(completion);
3339
3340         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3341                         irqmask);
3342
3343         if (r)
3344                 return r;
3345
3346         timeout = wait_for_completion_interruptible_timeout(&completion,
3347                         timeout);
3348
3349         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3350
3351         if (timeout == 0)
3352                 return -ETIMEDOUT;
3353
3354         if (timeout == -ERESTARTSYS)
3355                 return -ERESTARTSYS;
3356
3357         return 0;
3358 }
3359
3360 static void dispc_irq_vsync_on_frame_handler(void *data, u32 mask)
3361 {
3362         struct completion *completion;
3363         unsigned int i;
3364         u32 diff;
3365         int ret;
3366
3367         spin_lock(&dispc.irq_lock);
3368
3369         dispc.frame_counter++;
3370
3371         diff = dispc.frame_counter - dispc.fc_last_use;
3372         if (diff > 5 * 60 && dispc.fc_isr_registered) {
3373                 ret = omap_dispc_unregister_isr_unlocked(
3374                         dispc_irq_vsync_on_frame_handler,
3375                         data, DISPC_IRQ_VSYNC);
3376                 if (ret == 0)
3377                         dispc.fc_isr_registered = false;
3378         }
3379
3380         for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3381                 completion = xchg(&dispc.fc_complete[i], NULL);
3382                 if (completion != NULL)
3383                         complete(completion);
3384         }
3385
3386         spin_unlock(&dispc.irq_lock);
3387 }
3388
3389 int omap_dispc_wait_for_vsync_on_frame(u32 *frame,
3390         unsigned long timeout, bool force)
3391 {
3392         DECLARE_COMPLETION_ONSTACK(completion);
3393         bool need_to_wait = force;
3394         unsigned long flags;
3395         unsigned int i;
3396         long time;
3397         int ret;
3398
3399         spin_lock_irqsave(&dispc.irq_lock, flags);
3400
3401         if (!dispc.fc_isr_registered) {
3402                 ret = omap_dispc_register_isr_unlocked(
3403                         dispc_irq_vsync_on_frame_handler,
3404                         NULL, DISPC_IRQ_VSYNC);
3405                 if (ret)
3406                         goto out_unlock;
3407                 dispc.fc_isr_registered = true;
3408         }
3409         else {
3410                 need_to_wait |= *frame == dispc.frame_counter;
3411         }
3412         dispc.fc_last_use = dispc.frame_counter;
3413
3414         if (need_to_wait) {
3415                 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3416                         if (dispc.fc_complete[i] == NULL) {
3417                                 dispc.fc_complete[i] = &completion;
3418                                 break;
3419                         }
3420                 }
3421                 if (i == ARRAY_SIZE(dispc.fc_complete)) {
3422                         ret = -EBUSY;
3423                         goto out_unlock;
3424                 }
3425         }
3426
3427         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3428
3429         ret = 0;
3430         if (need_to_wait) {
3431                 time = wait_for_completion_interruptible_timeout(
3432                                 &completion, msecs_to_jiffies(17 * 2));
3433                 if (time == 0)
3434                         ret = -ETIMEDOUT;
3435                 else if (time < 0)
3436                         ret = time;
3437         }
3438         if (ret != 0) {
3439                 spin_lock(&dispc.irq_lock);
3440
3441                 for (i = 0; i < ARRAY_SIZE(dispc.fc_complete); i++) {
3442                         if (dispc.fc_complete[i] == &completion) {
3443                                 dispc.fc_complete[i] = NULL;
3444                                 break;
3445                         }
3446                 }
3447
3448                 spin_unlock(&dispc.irq_lock);
3449         }
3450
3451         *frame = dispc.frame_counter;
3452         return ret;
3453
3454 out_unlock:
3455         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3456         return ret;
3457 }
3458
3459 int omap_dispc_get_line_status(void)
3460 {
3461         int r;
3462
3463         r = dispc_runtime_get();
3464         if (r < 0)
3465                 return r;
3466
3467         r = dispc_read_reg(DISPC_LINE_STATUS);
3468
3469         dispc_runtime_put();
3470
3471         return r;
3472 }
3473
3474 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3475 void dispc_fake_vsync_irq(void)
3476 {
3477         u32 irqstatus = DISPC_IRQ_VSYNC;
3478         int i;
3479
3480         WARN_ON(!in_interrupt());
3481
3482         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3483                 struct omap_dispc_isr_data *isr_data;
3484                 isr_data = &dispc.registered_isr[i];
3485
3486                 if (!isr_data->isr)
3487                         continue;
3488
3489                 if (isr_data->mask & irqstatus)
3490                         isr_data->isr(isr_data->arg, irqstatus);
3491         }
3492 }
3493 #endif
3494
3495 static void _omap_dispc_initialize_irq(void)
3496 {
3497         unsigned long flags;
3498
3499         spin_lock_irqsave(&dispc.irq_lock, flags);
3500
3501         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3502
3503         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3504         if (dss_has_feature(FEAT_MGR_LCD2))
3505                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3506         if (dss_feat_get_num_ovls() > 3)
3507                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3508
3509         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3510          * so clear it */
3511         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3512
3513         _omap_dispc_set_irqs();
3514
3515         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3516 }
3517
3518 void dispc_enable_sidle(void)
3519 {
3520         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3521 }
3522
3523 void dispc_disable_sidle(void)
3524 {
3525         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3526 }
3527
3528 static void _omap_dispc_initial_config(void)
3529 {
3530         u32 l;
3531
3532         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3533         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3534                 l = dispc_read_reg(DISPC_DIVISOR);
3535                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3536                 l = FLD_MOD(l, 1, 0, 0);
3537                 l = FLD_MOD(l, 1, 23, 16);
3538                 dispc_write_reg(DISPC_DIVISOR, l);
3539         }
3540
3541         /* FUNCGATED */
3542         if (dss_has_feature(FEAT_FUNCGATED))
3543                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3544
3545         /* L3 firewall setting: enable access to OCM RAM */
3546         /* XXX this should be somewhere in plat-omap */
3547         if (cpu_is_omap24xx())
3548                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3549
3550         _dispc_setup_color_conv_coef();
3551
3552         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3553
3554         dispc_read_plane_fifo_sizes();
3555
3556         dispc_configure_burst_sizes();
3557
3558         dispc_ovl_enable_zorder_planes();
3559 }
3560
3561 /* DISPC HW IP initialisation */
3562 static int omap_dispchw_probe(struct platform_device *pdev)
3563 {
3564         u32 rev;
3565         int r = 0;
3566         struct resource *dispc_mem;
3567         struct clk *clk;
3568
3569         dispc.pdev = pdev;
3570
3571         clk = clk_get(&pdev->dev, "fck");
3572         if (IS_ERR(clk)) {
3573                 DSSERR("can't get fck\n");
3574                 r = PTR_ERR(clk);
3575                 goto err_get_clk;
3576         }
3577
3578         dispc.dss_clk = clk;
3579
3580         spin_lock_init(&dispc.irq_lock);
3581
3582 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3583         spin_lock_init(&dispc.irq_stats_lock);
3584         dispc.irq_stats.last_reset = jiffies;
3585 #endif
3586
3587         INIT_WORK(&dispc.error_work, dispc_error_worker);
3588
3589         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3590         if (!dispc_mem) {
3591                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3592                 r = -EINVAL;
3593                 goto err_ioremap;
3594         }
3595         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3596         if (!dispc.base) {
3597                 DSSERR("can't ioremap DISPC\n");
3598                 r = -ENOMEM;
3599                 goto err_ioremap;
3600         }
3601         dispc.irq = platform_get_irq(dispc.pdev, 0);
3602         if (dispc.irq < 0) {
3603                 DSSERR("platform_get_irq failed\n");
3604                 r = -ENODEV;
3605                 goto err_irq;
3606         }
3607
3608         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3609                 "OMAP DISPC", dispc.pdev);
3610         if (r < 0) {
3611                 DSSERR("request_irq failed\n");
3612                 goto err_irq;
3613         }
3614
3615         pdev->dev.coherent_dma_mask = ~0;
3616         dispc.table_virt = dma_alloc_writecombine(&pdev->dev,
3617                 TABLE_SIZE, &dispc.table_phys, GFP_KERNEL);
3618         if (dispc.table_virt == NULL) {
3619                 dev_err(&pdev->dev, "failed to alloc palette memory\n");
3620                 goto err_palette;
3621         }
3622         memset(dispc.table_virt, 0, TABLE_SIZE);
3623
3624         pm_runtime_enable(&pdev->dev);
3625
3626         r = dispc_runtime_get();
3627         if (r)
3628                 goto err_runtime_get;
3629
3630         _omap_dispc_initial_config();
3631
3632         _omap_dispc_initialize_irq();
3633
3634         rev = dispc_read_reg(DISPC_REVISION);
3635         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3636                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3637
3638         dispc_runtime_put();
3639
3640         return 0;
3641
3642 err_runtime_get:
3643         pm_runtime_disable(&pdev->dev);
3644         dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3645                 dispc.table_virt, dispc.table_phys);
3646 err_palette:
3647         free_irq(dispc.irq, dispc.pdev);
3648 err_irq:
3649         iounmap(dispc.base);
3650 err_ioremap:
3651         clk_put(dispc.dss_clk);
3652 err_get_clk:
3653         return r;
3654 }
3655
3656 static int omap_dispchw_remove(struct platform_device *pdev)
3657 {
3658         pm_runtime_disable(&pdev->dev);
3659
3660         dma_free_writecombine(&pdev->dev, TABLE_SIZE,
3661                 dispc.table_virt, dispc.table_phys);
3662
3663         clk_put(dispc.dss_clk);
3664
3665         free_irq(dispc.irq, dispc.pdev);
3666         iounmap(dispc.base);
3667         return 0;
3668 }
3669
3670 static int dispc_runtime_suspend(struct device *dev)
3671 {
3672         dispc_save_context();
3673         dss_runtime_put();
3674
3675         return 0;
3676 }
3677
3678 static int dispc_runtime_resume(struct device *dev)
3679 {
3680         int r;
3681
3682         r = dss_runtime_get();
3683         if (r < 0)
3684                 return r;
3685
3686         dispc_restore_context();
3687
3688         return 0;
3689 }
3690
3691 static const struct dev_pm_ops dispc_pm_ops = {
3692         .runtime_suspend = dispc_runtime_suspend,
3693         .runtime_resume = dispc_runtime_resume,
3694 };
3695
3696 static struct platform_driver omap_dispchw_driver = {
3697         .remove         = omap_dispchw_remove,
3698         .driver         = {
3699                 .name   = "omapdss_dispc",
3700                 .owner  = THIS_MODULE,
3701                 .pm     = &dispc_pm_ops,
3702         },
3703 };
3704
3705 int dispc_init_platform_driver(void)
3706 {
3707         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3708 }
3709
3710 void dispc_uninit_platform_driver(void)
3711 {
3712         return platform_driver_unregister(&omap_dispchw_driver);
3713 }