drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34
  35 #include <mach/sram.h>
  36 #include <mach/board.h>
  37 #include <mach/clock.h>
  38
  39 #include <mach/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 #define REG_GET(idx, start, end) \
 143         FLD_GET(dispc_read_reg(idx), start, end)
 144
 145 #define REG_FLD_MOD(idx, val, start, end)                               \
 146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 147
 148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 149         DISPC_VID_ATTRIBUTES(0),
 150         DISPC_VID_ATTRIBUTES(1) };
 151
 152 static struct {
 153         void __iomem    *base;
 154
 155         struct clk      *dpll4_m4_ck;
 156
 157         spinlock_t      irq_lock;
 158
 159         unsigned long   cache_req_pck;
 160         unsigned long   cache_prate;
 161         struct dispc_clock_info cache_cinfo;
 162
 163         u32             irq_error_mask;
 164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 165
 166         spinlock_t error_lock;
 167         u32 error_irqs;
 168         struct work_struct error_work;
 169
 170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 171 } dispc;
 172
 173 static void omap_dispc_set_irqs(void);
 174
 175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 176 {
 177         __raw_writel(val, dispc.base + idx.idx);
 178 }
 179
 180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 181 {
 182         return __raw_readl(dispc.base + idx.idx);
 183 }
 184
 185 #define SR(reg) \
 186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 187 #define RR(reg) \
 188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 189
 190 void dispc_save_context(void)
 191 {
 192         if (cpu_is_omap24xx())
 193                 return;
 194
 195         SR(SYSCONFIG);
 196         SR(IRQENABLE);
 197         SR(CONTROL);
 198         SR(CONFIG);
 199         SR(DEFAULT_COLOR0);
 200         SR(DEFAULT_COLOR1);
 201         SR(TRANS_COLOR0);
 202         SR(TRANS_COLOR1);
 203         SR(LINE_NUMBER);
 204         SR(TIMING_H);
 205         SR(TIMING_V);
 206         SR(POL_FREQ);
 207         SR(DIVISOR);
 208         SR(GLOBAL_ALPHA);
 209         SR(SIZE_DIG);
 210         SR(SIZE_LCD);
 211
 212         SR(GFX_BA0);
 213         SR(GFX_BA1);
 214         SR(GFX_POSITION);
 215         SR(GFX_SIZE);
 216         SR(GFX_ATTRIBUTES);
 217         SR(GFX_FIFO_THRESHOLD);
 218         SR(GFX_ROW_INC);
 219         SR(GFX_PIXEL_INC);
 220         SR(GFX_WINDOW_SKIP);
 221         SR(GFX_TABLE_BA);
 222
 223         SR(DATA_CYCLE1);
 224         SR(DATA_CYCLE2);
 225         SR(DATA_CYCLE3);
 226
 227         SR(CPR_COEF_R);
 228         SR(CPR_COEF_G);
 229         SR(CPR_COEF_B);
 230
 231         SR(GFX_PRELOAD);
 232
 233         /* VID1 */
 234         SR(VID_BA0(0));
 235         SR(VID_BA1(0));
 236         SR(VID_POSITION(0));
 237         SR(VID_SIZE(0));
 238         SR(VID_ATTRIBUTES(0));
 239         SR(VID_FIFO_THRESHOLD(0));
 240         SR(VID_ROW_INC(0));
 241         SR(VID_PIXEL_INC(0));
 242         SR(VID_FIR(0));
 243         SR(VID_PICTURE_SIZE(0));
 244         SR(VID_ACCU0(0));
 245         SR(VID_ACCU1(0));
 246
 247         SR(VID_FIR_COEF_H(0, 0));
 248         SR(VID_FIR_COEF_H(0, 1));
 249         SR(VID_FIR_COEF_H(0, 2));
 250         SR(VID_FIR_COEF_H(0, 3));
 251         SR(VID_FIR_COEF_H(0, 4));
 252         SR(VID_FIR_COEF_H(0, 5));
 253         SR(VID_FIR_COEF_H(0, 6));
 254         SR(VID_FIR_COEF_H(0, 7));
 255
 256         SR(VID_FIR_COEF_HV(0, 0));
 257         SR(VID_FIR_COEF_HV(0, 1));
 258         SR(VID_FIR_COEF_HV(0, 2));
 259         SR(VID_FIR_COEF_HV(0, 3));
 260         SR(VID_FIR_COEF_HV(0, 4));
 261         SR(VID_FIR_COEF_HV(0, 5));
 262         SR(VID_FIR_COEF_HV(0, 6));
 263         SR(VID_FIR_COEF_HV(0, 7));
 264
 265         SR(VID_CONV_COEF(0, 0));
 266         SR(VID_CONV_COEF(0, 1));
 267         SR(VID_CONV_COEF(0, 2));
 268         SR(VID_CONV_COEF(0, 3));
 269         SR(VID_CONV_COEF(0, 4));
 270
 271         SR(VID_FIR_COEF_V(0, 0));
 272         SR(VID_FIR_COEF_V(0, 1));
 273         SR(VID_FIR_COEF_V(0, 2));
 274         SR(VID_FIR_COEF_V(0, 3));
 275         SR(VID_FIR_COEF_V(0, 4));
 276         SR(VID_FIR_COEF_V(0, 5));
 277         SR(VID_FIR_COEF_V(0, 6));
 278         SR(VID_FIR_COEF_V(0, 7));
 279
 280         SR(VID_PRELOAD(0));
 281
 282         /* VID2 */
 283         SR(VID_BA0(1));
 284         SR(VID_BA1(1));
 285         SR(VID_POSITION(1));
 286         SR(VID_SIZE(1));
 287         SR(VID_ATTRIBUTES(1));
 288         SR(VID_FIFO_THRESHOLD(1));
 289         SR(VID_ROW_INC(1));
 290         SR(VID_PIXEL_INC(1));
 291         SR(VID_FIR(1));
 292         SR(VID_PICTURE_SIZE(1));
 293         SR(VID_ACCU0(1));
 294         SR(VID_ACCU1(1));
 295
 296         SR(VID_FIR_COEF_H(1, 0));
 297         SR(VID_FIR_COEF_H(1, 1));
 298         SR(VID_FIR_COEF_H(1, 2));
 299         SR(VID_FIR_COEF_H(1, 3));
 300         SR(VID_FIR_COEF_H(1, 4));
 301         SR(VID_FIR_COEF_H(1, 5));
 302         SR(VID_FIR_COEF_H(1, 6));
 303         SR(VID_FIR_COEF_H(1, 7));
 304
 305         SR(VID_FIR_COEF_HV(1, 0));
 306         SR(VID_FIR_COEF_HV(1, 1));
 307         SR(VID_FIR_COEF_HV(1, 2));
 308         SR(VID_FIR_COEF_HV(1, 3));
 309         SR(VID_FIR_COEF_HV(1, 4));
 310         SR(VID_FIR_COEF_HV(1, 5));
 311         SR(VID_FIR_COEF_HV(1, 6));
 312         SR(VID_FIR_COEF_HV(1, 7));
 313
 314         SR(VID_CONV_COEF(1, 0));
 315         SR(VID_CONV_COEF(1, 1));
 316         SR(VID_CONV_COEF(1, 2));
 317         SR(VID_CONV_COEF(1, 3));
 318         SR(VID_CONV_COEF(1, 4));
 319
 320         SR(VID_FIR_COEF_V(1, 0));
 321         SR(VID_FIR_COEF_V(1, 1));
 322         SR(VID_FIR_COEF_V(1, 2));
 323         SR(VID_FIR_COEF_V(1, 3));
 324         SR(VID_FIR_COEF_V(1, 4));
 325         SR(VID_FIR_COEF_V(1, 5));
 326         SR(VID_FIR_COEF_V(1, 6));
 327         SR(VID_FIR_COEF_V(1, 7));
 328
 329         SR(VID_PRELOAD(1));
 330 }
 331
 332 void dispc_restore_context(void)
 333 {
 334         RR(SYSCONFIG);
 335         RR(IRQENABLE);
 336         /*RR(CONTROL);*/
 337         RR(CONFIG);
 338         RR(DEFAULT_COLOR0);
 339         RR(DEFAULT_COLOR1);
 340         RR(TRANS_COLOR0);
 341         RR(TRANS_COLOR1);
 342         RR(LINE_NUMBER);
 343         RR(TIMING_H);
 344         RR(TIMING_V);
 345         RR(POL_FREQ);
 346         RR(DIVISOR);
 347         RR(GLOBAL_ALPHA);
 348         RR(SIZE_DIG);
 349         RR(SIZE_LCD);
 350
 351         RR(GFX_BA0);
 352         RR(GFX_BA1);
 353         RR(GFX_POSITION);
 354         RR(GFX_SIZE);
 355         RR(GFX_ATTRIBUTES);
 356         RR(GFX_FIFO_THRESHOLD);
 357         RR(GFX_ROW_INC);
 358         RR(GFX_PIXEL_INC);
 359         RR(GFX_WINDOW_SKIP);
 360         RR(GFX_TABLE_BA);
 361
 362         RR(DATA_CYCLE1);
 363         RR(DATA_CYCLE2);
 364         RR(DATA_CYCLE3);
 365
 366         RR(CPR_COEF_R);
 367         RR(CPR_COEF_G);
 368         RR(CPR_COEF_B);
 369
 370         RR(GFX_PRELOAD);
 371
 372         /* VID1 */
 373         RR(VID_BA0(0));
 374         RR(VID_BA1(0));
 375         RR(VID_POSITION(0));
 376         RR(VID_SIZE(0));
 377         RR(VID_ATTRIBUTES(0));
 378         RR(VID_FIFO_THRESHOLD(0));
 379         RR(VID_ROW_INC(0));
 380         RR(VID_PIXEL_INC(0));
 381         RR(VID_FIR(0));
 382         RR(VID_PICTURE_SIZE(0));
 383         RR(VID_ACCU0(0));
 384         RR(VID_ACCU1(0));
 385
 386         RR(VID_FIR_COEF_H(0, 0));
 387         RR(VID_FIR_COEF_H(0, 1));
 388         RR(VID_FIR_COEF_H(0, 2));
 389         RR(VID_FIR_COEF_H(0, 3));
 390         RR(VID_FIR_COEF_H(0, 4));
 391         RR(VID_FIR_COEF_H(0, 5));
 392         RR(VID_FIR_COEF_H(0, 6));
 393         RR(VID_FIR_COEF_H(0, 7));
 394
 395         RR(VID_FIR_COEF_HV(0, 0));
 396         RR(VID_FIR_COEF_HV(0, 1));
 397         RR(VID_FIR_COEF_HV(0, 2));
 398         RR(VID_FIR_COEF_HV(0, 3));
 399         RR(VID_FIR_COEF_HV(0, 4));
 400         RR(VID_FIR_COEF_HV(0, 5));
 401         RR(VID_FIR_COEF_HV(0, 6));
 402         RR(VID_FIR_COEF_HV(0, 7));
 403
 404         RR(VID_CONV_COEF(0, 0));
 405         RR(VID_CONV_COEF(0, 1));
 406         RR(VID_CONV_COEF(0, 2));
 407         RR(VID_CONV_COEF(0, 3));
 408         RR(VID_CONV_COEF(0, 4));
 409
 410         RR(VID_FIR_COEF_V(0, 0));
 411         RR(VID_FIR_COEF_V(0, 1));
 412         RR(VID_FIR_COEF_V(0, 2));
 413         RR(VID_FIR_COEF_V(0, 3));
 414         RR(VID_FIR_COEF_V(0, 4));
 415         RR(VID_FIR_COEF_V(0, 5));
 416         RR(VID_FIR_COEF_V(0, 6));
 417         RR(VID_FIR_COEF_V(0, 7));
 418
 419         RR(VID_PRELOAD(0));
 420
 421         /* VID2 */
 422         RR(VID_BA0(1));
 423         RR(VID_BA1(1));
 424         RR(VID_POSITION(1));
 425         RR(VID_SIZE(1));
 426         RR(VID_ATTRIBUTES(1));
 427         RR(VID_FIFO_THRESHOLD(1));
 428         RR(VID_ROW_INC(1));
 429         RR(VID_PIXEL_INC(1));
 430         RR(VID_FIR(1));
 431         RR(VID_PICTURE_SIZE(1));
 432         RR(VID_ACCU0(1));
 433         RR(VID_ACCU1(1));
 434
 435         RR(VID_FIR_COEF_H(1, 0));
 436         RR(VID_FIR_COEF_H(1, 1));
 437         RR(VID_FIR_COEF_H(1, 2));
 438         RR(VID_FIR_COEF_H(1, 3));
 439         RR(VID_FIR_COEF_H(1, 4));
 440         RR(VID_FIR_COEF_H(1, 5));
 441         RR(VID_FIR_COEF_H(1, 6));
 442         RR(VID_FIR_COEF_H(1, 7));
 443
 444         RR(VID_FIR_COEF_HV(1, 0));
 445         RR(VID_FIR_COEF_HV(1, 1));
 446         RR(VID_FIR_COEF_HV(1, 2));
 447         RR(VID_FIR_COEF_HV(1, 3));
 448         RR(VID_FIR_COEF_HV(1, 4));
 449         RR(VID_FIR_COEF_HV(1, 5));
 450         RR(VID_FIR_COEF_HV(1, 6));
 451         RR(VID_FIR_COEF_HV(1, 7));
 452
 453         RR(VID_CONV_COEF(1, 0));
 454         RR(VID_CONV_COEF(1, 1));
 455         RR(VID_CONV_COEF(1, 2));
 456         RR(VID_CONV_COEF(1, 3));
 457         RR(VID_CONV_COEF(1, 4));
 458
 459         RR(VID_FIR_COEF_V(1, 0));
 460         RR(VID_FIR_COEF_V(1, 1));
 461         RR(VID_FIR_COEF_V(1, 2));
 462         RR(VID_FIR_COEF_V(1, 3));
 463         RR(VID_FIR_COEF_V(1, 4));
 464         RR(VID_FIR_COEF_V(1, 5));
 465         RR(VID_FIR_COEF_V(1, 6));
 466         RR(VID_FIR_COEF_V(1, 7));
 467
 468         RR(VID_PRELOAD(1));
 469
 470         /* enable last, because LCD & DIGIT enable are here */
 471         RR(CONTROL);
 472 }
 473
 474 #undef SR
 475 #undef RR
 476
 477 static inline void enable_clocks(bool enable)
 478 {
 479         if (enable)
 480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 481         else
 482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 483 }
 484
 485 void dispc_go(enum omap_channel channel)
 486 {
 487         int bit;
 488         unsigned long tmo;
 489
 490         enable_clocks(1);
 491
 492         if (channel == OMAP_DSS_CHANNEL_LCD)
 493                 bit = 0; /* LCDENABLE */
 494         else
 495                 bit = 1; /* DIGITALENABLE */
 496
 497         /* if the channel is not enabled, we don't need GO */
 498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 499                 goto end;
 500
 501         if (channel == OMAP_DSS_CHANNEL_LCD)
 502                 bit = 5; /* GOLCD */
 503         else
 504                 bit = 6; /* GODIGIT */
 505
 506         tmo = jiffies + msecs_to_jiffies(200);
 507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 508                 if (time_after(jiffies, tmo)) {
 509                         DSSERR("timeout waiting GO flag\n");
 510                         goto end;
 511                 }
 512                 cpu_relax();
 513         }
 514
 515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 516
 517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 518 end:
 519         enable_clocks(0);
 520 }
 521
 522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 523 {
 524         BUG_ON(plane == OMAP_DSS_GFX);
 525
 526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 527 }
 528
 529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         BUG_ON(plane == OMAP_DSS_GFX);
 532
 533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 534 }
 535
 536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 537 {
 538         BUG_ON(plane == OMAP_DSS_GFX);
 539
 540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 541 }
 542
 543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 544                 int vscaleup, int five_taps)
 545 {
 546         /* Coefficients for horizontal up-sampling */
 547         static const u32 coef_hup[8] = {
 548                 0x00800000,
 549                 0x0D7CF800,
 550                 0x1E70F5FF,
 551                 0x335FF5FE,
 552                 0xF74949F7,
 553                 0xF55F33FB,
 554                 0xF5701EFE,
 555                 0xF87C0DFF,
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const u32 coef_hdown[8] = {
 560                 0x24382400,
 561                 0x28371FFE,
 562                 0x2C361BFB,
 563                 0x303516F9,
 564                 0x11343311,
 565                 0x1635300C,
 566                 0x1B362C08,
 567                 0x1F372804,
 568         };
 569
 570         /* Coefficients for horizontal and vertical up-sampling */
 571         static const u32 coef_hvup[2][8] = {
 572                 {
 573                 0x00800000,
 574                 0x037B02FF,
 575                 0x0C6F05FE,
 576                 0x205907FB,
 577                 0x00404000,
 578                 0x075920FE,
 579                 0x056F0CFF,
 580                 0x027B0300,
 581                 },
 582                 {
 583                 0x00800000,
 584                 0x0D7CF8FF,
 585                 0x1E70F5FE,
 586                 0x335FF5FB,
 587                 0xF7404000,
 588                 0xF55F33FE,
 589                 0xF5701EFF,
 590                 0xF87C0D00,
 591                 },
 592         };
 593
 594         /* Coefficients for horizontal and vertical down-sampling */
 595         static const u32 coef_hvdown[2][8] = {
 596                 {
 597                 0x24382400,
 598                 0x28391F04,
 599                 0x2D381B08,
 600                 0x3237170C,
 601                 0x123737F7,
 602                 0x173732F9,
 603                 0x1B382DFB,
 604                 0x1F3928FE,
 605                 },
 606                 {
 607                 0x24382400,
 608                 0x28371F04,
 609                 0x2C361B08,
 610                 0x3035160C,
 611                 0x113433F7,
 612                 0x163530F9,
 613                 0x1B362CFB,
 614                 0x1F3728FE,
 615                 },
 616         };
 617
 618         /* Coefficients for vertical up-sampling */
 619         static const u32 coef_vup[8] = {
 620                 0x00000000,
 621                 0x0000FF00,
 622                 0x0000FEFF,
 623                 0x0000FBFE,
 624                 0x000000F7,
 625                 0x0000FEFB,
 626                 0x0000FFFE,
 627                 0x000000FF,
 628         };
 629
 630
 631         /* Coefficients for vertical down-sampling */
 632         static const u32 coef_vdown[8] = {
 633                 0x00000000,
 634                 0x000004FE,
 635                 0x000008FB,
 636                 0x00000CF9,
 637                 0x0000F711,
 638                 0x0000F90C,
 639                 0x0000FB08,
 640                 0x0000FE04,
 641         };
 642
 643         const u32 *h_coef;
 644         const u32 *hv_coef;
 645         const u32 *hv_coef_mod;
 646         const u32 *v_coef;
 647         int i;
 648
 649         if (hscaleup)
 650                 h_coef = coef_hup;
 651         else
 652                 h_coef = coef_hdown;
 653
 654         if (vscaleup) {
 655                 hv_coef = coef_hvup[five_taps];
 656                 v_coef = coef_vup;
 657
 658                 if (hscaleup)
 659                         hv_coef_mod = NULL;
 660                 else
 661                         hv_coef_mod = coef_hvdown[five_taps];
 662         } else {
 663                 hv_coef = coef_hvdown[five_taps];
 664                 v_coef = coef_vdown;
 665
 666                 if (hscaleup)
 667                         hv_coef_mod = coef_hvup[five_taps];
 668                 else
 669                         hv_coef_mod = NULL;
 670         }
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = h_coef[i];
 676
 677                 hv = hv_coef[i];
 678
 679                 if (hv_coef_mod) {
 680                         hv &= 0xffffff00;
 681                         hv |= (hv_coef_mod[i] & 0xff);
 682                 }
 683
 684                 _dispc_write_firh_reg(plane, i, h);
 685                 _dispc_write_firhv_reg(plane, i, hv);
 686         }
 687
 688         if (!five_taps)
 689                 return;
 690
 691         for (i = 0; i < 8; i++) {
 692                 u32 v;
 693                 v = v_coef[i];
 694                 _dispc_write_firv_reg(plane, i, v);
 695         }
 696 }
 697
 698 static void _dispc_setup_color_conv_coef(void)
 699 {
 700         const struct color_conv_coef {
 701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 702                 int  full_range;
 703         }  ctbl_bt601_5 = {
 704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 705         };
 706
 707         const struct color_conv_coef *ct;
 708
 709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 710
 711         ct = &ctbl_bt601_5;
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 718
 719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 724
 725 #undef CVAL
 726
 727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 729 }
 730
 731
 732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 733 {
 734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 735                 DISPC_VID_BA0(0),
 736                 DISPC_VID_BA0(1) };
 737
 738         dispc_write_reg(ba0_reg[plane], paddr);
 739 }
 740
 741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 742 {
 743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 744                                       DISPC_VID_BA1(0),
 745                                       DISPC_VID_BA1(1) };
 746
 747         dispc_write_reg(ba1_reg[plane], paddr);
 748 }
 749
 750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 751 {
 752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 753                                       DISPC_VID_POSITION(0),
 754                                       DISPC_VID_POSITION(1) };
 755
 756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 757         dispc_write_reg(pos_reg[plane], val);
 758 }
 759
 760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 761 {
 762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 763                                       DISPC_VID_PICTURE_SIZE(0),
 764                                       DISPC_VID_PICTURE_SIZE(1) };
 765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 766         dispc_write_reg(siz_reg[plane], val);
 767 }
 768
 769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 770 {
 771         u32 val;
 772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 773                                       DISPC_VID_SIZE(1) };
 774
 775         BUG_ON(plane == OMAP_DSS_GFX);
 776
 777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 778         dispc_write_reg(vsi_reg[plane-1], val);
 779 }
 780
 781 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 782 {
 783
 784         BUG_ON(plane == OMAP_DSS_VIDEO1);
 785
 786         if (plane == OMAP_DSS_GFX)
 787                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 788         else if (plane == OMAP_DSS_VIDEO2)
 789                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 790 }
 791
 792 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 793 {
 794         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 795                                      DISPC_VID_PIXEL_INC(0),
 796                                      DISPC_VID_PIXEL_INC(1) };
 797
 798         dispc_write_reg(ri_reg[plane], inc);
 799 }
 800
 801 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 802 {
 803         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 804                                      DISPC_VID_ROW_INC(0),
 805                                      DISPC_VID_ROW_INC(1) };
 806
 807         dispc_write_reg(ri_reg[plane], inc);
 808 }
 809
 810 static void _dispc_set_color_mode(enum omap_plane plane,
 811                 enum omap_color_mode color_mode)
 812 {
 813         u32 m = 0;
 814
 815         switch (color_mode) {
 816         case OMAP_DSS_COLOR_CLUT1:
 817                 m = 0x0; break;
 818         case OMAP_DSS_COLOR_CLUT2:
 819                 m = 0x1; break;
 820         case OMAP_DSS_COLOR_CLUT4:
 821                 m = 0x2; break;
 822         case OMAP_DSS_COLOR_CLUT8:
 823                 m = 0x3; break;
 824         case OMAP_DSS_COLOR_RGB12U:
 825                 m = 0x4; break;
 826         case OMAP_DSS_COLOR_ARGB16:
 827                 m = 0x5; break;
 828         case OMAP_DSS_COLOR_RGB16:
 829                 m = 0x6; break;
 830         case OMAP_DSS_COLOR_RGB24U:
 831                 m = 0x8; break;
 832         case OMAP_DSS_COLOR_RGB24P:
 833                 m = 0x9; break;
 834         case OMAP_DSS_COLOR_YUV2:
 835                 m = 0xa; break;
 836         case OMAP_DSS_COLOR_UYVY:
 837                 m = 0xb; break;
 838         case OMAP_DSS_COLOR_ARGB32:
 839                 m = 0xc; break;
 840         case OMAP_DSS_COLOR_RGBA32:
 841                 m = 0xd; break;
 842         case OMAP_DSS_COLOR_RGBX32:
 843                 m = 0xe; break;
 844         default:
 845                 BUG(); break;
 846         }
 847
 848         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 849 }
 850
 851 static void _dispc_set_channel_out(enum omap_plane plane,
 852                 enum omap_channel channel)
 853 {
 854         int shift;
 855         u32 val;
 856
 857         switch (plane) {
 858         case OMAP_DSS_GFX:
 859                 shift = 8;
 860                 break;
 861         case OMAP_DSS_VIDEO1:
 862         case OMAP_DSS_VIDEO2:
 863                 shift = 16;
 864                 break;
 865         default:
 866                 BUG();
 867                 return;
 868         }
 869
 870         val = dispc_read_reg(dispc_reg_att[plane]);
 871         val = FLD_MOD(val, channel, shift, shift);
 872         dispc_write_reg(dispc_reg_att[plane], val);
 873 }
 874
 875 void dispc_set_burst_size(enum omap_plane plane,
 876                 enum omap_burst_size burst_size)
 877 {
 878         int shift;
 879         u32 val;
 880
 881         enable_clocks(1);
 882
 883         switch (plane) {
 884         case OMAP_DSS_GFX:
 885                 shift = 6;
 886                 break;
 887         case OMAP_DSS_VIDEO1:
 888         case OMAP_DSS_VIDEO2:
 889                 shift = 14;
 890                 break;
 891         default:
 892                 BUG();
 893                 return;
 894         }
 895
 896         val = dispc_read_reg(dispc_reg_att[plane]);
 897         val = FLD_MOD(val, burst_size, shift+1, shift);
 898         dispc_write_reg(dispc_reg_att[plane], val);
 899
 900         enable_clocks(0);
 901 }
 902
 903 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 904 {
 905         u32 val;
 906
 907         BUG_ON(plane == OMAP_DSS_GFX);
 908
 909         val = dispc_read_reg(dispc_reg_att[plane]);
 910         val = FLD_MOD(val, enable, 9, 9);
 911         dispc_write_reg(dispc_reg_att[plane], val);
 912 }
 913
 914 void dispc_set_lcd_size(u16 width, u16 height)
 915 {
 916         u32 val;
 917         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 918         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 919         enable_clocks(1);
 920         dispc_write_reg(DISPC_SIZE_LCD, val);
 921         enable_clocks(0);
 922 }
 923
 924 void dispc_set_digit_size(u16 width, u16 height)
 925 {
 926         u32 val;
 927         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 928         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 929         enable_clocks(1);
 930         dispc_write_reg(DISPC_SIZE_DIG, val);
 931         enable_clocks(0);
 932 }
 933
 934 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 935 {
 936         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 937                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 938                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 939         u32 size;
 940
 941         enable_clocks(1);
 942
 943         if (cpu_is_omap24xx())
 944                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 945         else if (cpu_is_omap34xx())
 946                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 947         else
 948                 BUG();
 949
 950         if (cpu_is_omap34xx()) {
 951                 /* FIFOMERGE */
 952                 if (REG_GET(DISPC_CONFIG, 14, 14))
 953                         size *= 3;
 954         }
 955
 956         enable_clocks(0);
 957
 958         return size;
 959 }
 960
 961 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 962 {
 963         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 964                                        DISPC_VID_FIFO_THRESHOLD(0),
 965                                        DISPC_VID_FIFO_THRESHOLD(1) };
 966         u32 size;
 967
 968         enable_clocks(1);
 969
 970         size = dispc_get_plane_fifo_size(plane);
 971
 972         BUG_ON(low > size || high > size);
 973
 974         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
 975                         plane, size,
 976                         REG_GET(ftrs_reg[plane], 11, 0),
 977                         REG_GET(ftrs_reg[plane], 27, 16),
 978                         low, high);
 979
 980         if (cpu_is_omap24xx())
 981                 dispc_write_reg(ftrs_reg[plane],
 982                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
 983         else
 984                 dispc_write_reg(ftrs_reg[plane],
 985                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
 986
 987         enable_clocks(0);
 988 }
 989
 990 void dispc_enable_fifomerge(bool enable)
 991 {
 992         enable_clocks(1);
 993
 994         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
 995         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
 996
 997         enable_clocks(0);
 998 }
 999
1000 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1001 {
1002         u32 val;
1003         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1004                                       DISPC_VID_FIR(1) };
1005
1006         BUG_ON(plane == OMAP_DSS_GFX);
1007
1008         if (cpu_is_omap24xx())
1009                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1010         else
1011                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1012         dispc_write_reg(fir_reg[plane-1], val);
1013 }
1014
1015 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1016 {
1017         u32 val;
1018         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1019                                       DISPC_VID_ACCU0(1) };
1020
1021         BUG_ON(plane == OMAP_DSS_GFX);
1022
1023         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1024         dispc_write_reg(ac0_reg[plane-1], val);
1025 }
1026
1027 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1028 {
1029         u32 val;
1030         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1031                                       DISPC_VID_ACCU1(1) };
1032
1033         BUG_ON(plane == OMAP_DSS_GFX);
1034
1035         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1036         dispc_write_reg(ac1_reg[plane-1], val);
1037 }
1038
1039
1040 static void _dispc_set_scaling(enum omap_plane plane,
1041                 u16 orig_width, u16 orig_height,
1042                 u16 out_width, u16 out_height,
1043                 bool ilace, bool five_taps,
1044                 bool fieldmode)
1045 {
1046         int fir_hinc;
1047         int fir_vinc;
1048         int hscaleup, vscaleup;
1049         int accu0 = 0;
1050         int accu1 = 0;
1051         u32 l;
1052
1053         BUG_ON(plane == OMAP_DSS_GFX);
1054
1055         hscaleup = orig_width <= out_width;
1056         vscaleup = orig_height <= out_height;
1057
1058         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1059
1060         if (!orig_width || orig_width == out_width)
1061                 fir_hinc = 0;
1062         else
1063                 fir_hinc = 1024 * orig_width / out_width;
1064
1065         if (!orig_height || orig_height == out_height)
1066                 fir_vinc = 0;
1067         else
1068                 fir_vinc = 1024 * orig_height / out_height;
1069
1070         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1071
1072         l = dispc_read_reg(dispc_reg_att[plane]);
1073         l &= ~((0x0f << 5) | (0x3 << 21));
1074
1075         l |= fir_hinc ? (1 << 5) : 0;
1076         l |= fir_vinc ? (1 << 6) : 0;
1077
1078         l |= hscaleup ? 0 : (1 << 7);
1079         l |= vscaleup ? 0 : (1 << 8);
1080
1081         l |= five_taps ? (1 << 21) : 0;
1082         l |= five_taps ? (1 << 22) : 0;
1083
1084         dispc_write_reg(dispc_reg_att[plane], l);
1085
1086         /*
1087          * field 0 = even field = bottom field
1088          * field 1 = odd field = top field
1089          */
1090         if (ilace && !fieldmode) {
1091                 accu1 = 0;
1092                 accu0 = fir_vinc / 2;
1093                 if (accu0 >= 1024/2) {
1094                         accu1 = 1024/2;
1095                         accu0 -= accu1;
1096                 }
1097         }
1098
1099         _dispc_set_vid_accu0(plane, 0, accu0);
1100         _dispc_set_vid_accu1(plane, 0, accu1);
1101 }
1102
1103 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1104                 bool mirroring, enum omap_color_mode color_mode)
1105 {
1106         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1107                         color_mode == OMAP_DSS_COLOR_UYVY) {
1108                 int vidrot = 0;
1109
1110                 if (mirroring) {
1111                         switch (rotation) {
1112                         case 0: vidrot = 2; break;
1113                         case 1: vidrot = 3; break;
1114                         case 2: vidrot = 0; break;
1115                         case 3: vidrot = 1; break;
1116                         }
1117                 } else {
1118                         switch (rotation) {
1119                         case 0: vidrot = 0; break;
1120                         case 1: vidrot = 1; break;
1121                         case 2: vidrot = 2; break;
1122                         case 3: vidrot = 3; break;
1123                         }
1124                 }
1125
1126                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1127
1128                 if (rotation == 1 || rotation == 3)
1129                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1130                 else
1131                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1132         } else {
1133                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1134                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1135         }
1136 }
1137
1138 static s32 pixinc(int pixels, u8 ps)
1139 {
1140         if (pixels == 1)
1141                 return 1;
1142         else if (pixels > 1)
1143                 return 1 + (pixels - 1) * ps;
1144         else if (pixels < 0)
1145                 return 1 - (-pixels + 1) * ps;
1146         else
1147                 BUG();
1148 }
1149
1150 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1151                 u16 screen_width,
1152                 u16 width, u16 height,
1153                 enum omap_color_mode color_mode, bool fieldmode,
1154                 unsigned *offset0, unsigned *offset1,
1155                 s32 *row_inc, s32 *pix_inc)
1156 {
1157         u8 ps;
1158
1159         switch (color_mode) {
1160         case OMAP_DSS_COLOR_RGB16:
1161         case OMAP_DSS_COLOR_ARGB16:
1162                 ps = 2;
1163                 break;
1164
1165         case OMAP_DSS_COLOR_RGB24P:
1166                 ps = 3;
1167                 break;
1168
1169         case OMAP_DSS_COLOR_RGB24U:
1170         case OMAP_DSS_COLOR_ARGB32:
1171         case OMAP_DSS_COLOR_RGBA32:
1172         case OMAP_DSS_COLOR_RGBX32:
1173         case OMAP_DSS_COLOR_YUV2:
1174         case OMAP_DSS_COLOR_UYVY:
1175                 ps = 4;
1176                 break;
1177
1178         default:
1179                 BUG();
1180                 return;
1181         }
1182
1183         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1184                         width, height);
1185         switch (rotation + mirror * 4) {
1186         case 0:
1187         case 2:
1188                 /*
1189                  * If the pixel format is YUV or UYVY divide the width
1190                  * of the image by 2 for 0 and 180 degree rotation.
1191                  */
1192                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1193                         color_mode == OMAP_DSS_COLOR_UYVY)
1194                         width = width >> 1;
1195         case 1:
1196         case 3:
1197                 *offset0 = 0;
1198                 if (fieldmode)
1199                         *offset1 = screen_width * ps;
1200                 else
1201                         *offset1 = 0;
1202
1203                 *row_inc = pixinc(1 + (screen_width - width) +
1204                                 (fieldmode ? screen_width : 0),
1205                                 ps);
1206                 *pix_inc = pixinc(1, ps);
1207                 break;
1208
1209         case 4:
1210         case 6:
1211                 /* If the pixel format is YUV or UYVY divide the width
1212                  * of the image by 2  for 0 degree and 180 degree
1213                  */
1214                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1215                         color_mode == OMAP_DSS_COLOR_UYVY)
1216                         width = width >> 1;
1217         case 5:
1218         case 7:
1219                 *offset0 = 0;
1220                 if (fieldmode)
1221                         *offset1 = screen_width * ps;
1222                 else
1223                         *offset1 = 0;
1224                 *row_inc = pixinc(1 - (screen_width + width) -
1225                                 (fieldmode ? screen_width : 0),
1226                                 ps);
1227                 *pix_inc = pixinc(1, ps);
1228                 break;
1229
1230         default:
1231                 BUG();
1232         }
1233 }
1234
1235 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1236                 u16 screen_width,
1237                 u16 width, u16 height,
1238                 enum omap_color_mode color_mode, bool fieldmode,
1239                 unsigned *offset0, unsigned *offset1,
1240                 s32 *row_inc, s32 *pix_inc)
1241 {
1242         u8 ps;
1243         u16 fbw, fbh;
1244
1245         switch (color_mode) {
1246         case OMAP_DSS_COLOR_RGB16:
1247         case OMAP_DSS_COLOR_ARGB16:
1248                 ps = 2;
1249                 break;
1250
1251         case OMAP_DSS_COLOR_RGB24P:
1252                 ps = 3;
1253                 break;
1254
1255         case OMAP_DSS_COLOR_RGB24U:
1256         case OMAP_DSS_COLOR_ARGB32:
1257         case OMAP_DSS_COLOR_RGBA32:
1258         case OMAP_DSS_COLOR_RGBX32:
1259                 ps = 4;
1260                 break;
1261
1262         case OMAP_DSS_COLOR_YUV2:
1263         case OMAP_DSS_COLOR_UYVY:
1264                 ps = 2;
1265                 break;
1266         default:
1267                 BUG();
1268                 return;
1269         }
1270
1271         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1272                         width, height);
1273
1274         /* width & height are overlay sizes, convert to fb sizes */
1275
1276         if (rotation == 0 || rotation == 2) {
1277                 fbw = width;
1278                 fbh = height;
1279         } else {
1280                 fbw = height;
1281                 fbh = width;
1282         }
1283
1284         /*
1285          * field 0 = even field = bottom field
1286          * field 1 = odd field = top field
1287          */
1288         switch (rotation + mirror * 4) {
1289         case 0:
1290                 *offset1 = 0;
1291                 if (fieldmode)
1292                         *offset0 = screen_width * ps;
1293                 else
1294                         *offset0 = 0;
1295                 *row_inc = pixinc(1 + (screen_width - fbw) +
1296                                 (fieldmode ? screen_width : 0),
1297                                 ps);
1298                 *pix_inc = pixinc(1, ps);
1299                 break;
1300         case 1:
1301                 *offset1 = screen_width * (fbh - 1) * ps;
1302                 if (fieldmode)
1303                         *offset0 = *offset1 + ps;
1304                 else
1305                         *offset0 = *offset1;
1306                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1307                                 (fieldmode ? 1 : 0), ps);
1308                 *pix_inc = pixinc(-screen_width, ps);
1309                 break;
1310         case 2:
1311                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1312                 if (fieldmode)
1313                         *offset0 = *offset1 - screen_width * ps;
1314                 else
1315                         *offset0 = *offset1;
1316                 *row_inc = pixinc(-1 -
1317                                 (screen_width - fbw) -
1318                                 (fieldmode ? screen_width : 0),
1319                                 ps);
1320                 *pix_inc = pixinc(-1, ps);
1321                 break;
1322         case 3:
1323                 *offset1 = (fbw - 1) * ps;
1324                 if (fieldmode)
1325                         *offset0 = *offset1 - ps;
1326                 else
1327                         *offset0 = *offset1;
1328                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1329                                 (fieldmode ? 1 : 0), ps);
1330                 *pix_inc = pixinc(screen_width, ps);
1331                 break;
1332
1333         /* mirroring */
1334         case 0 + 4:
1335                 *offset1 = (fbw - 1) * ps;
1336                 if (fieldmode)
1337                         *offset0 = *offset1 + screen_width * ps;
1338                 else
1339                         *offset0 = *offset1;
1340                 *row_inc = pixinc(screen_width * 2 - 1 +
1341                                 (fieldmode ? screen_width : 0),
1342                                 ps);
1343                 *pix_inc = pixinc(-1, ps);
1344                 break;
1345
1346         case 1 + 4:
1347                 *offset1 = 0;
1348                 if (fieldmode)
1349                         *offset0 = *offset1 + screen_width * ps;
1350                 else
1351                         *offset0 = *offset1;
1352                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1353                                 (fieldmode ? 1 : 0),
1354                                 ps);
1355                 *pix_inc = pixinc(screen_width, ps);
1356                 break;
1357
1358         case 2 + 4:
1359                 *offset1 = screen_width * (fbh - 1) * ps;
1360                 if (fieldmode)
1361                         *offset0 = *offset1 + screen_width * ps;
1362                 else
1363                         *offset0 = *offset1;
1364                 *row_inc = pixinc(1 - screen_width * 2 -
1365                                 (fieldmode ? screen_width : 0),
1366                                 ps);
1367                 *pix_inc = pixinc(1, ps);
1368                 break;
1369
1370         case 3 + 4:
1371                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1372                 if (fieldmode)
1373                         *offset0 = *offset1 + screen_width * ps;
1374                 else
1375                         *offset0 = *offset1;
1376                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1377                                 (fieldmode ? 1 : 0),
1378                                 ps);
1379                 *pix_inc = pixinc(-screen_width, ps);
1380                 break;
1381
1382         default:
1383                 BUG();
1384         }
1385 }
1386
1387 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1388                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1389 {
1390         u32 fclk = 0;
1391         /* FIXME venc pclk? */
1392         u64 tmp, pclk = dispc_pclk_rate();
1393
1394         if (height > out_height) {
1395                 /* FIXME get real display PPL */
1396                 unsigned int ppl = 800;
1397
1398                 tmp = pclk * height * out_width;
1399                 do_div(tmp, 2 * out_height * ppl);
1400                 fclk = tmp;
1401
1402                 if (height > 2 * out_height) {
1403                         tmp = pclk * (height - 2 * out_height) * out_width;
1404                         do_div(tmp, 2 * out_height * (ppl - out_width));
1405                         fclk = max(fclk, (u32) tmp);
1406                 }
1407         }
1408
1409         if (width > out_width) {
1410                 tmp = pclk * width;
1411                 do_div(tmp, out_width);
1412                 fclk = max(fclk, (u32) tmp);
1413
1414                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1415                         fclk <<= 1;
1416         }
1417
1418         return fclk;
1419 }
1420
1421 static unsigned long calc_fclk(u16 width, u16 height,
1422                 u16 out_width, u16 out_height)
1423 {
1424         unsigned int hf, vf;
1425
1426         /*
1427          * FIXME how to determine the 'A' factor
1428          * for the no downscaling case ?
1429          */
1430
1431         if (width > 3 * out_width)
1432                 hf = 4;
1433         else if (width > 2 * out_width)
1434                 hf = 3;
1435         else if (width > out_width)
1436                 hf = 2;
1437         else
1438                 hf = 1;
1439
1440         if (height > out_height)
1441                 vf = 2;
1442         else
1443                 vf = 1;
1444
1445         /* FIXME venc pclk? */
1446         return dispc_pclk_rate() * vf * hf;
1447 }
1448
1449 static int _dispc_setup_plane(enum omap_plane plane,
1450                 enum omap_channel channel_out,
1451                 u32 paddr, u16 screen_width,
1452                 u16 pos_x, u16 pos_y,
1453                 u16 width, u16 height,
1454                 u16 out_width, u16 out_height,
1455                 enum omap_color_mode color_mode,
1456                 bool ilace,
1457                 enum omap_dss_rotation_type rotation_type,
1458                 u8 rotation, int mirror,
1459                 u8 global_alpha)
1460 {
1461         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1462         bool five_taps = 0;
1463         bool fieldmode = 0;
1464         int cconv = 0;
1465         unsigned offset0, offset1;
1466         s32 row_inc;
1467         s32 pix_inc;
1468         u16 frame_height = height;
1469
1470         if (paddr == 0)
1471                 return -EINVAL;
1472
1473         if (ilace && height == out_height)
1474                 fieldmode = 1;
1475
1476         if (ilace) {
1477                 if (fieldmode)
1478                         height /= 2;
1479                 pos_y /= 2;
1480                 out_height /= 2;
1481
1482                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1483                                 "out_height %d\n",
1484                                 height, pos_y, out_height);
1485         }
1486
1487         if (plane == OMAP_DSS_GFX) {
1488                 if (width != out_width || height != out_height)
1489                         return -EINVAL;
1490
1491                 switch (color_mode) {
1492                 case OMAP_DSS_COLOR_ARGB16:
1493                 case OMAP_DSS_COLOR_RGB16:
1494                 case OMAP_DSS_COLOR_RGB24P:
1495                 case OMAP_DSS_COLOR_RGB24U:
1496                 case OMAP_DSS_COLOR_ARGB32:
1497                 case OMAP_DSS_COLOR_RGBA32:
1498                 case OMAP_DSS_COLOR_RGBX32:
1499                         break;
1500
1501                 default:
1502                         return -EINVAL;
1503                 }
1504         } else {
1505                 /* video plane */
1506
1507                 unsigned long fclk = 0;
1508
1509                 if (out_width < width / maxdownscale ||
1510                    out_width > width * 8)
1511                         return -EINVAL;
1512
1513                 if (out_height < height / maxdownscale ||
1514                    out_height > height * 8)
1515                         return -EINVAL;
1516
1517                 switch (color_mode) {
1518                 case OMAP_DSS_COLOR_RGB16:
1519                 case OMAP_DSS_COLOR_RGB24P:
1520                 case OMAP_DSS_COLOR_RGB24U:
1521                 case OMAP_DSS_COLOR_RGBX32:
1522                         break;
1523
1524                 case OMAP_DSS_COLOR_ARGB16:
1525                 case OMAP_DSS_COLOR_ARGB32:
1526                 case OMAP_DSS_COLOR_RGBA32:
1527                         if (plane == OMAP_DSS_VIDEO1)
1528                                 return -EINVAL;
1529                         break;
1530
1531                 case OMAP_DSS_COLOR_YUV2:
1532                 case OMAP_DSS_COLOR_UYVY:
1533                         cconv = 1;
1534                         break;
1535
1536                 default:
1537                         return -EINVAL;
1538                 }
1539
1540                 /* Must use 5-tap filter? */
1541                 five_taps = height > out_height * 2;
1542
1543                 if (!five_taps) {
1544                         fclk = calc_fclk(width, height,
1545                                         out_width, out_height);
1546
1547                         /* Try 5-tap filter if 3-tap fclk is too high */
1548                         if (cpu_is_omap34xx() && height > out_height &&
1549                                         fclk > dispc_fclk_rate())
1550                                 five_taps = true;
1551                 }
1552
1553                 if (width > (2048 >> five_taps))
1554                         return -EINVAL;
1555
1556                 if (five_taps)
1557                         fclk = calc_fclk_five_taps(width, height,
1558                                         out_width, out_height, color_mode);
1559
1560                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1561                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1562
1563                 if (fclk > dispc_fclk_rate())
1564                         return -EINVAL;
1565         }
1566
1567         if (rotation_type == OMAP_DSS_ROT_DMA)
1568                 calc_dma_rotation_offset(rotation, mirror,
1569                                 screen_width, width, frame_height, color_mode,
1570                                 fieldmode,
1571                                 &offset0, &offset1, &row_inc, &pix_inc);
1572         else
1573                 calc_vrfb_rotation_offset(rotation, mirror,
1574                                 screen_width, width, frame_height, color_mode,
1575                                 fieldmode,
1576                                 &offset0, &offset1, &row_inc, &pix_inc);
1577
1578         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1579                         offset0, offset1, row_inc, pix_inc);
1580
1581         _dispc_set_channel_out(plane, channel_out);
1582         _dispc_set_color_mode(plane, color_mode);
1583
1584         _dispc_set_plane_ba0(plane, paddr + offset0);
1585         _dispc_set_plane_ba1(plane, paddr + offset1);
1586
1587         _dispc_set_row_inc(plane, row_inc);
1588         _dispc_set_pix_inc(plane, pix_inc);
1589
1590         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1591                         out_width, out_height);
1592
1593         _dispc_set_plane_pos(plane, pos_x, pos_y);
1594
1595         _dispc_set_pic_size(plane, width, height);
1596
1597         if (plane != OMAP_DSS_GFX) {
1598                 _dispc_set_scaling(plane, width, height,
1599                                    out_width, out_height,
1600                                    ilace, five_taps, fieldmode);
1601                 _dispc_set_vid_size(plane, out_width, out_height);
1602                 _dispc_set_vid_color_conv(plane, cconv);
1603         }
1604
1605         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1606
1607         if (plane != OMAP_DSS_VIDEO1)
1608                 _dispc_setup_global_alpha(plane, global_alpha);
1609
1610         return 0;
1611 }
1612
1613 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1614 {
1615         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1616 }
1617
1618 static void dispc_disable_isr(void *data, u32 mask)
1619 {
1620         struct completion *compl = data;
1621         complete(compl);
1622 }
1623
1624 static void _enable_lcd_out(bool enable)
1625 {
1626         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1627 }
1628
1629 void dispc_enable_lcd_out(bool enable)
1630 {
1631         struct completion frame_done_completion;
1632         bool is_on;
1633         int r;
1634
1635         enable_clocks(1);
1636
1637         /* When we disable LCD output, we need to wait until frame is done.
1638          * Otherwise the DSS is still working, and turning off the clocks
1639          * prevents DSS from going to OFF mode */
1640         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1641
1642         if (!enable && is_on) {
1643                 init_completion(&frame_done_completion);
1644
1645                 r = omap_dispc_register_isr(dispc_disable_isr,
1646                                 &frame_done_completion,
1647                                 DISPC_IRQ_FRAMEDONE);
1648
1649                 if (r)
1650                         DSSERR("failed to register FRAMEDONE isr\n");
1651         }
1652
1653         _enable_lcd_out(enable);
1654
1655         if (!enable && is_on) {
1656                 if (!wait_for_completion_timeout(&frame_done_completion,
1657                                         msecs_to_jiffies(100)))
1658                         DSSERR("timeout waiting for FRAME DONE\n");
1659
1660                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1661                                 &frame_done_completion,
1662                                 DISPC_IRQ_FRAMEDONE);
1663
1664                 if (r)
1665                         DSSERR("failed to unregister FRAMEDONE isr\n");
1666         }
1667
1668         enable_clocks(0);
1669 }
1670
1671 static void _enable_digit_out(bool enable)
1672 {
1673         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1674 }
1675
1676 void dispc_enable_digit_out(bool enable)
1677 {
1678         struct completion frame_done_completion;
1679         int r;
1680
1681         enable_clocks(1);
1682
1683         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1684                 enable_clocks(0);
1685                 return;
1686         }
1687
1688         if (enable) {
1689                 /* When we enable digit output, we'll get an extra digit
1690                  * sync lost interrupt, that we need to ignore */
1691                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1692                 omap_dispc_set_irqs();
1693         }
1694
1695         /* When we disable digit output, we need to wait until fields are done.
1696          * Otherwise the DSS is still working, and turning off the clocks
1697          * prevents DSS from going to OFF mode. And when enabling, we need to
1698          * wait for the extra sync losts */
1699         init_completion(&frame_done_completion);
1700
1701         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1702                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1703         if (r)
1704                 DSSERR("failed to register EVSYNC isr\n");
1705
1706         _enable_digit_out(enable);
1707
1708         /* XXX I understand from TRM that we should only wait for the
1709          * current field to complete. But it seems we have to wait
1710          * for both fields */
1711         if (!wait_for_completion_timeout(&frame_done_completion,
1712                                 msecs_to_jiffies(100)))
1713                 DSSERR("timeout waiting for EVSYNC\n");
1714
1715         if (!wait_for_completion_timeout(&frame_done_completion,
1716                                 msecs_to_jiffies(100)))
1717                 DSSERR("timeout waiting for EVSYNC\n");
1718
1719         r = omap_dispc_unregister_isr(dispc_disable_isr,
1720                         &frame_done_completion,
1721                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1722         if (r)
1723                 DSSERR("failed to unregister EVSYNC isr\n");
1724
1725         if (enable) {
1726                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1727                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1728                 omap_dispc_set_irqs();
1729         }
1730
1731         enable_clocks(0);
1732 }
1733
1734 void dispc_lcd_enable_signal_polarity(bool act_high)
1735 {
1736         enable_clocks(1);
1737         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1738         enable_clocks(0);
1739 }
1740
1741 void dispc_lcd_enable_signal(bool enable)
1742 {
1743         enable_clocks(1);
1744         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1745         enable_clocks(0);
1746 }
1747
1748 void dispc_pck_free_enable(bool enable)
1749 {
1750         enable_clocks(1);
1751         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1752         enable_clocks(0);
1753 }
1754
1755 void dispc_enable_fifohandcheck(bool enable)
1756 {
1757         enable_clocks(1);
1758         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1759         enable_clocks(0);
1760 }
1761
1762
1763 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1764 {
1765         int mode;
1766
1767         switch (type) {
1768         case OMAP_DSS_LCD_DISPLAY_STN:
1769                 mode = 0;
1770                 break;
1771
1772         case OMAP_DSS_LCD_DISPLAY_TFT:
1773                 mode = 1;
1774                 break;
1775
1776         default:
1777                 BUG();
1778                 return;
1779         }
1780
1781         enable_clocks(1);
1782         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1783         enable_clocks(0);
1784 }
1785
1786 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1787 {
1788         enable_clocks(1);
1789         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1790         enable_clocks(0);
1791 }
1792
1793
1794 void dispc_set_default_color(enum omap_channel channel, u32 color)
1795 {
1796         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1797                                 DISPC_DEFAULT_COLOR1 };
1798
1799         enable_clocks(1);
1800         dispc_write_reg(def_reg[channel], color);
1801         enable_clocks(0);
1802 }
1803
1804 u32 dispc_get_default_color(enum omap_channel channel)
1805 {
1806         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1807                                 DISPC_DEFAULT_COLOR1 };
1808         u32 l;
1809
1810         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1811                channel != OMAP_DSS_CHANNEL_LCD);
1812
1813         enable_clocks(1);
1814         l = dispc_read_reg(def_reg[channel]);
1815         enable_clocks(0);
1816
1817         return l;
1818 }
1819
1820 void dispc_set_trans_key(enum omap_channel ch,
1821                 enum omap_dss_color_key_type type,
1822                 u32 trans_key)
1823 {
1824         const struct dispc_reg tr_reg[] = {
1825                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1826
1827         enable_clocks(1);
1828         if (ch == OMAP_DSS_CHANNEL_LCD)
1829                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1830         else /* OMAP_DSS_CHANNEL_DIGIT */
1831                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1832
1833         dispc_write_reg(tr_reg[ch], trans_key);
1834         enable_clocks(0);
1835 }
1836
1837 void dispc_get_trans_key(enum omap_channel ch,
1838                 enum omap_dss_color_key_type *type,
1839                 u32 *trans_key)
1840 {
1841         const struct dispc_reg tr_reg[] = {
1842                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1843
1844         enable_clocks(1);
1845         if (type) {
1846                 if (ch == OMAP_DSS_CHANNEL_LCD)
1847                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1848                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1849                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1850                 else
1851                         BUG();
1852         }
1853
1854         if (trans_key)
1855                 *trans_key = dispc_read_reg(tr_reg[ch]);
1856         enable_clocks(0);
1857 }
1858
1859 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1860 {
1861         enable_clocks(1);
1862         if (ch == OMAP_DSS_CHANNEL_LCD)
1863                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1864         else /* OMAP_DSS_CHANNEL_DIGIT */
1865                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1866         enable_clocks(0);
1867 }
1868 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1869 {
1870         enable_clocks(1);
1871         if (ch == OMAP_DSS_CHANNEL_LCD)
1872                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1873         else /* OMAP_DSS_CHANNEL_DIGIT */
1874                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1875         enable_clocks(0);
1876 }
1877 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1878 {
1879         bool enabled;
1880
1881         enable_clocks(1);
1882         if (ch == OMAP_DSS_CHANNEL_LCD)
1883                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1884         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1885                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1886         else
1887                 BUG();
1888         enable_clocks(0);
1889
1890         return enabled;
1891
1892 }
1893
1894
1895 bool dispc_trans_key_enabled(enum omap_channel ch)
1896 {
1897         bool enabled;
1898
1899         enable_clocks(1);
1900         if (ch == OMAP_DSS_CHANNEL_LCD)
1901                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1902         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1903                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1904         else BUG();
1905         enable_clocks(0);
1906
1907         return enabled;
1908 }
1909
1910
1911 void dispc_set_tft_data_lines(u8 data_lines)
1912 {
1913         int code;
1914
1915         switch (data_lines) {
1916         case 12:
1917                 code = 0;
1918                 break;
1919         case 16:
1920                 code = 1;
1921                 break;
1922         case 18:
1923                 code = 2;
1924                 break;
1925         case 24:
1926                 code = 3;
1927                 break;
1928         default:
1929                 BUG();
1930                 return;
1931         }
1932
1933         enable_clocks(1);
1934         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1935         enable_clocks(0);
1936 }
1937
1938 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1939 {
1940         u32 l;
1941         int stallmode;
1942         int gpout0 = 1;
1943         int gpout1;
1944
1945         switch (mode) {
1946         case OMAP_DSS_PARALLELMODE_BYPASS:
1947                 stallmode = 0;
1948                 gpout1 = 1;
1949                 break;
1950
1951         case OMAP_DSS_PARALLELMODE_RFBI:
1952                 stallmode = 1;
1953                 gpout1 = 0;
1954                 break;
1955
1956         case OMAP_DSS_PARALLELMODE_DSI:
1957                 stallmode = 1;
1958                 gpout1 = 1;
1959                 break;
1960
1961         default:
1962                 BUG();
1963                 return;
1964         }
1965
1966         enable_clocks(1);
1967
1968         l = dispc_read_reg(DISPC_CONTROL);
1969
1970         l = FLD_MOD(l, stallmode, 11, 11);
1971         l = FLD_MOD(l, gpout0, 15, 15);
1972         l = FLD_MOD(l, gpout1, 16, 16);
1973
1974         dispc_write_reg(DISPC_CONTROL, l);
1975
1976         enable_clocks(0);
1977 }
1978
1979 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1980                                    int vsw, int vfp, int vbp)
1981 {
1982         u32 timing_h, timing_v;
1983
1984         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1985                 BUG_ON(hsw < 1 || hsw > 64);
1986                 BUG_ON(hfp < 1 || hfp > 256);
1987                 BUG_ON(hbp < 1 || hbp > 256);
1988
1989                 BUG_ON(vsw < 1 || vsw > 64);
1990                 BUG_ON(vfp < 0 || vfp > 255);
1991                 BUG_ON(vbp < 0 || vbp > 255);
1992
1993                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1994                         FLD_VAL(hbp-1, 27, 20);
1995
1996                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1997                         FLD_VAL(vbp, 27, 20);
1998         } else {
1999                 BUG_ON(hsw < 1 || hsw > 256);
2000                 BUG_ON(hfp < 1 || hfp > 4096);
2001                 BUG_ON(hbp < 1 || hbp > 4096);
2002
2003                 BUG_ON(vsw < 1 || vsw > 256);
2004                 BUG_ON(vfp < 0 || vfp > 4095);
2005                 BUG_ON(vbp < 0 || vbp > 4095);
2006
2007                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2008                         FLD_VAL(hbp-1, 31, 20);
2009
2010                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2011                         FLD_VAL(vbp, 31, 20);
2012         }
2013
2014         enable_clocks(1);
2015         dispc_write_reg(DISPC_TIMING_H, timing_h);
2016         dispc_write_reg(DISPC_TIMING_V, timing_v);
2017         enable_clocks(0);
2018 }
2019
2020 /* change name to mode? */
2021 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2022 {
2023         unsigned xtot, ytot;
2024         unsigned long ht, vt;
2025
2026         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2027                         timings->vsw, timings->vfp, timings->vbp);
2028
2029         dispc_set_lcd_size(timings->x_res, timings->y_res);
2030
2031         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2032         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2033
2034         ht = (timings->pixel_clock * 1000) / xtot;
2035         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2036
2037         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2038         DSSDBG("pck %u\n", timings->pixel_clock);
2039         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2040                         timings->hsw, timings->hfp, timings->hbp,
2041                         timings->vsw, timings->vfp, timings->vbp);
2042
2043         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2044 }
2045
2046 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2047 {
2048         BUG_ON(lck_div < 1);
2049         BUG_ON(pck_div < 2);
2050
2051         enable_clocks(1);
2052         dispc_write_reg(DISPC_DIVISOR,
2053                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2054         enable_clocks(0);
2055 }
2056
2057 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2058 {
2059         u32 l;
2060         l = dispc_read_reg(DISPC_DIVISOR);
2061         *lck_div = FLD_GET(l, 23, 16);
2062         *pck_div = FLD_GET(l, 7, 0);
2063 }
2064
2065 unsigned long dispc_fclk_rate(void)
2066 {
2067         unsigned long r = 0;
2068
2069         if (dss_get_dispc_clk_source() == 0)
2070                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2071         else
2072 #ifdef CONFIG_OMAP2_DSS_DSI
2073                 r = dsi_get_dsi1_pll_rate();
2074 #else
2075         BUG();
2076 #endif
2077         return r;
2078 }
2079
2080 unsigned long dispc_lclk_rate(void)
2081 {
2082         int lcd;
2083         unsigned long r;
2084         u32 l;
2085
2086         l = dispc_read_reg(DISPC_DIVISOR);
2087
2088         lcd = FLD_GET(l, 23, 16);
2089
2090         r = dispc_fclk_rate();
2091
2092         return r / lcd;
2093 }
2094
2095 unsigned long dispc_pclk_rate(void)
2096 {
2097         int lcd, pcd;
2098         unsigned long r;
2099         u32 l;
2100
2101         l = dispc_read_reg(DISPC_DIVISOR);
2102
2103         lcd = FLD_GET(l, 23, 16);
2104         pcd = FLD_GET(l, 7, 0);
2105
2106         r = dispc_fclk_rate();
2107
2108         return r / lcd / pcd;
2109 }
2110
2111 void dispc_dump_clocks(struct seq_file *s)
2112 {
2113         int lcd, pcd;
2114
2115         enable_clocks(1);
2116
2117         dispc_get_lcd_divisor(&lcd, &pcd);
2118
2119         seq_printf(s, "- dispc -\n");
2120
2121         seq_printf(s, "dispc fclk source = %s\n",
2122                         dss_get_dispc_clk_source() == 0 ?
2123                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2124
2125         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
2126                         dispc_fclk_rate(),
2127                         lcd, pcd,
2128                         dispc_pclk_rate());
2129
2130         enable_clocks(0);
2131 }
2132
2133 void dispc_dump_regs(struct seq_file *s)
2134 {
2135 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2136
2137         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2138
2139         DUMPREG(DISPC_REVISION);
2140         DUMPREG(DISPC_SYSCONFIG);
2141         DUMPREG(DISPC_SYSSTATUS);
2142         DUMPREG(DISPC_IRQSTATUS);
2143         DUMPREG(DISPC_IRQENABLE);
2144         DUMPREG(DISPC_CONTROL);
2145         DUMPREG(DISPC_CONFIG);
2146         DUMPREG(DISPC_CAPABLE);
2147         DUMPREG(DISPC_DEFAULT_COLOR0);
2148         DUMPREG(DISPC_DEFAULT_COLOR1);
2149         DUMPREG(DISPC_TRANS_COLOR0);
2150         DUMPREG(DISPC_TRANS_COLOR1);
2151         DUMPREG(DISPC_LINE_STATUS);
2152         DUMPREG(DISPC_LINE_NUMBER);
2153         DUMPREG(DISPC_TIMING_H);
2154         DUMPREG(DISPC_TIMING_V);
2155         DUMPREG(DISPC_POL_FREQ);
2156         DUMPREG(DISPC_DIVISOR);
2157         DUMPREG(DISPC_GLOBAL_ALPHA);
2158         DUMPREG(DISPC_SIZE_DIG);
2159         DUMPREG(DISPC_SIZE_LCD);
2160
2161         DUMPREG(DISPC_GFX_BA0);
2162         DUMPREG(DISPC_GFX_BA1);
2163         DUMPREG(DISPC_GFX_POSITION);
2164         DUMPREG(DISPC_GFX_SIZE);
2165         DUMPREG(DISPC_GFX_ATTRIBUTES);
2166         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2167         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2168         DUMPREG(DISPC_GFX_ROW_INC);
2169         DUMPREG(DISPC_GFX_PIXEL_INC);
2170         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2171         DUMPREG(DISPC_GFX_TABLE_BA);
2172
2173         DUMPREG(DISPC_DATA_CYCLE1);
2174         DUMPREG(DISPC_DATA_CYCLE2);
2175         DUMPREG(DISPC_DATA_CYCLE3);
2176
2177         DUMPREG(DISPC_CPR_COEF_R);
2178         DUMPREG(DISPC_CPR_COEF_G);
2179         DUMPREG(DISPC_CPR_COEF_B);
2180
2181         DUMPREG(DISPC_GFX_PRELOAD);
2182
2183         DUMPREG(DISPC_VID_BA0(0));
2184         DUMPREG(DISPC_VID_BA1(0));
2185         DUMPREG(DISPC_VID_POSITION(0));
2186         DUMPREG(DISPC_VID_SIZE(0));
2187         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2188         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2189         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2190         DUMPREG(DISPC_VID_ROW_INC(0));
2191         DUMPREG(DISPC_VID_PIXEL_INC(0));
2192         DUMPREG(DISPC_VID_FIR(0));
2193         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2194         DUMPREG(DISPC_VID_ACCU0(0));
2195         DUMPREG(DISPC_VID_ACCU1(0));
2196
2197         DUMPREG(DISPC_VID_BA0(1));
2198         DUMPREG(DISPC_VID_BA1(1));
2199         DUMPREG(DISPC_VID_POSITION(1));
2200         DUMPREG(DISPC_VID_SIZE(1));
2201         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2202         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2203         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2204         DUMPREG(DISPC_VID_ROW_INC(1));
2205         DUMPREG(DISPC_VID_PIXEL_INC(1));
2206         DUMPREG(DISPC_VID_FIR(1));
2207         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2208         DUMPREG(DISPC_VID_ACCU0(1));
2209         DUMPREG(DISPC_VID_ACCU1(1));
2210
2211         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2212         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2213         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2214         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2215         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2216         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2217         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2218         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2219         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2220         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2221         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2222         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2223         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2224         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2225         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2226         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2227         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2228         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2229         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2230         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2231         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2232         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2233         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2234         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2235         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2236         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2237         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2238         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2239         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2240
2241         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2242         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2243         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2244         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2245         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2246         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2247         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2248         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2249         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2250         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2251         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2252         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2253         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2254         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2255         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2256         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2257         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2258         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2259         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2260         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2261         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2262         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2263         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2264         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2265         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2266         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2267         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2268         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2269         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2270
2271         DUMPREG(DISPC_VID_PRELOAD(0));
2272         DUMPREG(DISPC_VID_PRELOAD(1));
2273
2274         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2275 #undef DUMPREG
2276 }
2277
2278 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2279                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2280 {
2281         u32 l = 0;
2282
2283         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2284                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2285
2286         l |= FLD_VAL(onoff, 17, 17);
2287         l |= FLD_VAL(rf, 16, 16);
2288         l |= FLD_VAL(ieo, 15, 15);
2289         l |= FLD_VAL(ipc, 14, 14);
2290         l |= FLD_VAL(ihs, 13, 13);
2291         l |= FLD_VAL(ivs, 12, 12);
2292         l |= FLD_VAL(acbi, 11, 8);
2293         l |= FLD_VAL(acb, 7, 0);
2294
2295         enable_clocks(1);
2296         dispc_write_reg(DISPC_POL_FREQ, l);
2297         enable_clocks(0);
2298 }
2299
2300 void dispc_set_pol_freq(struct omap_panel *panel)
2301 {
2302         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2303                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2304                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2305                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2306                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2307                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2308                                  panel->acbi, panel->acb);
2309 }
2310
2311 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2312                 u16 *lck_div, u16 *pck_div)
2313 {
2314         u16 pcd_min = is_tft ? 2 : 3;
2315         unsigned long best_pck;
2316         u16 best_ld, cur_ld;
2317         u16 best_pd, cur_pd;
2318
2319         best_pck = 0;
2320         best_ld = 0;
2321         best_pd = 0;
2322
2323         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2324                 unsigned long lck = fck / cur_ld;
2325
2326                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2327                         unsigned long pck = lck / cur_pd;
2328                         long old_delta = abs(best_pck - req_pck);
2329                         long new_delta = abs(pck - req_pck);
2330
2331                         if (best_pck == 0 || new_delta < old_delta) {
2332                                 best_pck = pck;
2333                                 best_ld = cur_ld;
2334                                 best_pd = cur_pd;
2335
2336                                 if (pck == req_pck)
2337                                         goto found;
2338                         }
2339
2340                         if (pck < req_pck)
2341                                 break;
2342                 }
2343
2344                 if (lck / pcd_min < req_pck)
2345                         break;
2346         }
2347
2348 found:
2349         *lck_div = best_ld;
2350         *pck_div = best_pd;
2351 }
2352
2353 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2354                 struct dispc_clock_info *cinfo)
2355 {
2356         unsigned long prate;
2357         struct dispc_clock_info cur, best;
2358         int match = 0;
2359         int min_fck_per_pck;
2360         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2361
2362         if (cpu_is_omap34xx())
2363                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2364         else
2365                 prate = 0;
2366
2367         if (req_pck == dispc.cache_req_pck &&
2368                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2369                          dispc.cache_cinfo.fck == fck_rate)) {
2370                 DSSDBG("dispc clock info found from cache.\n");
2371                 *cinfo = dispc.cache_cinfo;
2372                 return 0;
2373         }
2374
2375         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2376
2377         if (min_fck_per_pck &&
2378                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2379                 DSSERR("Requested pixel clock not possible with the current "
2380                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2381                                 "the constraint off.\n");
2382                 min_fck_per_pck = 0;
2383         }
2384
2385 retry:
2386         memset(&cur, 0, sizeof(cur));
2387         memset(&best, 0, sizeof(best));
2388
2389         if (cpu_is_omap24xx()) {
2390                 /* XXX can we change the clock on omap2? */
2391                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2392                 cur.fck_div = 1;
2393
2394                 match = 1;
2395
2396                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2397                                 &cur.lck_div, &cur.pck_div);
2398
2399                 cur.lck = cur.fck / cur.lck_div;
2400                 cur.pck = cur.lck / cur.pck_div;
2401
2402                 best = cur;
2403
2404                 goto found;
2405         } else if (cpu_is_omap34xx()) {
2406                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2407                         cur.fck = prate / cur.fck_div * 2;
2408
2409                         if (cur.fck > DISPC_MAX_FCK)
2410                                 continue;
2411
2412                         if (min_fck_per_pck &&
2413                                         cur.fck < req_pck * min_fck_per_pck)
2414                                 continue;
2415
2416                         match = 1;
2417
2418                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2419                                         &cur.lck_div, &cur.pck_div);
2420
2421                         cur.lck = cur.fck / cur.lck_div;
2422                         cur.pck = cur.lck / cur.pck_div;
2423
2424                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2425                                 best = cur;
2426
2427                                 if (cur.pck == req_pck)
2428                                         goto found;
2429                         }
2430                 }
2431         } else {
2432                 BUG();
2433         }
2434
2435 found:
2436         if (!match) {
2437                 if (min_fck_per_pck) {
2438                         DSSERR("Could not find suitable clock settings.\n"
2439                                         "Turning FCK/PCK constraint off and"
2440                                         "trying again.\n");
2441                         min_fck_per_pck = 0;
2442                         goto retry;
2443                 }
2444
2445                 DSSERR("Could not find suitable clock settings.\n");
2446
2447                 return -EINVAL;
2448         }
2449
2450         if (cinfo)
2451                 *cinfo = best;
2452
2453         dispc.cache_req_pck = req_pck;
2454         dispc.cache_prate = prate;
2455         dispc.cache_cinfo = best;
2456
2457         return 0;
2458 }
2459
2460 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2461 {
2462         unsigned long prate;
2463         int r;
2464
2465         if (cpu_is_omap34xx()) {
2466                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2467                 DSSDBG("dpll4_m4 = %ld\n", prate);
2468         }
2469
2470         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2471         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2472         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2473
2474         if (cpu_is_omap34xx()) {
2475                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2476                 if (r)
2477                         return r;
2478         }
2479
2480         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2481
2482         return 0;
2483 }
2484
2485 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2486 {
2487         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2488
2489         if (cpu_is_omap34xx()) {
2490                 unsigned long prate;
2491                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2492                 cinfo->fck_div = prate / (cinfo->fck / 2);
2493         } else {
2494                 cinfo->fck_div = 0;
2495         }
2496
2497         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2498         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2499
2500         cinfo->lck = cinfo->fck / cinfo->lck_div;
2501         cinfo->pck = cinfo->lck / cinfo->pck_div;
2502
2503         return 0;
2504 }
2505
2506 static void omap_dispc_set_irqs(void)
2507 {
2508         unsigned long flags;
2509         u32 mask = dispc.irq_error_mask;
2510         int i;
2511         struct omap_dispc_isr_data *isr_data;
2512
2513         spin_lock_irqsave(&dispc.irq_lock, flags);
2514
2515         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2516                 isr_data = &dispc.registered_isr[i];
2517
2518                 if (isr_data->isr == NULL)
2519                         continue;
2520
2521                 mask |= isr_data->mask;
2522         }
2523
2524         enable_clocks(1);
2525         dispc_write_reg(DISPC_IRQENABLE, mask);
2526         enable_clocks(0);
2527
2528         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2529 }
2530
2531 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2532 {
2533         int i;
2534         int ret;
2535         unsigned long flags;
2536         struct omap_dispc_isr_data *isr_data;
2537
2538         if (isr == NULL)
2539                 return -EINVAL;
2540
2541         spin_lock_irqsave(&dispc.irq_lock, flags);
2542
2543         /* check for duplicate entry */
2544         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2545                 isr_data = &dispc.registered_isr[i];
2546                 if (isr_data->isr == isr && isr_data->arg == arg &&
2547                                 isr_data->mask == mask) {
2548                         ret = -EINVAL;
2549                         goto err;
2550                 }
2551         }
2552
2553         isr_data = NULL;
2554         ret = -EBUSY;
2555
2556         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2557                 isr_data = &dispc.registered_isr[i];
2558
2559                 if (isr_data->isr != NULL)
2560                         continue;
2561
2562                 isr_data->isr = isr;
2563                 isr_data->arg = arg;
2564                 isr_data->mask = mask;
2565                 ret = 0;
2566
2567                 break;
2568         }
2569 err:
2570         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2571
2572         if (ret == 0)
2573                 omap_dispc_set_irqs();
2574
2575         return ret;
2576 }
2577 EXPORT_SYMBOL(omap_dispc_register_isr);
2578
2579 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2580 {
2581         int i;
2582         unsigned long flags;
2583         int ret = -EINVAL;
2584         struct omap_dispc_isr_data *isr_data;
2585
2586         spin_lock_irqsave(&dispc.irq_lock, flags);
2587
2588         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2589                 isr_data = &dispc.registered_isr[i];
2590                 if (isr_data->isr != isr || isr_data->arg != arg ||
2591                                 isr_data->mask != mask)
2592                         continue;
2593
2594                 /* found the correct isr */
2595
2596                 isr_data->isr = NULL;
2597                 isr_data->arg = NULL;
2598                 isr_data->mask = 0;
2599
2600                 ret = 0;
2601                 break;
2602         }
2603
2604         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2605
2606         if (ret == 0)
2607                 omap_dispc_set_irqs();
2608
2609         return ret;
2610 }
2611 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2612
2613 #ifdef DEBUG
2614 static void print_irq_status(u32 status)
2615 {
2616         if ((status & dispc.irq_error_mask) == 0)
2617                 return;
2618
2619         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2620
2621 #define PIS(x) \
2622         if (status & DISPC_IRQ_##x) \
2623                 printk(#x " ");
2624         PIS(GFX_FIFO_UNDERFLOW);
2625         PIS(OCP_ERR);
2626         PIS(VID1_FIFO_UNDERFLOW);
2627         PIS(VID2_FIFO_UNDERFLOW);
2628         PIS(SYNC_LOST);
2629         PIS(SYNC_LOST_DIGIT);
2630 #undef PIS
2631
2632         printk("\n");
2633 }
2634 #endif
2635
2636 /* Called from dss.c. Note that we don't touch clocks here,
2637  * but we presume they are on because we got an IRQ. However,
2638  * an irq handler may turn the clocks off, so we may not have
2639  * clock later in the function. */
2640 void dispc_irq_handler(void)
2641 {
2642         int i;
2643         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2644         u32 handledirqs = 0;
2645         u32 unhandled_errors;
2646         struct omap_dispc_isr_data *isr_data;
2647
2648 #ifdef DEBUG
2649         if (dss_debug)
2650                 print_irq_status(irqstatus);
2651 #endif
2652         /* Ack the interrupt. Do it here before clocks are possibly turned
2653          * off */
2654         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2655
2656         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2657                 isr_data = &dispc.registered_isr[i];
2658
2659                 if (!isr_data->isr)
2660                         continue;
2661
2662                 if (isr_data->mask & irqstatus) {
2663                         isr_data->isr(isr_data->arg, irqstatus);
2664                         handledirqs |= isr_data->mask;
2665                 }
2666         }
2667
2668         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2669
2670         if (unhandled_errors) {
2671                 spin_lock(&dispc.error_lock);
2672                 dispc.error_irqs |= unhandled_errors;
2673                 spin_unlock(&dispc.error_lock);
2674
2675                 dispc.irq_error_mask &= ~unhandled_errors;
2676                 omap_dispc_set_irqs();
2677
2678                 schedule_work(&dispc.error_work);
2679         }
2680 }
2681
2682 static void dispc_error_worker(struct work_struct *work)
2683 {
2684         int i;
2685         u32 errors;
2686         unsigned long flags;
2687
2688         spin_lock_irqsave(&dispc.error_lock, flags);
2689         errors = dispc.error_irqs;
2690         dispc.error_irqs = 0;
2691         spin_unlock_irqrestore(&dispc.error_lock, flags);
2692
2693         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2694                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2695                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2696                         struct omap_overlay *ovl;
2697                         ovl = omap_dss_get_overlay(i);
2698
2699                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2700                                 continue;
2701
2702                         if (ovl->id == 0) {
2703                                 dispc_enable_plane(ovl->id, 0);
2704                                 dispc_go(ovl->manager->id);
2705                                 mdelay(50);
2706                                 break;
2707                         }
2708                 }
2709         }
2710
2711         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2712                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2713                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2714                         struct omap_overlay *ovl;
2715                         ovl = omap_dss_get_overlay(i);
2716
2717                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2718                                 continue;
2719
2720                         if (ovl->id == 1) {
2721                                 dispc_enable_plane(ovl->id, 0);
2722                                 dispc_go(ovl->manager->id);
2723                                 mdelay(50);
2724                                 break;
2725                         }
2726                 }
2727         }
2728
2729         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2730                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2731                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2732                         struct omap_overlay *ovl;
2733                         ovl = omap_dss_get_overlay(i);
2734
2735                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2736                                 continue;
2737
2738                         if (ovl->id == 2) {
2739                                 dispc_enable_plane(ovl->id, 0);
2740                                 dispc_go(ovl->manager->id);
2741                                 mdelay(50);
2742                                 break;
2743                         }
2744                 }
2745         }
2746
2747         if (errors & DISPC_IRQ_SYNC_LOST) {
2748                 struct omap_overlay_manager *manager = NULL;
2749                 bool enable = false;
2750
2751                 DSSERR("SYNC_LOST, disabling LCD\n");
2752
2753                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2754                         struct omap_overlay_manager *mgr;
2755                         mgr = omap_dss_get_overlay_manager(i);
2756
2757                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2758                                 manager = mgr;
2759                                 enable = mgr->display->state ==
2760                                                 OMAP_DSS_DISPLAY_ACTIVE;
2761                                 mgr->display->disable(mgr->display);
2762                                 break;
2763                         }
2764                 }
2765
2766                 if (manager) {
2767                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2768                                 struct omap_overlay *ovl;
2769                                 ovl = omap_dss_get_overlay(i);
2770
2771                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2772                                         continue;
2773
2774                                 if (ovl->id != 0 && ovl->manager == manager)
2775                                         dispc_enable_plane(ovl->id, 0);
2776                         }
2777
2778                         dispc_go(manager->id);
2779                         mdelay(50);
2780                         if (enable)
2781                                 manager->display->enable(manager->display);
2782                 }
2783         }
2784
2785         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2786                 struct omap_overlay_manager *manager = NULL;
2787                 bool enable = false;
2788
2789                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2790
2791                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2792                         struct omap_overlay_manager *mgr;
2793                         mgr = omap_dss_get_overlay_manager(i);
2794
2795                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2796                                 manager = mgr;
2797                                 enable = mgr->display->state ==
2798                                                 OMAP_DSS_DISPLAY_ACTIVE;
2799                                 mgr->display->disable(mgr->display);
2800                                 break;
2801                         }
2802                 }
2803
2804                 if (manager) {
2805                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2806                                 struct omap_overlay *ovl;
2807                                 ovl = omap_dss_get_overlay(i);
2808
2809                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2810                                         continue;
2811
2812                                 if (ovl->id != 0 && ovl->manager == manager)
2813                                         dispc_enable_plane(ovl->id, 0);
2814                         }
2815
2816                         dispc_go(manager->id);
2817                         mdelay(50);
2818                         if (enable)
2819                                 manager->display->enable(manager->display);
2820                 }
2821         }
2822
2823         if (errors & DISPC_IRQ_OCP_ERR) {
2824                 DSSERR("OCP_ERR\n");
2825                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2826                         struct omap_overlay_manager *mgr;
2827                         mgr = omap_dss_get_overlay_manager(i);
2828
2829                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2830                                 mgr->display->disable(mgr->display);
2831                 }
2832         }
2833
2834         dispc.irq_error_mask |= errors;
2835         omap_dispc_set_irqs();
2836 }
2837
2838 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2839 {
2840         void dispc_irq_wait_handler(void *data, u32 mask)
2841         {
2842                 complete((struct completion *)data);
2843         }
2844
2845         int r;
2846         DECLARE_COMPLETION_ONSTACK(completion);
2847
2848         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2849                         irqmask);
2850
2851         if (r)
2852                 return r;
2853
2854         timeout = wait_for_completion_timeout(&completion, timeout);
2855
2856         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2857
2858         if (timeout == 0)
2859                 return -ETIMEDOUT;
2860
2861         if (timeout == -ERESTARTSYS)
2862                 return -ERESTARTSYS;
2863
2864         return 0;
2865 }
2866
2867 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2868                 unsigned long timeout)
2869 {
2870         void dispc_irq_wait_handler(void *data, u32 mask)
2871         {
2872                 complete((struct completion *)data);
2873         }
2874
2875         int r;
2876         DECLARE_COMPLETION_ONSTACK(completion);
2877
2878         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2879                         irqmask);
2880
2881         if (r)
2882                 return r;
2883
2884         timeout = wait_for_completion_interruptible_timeout(&completion,
2885                         timeout);
2886
2887         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2888
2889         if (timeout == 0)
2890                 return -ETIMEDOUT;
2891
2892         if (timeout == -ERESTARTSYS)
2893                 return -ERESTARTSYS;
2894
2895         return 0;
2896 }
2897
2898 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2899 void dispc_fake_vsync_irq(void)
2900 {
2901         u32 irqstatus = DISPC_IRQ_VSYNC;
2902         int i;
2903
2904         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2905                 struct omap_dispc_isr_data *isr_data;
2906                 isr_data = &dispc.registered_isr[i];
2907
2908                 if (!isr_data->isr)
2909                         continue;
2910
2911                 if (isr_data->mask & irqstatus)
2912                         isr_data->isr(isr_data->arg, irqstatus);
2913         }
2914 }
2915 #endif
2916
2917 static void _omap_dispc_initialize_irq(void)
2918 {
2919         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2920
2921         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2922
2923         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2924          * so clear it */
2925         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2926
2927         omap_dispc_set_irqs();
2928 }
2929
2930 void dispc_enable_sidle(void)
2931 {
2932         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
2933 }
2934
2935 void dispc_disable_sidle(void)
2936 {
2937         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
2938 }
2939
2940 static void _omap_dispc_initial_config(void)
2941 {
2942         u32 l;
2943
2944         l = dispc_read_reg(DISPC_SYSCONFIG);
2945         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2946         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2947         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2948         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2949         dispc_write_reg(DISPC_SYSCONFIG, l);
2950
2951         /* FUNCGATED */
2952         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2953
2954         /* L3 firewall setting: enable access to OCM RAM */
2955         if (cpu_is_omap24xx())
2956                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2957
2958         _dispc_setup_color_conv_coef();
2959
2960         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2961 }
2962
2963 int dispc_init(void)
2964 {
2965         u32 rev;
2966
2967         spin_lock_init(&dispc.irq_lock);
2968         spin_lock_init(&dispc.error_lock);
2969
2970         INIT_WORK(&dispc.error_work, dispc_error_worker);
2971
2972         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2973         if (!dispc.base) {
2974                 DSSERR("can't ioremap DISPC\n");
2975                 return -ENOMEM;
2976         }
2977
2978         if (cpu_is_omap34xx()) {
2979                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2980                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2981                         DSSERR("Failed to get dpll4_m4_ck\n");
2982                         return -ENODEV;
2983                 }
2984         }
2985
2986         enable_clocks(1);
2987
2988         _omap_dispc_initial_config();
2989
2990         _omap_dispc_initialize_irq();
2991
2992         dispc_save_context();
2993
2994         rev = dispc_read_reg(DISPC_REVISION);
2995         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2996                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2997
2998         enable_clocks(0);
2999
3000         return 0;
3001 }
3002
3003 void dispc_exit(void)
3004 {
3005         if (cpu_is_omap34xx())
3006                 clk_put(dispc.dpll4_m4_ck);
3007         iounmap(dispc.base);
3008 }
3009
3010 int dispc_enable_plane(enum omap_plane plane, bool enable)
3011 {
3012         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3013
3014         enable_clocks(1);
3015         _dispc_enable_plane(plane, enable);
3016         enable_clocks(0);
3017
3018         return 0;
3019 }
3020
3021 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
3022                        u32 paddr, u16 screen_width,
3023                        u16 pos_x, u16 pos_y,
3024                        u16 width, u16 height,
3025                        u16 out_width, u16 out_height,
3026                        enum omap_color_mode color_mode,
3027                        bool ilace,
3028                        enum omap_dss_rotation_type rotation_type,
3029                        u8 rotation, bool mirror, u8 global_alpha)
3030 {
3031         int r = 0;
3032
3033         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
3034                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3035                plane, channel_out, paddr, screen_width, pos_x, pos_y,
3036                width, height,
3037                out_width, out_height,
3038                ilace, color_mode,
3039                rotation, mirror);
3040
3041         enable_clocks(1);
3042
3043         r = _dispc_setup_plane(plane, channel_out,
3044                            paddr, screen_width,
3045                            pos_x, pos_y,
3046                            width, height,
3047                            out_width, out_height,
3048                            color_mode, ilace,
3049                            rotation_type,
3050                            rotation, mirror,
3051                            global_alpha);
3052
3053         enable_clocks(0);
3054
3055         return r;
3056 }
3057
3058 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
3059                                  int x2, int y2, int w2, int h2)
3060 {
3061         if (x1 >= (x2+w2))
3062                 return 0;
3063
3064         if ((x1+w1) <= x2)
3065                 return 0;
3066
3067         if (y1 >= (y2+h2))
3068                 return 0;
3069
3070         if ((y1+h1) <= y2)
3071                 return 0;
3072
3073         return 1;
3074 }
3075
3076 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
3077 {
3078         if (pi->width != pi->out_width)
3079                 return 1;
3080
3081         if (pi->height != pi->out_height)
3082                 return 1;
3083
3084         return 0;
3085 }
3086
3087 /* returns the area that needs updating */
3088 void dispc_setup_partial_planes(struct omap_display *display,
3089                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
3090 {
3091         struct omap_overlay_manager *mgr;
3092         int i;
3093
3094         int x, y, w, h;
3095
3096         x = *xi;
3097         y = *yi;
3098         w = *wi;
3099         h = *hi;
3100
3101         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
3102                 *xi, *yi, *wi, *hi);
3103
3104
3105         mgr = display->manager;
3106
3107         if (!mgr) {
3108                 DSSDBG("no manager\n");
3109                 return;
3110         }
3111
3112         for (i = 0; i < mgr->num_overlays; i++) {
3113                 struct omap_overlay *ovl;
3114                 struct omap_overlay_info *pi;
3115                 ovl = mgr->overlays[i];
3116
3117                 if (ovl->manager != mgr)
3118                         continue;
3119
3120                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
3121                         continue;
3122
3123                 pi = &ovl->info;
3124
3125                 if (!pi->enabled)
3126                         continue;
3127                 /*
3128                  * If the plane is intersecting and scaled, we
3129                  * enlarge the update region to accomodate the
3130                  * whole area
3131                  */
3132
3133                 if (dispc_is_intersecting(x, y, w, h,
3134                                           pi->pos_x, pi->pos_y,
3135                                           pi->out_width, pi->out_height)) {
3136                         if (dispc_is_overlay_scaled(pi)) {
3137
3138                                 int x1, y1, x2, y2;
3139
3140                                 if (x > pi->pos_x)
3141                                         x1 = pi->pos_x;
3142                                 else
3143                                         x1 = x;
3144
3145                                 if (y > pi->pos_y)
3146                                         y1 = pi->pos_y;
3147                                 else
3148                                         y1 = y;
3149
3150                                 if ((x + w) < (pi->pos_x + pi->out_width))
3151                                         x2 = pi->pos_x + pi->out_width;
3152                                 else
3153                                         x2 = x + w;
3154
3155                                 if ((y + h) < (pi->pos_y + pi->out_height))
3156                                         y2 = pi->pos_y + pi->out_height;
3157                                 else
3158                                         y2 = y + h;
3159
3160                                 x = x1;
3161                                 y = y1;
3162                                 w = x2 - x1;
3163                                 h = y2 - y1;
3164
3165                                 DSSDBG("Update area after enlarge due to "
3166                                         "scaling %d, %d %dx%d\n",
3167                                         x, y, w, h);
3168                         }
3169                 }
3170         }
3171
3172         for (i = 0; i < mgr->num_overlays; i++) {
3173                 struct omap_overlay *ovl = mgr->overlays[i];
3174                 struct omap_overlay_info *pi = &ovl->info;
3175
3176                 int px = pi->pos_x;
3177                 int py = pi->pos_y;
3178                 int pw = pi->width;
3179                 int ph = pi->height;
3180                 int pow = pi->out_width;
3181                 int poh = pi->out_height;
3182                 u32 pa = pi->paddr;
3183                 int psw = pi->screen_width;
3184                 int bpp;
3185
3186                 if (ovl->manager != mgr)
3187                         continue;
3188
3189                 /*
3190                  * If plane is not enabled or the update region
3191                  * does not intersect with the plane in question,
3192                  * we really disable the plane from hardware
3193                  */
3194
3195                 if (!pi->enabled ||
3196                     !dispc_is_intersecting(x, y, w, h,
3197                                            px, py, pow, poh)) {
3198                         dispc_enable_plane(ovl->id, 0);
3199                         continue;
3200                 }
3201
3202                 switch (pi->color_mode) {
3203                 case OMAP_DSS_COLOR_RGB16:
3204                 case OMAP_DSS_COLOR_ARGB16:
3205                 case OMAP_DSS_COLOR_YUV2:
3206                 case OMAP_DSS_COLOR_UYVY:
3207                         bpp = 16;
3208                         break;
3209
3210                 case OMAP_DSS_COLOR_RGB24P:
3211                         bpp = 24;
3212                         break;
3213
3214                 case OMAP_DSS_COLOR_RGB24U:
3215                 case OMAP_DSS_COLOR_ARGB32:
3216                 case OMAP_DSS_COLOR_RGBA32:
3217                 case OMAP_DSS_COLOR_RGBX32:
3218                         bpp = 32;
3219                         break;
3220
3221                 default:
3222                         BUG();
3223                         return;
3224                 }
3225
3226                 if (x > pi->pos_x) {
3227                         px = 0;
3228                         pw -= (x - pi->pos_x);
3229                         pa += (x - pi->pos_x) * bpp / 8;
3230                 } else {
3231                         px = pi->pos_x - x;
3232                 }
3233
3234                 if (y > pi->pos_y) {
3235                         py = 0;
3236                         ph -= (y - pi->pos_y);
3237                         pa += (y - pi->pos_y) * psw * bpp / 8;
3238                 } else {
3239                         py = pi->pos_y - y;
3240                 }
3241
3242                 if (w < (px+pw))
3243                         pw -= (px+pw) - (w);
3244
3245                 if (h < (py+ph))
3246                         ph -= (py+ph) - (h);
3247
3248                 /* Can't scale the GFX plane */
3249                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3250                                 dispc_is_overlay_scaled(pi) == 0) {
3251                         pow = pw;
3252                         poh = ph;
3253                 }
3254
3255                 DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3256                                 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3257
3258                 dispc_setup_plane(ovl->id, mgr->id,
3259                                 pa, psw,
3260                                 px, py,
3261                                 pw, ph,
3262                                 pow, poh,
3263                                 pi->color_mode, 0,
3264                                 pi->rotation_type,
3265                                 pi->rotation,
3266                                 pi->mirror,
3267                                 pi->global_alpha);
3268
3269                 dispc_enable_plane(ovl->id, 1);
3270         }
3271
3272         *xi = x;
3273         *yi = y;
3274         *wi = w;
3275         *hi = h;
3276
3277 }
3278