drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34
  35 #include <mach/sram.h>
  36 #include <mach/board.h>
  37 #include <mach/clock.h>
  38
  39 #include <mach/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 #define REG_GET(idx, start, end) \
 143         FLD_GET(dispc_read_reg(idx), start, end)
 144
 145 #define REG_FLD_MOD(idx, val, start, end)                               \
 146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 147
 148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 149         DISPC_VID_ATTRIBUTES(0),
 150         DISPC_VID_ATTRIBUTES(1) };
 151
 152 static struct {
 153         void __iomem    *base;
 154
 155         struct clk      *dpll4_m4_ck;
 156
 157         spinlock_t      irq_lock;
 158
 159         unsigned long   cache_req_pck;
 160         unsigned long   cache_prate;
 161         struct dispc_clock_info cache_cinfo;
 162
 163         u32             irq_error_mask;
 164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 165
 166         spinlock_t error_lock;
 167         u32 error_irqs;
 168         struct work_struct error_work;
 169
 170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 171 } dispc;
 172
 173 static void omap_dispc_set_irqs(void);
 174
 175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 176 {
 177         __raw_writel(val, dispc.base + idx.idx);
 178 }
 179
 180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 181 {
 182         return __raw_readl(dispc.base + idx.idx);
 183 }
 184
 185 #define SR(reg) \
 186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 187 #define RR(reg) \
 188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 189
 190 void dispc_save_context(void)
 191 {
 192         if (cpu_is_omap24xx())
 193                 return;
 194
 195         SR(SYSCONFIG);
 196         SR(IRQENABLE);
 197         SR(CONTROL);
 198         SR(CONFIG);
 199         SR(DEFAULT_COLOR0);
 200         SR(DEFAULT_COLOR1);
 201         SR(TRANS_COLOR0);
 202         SR(TRANS_COLOR1);
 203         SR(LINE_NUMBER);
 204         SR(TIMING_H);
 205         SR(TIMING_V);
 206         SR(POL_FREQ);
 207         SR(DIVISOR);
 208         SR(GLOBAL_ALPHA);
 209         SR(SIZE_DIG);
 210         SR(SIZE_LCD);
 211
 212         SR(GFX_BA0);
 213         SR(GFX_BA1);
 214         SR(GFX_POSITION);
 215         SR(GFX_SIZE);
 216         SR(GFX_ATTRIBUTES);
 217         SR(GFX_FIFO_THRESHOLD);
 218         SR(GFX_ROW_INC);
 219         SR(GFX_PIXEL_INC);
 220         SR(GFX_WINDOW_SKIP);
 221         SR(GFX_TABLE_BA);
 222
 223         SR(DATA_CYCLE1);
 224         SR(DATA_CYCLE2);
 225         SR(DATA_CYCLE3);
 226
 227         SR(CPR_COEF_R);
 228         SR(CPR_COEF_G);
 229         SR(CPR_COEF_B);
 230
 231         SR(GFX_PRELOAD);
 232
 233         /* VID1 */
 234         SR(VID_BA0(0));
 235         SR(VID_BA1(0));
 236         SR(VID_POSITION(0));
 237         SR(VID_SIZE(0));
 238         SR(VID_ATTRIBUTES(0));
 239         SR(VID_FIFO_THRESHOLD(0));
 240         SR(VID_ROW_INC(0));
 241         SR(VID_PIXEL_INC(0));
 242         SR(VID_FIR(0));
 243         SR(VID_PICTURE_SIZE(0));
 244         SR(VID_ACCU0(0));
 245         SR(VID_ACCU1(0));
 246
 247         SR(VID_FIR_COEF_H(0, 0));
 248         SR(VID_FIR_COEF_H(0, 1));
 249         SR(VID_FIR_COEF_H(0, 2));
 250         SR(VID_FIR_COEF_H(0, 3));
 251         SR(VID_FIR_COEF_H(0, 4));
 252         SR(VID_FIR_COEF_H(0, 5));
 253         SR(VID_FIR_COEF_H(0, 6));
 254         SR(VID_FIR_COEF_H(0, 7));
 255
 256         SR(VID_FIR_COEF_HV(0, 0));
 257         SR(VID_FIR_COEF_HV(0, 1));
 258         SR(VID_FIR_COEF_HV(0, 2));
 259         SR(VID_FIR_COEF_HV(0, 3));
 260         SR(VID_FIR_COEF_HV(0, 4));
 261         SR(VID_FIR_COEF_HV(0, 5));
 262         SR(VID_FIR_COEF_HV(0, 6));
 263         SR(VID_FIR_COEF_HV(0, 7));
 264
 265         SR(VID_CONV_COEF(0, 0));
 266         SR(VID_CONV_COEF(0, 1));
 267         SR(VID_CONV_COEF(0, 2));
 268         SR(VID_CONV_COEF(0, 3));
 269         SR(VID_CONV_COEF(0, 4));
 270
 271         SR(VID_FIR_COEF_V(0, 0));
 272         SR(VID_FIR_COEF_V(0, 1));
 273         SR(VID_FIR_COEF_V(0, 2));
 274         SR(VID_FIR_COEF_V(0, 3));
 275         SR(VID_FIR_COEF_V(0, 4));
 276         SR(VID_FIR_COEF_V(0, 5));
 277         SR(VID_FIR_COEF_V(0, 6));
 278         SR(VID_FIR_COEF_V(0, 7));
 279
 280         SR(VID_PRELOAD(0));
 281
 282         /* VID2 */
 283         SR(VID_BA0(1));
 284         SR(VID_BA1(1));
 285         SR(VID_POSITION(1));
 286         SR(VID_SIZE(1));
 287         SR(VID_ATTRIBUTES(1));
 288         SR(VID_FIFO_THRESHOLD(1));
 289         SR(VID_ROW_INC(1));
 290         SR(VID_PIXEL_INC(1));
 291         SR(VID_FIR(1));
 292         SR(VID_PICTURE_SIZE(1));
 293         SR(VID_ACCU0(1));
 294         SR(VID_ACCU1(1));
 295
 296         SR(VID_FIR_COEF_H(1, 0));
 297         SR(VID_FIR_COEF_H(1, 1));
 298         SR(VID_FIR_COEF_H(1, 2));
 299         SR(VID_FIR_COEF_H(1, 3));
 300         SR(VID_FIR_COEF_H(1, 4));
 301         SR(VID_FIR_COEF_H(1, 5));
 302         SR(VID_FIR_COEF_H(1, 6));
 303         SR(VID_FIR_COEF_H(1, 7));
 304
 305         SR(VID_FIR_COEF_HV(1, 0));
 306         SR(VID_FIR_COEF_HV(1, 1));
 307         SR(VID_FIR_COEF_HV(1, 2));
 308         SR(VID_FIR_COEF_HV(1, 3));
 309         SR(VID_FIR_COEF_HV(1, 4));
 310         SR(VID_FIR_COEF_HV(1, 5));
 311         SR(VID_FIR_COEF_HV(1, 6));
 312         SR(VID_FIR_COEF_HV(1, 7));
 313
 314         SR(VID_CONV_COEF(1, 0));
 315         SR(VID_CONV_COEF(1, 1));
 316         SR(VID_CONV_COEF(1, 2));
 317         SR(VID_CONV_COEF(1, 3));
 318         SR(VID_CONV_COEF(1, 4));
 319
 320         SR(VID_FIR_COEF_V(1, 0));
 321         SR(VID_FIR_COEF_V(1, 1));
 322         SR(VID_FIR_COEF_V(1, 2));
 323         SR(VID_FIR_COEF_V(1, 3));
 324         SR(VID_FIR_COEF_V(1, 4));
 325         SR(VID_FIR_COEF_V(1, 5));
 326         SR(VID_FIR_COEF_V(1, 6));
 327         SR(VID_FIR_COEF_V(1, 7));
 328
 329         SR(VID_PRELOAD(1));
 330 }
 331
 332 void dispc_restore_context(void)
 333 {
 334         RR(SYSCONFIG);
 335         RR(IRQENABLE);
 336         /*RR(CONTROL);*/
 337         RR(CONFIG);
 338         RR(DEFAULT_COLOR0);
 339         RR(DEFAULT_COLOR1);
 340         RR(TRANS_COLOR0);
 341         RR(TRANS_COLOR1);
 342         RR(LINE_NUMBER);
 343         RR(TIMING_H);
 344         RR(TIMING_V);
 345         RR(POL_FREQ);
 346         RR(DIVISOR);
 347         RR(GLOBAL_ALPHA);
 348         RR(SIZE_DIG);
 349         RR(SIZE_LCD);
 350
 351         RR(GFX_BA0);
 352         RR(GFX_BA1);
 353         RR(GFX_POSITION);
 354         RR(GFX_SIZE);
 355         RR(GFX_ATTRIBUTES);
 356         RR(GFX_FIFO_THRESHOLD);
 357         RR(GFX_ROW_INC);
 358         RR(GFX_PIXEL_INC);
 359         RR(GFX_WINDOW_SKIP);
 360         RR(GFX_TABLE_BA);
 361
 362         RR(DATA_CYCLE1);
 363         RR(DATA_CYCLE2);
 364         RR(DATA_CYCLE3);
 365
 366         RR(CPR_COEF_R);
 367         RR(CPR_COEF_G);
 368         RR(CPR_COEF_B);
 369
 370         RR(GFX_PRELOAD);
 371
 372         /* VID1 */
 373         RR(VID_BA0(0));
 374         RR(VID_BA1(0));
 375         RR(VID_POSITION(0));
 376         RR(VID_SIZE(0));
 377         RR(VID_ATTRIBUTES(0));
 378         RR(VID_FIFO_THRESHOLD(0));
 379         RR(VID_ROW_INC(0));
 380         RR(VID_PIXEL_INC(0));
 381         RR(VID_FIR(0));
 382         RR(VID_PICTURE_SIZE(0));
 383         RR(VID_ACCU0(0));
 384         RR(VID_ACCU1(0));
 385
 386         RR(VID_FIR_COEF_H(0, 0));
 387         RR(VID_FIR_COEF_H(0, 1));
 388         RR(VID_FIR_COEF_H(0, 2));
 389         RR(VID_FIR_COEF_H(0, 3));
 390         RR(VID_FIR_COEF_H(0, 4));
 391         RR(VID_FIR_COEF_H(0, 5));
 392         RR(VID_FIR_COEF_H(0, 6));
 393         RR(VID_FIR_COEF_H(0, 7));
 394
 395         RR(VID_FIR_COEF_HV(0, 0));
 396         RR(VID_FIR_COEF_HV(0, 1));
 397         RR(VID_FIR_COEF_HV(0, 2));
 398         RR(VID_FIR_COEF_HV(0, 3));
 399         RR(VID_FIR_COEF_HV(0, 4));
 400         RR(VID_FIR_COEF_HV(0, 5));
 401         RR(VID_FIR_COEF_HV(0, 6));
 402         RR(VID_FIR_COEF_HV(0, 7));
 403
 404         RR(VID_CONV_COEF(0, 0));
 405         RR(VID_CONV_COEF(0, 1));
 406         RR(VID_CONV_COEF(0, 2));
 407         RR(VID_CONV_COEF(0, 3));
 408         RR(VID_CONV_COEF(0, 4));
 409
 410         RR(VID_FIR_COEF_V(0, 0));
 411         RR(VID_FIR_COEF_V(0, 1));
 412         RR(VID_FIR_COEF_V(0, 2));
 413         RR(VID_FIR_COEF_V(0, 3));
 414         RR(VID_FIR_COEF_V(0, 4));
 415         RR(VID_FIR_COEF_V(0, 5));
 416         RR(VID_FIR_COEF_V(0, 6));
 417         RR(VID_FIR_COEF_V(0, 7));
 418
 419         RR(VID_PRELOAD(0));
 420
 421         /* VID2 */
 422         RR(VID_BA0(1));
 423         RR(VID_BA1(1));
 424         RR(VID_POSITION(1));
 425         RR(VID_SIZE(1));
 426         RR(VID_ATTRIBUTES(1));
 427         RR(VID_FIFO_THRESHOLD(1));
 428         RR(VID_ROW_INC(1));
 429         RR(VID_PIXEL_INC(1));
 430         RR(VID_FIR(1));
 431         RR(VID_PICTURE_SIZE(1));
 432         RR(VID_ACCU0(1));
 433         RR(VID_ACCU1(1));
 434
 435         RR(VID_FIR_COEF_H(1, 0));
 436         RR(VID_FIR_COEF_H(1, 1));
 437         RR(VID_FIR_COEF_H(1, 2));
 438         RR(VID_FIR_COEF_H(1, 3));
 439         RR(VID_FIR_COEF_H(1, 4));
 440         RR(VID_FIR_COEF_H(1, 5));
 441         RR(VID_FIR_COEF_H(1, 6));
 442         RR(VID_FIR_COEF_H(1, 7));
 443
 444         RR(VID_FIR_COEF_HV(1, 0));
 445         RR(VID_FIR_COEF_HV(1, 1));
 446         RR(VID_FIR_COEF_HV(1, 2));
 447         RR(VID_FIR_COEF_HV(1, 3));
 448         RR(VID_FIR_COEF_HV(1, 4));
 449         RR(VID_FIR_COEF_HV(1, 5));
 450         RR(VID_FIR_COEF_HV(1, 6));
 451         RR(VID_FIR_COEF_HV(1, 7));
 452
 453         RR(VID_CONV_COEF(1, 0));
 454         RR(VID_CONV_COEF(1, 1));
 455         RR(VID_CONV_COEF(1, 2));
 456         RR(VID_CONV_COEF(1, 3));
 457         RR(VID_CONV_COEF(1, 4));
 458
 459         RR(VID_FIR_COEF_V(1, 0));
 460         RR(VID_FIR_COEF_V(1, 1));
 461         RR(VID_FIR_COEF_V(1, 2));
 462         RR(VID_FIR_COEF_V(1, 3));
 463         RR(VID_FIR_COEF_V(1, 4));
 464         RR(VID_FIR_COEF_V(1, 5));
 465         RR(VID_FIR_COEF_V(1, 6));
 466         RR(VID_FIR_COEF_V(1, 7));
 467
 468         RR(VID_PRELOAD(1));
 469
 470         /* enable last, because LCD & DIGIT enable are here */
 471         RR(CONTROL);
 472 }
 473
 474 #undef SR
 475 #undef RR
 476
 477 static inline void enable_clocks(bool enable)
 478 {
 479         if (enable)
 480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 481         else
 482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 483 }
 484
 485 void dispc_go(enum omap_channel channel)
 486 {
 487         int bit;
 488         unsigned long tmo;
 489
 490         enable_clocks(1);
 491
 492         if (channel == OMAP_DSS_CHANNEL_LCD)
 493                 bit = 0; /* LCDENABLE */
 494         else
 495                 bit = 1; /* DIGITALENABLE */
 496
 497         /* if the channel is not enabled, we don't need GO */
 498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 499                 goto end;
 500
 501         if (channel == OMAP_DSS_CHANNEL_LCD)
 502                 bit = 5; /* GOLCD */
 503         else
 504                 bit = 6; /* GODIGIT */
 505
 506         tmo = jiffies + msecs_to_jiffies(200);
 507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 508                 if (time_after(jiffies, tmo)) {
 509                         DSSERR("timeout waiting GO flag\n");
 510                         goto end;
 511                 }
 512                 cpu_relax();
 513         }
 514
 515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 516
 517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 518 end:
 519         enable_clocks(0);
 520 }
 521
 522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 523 {
 524         BUG_ON(plane == OMAP_DSS_GFX);
 525
 526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 527 }
 528
 529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         BUG_ON(plane == OMAP_DSS_GFX);
 532
 533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 534 }
 535
 536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 537 {
 538         BUG_ON(plane == OMAP_DSS_GFX);
 539
 540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 541 }
 542
 543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 544                 int vscaleup, int five_taps)
 545 {
 546         /* Coefficients for horizontal up-sampling */
 547         static const u32 coef_hup[8] = {
 548                 0x00800000,
 549                 0x0D7CF800,
 550                 0x1E70F5FF,
 551                 0x335FF5FE,
 552                 0xF74949F7,
 553                 0xF55F33FB,
 554                 0xF5701EFE,
 555                 0xF87C0DFF,
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const u32 coef_hdown[8] = {
 560                 0x24382400,
 561                 0x28371FFE,
 562                 0x2C361BFB,
 563                 0x303516F9,
 564                 0x11343311,
 565                 0x1635300C,
 566                 0x1B362C08,
 567                 0x1F372804,
 568         };
 569
 570         /* Coefficients for horizontal and vertical up-sampling */
 571         static const u32 coef_hvup[2][8] = {
 572                 {
 573                 0x00800000,
 574                 0x037B02FF,
 575                 0x0C6F05FE,
 576                 0x205907FB,
 577                 0x00404000,
 578                 0x075920FE,
 579                 0x056F0CFF,
 580                 0x027B0300,
 581                 },
 582                 {
 583                 0x00800000,
 584                 0x0D7CF8FF,
 585                 0x1E70F5FE,
 586                 0x335FF5FB,
 587                 0xF7404000,
 588                 0xF55F33FE,
 589                 0xF5701EFF,
 590                 0xF87C0D00,
 591                 },
 592         };
 593
 594         /* Coefficients for horizontal and vertical down-sampling */
 595         static const u32 coef_hvdown[2][8] = {
 596                 {
 597                 0x24382400,
 598                 0x28391F04,
 599                 0x2D381B08,
 600                 0x3237170C,
 601                 0x123737F7,
 602                 0x173732F9,
 603                 0x1B382DFB,
 604                 0x1F3928FE,
 605                 },
 606                 {
 607                 0x24382400,
 608                 0x28371F04,
 609                 0x2C361B08,
 610                 0x3035160C,
 611                 0x113433F7,
 612                 0x163530F9,
 613                 0x1B362CFB,
 614                 0x1F3728FE,
 615                 },
 616         };
 617
 618         /* Coefficients for vertical up-sampling */
 619         static const u32 coef_vup[8] = {
 620                 0x00000000,
 621                 0x0000FF00,
 622                 0x0000FEFF,
 623                 0x0000FBFE,
 624                 0x000000F7,
 625                 0x0000FEFB,
 626                 0x0000FFFE,
 627                 0x000000FF,
 628         };
 629
 630
 631         /* Coefficients for vertical down-sampling */
 632         static const u32 coef_vdown[8] = {
 633                 0x00000000,
 634                 0x000004FE,
 635                 0x000008FB,
 636                 0x00000CF9,
 637                 0x0000F711,
 638                 0x0000F90C,
 639                 0x0000FB08,
 640                 0x0000FE04,
 641         };
 642
 643         const u32 *h_coef;
 644         const u32 *hv_coef;
 645         const u32 *hv_coef_mod;
 646         const u32 *v_coef;
 647         int i;
 648
 649         if (hscaleup)
 650                 h_coef = coef_hup;
 651         else
 652                 h_coef = coef_hdown;
 653
 654         if (vscaleup) {
 655                 hv_coef = coef_hvup[five_taps];
 656                 v_coef = coef_vup;
 657
 658                 if (hscaleup)
 659                         hv_coef_mod = NULL;
 660                 else
 661                         hv_coef_mod = coef_hvdown[five_taps];
 662         } else {
 663                 hv_coef = coef_hvdown[five_taps];
 664                 v_coef = coef_vdown;
 665
 666                 if (hscaleup)
 667                         hv_coef_mod = coef_hvup[five_taps];
 668                 else
 669                         hv_coef_mod = NULL;
 670         }
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = h_coef[i];
 676
 677                 hv = hv_coef[i];
 678
 679                 if (hv_coef_mod) {
 680                         hv &= 0xffffff00;
 681                         hv |= (hv_coef_mod[i] & 0xff);
 682                 }
 683
 684                 _dispc_write_firh_reg(plane, i, h);
 685                 _dispc_write_firhv_reg(plane, i, hv);
 686         }
 687
 688         if (!five_taps)
 689                 return;
 690
 691         for (i = 0; i < 8; i++) {
 692                 u32 v;
 693                 v = v_coef[i];
 694                 _dispc_write_firv_reg(plane, i, v);
 695         }
 696 }
 697
 698 static void _dispc_setup_color_conv_coef(void)
 699 {
 700         const struct color_conv_coef {
 701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 702                 int  full_range;
 703         }  ctbl_bt601_5 = {
 704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 705         };
 706
 707         const struct color_conv_coef *ct;
 708
 709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 710
 711         ct = &ctbl_bt601_5;
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 718
 719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 724
 725 #undef CVAL
 726
 727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 729 }
 730
 731
 732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 733 {
 734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 735                 DISPC_VID_BA0(0),
 736                 DISPC_VID_BA0(1) };
 737
 738         dispc_write_reg(ba0_reg[plane], paddr);
 739 }
 740
 741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 742 {
 743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 744                                       DISPC_VID_BA1(0),
 745                                       DISPC_VID_BA1(1) };
 746
 747         dispc_write_reg(ba1_reg[plane], paddr);
 748 }
 749
 750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 751 {
 752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 753                                       DISPC_VID_POSITION(0),
 754                                       DISPC_VID_POSITION(1) };
 755
 756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 757         dispc_write_reg(pos_reg[plane], val);
 758 }
 759
 760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 761 {
 762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 763                                       DISPC_VID_PICTURE_SIZE(0),
 764                                       DISPC_VID_PICTURE_SIZE(1) };
 765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 766         dispc_write_reg(siz_reg[plane], val);
 767 }
 768
 769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 770 {
 771         u32 val;
 772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 773                                       DISPC_VID_SIZE(1) };
 774
 775         BUG_ON(plane == OMAP_DSS_GFX);
 776
 777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 778         dispc_write_reg(vsi_reg[plane-1], val);
 779 }
 780
 781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 782 {
 783         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 784                                      DISPC_VID_PIXEL_INC(0),
 785                                      DISPC_VID_PIXEL_INC(1) };
 786
 787         dispc_write_reg(ri_reg[plane], inc);
 788 }
 789
 790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 791 {
 792         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 793                                      DISPC_VID_ROW_INC(0),
 794                                      DISPC_VID_ROW_INC(1) };
 795
 796         dispc_write_reg(ri_reg[plane], inc);
 797 }
 798
 799 static void _dispc_set_color_mode(enum omap_plane plane,
 800                 enum omap_color_mode color_mode)
 801 {
 802         u32 m = 0;
 803
 804         switch (color_mode) {
 805         case OMAP_DSS_COLOR_CLUT1:
 806                 m = 0x0; break;
 807         case OMAP_DSS_COLOR_CLUT2:
 808                 m = 0x1; break;
 809         case OMAP_DSS_COLOR_CLUT4:
 810                 m = 0x2; break;
 811         case OMAP_DSS_COLOR_CLUT8:
 812                 m = 0x3; break;
 813         case OMAP_DSS_COLOR_RGB12U:
 814                 m = 0x4; break;
 815         case OMAP_DSS_COLOR_ARGB16:
 816                 m = 0x5; break;
 817         case OMAP_DSS_COLOR_RGB16:
 818                 m = 0x6; break;
 819         case OMAP_DSS_COLOR_RGB24U:
 820                 m = 0x8; break;
 821         case OMAP_DSS_COLOR_RGB24P:
 822                 m = 0x9; break;
 823         case OMAP_DSS_COLOR_YUV2:
 824                 m = 0xa; break;
 825         case OMAP_DSS_COLOR_UYVY:
 826                 m = 0xb; break;
 827         case OMAP_DSS_COLOR_ARGB32:
 828                 m = 0xc; break;
 829         case OMAP_DSS_COLOR_RGBA32:
 830                 m = 0xd; break;
 831         case OMAP_DSS_COLOR_RGBX32:
 832                 m = 0xe; break;
 833         default:
 834                 BUG(); break;
 835         }
 836
 837         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 838 }
 839
 840 static void _dispc_set_channel_out(enum omap_plane plane,
 841                 enum omap_channel channel)
 842 {
 843         int shift;
 844         u32 val;
 845
 846         switch (plane) {
 847         case OMAP_DSS_GFX:
 848                 shift = 8;
 849                 break;
 850         case OMAP_DSS_VIDEO1:
 851         case OMAP_DSS_VIDEO2:
 852                 shift = 16;
 853                 break;
 854         default:
 855                 BUG();
 856                 return;
 857         }
 858
 859         val = dispc_read_reg(dispc_reg_att[plane]);
 860         val = FLD_MOD(val, channel, shift, shift);
 861         dispc_write_reg(dispc_reg_att[plane], val);
 862 }
 863
 864 void dispc_set_burst_size(enum omap_plane plane,
 865                 enum omap_burst_size burst_size)
 866 {
 867         int shift;
 868         u32 val;
 869
 870         enable_clocks(1);
 871
 872         switch (plane) {
 873         case OMAP_DSS_GFX:
 874                 shift = 6;
 875                 break;
 876         case OMAP_DSS_VIDEO1:
 877         case OMAP_DSS_VIDEO2:
 878                 shift = 14;
 879                 break;
 880         default:
 881                 BUG();
 882                 return;
 883         }
 884
 885         val = dispc_read_reg(dispc_reg_att[plane]);
 886         val = FLD_MOD(val, burst_size, shift+1, shift);
 887         dispc_write_reg(dispc_reg_att[plane], val);
 888
 889         enable_clocks(0);
 890 }
 891
 892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 893 {
 894         u32 val;
 895
 896         BUG_ON(plane == OMAP_DSS_GFX);
 897
 898         val = dispc_read_reg(dispc_reg_att[plane]);
 899         val = FLD_MOD(val, enable, 9, 9);
 900         dispc_write_reg(dispc_reg_att[plane], val);
 901 }
 902
 903 void dispc_set_lcd_size(u16 width, u16 height)
 904 {
 905         u32 val;
 906         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 907         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 908         enable_clocks(1);
 909         dispc_write_reg(DISPC_SIZE_LCD, val);
 910         enable_clocks(0);
 911 }
 912
 913 void dispc_set_digit_size(u16 width, u16 height)
 914 {
 915         u32 val;
 916         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 917         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 918         enable_clocks(1);
 919         dispc_write_reg(DISPC_SIZE_DIG, val);
 920         enable_clocks(0);
 921 }
 922
 923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 924 {
 925         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 926                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 927                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 928         u32 size;
 929
 930         enable_clocks(1);
 931
 932         if (cpu_is_omap24xx())
 933                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 934         else if (cpu_is_omap34xx())
 935                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 936         else
 937                 BUG();
 938
 939         if (cpu_is_omap34xx()) {
 940                 /* FIFOMERGE */
 941                 if (REG_GET(DISPC_CONFIG, 14, 14))
 942                         size *= 3;
 943         }
 944
 945         enable_clocks(0);
 946
 947         return size;
 948 }
 949
 950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 951 {
 952         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 953                                        DISPC_VID_FIFO_THRESHOLD(0),
 954                                        DISPC_VID_FIFO_THRESHOLD(1) };
 955         u32 size;
 956
 957         enable_clocks(1);
 958
 959         size = dispc_get_plane_fifo_size(plane);
 960
 961         BUG_ON(low > size || high > size);
 962
 963         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
 964                         plane, size,
 965                         REG_GET(ftrs_reg[plane], 11, 0),
 966                         REG_GET(ftrs_reg[plane], 27, 16),
 967                         low, high);
 968
 969         if (cpu_is_omap24xx())
 970                 dispc_write_reg(ftrs_reg[plane],
 971                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
 972         else
 973                 dispc_write_reg(ftrs_reg[plane],
 974                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
 975
 976         enable_clocks(0);
 977 }
 978
 979 void dispc_enable_fifomerge(bool enable)
 980 {
 981         enable_clocks(1);
 982
 983         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
 984         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
 985
 986         enable_clocks(0);
 987 }
 988
 989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
 990 {
 991         u32 val;
 992         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
 993                                       DISPC_VID_FIR(1) };
 994
 995         BUG_ON(plane == OMAP_DSS_GFX);
 996
 997         if (cpu_is_omap24xx())
 998                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
 999         else
1000                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1001         dispc_write_reg(fir_reg[plane-1], val);
1002 }
1003
1004 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1005 {
1006         u32 val;
1007         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1008                                       DISPC_VID_ACCU0(1) };
1009
1010         BUG_ON(plane == OMAP_DSS_GFX);
1011
1012         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1013         dispc_write_reg(ac0_reg[plane-1], val);
1014 }
1015
1016 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1017 {
1018         u32 val;
1019         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1020                                       DISPC_VID_ACCU1(1) };
1021
1022         BUG_ON(plane == OMAP_DSS_GFX);
1023
1024         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1025         dispc_write_reg(ac1_reg[plane-1], val);
1026 }
1027
1028
1029 static void _dispc_set_scaling(enum omap_plane plane,
1030                 u16 orig_width, u16 orig_height,
1031                 u16 out_width, u16 out_height,
1032                 bool ilace, bool five_taps)
1033 {
1034         int fir_hinc;
1035         int fir_vinc;
1036         int hscaleup, vscaleup;
1037         int fieldmode = 0;
1038         int accu0 = 0;
1039         int accu1 = 0;
1040         u32 l;
1041
1042         BUG_ON(plane == OMAP_DSS_GFX);
1043
1044         hscaleup = orig_width <= out_width;
1045         vscaleup = orig_height <= out_height;
1046
1047         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1048
1049         if (!orig_width || orig_width == out_width)
1050                 fir_hinc = 0;
1051         else
1052                 fir_hinc = 1024 * orig_width / out_width;
1053
1054         if (!orig_height || orig_height == out_height)
1055                 fir_vinc = 0;
1056         else
1057                 fir_vinc = 1024 * orig_height / out_height;
1058
1059         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1060
1061         l = dispc_read_reg(dispc_reg_att[plane]);
1062         l &= ~((0x0f << 5) | (0x3 << 21));
1063
1064         l |= fir_hinc ? (1 << 5) : 0;
1065         l |= fir_vinc ? (1 << 6) : 0;
1066
1067         l |= hscaleup ? 0 : (1 << 7);
1068         l |= vscaleup ? 0 : (1 << 8);
1069
1070         l |= five_taps ? (1 << 21) : 0;
1071         l |= five_taps ? (1 << 22) : 0;
1072
1073         dispc_write_reg(dispc_reg_att[plane], l);
1074
1075         if (ilace) {
1076                 if (fieldmode) {
1077                         accu0 = fir_vinc / 2;
1078                         accu1 = 0;
1079                 } else {
1080                         accu0 = 0;
1081                         accu1 = fir_vinc / 2;
1082                         if (accu1 >= 1024/2) {
1083                                 accu0 = 1024/2;
1084                                 accu1 -= accu0;
1085                         }
1086                 }
1087         }
1088
1089         _dispc_set_vid_accu0(plane, 0, accu0);
1090         _dispc_set_vid_accu1(plane, 0, accu1);
1091 }
1092
1093 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1094                 bool mirroring, enum omap_color_mode color_mode)
1095 {
1096         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1097                         color_mode == OMAP_DSS_COLOR_UYVY) {
1098                 int vidrot = 0;
1099
1100                 if (mirroring) {
1101                         switch (rotation) {
1102                         case 0: vidrot = 2; break;
1103                         case 1: vidrot = 3; break;
1104                         case 2: vidrot = 0; break;
1105                         case 3: vidrot = 1; break;
1106                         }
1107                 } else {
1108                         switch (rotation) {
1109                         case 0: vidrot = 0; break;
1110                         case 1: vidrot = 1; break;
1111                         case 2: vidrot = 2; break;
1112                         case 3: vidrot = 3; break;
1113                         }
1114                 }
1115
1116                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1117
1118                 if (rotation == 1 || rotation == 3)
1119                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1120                 else
1121                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1122         } else {
1123                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1124                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1125         }
1126 }
1127
1128 static s32 pixinc(int pixels, u8 ps)
1129 {
1130         if (pixels == 1)
1131                 return 1;
1132         else if (pixels > 1)
1133                 return 1 + (pixels - 1) * ps;
1134         else if (pixels < 0)
1135                 return 1 - (-pixels + 1) * ps;
1136         else
1137                 BUG();
1138 }
1139
1140 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1141                 u16 screen_width,
1142                 u16 width, u16 height,
1143                 enum omap_color_mode color_mode, bool fieldmode,
1144                 unsigned *offset0, unsigned *offset1,
1145                 s32 *row_inc, s32 *pix_inc)
1146 {
1147         u8 ps;
1148
1149         switch (color_mode) {
1150         case OMAP_DSS_COLOR_RGB16:
1151         case OMAP_DSS_COLOR_ARGB16:
1152                 ps = 2;
1153                 break;
1154
1155         case OMAP_DSS_COLOR_RGB24P:
1156                 ps = 3;
1157                 break;
1158
1159         case OMAP_DSS_COLOR_RGB24U:
1160         case OMAP_DSS_COLOR_ARGB32:
1161         case OMAP_DSS_COLOR_RGBA32:
1162         case OMAP_DSS_COLOR_RGBX32:
1163         case OMAP_DSS_COLOR_YUV2:
1164         case OMAP_DSS_COLOR_UYVY:
1165                 ps = 4;
1166                 break;
1167
1168         default:
1169                 BUG();
1170                 return;
1171         }
1172
1173         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1174                         width, height);
1175         switch (rotation + mirror * 4) {
1176         case 0:
1177         case 2:
1178                 /*
1179                  * If the pixel format is YUV or UYVY divide the width
1180                  * of the image by 2 for 0 and 180 degree rotation.
1181                  */
1182                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1183                         color_mode == OMAP_DSS_COLOR_UYVY)
1184                         width = width >> 1;
1185         case 1:
1186         case 3:
1187                 *offset0 = 0;
1188                 if (fieldmode)
1189                         *offset1 = screen_width * ps;
1190                 else
1191                         *offset1 = 0;
1192
1193                 *row_inc = pixinc(1 + (screen_width - width) +
1194                                 (fieldmode ? screen_width : 0),
1195                                 ps);
1196                 *pix_inc = pixinc(1, ps);
1197                 break;
1198
1199         case 4:
1200         case 6:
1201                 /* If the pixel format is YUV or UYVY divide the width
1202                  * of the image by 2  for 0 degree and 180 degree
1203                  */
1204                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1205                         color_mode == OMAP_DSS_COLOR_UYVY)
1206                         width = width >> 1;
1207         case 5:
1208         case 7:
1209                 *offset0 = 0;
1210                 if (fieldmode)
1211                         *offset1 = screen_width * ps;
1212                 else
1213                         *offset1 = 0;
1214                 *row_inc = pixinc(1 - (screen_width + width) -
1215                                 (fieldmode ? screen_width : 0),
1216                                 ps);
1217                 *pix_inc = pixinc(1, ps);
1218                 break;
1219
1220         default:
1221                 BUG();
1222         }
1223 }
1224
1225 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1226                 u16 screen_width,
1227                 u16 width, u16 height,
1228                 enum omap_color_mode color_mode, bool fieldmode,
1229                 unsigned *offset0, unsigned *offset1,
1230                 s32 *row_inc, s32 *pix_inc)
1231 {
1232         u8 ps;
1233         u16 fbw, fbh;
1234
1235         switch (color_mode) {
1236         case OMAP_DSS_COLOR_RGB16:
1237         case OMAP_DSS_COLOR_ARGB16:
1238                 ps = 2;
1239                 break;
1240
1241         case OMAP_DSS_COLOR_RGB24P:
1242                 ps = 3;
1243                 break;
1244
1245         case OMAP_DSS_COLOR_RGB24U:
1246         case OMAP_DSS_COLOR_ARGB32:
1247         case OMAP_DSS_COLOR_RGBA32:
1248         case OMAP_DSS_COLOR_RGBX32:
1249                 ps = 4;
1250                 break;
1251
1252         case OMAP_DSS_COLOR_YUV2:
1253         case OMAP_DSS_COLOR_UYVY:
1254                 ps = 2;
1255                 break;
1256         default:
1257                 BUG();
1258                 return;
1259         }
1260
1261         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1262                         width, height);
1263
1264         /* width & height are overlay sizes, convert to fb sizes */
1265
1266         if (rotation == 0 || rotation == 2) {
1267                 fbw = width;
1268                 fbh = height;
1269         } else {
1270                 fbw = height;
1271                 fbh = width;
1272         }
1273
1274         switch (rotation + mirror * 4) {
1275         case 0:
1276                 *offset0 = 0;
1277                 if (fieldmode)
1278                         *offset1 = screen_width * ps;
1279                 else
1280                         *offset1 = 0;
1281                 *row_inc = pixinc(1 + (screen_width - fbw) +
1282                                 (fieldmode ? screen_width : 0),
1283                                 ps);
1284                 *pix_inc = pixinc(1, ps);
1285                 break;
1286         case 1:
1287                 *offset0 = screen_width * (fbh - 1) * ps;
1288                 if (fieldmode)
1289                         *offset1 = *offset0 + ps;
1290                 else
1291                         *offset1 = *offset0;
1292                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1293                                 (fieldmode ? 1 : 0), ps);
1294                 *pix_inc = pixinc(-screen_width, ps);
1295                 break;
1296         case 2:
1297                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1298                 if (fieldmode)
1299                         *offset1 = *offset0 - screen_width * ps;
1300                 else
1301                         *offset1 = *offset0;
1302                 *row_inc = pixinc(-1 -
1303                                 (screen_width - fbw) -
1304                                 (fieldmode ? screen_width : 0),
1305                                 ps);
1306                 *pix_inc = pixinc(-1, ps);
1307                 break;
1308         case 3:
1309                 *offset0 = (fbw - 1) * ps;
1310                 if (fieldmode)
1311                         *offset1 = *offset0 - ps;
1312                 else
1313                         *offset1 = *offset0;
1314                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1315                                 (fieldmode ? 1 : 0), ps);
1316                 *pix_inc = pixinc(screen_width, ps);
1317                 break;
1318
1319         /* mirroring */
1320         case 0 + 4:
1321                 *offset0 = (fbw - 1) * ps;
1322                 if (fieldmode)
1323                         *offset1 = *offset0 + screen_width * ps;
1324                 else
1325                         *offset1 = *offset0;
1326                 *row_inc = pixinc(screen_width * 2 - 1 +
1327                                 (fieldmode ? screen_width : 0),
1328                                 ps);
1329                 *pix_inc = pixinc(-1, ps);
1330                 break;
1331
1332         case 1 + 4:
1333                 *offset0 = 0;
1334                 if (fieldmode)
1335                         *offset1 = *offset0 + screen_width * ps;
1336                 else
1337                         *offset1 = *offset0;
1338                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1339                                 (fieldmode ? 1 : 0),
1340                                 ps);
1341                 *pix_inc = pixinc(screen_width, ps);
1342                 break;
1343
1344         case 2 + 4:
1345                 *offset0 = screen_width * (fbh - 1) * ps;
1346                 if (fieldmode)
1347                         *offset1 = *offset0 + screen_width * ps;
1348                 else
1349                         *offset1 = *offset0;
1350                 *row_inc = pixinc(1 - screen_width * 2 -
1351                                 (fieldmode ? screen_width : 0),
1352                                 ps);
1353                 *pix_inc = pixinc(1, ps);
1354                 break;
1355
1356         case 3 + 4:
1357                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1358                 if (fieldmode)
1359                         *offset1 = *offset0 + screen_width * ps;
1360                 else
1361                         *offset1 = *offset0;
1362                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1363                                 (fieldmode ? 1 : 0),
1364                                 ps);
1365                 *pix_inc = pixinc(-screen_width, ps);
1366                 break;
1367
1368         default:
1369                 BUG();
1370         }
1371 }
1372
1373 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1374                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1375 {
1376         u32 fclk = 0;
1377         /* FIXME venc pclk? */
1378         u64 tmp, pclk = dispc_pclk_rate();
1379
1380         if (height > out_height) {
1381                 /* FIXME get real display PPL */
1382                 unsigned int ppl = 800;
1383
1384                 tmp = pclk * height * out_width;
1385                 do_div(tmp, 2 * out_height * ppl);
1386                 fclk = tmp;
1387
1388                 if (height > 2 * out_height) {
1389                         tmp = pclk * (height - 2 * out_height) * out_width;
1390                         do_div(tmp, 2 * out_height * (ppl - out_width));
1391                         fclk = max(fclk, (u32) tmp);
1392                 }
1393         }
1394
1395         if (width > out_width) {
1396                 tmp = pclk * width;
1397                 do_div(tmp, out_width);
1398                 fclk = max(fclk, (u32) tmp);
1399
1400                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1401                         fclk <<= 1;
1402         }
1403
1404         return fclk;
1405 }
1406
1407 static unsigned long calc_fclk(u16 width, u16 height,
1408                 u16 out_width, u16 out_height)
1409 {
1410         unsigned int hf, vf;
1411
1412         /*
1413          * FIXME how to determine the 'A' factor
1414          * for the no downscaling case ?
1415          */
1416
1417         if (width > 3 * out_width)
1418                 hf = 4;
1419         else if (width > 2 * out_width)
1420                 hf = 3;
1421         else if (width > out_width)
1422                 hf = 2;
1423         else
1424                 hf = 1;
1425
1426         if (height > out_height)
1427                 vf = 2;
1428         else
1429                 vf = 1;
1430
1431         /* FIXME venc pclk? */
1432         return dispc_pclk_rate() * vf * hf;
1433 }
1434
1435 static int _dispc_setup_plane(enum omap_plane plane,
1436                 enum omap_channel channel_out,
1437                 u32 paddr, u16 screen_width,
1438                 u16 pos_x, u16 pos_y,
1439                 u16 width, u16 height,
1440                 u16 out_width, u16 out_height,
1441                 enum omap_color_mode color_mode,
1442                 bool ilace,
1443                 enum omap_dss_rotation_type rotation_type,
1444                 u8 rotation, int mirror)
1445 {
1446         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1447         bool five_taps = 0;
1448         bool fieldmode = 0;
1449         int cconv = 0;
1450         unsigned offset0, offset1;
1451         s32 row_inc;
1452         s32 pix_inc;
1453         u16 frame_height = height;
1454
1455         if (paddr == 0)
1456                 return -EINVAL;
1457
1458         if (ilace && height >= out_height)
1459                 fieldmode = 1;
1460
1461         if (ilace) {
1462                 if (fieldmode)
1463                         height /= 2;
1464                 pos_y /= 2;
1465                 out_height /= 2;
1466
1467                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1468                                 "out_height %d\n",
1469                                 height, pos_y, out_height);
1470         }
1471
1472         if (plane == OMAP_DSS_GFX) {
1473                 if (width != out_width || height != out_height)
1474                         return -EINVAL;
1475
1476                 switch (color_mode) {
1477                 case OMAP_DSS_COLOR_ARGB16:
1478                 case OMAP_DSS_COLOR_RGB16:
1479                 case OMAP_DSS_COLOR_RGB24P:
1480                 case OMAP_DSS_COLOR_RGB24U:
1481                 case OMAP_DSS_COLOR_ARGB32:
1482                 case OMAP_DSS_COLOR_RGBA32:
1483                 case OMAP_DSS_COLOR_RGBX32:
1484                         break;
1485
1486                 default:
1487                         return -EINVAL;
1488                 }
1489         } else {
1490                 /* video plane */
1491
1492                 unsigned long fclk = 0;
1493
1494                 if (out_width < width / maxdownscale ||
1495                    out_width > width * 8)
1496                         return -EINVAL;
1497
1498                 if (out_height < height / maxdownscale ||
1499                    out_height > height * 8)
1500                         return -EINVAL;
1501
1502                 switch (color_mode) {
1503                 case OMAP_DSS_COLOR_RGB16:
1504                 case OMAP_DSS_COLOR_RGB24P:
1505                 case OMAP_DSS_COLOR_RGB24U:
1506                 case OMAP_DSS_COLOR_RGBX32:
1507                         break;
1508
1509                 case OMAP_DSS_COLOR_ARGB16:
1510                 case OMAP_DSS_COLOR_ARGB32:
1511                 case OMAP_DSS_COLOR_RGBA32:
1512                         if (plane == OMAP_DSS_VIDEO1)
1513                                 return -EINVAL;
1514                         break;
1515
1516                 case OMAP_DSS_COLOR_YUV2:
1517                 case OMAP_DSS_COLOR_UYVY:
1518                         cconv = 1;
1519                         break;
1520
1521                 default:
1522                         return -EINVAL;
1523                 }
1524
1525                 /* Must use 5-tap filter? */
1526                 five_taps = height > out_height * 2;
1527
1528                 if (!five_taps) {
1529                         fclk = calc_fclk(width, height,
1530                                         out_width, out_height);
1531
1532                         /* Try 5-tap filter if 3-tap fclk is too high */
1533                         if (cpu_is_omap34xx() && height > out_height &&
1534                                         fclk > dispc_fclk_rate())
1535                                 five_taps = true;
1536                 }
1537
1538                 if (width > (2048 >> five_taps))
1539                         return -EINVAL;
1540
1541                 if (five_taps)
1542                         fclk = calc_fclk_five_taps(width, height,
1543                                         out_width, out_height, color_mode);
1544
1545                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1546                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1547
1548                 if (fclk > dispc_fclk_rate())
1549                         return -EINVAL;
1550         }
1551
1552         if (rotation_type == OMAP_DSS_ROT_DMA)
1553                 calc_dma_rotation_offset(rotation, mirror,
1554                                 screen_width, width, frame_height, color_mode,
1555                                 fieldmode,
1556                                 &offset0, &offset1, &row_inc, &pix_inc);
1557         else
1558                 calc_vrfb_rotation_offset(rotation, mirror,
1559                                 screen_width, width, frame_height, color_mode,
1560                                 fieldmode,
1561                                 &offset0, &offset1, &row_inc, &pix_inc);
1562
1563         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1564                         offset0, offset1, row_inc, pix_inc);
1565
1566         _dispc_set_channel_out(plane, channel_out);
1567         _dispc_set_color_mode(plane, color_mode);
1568
1569         _dispc_set_plane_ba0(plane, paddr + offset0);
1570         _dispc_set_plane_ba1(plane, paddr + offset1);
1571
1572         _dispc_set_row_inc(plane, row_inc);
1573         _dispc_set_pix_inc(plane, pix_inc);
1574
1575         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1576                         out_width, out_height);
1577
1578         _dispc_set_plane_pos(plane, pos_x, pos_y);
1579
1580         _dispc_set_pic_size(plane, width, height);
1581
1582         if (plane != OMAP_DSS_GFX) {
1583                 _dispc_set_scaling(plane, width, height,
1584                                    out_width, out_height,
1585                                    ilace, five_taps);
1586                 _dispc_set_vid_size(plane, out_width, out_height);
1587                 _dispc_set_vid_color_conv(plane, cconv);
1588         }
1589
1590         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1591
1592         return 0;
1593 }
1594
1595 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1596 {
1597         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1598 }
1599
1600 static void dispc_disable_isr(void *data, u32 mask)
1601 {
1602         struct completion *compl = data;
1603         complete(compl);
1604 }
1605
1606 static void _enable_lcd_out(bool enable)
1607 {
1608         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1609 }
1610
1611 void dispc_enable_lcd_out(bool enable)
1612 {
1613         struct completion frame_done_completion;
1614         bool is_on;
1615         int r;
1616
1617         enable_clocks(1);
1618
1619         /* When we disable LCD output, we need to wait until frame is done.
1620          * Otherwise the DSS is still working, and turning off the clocks
1621          * prevents DSS from going to OFF mode */
1622         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1623
1624         if (!enable && is_on) {
1625                 init_completion(&frame_done_completion);
1626
1627                 r = omap_dispc_register_isr(dispc_disable_isr,
1628                                 &frame_done_completion,
1629                                 DISPC_IRQ_FRAMEDONE);
1630
1631                 if (r)
1632                         DSSERR("failed to register FRAMEDONE isr\n");
1633         }
1634
1635         _enable_lcd_out(enable);
1636
1637         if (!enable && is_on) {
1638                 if (!wait_for_completion_timeout(&frame_done_completion,
1639                                         msecs_to_jiffies(100)))
1640                         DSSERR("timeout waiting for FRAME DONE\n");
1641
1642                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1643                                 &frame_done_completion,
1644                                 DISPC_IRQ_FRAMEDONE);
1645
1646                 if (r)
1647                         DSSERR("failed to unregister FRAMEDONE isr\n");
1648         }
1649
1650         enable_clocks(0);
1651 }
1652
1653 static void _enable_digit_out(bool enable)
1654 {
1655         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1656 }
1657
1658 void dispc_enable_digit_out(bool enable)
1659 {
1660         struct completion frame_done_completion;
1661         int r;
1662
1663         enable_clocks(1);
1664
1665         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1666                 enable_clocks(0);
1667                 return;
1668         }
1669
1670         if (enable) {
1671                 /* When we enable digit output, we'll get an extra digit
1672                  * sync lost interrupt, that we need to ignore */
1673                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1674                 omap_dispc_set_irqs();
1675         }
1676
1677         /* When we disable digit output, we need to wait until fields are done.
1678          * Otherwise the DSS is still working, and turning off the clocks
1679          * prevents DSS from going to OFF mode. And when enabling, we need to
1680          * wait for the extra sync losts */
1681         init_completion(&frame_done_completion);
1682
1683         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1684                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1685         if (r)
1686                 DSSERR("failed to register EVSYNC isr\n");
1687
1688         _enable_digit_out(enable);
1689
1690         /* XXX I understand from TRM that we should only wait for the
1691          * current field to complete. But it seems we have to wait
1692          * for both fields */
1693         if (!wait_for_completion_timeout(&frame_done_completion,
1694                                 msecs_to_jiffies(100)))
1695                 DSSERR("timeout waiting for EVSYNC\n");
1696
1697         if (!wait_for_completion_timeout(&frame_done_completion,
1698                                 msecs_to_jiffies(100)))
1699                 DSSERR("timeout waiting for EVSYNC\n");
1700
1701         r = omap_dispc_unregister_isr(dispc_disable_isr,
1702                         &frame_done_completion,
1703                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1704         if (r)
1705                 DSSERR("failed to unregister EVSYNC isr\n");
1706
1707         if (enable) {
1708                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1709                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1710                 omap_dispc_set_irqs();
1711         }
1712
1713         enable_clocks(0);
1714 }
1715
1716 void dispc_lcd_enable_signal_polarity(bool act_high)
1717 {
1718         enable_clocks(1);
1719         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1720         enable_clocks(0);
1721 }
1722
1723 void dispc_lcd_enable_signal(bool enable)
1724 {
1725         enable_clocks(1);
1726         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1727         enable_clocks(0);
1728 }
1729
1730 void dispc_pck_free_enable(bool enable)
1731 {
1732         enable_clocks(1);
1733         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1734         enable_clocks(0);
1735 }
1736
1737 void dispc_enable_fifohandcheck(bool enable)
1738 {
1739         enable_clocks(1);
1740         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1741         enable_clocks(0);
1742 }
1743
1744
1745 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1746 {
1747         int mode;
1748
1749         switch (type) {
1750         case OMAP_DSS_LCD_DISPLAY_STN:
1751                 mode = 0;
1752                 break;
1753
1754         case OMAP_DSS_LCD_DISPLAY_TFT:
1755                 mode = 1;
1756                 break;
1757
1758         default:
1759                 BUG();
1760                 return;
1761         }
1762
1763         enable_clocks(1);
1764         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1765         enable_clocks(0);
1766 }
1767
1768 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1769 {
1770         enable_clocks(1);
1771         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1772         enable_clocks(0);
1773 }
1774
1775
1776 void dispc_set_default_color(enum omap_channel channel, u32 color)
1777 {
1778         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1779                                 DISPC_DEFAULT_COLOR1 };
1780
1781         enable_clocks(1);
1782         dispc_write_reg(def_reg[channel], color);
1783         enable_clocks(0);
1784 }
1785
1786 u32 dispc_get_default_color(enum omap_channel channel)
1787 {
1788         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1789                                 DISPC_DEFAULT_COLOR1 };
1790         u32 l;
1791
1792         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1793                channel != OMAP_DSS_CHANNEL_LCD);
1794
1795         enable_clocks(1);
1796         l = dispc_read_reg(def_reg[channel]);
1797         enable_clocks(0);
1798
1799         return l;
1800 }
1801
1802 void dispc_set_trans_key(enum omap_channel ch,
1803                 enum omap_dss_color_key_type type,
1804                 u32 trans_key)
1805 {
1806         const struct dispc_reg tr_reg[] = {
1807                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1808
1809         enable_clocks(1);
1810         if (ch == OMAP_DSS_CHANNEL_LCD)
1811                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1812         else /* OMAP_DSS_CHANNEL_DIGIT */
1813                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1814
1815         dispc_write_reg(tr_reg[ch], trans_key);
1816         enable_clocks(0);
1817 }
1818
1819 void dispc_get_trans_key(enum omap_channel ch,
1820                 enum omap_dss_color_key_type *type,
1821                 u32 *trans_key)
1822 {
1823         const struct dispc_reg tr_reg[] = {
1824                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1825
1826         enable_clocks(1);
1827         if (type) {
1828                 if (ch == OMAP_DSS_CHANNEL_LCD)
1829                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1830                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1831                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1832                 else
1833                         BUG();
1834         }
1835
1836         if (trans_key)
1837                 *trans_key = dispc_read_reg(tr_reg[ch]);
1838         enable_clocks(0);
1839 }
1840
1841 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1842 {
1843         enable_clocks(1);
1844         if (ch == OMAP_DSS_CHANNEL_LCD)
1845                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1846         else /* OMAP_DSS_CHANNEL_DIGIT */
1847                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1848         enable_clocks(0);
1849 }
1850
1851 bool dispc_trans_key_enabled(enum omap_channel ch)
1852 {
1853         bool enabled;
1854
1855         enable_clocks(1);
1856         if (ch == OMAP_DSS_CHANNEL_LCD)
1857                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1858         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1859                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1860         else BUG();
1861         enable_clocks(0);
1862
1863         return enabled;
1864 }
1865
1866
1867 void dispc_set_tft_data_lines(u8 data_lines)
1868 {
1869         int code;
1870
1871         switch (data_lines) {
1872         case 12:
1873                 code = 0;
1874                 break;
1875         case 16:
1876                 code = 1;
1877                 break;
1878         case 18:
1879                 code = 2;
1880                 break;
1881         case 24:
1882                 code = 3;
1883                 break;
1884         default:
1885                 BUG();
1886                 return;
1887         }
1888
1889         enable_clocks(1);
1890         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1891         enable_clocks(0);
1892 }
1893
1894 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1895 {
1896         u32 l;
1897         int stallmode;
1898         int gpout0 = 1;
1899         int gpout1;
1900
1901         switch (mode) {
1902         case OMAP_DSS_PARALLELMODE_BYPASS:
1903                 stallmode = 0;
1904                 gpout1 = 1;
1905                 break;
1906
1907         case OMAP_DSS_PARALLELMODE_RFBI:
1908                 stallmode = 1;
1909                 gpout1 = 0;
1910                 break;
1911
1912         case OMAP_DSS_PARALLELMODE_DSI:
1913                 stallmode = 1;
1914                 gpout1 = 1;
1915                 break;
1916
1917         default:
1918                 BUG();
1919                 return;
1920         }
1921
1922         enable_clocks(1);
1923
1924         l = dispc_read_reg(DISPC_CONTROL);
1925
1926         l = FLD_MOD(l, stallmode, 11, 11);
1927         l = FLD_MOD(l, gpout0, 15, 15);
1928         l = FLD_MOD(l, gpout1, 16, 16);
1929
1930         dispc_write_reg(DISPC_CONTROL, l);
1931
1932         enable_clocks(0);
1933 }
1934
1935 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1936                                    int vsw, int vfp, int vbp)
1937 {
1938         u32 timing_h, timing_v;
1939
1940         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1941                 BUG_ON(hsw < 1 || hsw > 64);
1942                 BUG_ON(hfp < 1 || hfp > 256);
1943                 BUG_ON(hbp < 1 || hbp > 256);
1944
1945                 BUG_ON(vsw < 1 || vsw > 64);
1946                 BUG_ON(vfp < 0 || vfp > 255);
1947                 BUG_ON(vbp < 0 || vbp > 255);
1948
1949                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1950                         FLD_VAL(hbp-1, 27, 20);
1951
1952                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1953                         FLD_VAL(vbp, 27, 20);
1954         } else {
1955                 BUG_ON(hsw < 1 || hsw > 256);
1956                 BUG_ON(hfp < 1 || hfp > 4096);
1957                 BUG_ON(hbp < 1 || hbp > 4096);
1958
1959                 BUG_ON(vsw < 1 || vsw > 256);
1960                 BUG_ON(vfp < 0 || vfp > 4095);
1961                 BUG_ON(vbp < 0 || vbp > 4095);
1962
1963                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1964                         FLD_VAL(hbp-1, 31, 20);
1965
1966                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1967                         FLD_VAL(vbp, 31, 20);
1968         }
1969
1970         enable_clocks(1);
1971         dispc_write_reg(DISPC_TIMING_H, timing_h);
1972         dispc_write_reg(DISPC_TIMING_V, timing_v);
1973         enable_clocks(0);
1974 }
1975
1976 /* change name to mode? */
1977 void dispc_set_lcd_timings(struct omap_video_timings *timings)
1978 {
1979         unsigned xtot, ytot;
1980         unsigned long ht, vt;
1981
1982         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
1983                         timings->vsw, timings->vfp, timings->vbp);
1984
1985         dispc_set_lcd_size(timings->x_res, timings->y_res);
1986
1987         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
1988         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
1989
1990         ht = (timings->pixel_clock * 1000) / xtot;
1991         vt = (timings->pixel_clock * 1000) / xtot / ytot;
1992
1993         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
1994         DSSDBG("pck %u\n", timings->pixel_clock);
1995         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
1996                         timings->hsw, timings->hfp, timings->hbp,
1997                         timings->vsw, timings->vfp, timings->vbp);
1998
1999         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2000 }
2001
2002 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2003 {
2004         BUG_ON(lck_div < 1);
2005         BUG_ON(pck_div < 2);
2006
2007         enable_clocks(1);
2008         dispc_write_reg(DISPC_DIVISOR,
2009                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2010         enable_clocks(0);
2011 }
2012
2013 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2014 {
2015         u32 l;
2016         l = dispc_read_reg(DISPC_DIVISOR);
2017         *lck_div = FLD_GET(l, 23, 16);
2018         *pck_div = FLD_GET(l, 7, 0);
2019 }
2020
2021 unsigned long dispc_fclk_rate(void)
2022 {
2023         unsigned long r = 0;
2024
2025         if (dss_get_dispc_clk_source() == 0)
2026                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2027         else
2028 #ifdef CONFIG_OMAP2_DSS_DSI
2029                 r = dsi_get_dsi1_pll_rate();
2030 #else
2031         BUG();
2032 #endif
2033         return r;
2034 }
2035
2036 unsigned long dispc_lclk_rate(void)
2037 {
2038         int lcd;
2039         unsigned long r;
2040         u32 l;
2041
2042         l = dispc_read_reg(DISPC_DIVISOR);
2043
2044         lcd = FLD_GET(l, 23, 16);
2045
2046         r = dispc_fclk_rate();
2047
2048         return r / lcd;
2049 }
2050
2051 unsigned long dispc_pclk_rate(void)
2052 {
2053         int lcd, pcd;
2054         unsigned long r;
2055         u32 l;
2056
2057         l = dispc_read_reg(DISPC_DIVISOR);
2058
2059         lcd = FLD_GET(l, 23, 16);
2060         pcd = FLD_GET(l, 7, 0);
2061
2062         r = dispc_fclk_rate();
2063
2064         return r / lcd / pcd;
2065 }
2066
2067 void dispc_dump_clocks(struct seq_file *s)
2068 {
2069         int lcd, pcd;
2070
2071         enable_clocks(1);
2072
2073         dispc_get_lcd_divisor(&lcd, &pcd);
2074
2075         seq_printf(s, "- dispc -\n");
2076
2077         seq_printf(s, "dispc fclk source = %s\n",
2078                         dss_get_dispc_clk_source() == 0 ?
2079                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2080
2081         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
2082                         dispc_fclk_rate(),
2083                         lcd, pcd,
2084                         dispc_pclk_rate());
2085
2086         enable_clocks(0);
2087 }
2088
2089 void dispc_dump_regs(struct seq_file *s)
2090 {
2091 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2092
2093         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2094
2095         DUMPREG(DISPC_REVISION);
2096         DUMPREG(DISPC_SYSCONFIG);
2097         DUMPREG(DISPC_SYSSTATUS);
2098         DUMPREG(DISPC_IRQSTATUS);
2099         DUMPREG(DISPC_IRQENABLE);
2100         DUMPREG(DISPC_CONTROL);
2101         DUMPREG(DISPC_CONFIG);
2102         DUMPREG(DISPC_CAPABLE);
2103         DUMPREG(DISPC_DEFAULT_COLOR0);
2104         DUMPREG(DISPC_DEFAULT_COLOR1);
2105         DUMPREG(DISPC_TRANS_COLOR0);
2106         DUMPREG(DISPC_TRANS_COLOR1);
2107         DUMPREG(DISPC_LINE_STATUS);
2108         DUMPREG(DISPC_LINE_NUMBER);
2109         DUMPREG(DISPC_TIMING_H);
2110         DUMPREG(DISPC_TIMING_V);
2111         DUMPREG(DISPC_POL_FREQ);
2112         DUMPREG(DISPC_DIVISOR);
2113         DUMPREG(DISPC_GLOBAL_ALPHA);
2114         DUMPREG(DISPC_SIZE_DIG);
2115         DUMPREG(DISPC_SIZE_LCD);
2116
2117         DUMPREG(DISPC_GFX_BA0);
2118         DUMPREG(DISPC_GFX_BA1);
2119         DUMPREG(DISPC_GFX_POSITION);
2120         DUMPREG(DISPC_GFX_SIZE);
2121         DUMPREG(DISPC_GFX_ATTRIBUTES);
2122         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2123         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2124         DUMPREG(DISPC_GFX_ROW_INC);
2125         DUMPREG(DISPC_GFX_PIXEL_INC);
2126         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2127         DUMPREG(DISPC_GFX_TABLE_BA);
2128
2129         DUMPREG(DISPC_DATA_CYCLE1);
2130         DUMPREG(DISPC_DATA_CYCLE2);
2131         DUMPREG(DISPC_DATA_CYCLE3);
2132
2133         DUMPREG(DISPC_CPR_COEF_R);
2134         DUMPREG(DISPC_CPR_COEF_G);
2135         DUMPREG(DISPC_CPR_COEF_B);
2136
2137         DUMPREG(DISPC_GFX_PRELOAD);
2138
2139         DUMPREG(DISPC_VID_BA0(0));
2140         DUMPREG(DISPC_VID_BA1(0));
2141         DUMPREG(DISPC_VID_POSITION(0));
2142         DUMPREG(DISPC_VID_SIZE(0));
2143         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2144         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2145         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2146         DUMPREG(DISPC_VID_ROW_INC(0));
2147         DUMPREG(DISPC_VID_PIXEL_INC(0));
2148         DUMPREG(DISPC_VID_FIR(0));
2149         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2150         DUMPREG(DISPC_VID_ACCU0(0));
2151         DUMPREG(DISPC_VID_ACCU1(0));
2152
2153         DUMPREG(DISPC_VID_BA0(1));
2154         DUMPREG(DISPC_VID_BA1(1));
2155         DUMPREG(DISPC_VID_POSITION(1));
2156         DUMPREG(DISPC_VID_SIZE(1));
2157         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2158         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2159         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2160         DUMPREG(DISPC_VID_ROW_INC(1));
2161         DUMPREG(DISPC_VID_PIXEL_INC(1));
2162         DUMPREG(DISPC_VID_FIR(1));
2163         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2164         DUMPREG(DISPC_VID_ACCU0(1));
2165         DUMPREG(DISPC_VID_ACCU1(1));
2166
2167         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2168         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2169         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2170         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2171         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2172         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2173         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2174         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2175         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2176         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2177         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2178         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2179         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2180         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2181         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2182         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2183         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2184         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2185         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2186         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2187         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2188         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2189         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2190         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2191         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2192         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2193         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2194         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2195         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2196
2197         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2198         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2199         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2200         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2201         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2202         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2203         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2204         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2205         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2206         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2207         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2208         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2209         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2210         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2211         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2212         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2213         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2214         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2215         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2216         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2217         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2218         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2219         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2220         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2221         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2222         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2223         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2224         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2225         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2226
2227         DUMPREG(DISPC_VID_PRELOAD(0));
2228         DUMPREG(DISPC_VID_PRELOAD(1));
2229
2230         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2231 #undef DUMPREG
2232 }
2233
2234 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2235                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2236 {
2237         u32 l = 0;
2238
2239         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2240                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2241
2242         l |= FLD_VAL(onoff, 17, 17);
2243         l |= FLD_VAL(rf, 16, 16);
2244         l |= FLD_VAL(ieo, 15, 15);
2245         l |= FLD_VAL(ipc, 14, 14);
2246         l |= FLD_VAL(ihs, 13, 13);
2247         l |= FLD_VAL(ivs, 12, 12);
2248         l |= FLD_VAL(acbi, 11, 8);
2249         l |= FLD_VAL(acb, 7, 0);
2250
2251         enable_clocks(1);
2252         dispc_write_reg(DISPC_POL_FREQ, l);
2253         enable_clocks(0);
2254 }
2255
2256 void dispc_set_pol_freq(struct omap_panel *panel)
2257 {
2258         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2259                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2260                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2261                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2262                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2263                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2264                                  panel->acbi, panel->acb);
2265 }
2266
2267 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2268                 u16 *lck_div, u16 *pck_div)
2269 {
2270         u16 pcd_min = is_tft ? 2 : 3;
2271         unsigned long best_pck;
2272         u16 best_ld, cur_ld;
2273         u16 best_pd, cur_pd;
2274
2275         best_pck = 0;
2276         best_ld = 0;
2277         best_pd = 0;
2278
2279         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2280                 unsigned long lck = fck / cur_ld;
2281
2282                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2283                         unsigned long pck = lck / cur_pd;
2284                         long old_delta = abs(best_pck - req_pck);
2285                         long new_delta = abs(pck - req_pck);
2286
2287                         if (best_pck == 0 || new_delta < old_delta) {
2288                                 best_pck = pck;
2289                                 best_ld = cur_ld;
2290                                 best_pd = cur_pd;
2291
2292                                 if (pck == req_pck)
2293                                         goto found;
2294                         }
2295
2296                         if (pck < req_pck)
2297                                 break;
2298                 }
2299
2300                 if (lck / pcd_min < req_pck)
2301                         break;
2302         }
2303
2304 found:
2305         *lck_div = best_ld;
2306         *pck_div = best_pd;
2307 }
2308
2309 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2310                 struct dispc_clock_info *cinfo)
2311 {
2312         unsigned long prate;
2313         struct dispc_clock_info cur, best;
2314         int match = 0;
2315         int min_fck_per_pck;
2316         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2317
2318         if (cpu_is_omap34xx())
2319                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2320         else
2321                 prate = 0;
2322
2323         if (req_pck == dispc.cache_req_pck &&
2324                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2325                          dispc.cache_cinfo.fck == fck_rate)) {
2326                 DSSDBG("dispc clock info found from cache.\n");
2327                 *cinfo = dispc.cache_cinfo;
2328                 return 0;
2329         }
2330
2331         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2332
2333         if (min_fck_per_pck &&
2334                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2335                 DSSERR("Requested pixel clock not possible with the current "
2336                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2337                                 "the constraint off.\n");
2338                 min_fck_per_pck = 0;
2339         }
2340
2341 retry:
2342         memset(&cur, 0, sizeof(cur));
2343         memset(&best, 0, sizeof(best));
2344
2345         if (cpu_is_omap24xx()) {
2346                 /* XXX can we change the clock on omap2? */
2347                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2348                 cur.fck_div = 1;
2349
2350                 match = 1;
2351
2352                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2353                                 &cur.lck_div, &cur.pck_div);
2354
2355                 cur.lck = cur.fck / cur.lck_div;
2356                 cur.pck = cur.lck / cur.pck_div;
2357
2358                 best = cur;
2359
2360                 goto found;
2361         } else if (cpu_is_omap34xx()) {
2362                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2363                         cur.fck = prate / cur.fck_div * 2;
2364
2365                         if (cur.fck > DISPC_MAX_FCK)
2366                                 continue;
2367
2368                         if (min_fck_per_pck &&
2369                                         cur.fck < req_pck * min_fck_per_pck)
2370                                 continue;
2371
2372                         match = 1;
2373
2374                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2375                                         &cur.lck_div, &cur.pck_div);
2376
2377                         cur.lck = cur.fck / cur.lck_div;
2378                         cur.pck = cur.lck / cur.pck_div;
2379
2380                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2381                                 best = cur;
2382
2383                                 if (cur.pck == req_pck)
2384                                         goto found;
2385                         }
2386                 }
2387         } else {
2388                 BUG();
2389         }
2390
2391 found:
2392         if (!match) {
2393                 if (min_fck_per_pck) {
2394                         DSSERR("Could not find suitable clock settings.\n"
2395                                         "Turning FCK/PCK constraint off and"
2396                                         "trying again.\n");
2397                         min_fck_per_pck = 0;
2398                         goto retry;
2399                 }
2400
2401                 DSSERR("Could not find suitable clock settings.\n");
2402
2403                 return -EINVAL;
2404         }
2405
2406         if (cinfo)
2407                 *cinfo = best;
2408
2409         dispc.cache_req_pck = req_pck;
2410         dispc.cache_prate = prate;
2411         dispc.cache_cinfo = best;
2412
2413         return 0;
2414 }
2415
2416 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2417 {
2418         unsigned long prate;
2419         int r;
2420
2421         if (cpu_is_omap34xx()) {
2422                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2423                 DSSDBG("dpll4_m4 = %ld\n", prate);
2424         }
2425
2426         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2427         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2428         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2429
2430         if (cpu_is_omap34xx()) {
2431                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2432                 if (r)
2433                         return r;
2434         }
2435
2436         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2437
2438         return 0;
2439 }
2440
2441 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2442 {
2443         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2444
2445         if (cpu_is_omap34xx()) {
2446                 unsigned long prate;
2447                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2448                 cinfo->fck_div = prate / (cinfo->fck / 2);
2449         } else {
2450                 cinfo->fck_div = 0;
2451         }
2452
2453         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2454         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2455
2456         cinfo->lck = cinfo->fck / cinfo->lck_div;
2457         cinfo->pck = cinfo->lck / cinfo->pck_div;
2458
2459         return 0;
2460 }
2461
2462 static void omap_dispc_set_irqs(void)
2463 {
2464         unsigned long flags;
2465         u32 mask = dispc.irq_error_mask;
2466         int i;
2467         struct omap_dispc_isr_data *isr_data;
2468
2469         spin_lock_irqsave(&dispc.irq_lock, flags);
2470
2471         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2472                 isr_data = &dispc.registered_isr[i];
2473
2474                 if (isr_data->isr == NULL)
2475                         continue;
2476
2477                 mask |= isr_data->mask;
2478         }
2479
2480         enable_clocks(1);
2481         dispc_write_reg(DISPC_IRQENABLE, mask);
2482         enable_clocks(0);
2483
2484         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2485 }
2486
2487 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2488 {
2489         int i;
2490         int ret;
2491         unsigned long flags;
2492         struct omap_dispc_isr_data *isr_data;
2493
2494         if (isr == NULL)
2495                 return -EINVAL;
2496
2497         spin_lock_irqsave(&dispc.irq_lock, flags);
2498
2499         /* check for duplicate entry */
2500         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2501                 isr_data = &dispc.registered_isr[i];
2502                 if (isr_data->isr == isr && isr_data->arg == arg &&
2503                                 isr_data->mask == mask) {
2504                         ret = -EINVAL;
2505                         goto err;
2506                 }
2507         }
2508
2509         isr_data = NULL;
2510         ret = -EBUSY;
2511
2512         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2513                 isr_data = &dispc.registered_isr[i];
2514
2515                 if (isr_data->isr != NULL)
2516                         continue;
2517
2518                 isr_data->isr = isr;
2519                 isr_data->arg = arg;
2520                 isr_data->mask = mask;
2521                 ret = 0;
2522
2523                 break;
2524         }
2525 err:
2526         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2527
2528         if (ret == 0)
2529                 omap_dispc_set_irqs();
2530
2531         return ret;
2532 }
2533 EXPORT_SYMBOL(omap_dispc_register_isr);
2534
2535 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2536 {
2537         int i;
2538         unsigned long flags;
2539         int ret = -EINVAL;
2540         struct omap_dispc_isr_data *isr_data;
2541
2542         spin_lock_irqsave(&dispc.irq_lock, flags);
2543
2544         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2545                 isr_data = &dispc.registered_isr[i];
2546                 if (isr_data->isr != isr || isr_data->arg != arg ||
2547                                 isr_data->mask != mask)
2548                         continue;
2549
2550                 /* found the correct isr */
2551
2552                 isr_data->isr = NULL;
2553                 isr_data->arg = NULL;
2554                 isr_data->mask = 0;
2555
2556                 ret = 0;
2557                 break;
2558         }
2559
2560         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2561
2562         if (ret == 0)
2563                 omap_dispc_set_irqs();
2564
2565         return ret;
2566 }
2567 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2568
2569 #ifdef DEBUG
2570 static void print_irq_status(u32 status)
2571 {
2572         if ((status & dispc.irq_error_mask) == 0)
2573                 return;
2574
2575         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2576
2577 #define PIS(x) \
2578         if (status & DISPC_IRQ_##x) \
2579                 printk(#x " ");
2580         PIS(GFX_FIFO_UNDERFLOW);
2581         PIS(OCP_ERR);
2582         PIS(VID1_FIFO_UNDERFLOW);
2583         PIS(VID2_FIFO_UNDERFLOW);
2584         PIS(SYNC_LOST);
2585         PIS(SYNC_LOST_DIGIT);
2586 #undef PIS
2587
2588         printk("\n");
2589 }
2590 #endif
2591
2592 /* Called from dss.c. Note that we don't touch clocks here,
2593  * but we presume they are on because we got an IRQ. However,
2594  * an irq handler may turn the clocks off, so we may not have
2595  * clock later in the function. */
2596 void dispc_irq_handler(void)
2597 {
2598         int i;
2599         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2600         u32 handledirqs = 0;
2601         u32 unhandled_errors;
2602         struct omap_dispc_isr_data *isr_data;
2603
2604 #ifdef DEBUG
2605         if (dss_debug)
2606                 print_irq_status(irqstatus);
2607 #endif
2608         /* Ack the interrupt. Do it here before clocks are possibly turned
2609          * off */
2610         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2611
2612         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2613                 isr_data = &dispc.registered_isr[i];
2614
2615                 if (!isr_data->isr)
2616                         continue;
2617
2618                 if (isr_data->mask & irqstatus) {
2619                         isr_data->isr(isr_data->arg, irqstatus);
2620                         handledirqs |= isr_data->mask;
2621                 }
2622         }
2623
2624         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2625
2626         if (unhandled_errors) {
2627                 spin_lock(&dispc.error_lock);
2628                 dispc.error_irqs |= unhandled_errors;
2629                 spin_unlock(&dispc.error_lock);
2630
2631                 dispc.irq_error_mask &= ~unhandled_errors;
2632                 omap_dispc_set_irqs();
2633
2634                 schedule_work(&dispc.error_work);
2635         }
2636 }
2637
2638 static void dispc_error_worker(struct work_struct *work)
2639 {
2640         int i;
2641         u32 errors;
2642         unsigned long flags;
2643
2644         spin_lock_irqsave(&dispc.error_lock, flags);
2645         errors = dispc.error_irqs;
2646         dispc.error_irqs = 0;
2647         spin_unlock_irqrestore(&dispc.error_lock, flags);
2648
2649         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2650                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2651                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2652                         struct omap_overlay *ovl;
2653                         ovl = omap_dss_get_overlay(i);
2654
2655                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2656                                 continue;
2657
2658                         if (ovl->id == 0) {
2659                                 dispc_enable_plane(ovl->id, 0);
2660                                 dispc_go(ovl->manager->id);
2661                                 mdelay(50);
2662                                 break;
2663                         }
2664                 }
2665         }
2666
2667         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2668                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2669                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2670                         struct omap_overlay *ovl;
2671                         ovl = omap_dss_get_overlay(i);
2672
2673                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2674                                 continue;
2675
2676                         if (ovl->id == 1) {
2677                                 dispc_enable_plane(ovl->id, 0);
2678                                 dispc_go(ovl->manager->id);
2679                                 mdelay(50);
2680                                 break;
2681                         }
2682                 }
2683         }
2684
2685         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2686                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2687                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2688                         struct omap_overlay *ovl;
2689                         ovl = omap_dss_get_overlay(i);
2690
2691                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2692                                 continue;
2693
2694                         if (ovl->id == 2) {
2695                                 dispc_enable_plane(ovl->id, 0);
2696                                 dispc_go(ovl->manager->id);
2697                                 mdelay(50);
2698                                 break;
2699                         }
2700                 }
2701         }
2702
2703         if (errors & DISPC_IRQ_SYNC_LOST) {
2704                 struct omap_overlay_manager *manager = NULL;
2705                 bool enable = false;
2706
2707                 DSSERR("SYNC_LOST, disabling LCD\n");
2708
2709                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2710                         struct omap_overlay_manager *mgr;
2711                         mgr = omap_dss_get_overlay_manager(i);
2712
2713                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2714                                 manager = mgr;
2715                                 enable = mgr->display->state ==
2716                                                 OMAP_DSS_DISPLAY_ACTIVE;
2717                                 mgr->display->disable(mgr->display);
2718                                 break;
2719                         }
2720                 }
2721
2722                 if (manager) {
2723                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2724                                 struct omap_overlay *ovl;
2725                                 ovl = omap_dss_get_overlay(i);
2726
2727                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2728                                         continue;
2729
2730                                 if (ovl->id != 0 && ovl->manager == manager)
2731                                         dispc_enable_plane(ovl->id, 0);
2732                         }
2733
2734                         dispc_go(manager->id);
2735                         mdelay(50);
2736                         if (enable)
2737                                 manager->display->enable(manager->display);
2738                 }
2739         }
2740
2741         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2742                 struct omap_overlay_manager *manager = NULL;
2743                 bool enable = false;
2744
2745                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2746
2747                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2748                         struct omap_overlay_manager *mgr;
2749                         mgr = omap_dss_get_overlay_manager(i);
2750
2751                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2752                                 manager = mgr;
2753                                 enable = mgr->display->state ==
2754                                                 OMAP_DSS_DISPLAY_ACTIVE;
2755                                 mgr->display->disable(mgr->display);
2756                                 break;
2757                         }
2758                 }
2759
2760                 if (manager) {
2761                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2762                                 struct omap_overlay *ovl;
2763                                 ovl = omap_dss_get_overlay(i);
2764
2765                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2766                                         continue;
2767
2768                                 if (ovl->id != 0 && ovl->manager == manager)
2769                                         dispc_enable_plane(ovl->id, 0);
2770                         }
2771
2772                         dispc_go(manager->id);
2773                         mdelay(50);
2774                         if (enable)
2775                                 manager->display->enable(manager->display);
2776                 }
2777         }
2778
2779         if (errors & DISPC_IRQ_OCP_ERR) {
2780                 DSSERR("OCP_ERR\n");
2781                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2782                         struct omap_overlay_manager *mgr;
2783                         mgr = omap_dss_get_overlay_manager(i);
2784
2785                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2786                                 mgr->display->disable(mgr->display);
2787                 }
2788         }
2789
2790         dispc.irq_error_mask |= errors;
2791         omap_dispc_set_irqs();
2792 }
2793
2794 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2795 {
2796         void dispc_irq_wait_handler(void *data, u32 mask)
2797         {
2798                 complete((struct completion *)data);
2799         }
2800
2801         int r;
2802         DECLARE_COMPLETION_ONSTACK(completion);
2803
2804         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2805                         irqmask);
2806
2807         if (r)
2808                 return r;
2809
2810         timeout = wait_for_completion_timeout(&completion, timeout);
2811
2812         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2813
2814         if (timeout == 0)
2815                 return -ETIMEDOUT;
2816
2817         if (timeout == -ERESTARTSYS)
2818                 return -ERESTARTSYS;
2819
2820         return 0;
2821 }
2822
2823 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2824                 unsigned long timeout)
2825 {
2826         void dispc_irq_wait_handler(void *data, u32 mask)
2827         {
2828                 complete((struct completion *)data);
2829         }
2830
2831         int r;
2832         DECLARE_COMPLETION_ONSTACK(completion);
2833
2834         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2835                         irqmask);
2836
2837         if (r)
2838                 return r;
2839
2840         timeout = wait_for_completion_interruptible_timeout(&completion,
2841                         timeout);
2842
2843         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2844
2845         if (timeout == 0)
2846                 return -ETIMEDOUT;
2847
2848         if (timeout == -ERESTARTSYS)
2849                 return -ERESTARTSYS;
2850
2851         return 0;
2852 }
2853
2854 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2855 void dispc_fake_vsync_irq(void)
2856 {
2857         u32 irqstatus = DISPC_IRQ_VSYNC;
2858         int i;
2859
2860         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2861                 struct omap_dispc_isr_data *isr_data;
2862                 isr_data = &dispc.registered_isr[i];
2863
2864                 if (!isr_data->isr)
2865                         continue;
2866
2867                 if (isr_data->mask & irqstatus)
2868                         isr_data->isr(isr_data->arg, irqstatus);
2869         }
2870 }
2871 #endif
2872
2873 static void _omap_dispc_initialize_irq(void)
2874 {
2875         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2876
2877         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2878
2879         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2880          * so clear it */
2881         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2882
2883         omap_dispc_set_irqs();
2884 }
2885
2886 void dispc_enable_sidle(void)
2887 {
2888         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
2889 }
2890
2891 void dispc_disable_sidle(void)
2892 {
2893         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
2894 }
2895
2896 static void _omap_dispc_initial_config(void)
2897 {
2898         u32 l;
2899
2900         l = dispc_read_reg(DISPC_SYSCONFIG);
2901         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2902         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2903         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2904         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2905         dispc_write_reg(DISPC_SYSCONFIG, l);
2906
2907         /* FUNCGATED */
2908         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2909
2910         /* L3 firewall setting: enable access to OCM RAM */
2911         if (cpu_is_omap24xx())
2912                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2913
2914         _dispc_setup_color_conv_coef();
2915
2916         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2917 }
2918
2919 int dispc_init(void)
2920 {
2921         u32 rev;
2922
2923         spin_lock_init(&dispc.irq_lock);
2924         spin_lock_init(&dispc.error_lock);
2925
2926         INIT_WORK(&dispc.error_work, dispc_error_worker);
2927
2928         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2929         if (!dispc.base) {
2930                 DSSERR("can't ioremap DISPC\n");
2931                 return -ENOMEM;
2932         }
2933
2934         if (cpu_is_omap34xx()) {
2935                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2936                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2937                         DSSERR("Failed to get dpll4_m4_ck\n");
2938                         return -ENODEV;
2939                 }
2940         }
2941
2942         enable_clocks(1);
2943
2944         _omap_dispc_initial_config();
2945
2946         _omap_dispc_initialize_irq();
2947
2948         dispc_save_context();
2949
2950         rev = dispc_read_reg(DISPC_REVISION);
2951         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2952                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2953
2954         enable_clocks(0);
2955
2956         return 0;
2957 }
2958
2959 void dispc_exit(void)
2960 {
2961         if (cpu_is_omap34xx())
2962                 clk_put(dispc.dpll4_m4_ck);
2963         iounmap(dispc.base);
2964 }
2965
2966 int dispc_enable_plane(enum omap_plane plane, bool enable)
2967 {
2968         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2969
2970         enable_clocks(1);
2971         _dispc_enable_plane(plane, enable);
2972         enable_clocks(0);
2973
2974         return 0;
2975 }
2976
2977 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
2978                        u32 paddr, u16 screen_width,
2979                        u16 pos_x, u16 pos_y,
2980                        u16 width, u16 height,
2981                        u16 out_width, u16 out_height,
2982                        enum omap_color_mode color_mode,
2983                        bool ilace,
2984                        enum omap_dss_rotation_type rotation_type,
2985                        u8 rotation, bool mirror)
2986 {
2987         int r = 0;
2988
2989         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
2990                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
2991                plane, channel_out, paddr, screen_width, pos_x, pos_y,
2992                width, height,
2993                out_width, out_height,
2994                ilace, color_mode,
2995                rotation, mirror);
2996
2997         enable_clocks(1);
2998
2999         r = _dispc_setup_plane(plane, channel_out,
3000                            paddr, screen_width,
3001                            pos_x, pos_y,
3002                            width, height,
3003                            out_width, out_height,
3004                            color_mode, ilace,
3005                            rotation_type,
3006                            rotation, mirror);
3007
3008         enable_clocks(0);
3009
3010         return r;
3011 }
3012
3013 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
3014                                  int x2, int y2, int w2, int h2)
3015 {
3016         if (x1 >= (x2+w2))
3017                 return 0;
3018
3019         if ((x1+w1) <= x2)
3020                 return 0;
3021
3022         if (y1 >= (y2+h2))
3023                 return 0;
3024
3025         if ((y1+h1) <= y2)
3026                 return 0;
3027
3028         return 1;
3029 }
3030
3031 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
3032 {
3033         if (pi->width != pi->out_width)
3034                 return 1;
3035
3036         if (pi->height != pi->out_height)
3037                 return 1;
3038
3039         return 0;
3040 }
3041
3042 /* returns the area that needs updating */
3043 void dispc_setup_partial_planes(struct omap_display *display,
3044                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
3045 {
3046         struct omap_overlay_manager *mgr;
3047         int i;
3048
3049         int x, y, w, h;
3050
3051         x = *xi;
3052         y = *yi;
3053         w = *wi;
3054         h = *hi;
3055
3056         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
3057                 *xi, *yi, *wi, *hi);
3058
3059
3060         mgr = display->manager;
3061
3062         if (!mgr) {
3063                 DSSDBG("no manager\n");
3064                 return;
3065         }
3066
3067         for (i = 0; i < mgr->num_overlays; i++) {
3068                 struct omap_overlay *ovl;
3069                 struct omap_overlay_info *pi;
3070                 ovl = mgr->overlays[i];
3071
3072                 if (ovl->manager != mgr)
3073                         continue;
3074
3075                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
3076                         continue;
3077
3078                 pi = &ovl->info;
3079
3080                 if (!pi->enabled)
3081                         continue;
3082                 /*
3083                  * If the plane is intersecting and scaled, we
3084                  * enlarge the update region to accomodate the
3085                  * whole area
3086                  */
3087
3088                 if (dispc_is_intersecting(x, y, w, h,
3089                                           pi->pos_x, pi->pos_y,
3090                                           pi->out_width, pi->out_height)) {
3091                         if (dispc_is_overlay_scaled(pi)) {
3092
3093                                 int x1, y1, x2, y2;
3094
3095                                 if (x > pi->pos_x)
3096                                         x1 = pi->pos_x;
3097                                 else
3098                                         x1 = x;
3099
3100                                 if (y > pi->pos_y)
3101                                         y1 = pi->pos_y;
3102                                 else
3103                                         y1 = y;
3104
3105                                 if ((x + w) < (pi->pos_x + pi->out_width))
3106                                         x2 = pi->pos_x + pi->out_width;
3107                                 else
3108                                         x2 = x + w;
3109
3110                                 if ((y + h) < (pi->pos_y + pi->out_height))
3111                                         y2 = pi->pos_y + pi->out_height;
3112                                 else
3113                                         y2 = y + h;
3114
3115                                 x = x1;
3116                                 y = y1;
3117                                 w = x2 - x1;
3118                                 h = y2 - y1;
3119
3120                                 DSSDBG("Update area after enlarge due to "
3121                                         "scaling %d, %d %dx%d\n",
3122                                         x, y, w, h);
3123                         }
3124                 }
3125         }
3126
3127         for (i = 0; i < mgr->num_overlays; i++) {
3128                 struct omap_overlay *ovl = mgr->overlays[i];
3129                 struct omap_overlay_info *pi = &ovl->info;
3130
3131                 int px = pi->pos_x;
3132                 int py = pi->pos_y;
3133                 int pw = pi->width;
3134                 int ph = pi->height;
3135                 int pow = pi->out_width;
3136                 int poh = pi->out_height;
3137                 u32 pa = pi->paddr;
3138                 int psw = pi->screen_width;
3139                 int bpp;
3140
3141                 if (ovl->manager != mgr)
3142                         continue;
3143
3144                 /*
3145                  * If plane is not enabled or the update region
3146                  * does not intersect with the plane in question,
3147                  * we really disable the plane from hardware
3148                  */
3149
3150                 if (!pi->enabled ||
3151                     !dispc_is_intersecting(x, y, w, h,
3152                                            px, py, pow, poh)) {
3153                         dispc_enable_plane(ovl->id, 0);
3154                         continue;
3155                 }
3156
3157                 switch (pi->color_mode) {
3158                 case OMAP_DSS_COLOR_RGB16:
3159                 case OMAP_DSS_COLOR_ARGB16:
3160                 case OMAP_DSS_COLOR_YUV2:
3161                 case OMAP_DSS_COLOR_UYVY:
3162                         bpp = 16;
3163                         break;
3164
3165                 case OMAP_DSS_COLOR_RGB24P:
3166                         bpp = 24;
3167                         break;
3168
3169                 case OMAP_DSS_COLOR_RGB24U:
3170                 case OMAP_DSS_COLOR_ARGB32:
3171                 case OMAP_DSS_COLOR_RGBA32:
3172                 case OMAP_DSS_COLOR_RGBX32:
3173                         bpp = 32;
3174                         break;
3175
3176                 default:
3177                         BUG();
3178                         return;
3179                 }
3180
3181                 if (x > pi->pos_x) {
3182                         px = 0;
3183                         pw -= (x - pi->pos_x);
3184                         pa += (x - pi->pos_x) * bpp / 8;
3185                 } else {
3186                         px = pi->pos_x - x;
3187                 }
3188
3189                 if (y > pi->pos_y) {
3190                         py = 0;
3191                         ph -= (y - pi->pos_y);
3192                         pa += (y - pi->pos_y) * psw * bpp / 8;
3193                 } else {
3194                         py = pi->pos_y - y;
3195                 }
3196
3197                 if (w < (px+pw))
3198                         pw -= (px+pw) - (w);
3199
3200                 if (h < (py+ph))
3201                         ph -= (py+ph) - (h);
3202
3203                 /* Can't scale the GFX plane */
3204                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3205                                 dispc_is_overlay_scaled(pi) == 0) {
3206                         pow = pw;
3207                         poh = ph;
3208                 }
3209
3210                 DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3211                                 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3212
3213                 dispc_setup_plane(ovl->id, mgr->id,
3214                                 pa, psw,
3215                                 px, py,
3216                                 pw, ph,
3217                                 pow, poh,
3218                                 pi->color_mode, 0,
3219                                 pi->rotation_type,
3220                                 pi->rotation,
3221                                 pi->mirror);
3222
3223                 dispc_enable_plane(ovl->id, 1);
3224         }
3225
3226         *xi = x;
3227         *yi = y;
3228         *wi = w;
3229         *hi = h;
3230
3231 }
3232