drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34
  35 #include <mach/sram.h>
  36 #include <mach/board.h>
  37 #include <mach/clock.h>
  38
  39 #include <mach/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 #define REG_GET(idx, start, end) \
 143         FLD_GET(dispc_read_reg(idx), start, end)
 144
 145 #define REG_FLD_MOD(idx, val, start, end)                               \
 146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 147
 148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 149         DISPC_VID_ATTRIBUTES(0),
 150         DISPC_VID_ATTRIBUTES(1) };
 151
 152 static struct {
 153         void __iomem    *base;
 154
 155         struct clk      *dpll4_m4_ck;
 156
 157         spinlock_t      irq_lock;
 158
 159         unsigned long   cache_req_pck;
 160         unsigned long   cache_prate;
 161         struct dispc_clock_info cache_cinfo;
 162
 163         u32             irq_error_mask;
 164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 165
 166         spinlock_t error_lock;
 167         u32 error_irqs;
 168         struct work_struct error_work;
 169
 170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 171 } dispc;
 172
 173 static void omap_dispc_set_irqs(void);
 174
 175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 176 {
 177         __raw_writel(val, dispc.base + idx.idx);
 178 }
 179
 180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 181 {
 182         return __raw_readl(dispc.base + idx.idx);
 183 }
 184
 185 #define SR(reg) \
 186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 187 #define RR(reg) \
 188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 189
 190 void dispc_save_context(void)
 191 {
 192         if (cpu_is_omap24xx())
 193                 return;
 194
 195         SR(SYSCONFIG);
 196         SR(IRQENABLE);
 197         SR(CONTROL);
 198         SR(CONFIG);
 199         SR(DEFAULT_COLOR0);
 200         SR(DEFAULT_COLOR1);
 201         SR(TRANS_COLOR0);
 202         SR(TRANS_COLOR1);
 203         SR(LINE_NUMBER);
 204         SR(TIMING_H);
 205         SR(TIMING_V);
 206         SR(POL_FREQ);
 207         SR(DIVISOR);
 208         SR(GLOBAL_ALPHA);
 209         SR(SIZE_DIG);
 210         SR(SIZE_LCD);
 211
 212         SR(GFX_BA0);
 213         SR(GFX_BA1);
 214         SR(GFX_POSITION);
 215         SR(GFX_SIZE);
 216         SR(GFX_ATTRIBUTES);
 217         SR(GFX_FIFO_THRESHOLD);
 218         SR(GFX_ROW_INC);
 219         SR(GFX_PIXEL_INC);
 220         SR(GFX_WINDOW_SKIP);
 221         SR(GFX_TABLE_BA);
 222
 223         SR(DATA_CYCLE1);
 224         SR(DATA_CYCLE2);
 225         SR(DATA_CYCLE3);
 226
 227         SR(CPR_COEF_R);
 228         SR(CPR_COEF_G);
 229         SR(CPR_COEF_B);
 230
 231         SR(GFX_PRELOAD);
 232
 233         /* VID1 */
 234         SR(VID_BA0(0));
 235         SR(VID_BA1(0));
 236         SR(VID_POSITION(0));
 237         SR(VID_SIZE(0));
 238         SR(VID_ATTRIBUTES(0));
 239         SR(VID_FIFO_THRESHOLD(0));
 240         SR(VID_ROW_INC(0));
 241         SR(VID_PIXEL_INC(0));
 242         SR(VID_FIR(0));
 243         SR(VID_PICTURE_SIZE(0));
 244         SR(VID_ACCU0(0));
 245         SR(VID_ACCU1(0));
 246
 247         SR(VID_FIR_COEF_H(0, 0));
 248         SR(VID_FIR_COEF_H(0, 1));
 249         SR(VID_FIR_COEF_H(0, 2));
 250         SR(VID_FIR_COEF_H(0, 3));
 251         SR(VID_FIR_COEF_H(0, 4));
 252         SR(VID_FIR_COEF_H(0, 5));
 253         SR(VID_FIR_COEF_H(0, 6));
 254         SR(VID_FIR_COEF_H(0, 7));
 255
 256         SR(VID_FIR_COEF_HV(0, 0));
 257         SR(VID_FIR_COEF_HV(0, 1));
 258         SR(VID_FIR_COEF_HV(0, 2));
 259         SR(VID_FIR_COEF_HV(0, 3));
 260         SR(VID_FIR_COEF_HV(0, 4));
 261         SR(VID_FIR_COEF_HV(0, 5));
 262         SR(VID_FIR_COEF_HV(0, 6));
 263         SR(VID_FIR_COEF_HV(0, 7));
 264
 265         SR(VID_CONV_COEF(0, 0));
 266         SR(VID_CONV_COEF(0, 1));
 267         SR(VID_CONV_COEF(0, 2));
 268         SR(VID_CONV_COEF(0, 3));
 269         SR(VID_CONV_COEF(0, 4));
 270
 271         SR(VID_FIR_COEF_V(0, 0));
 272         SR(VID_FIR_COEF_V(0, 1));
 273         SR(VID_FIR_COEF_V(0, 2));
 274         SR(VID_FIR_COEF_V(0, 3));
 275         SR(VID_FIR_COEF_V(0, 4));
 276         SR(VID_FIR_COEF_V(0, 5));
 277         SR(VID_FIR_COEF_V(0, 6));
 278         SR(VID_FIR_COEF_V(0, 7));
 279
 280         SR(VID_PRELOAD(0));
 281
 282         /* VID2 */
 283         SR(VID_BA0(1));
 284         SR(VID_BA1(1));
 285         SR(VID_POSITION(1));
 286         SR(VID_SIZE(1));
 287         SR(VID_ATTRIBUTES(1));
 288         SR(VID_FIFO_THRESHOLD(1));
 289         SR(VID_ROW_INC(1));
 290         SR(VID_PIXEL_INC(1));
 291         SR(VID_FIR(1));
 292         SR(VID_PICTURE_SIZE(1));
 293         SR(VID_ACCU0(1));
 294         SR(VID_ACCU1(1));
 295
 296         SR(VID_FIR_COEF_H(1, 0));
 297         SR(VID_FIR_COEF_H(1, 1));
 298         SR(VID_FIR_COEF_H(1, 2));
 299         SR(VID_FIR_COEF_H(1, 3));
 300         SR(VID_FIR_COEF_H(1, 4));
 301         SR(VID_FIR_COEF_H(1, 5));
 302         SR(VID_FIR_COEF_H(1, 6));
 303         SR(VID_FIR_COEF_H(1, 7));
 304
 305         SR(VID_FIR_COEF_HV(1, 0));
 306         SR(VID_FIR_COEF_HV(1, 1));
 307         SR(VID_FIR_COEF_HV(1, 2));
 308         SR(VID_FIR_COEF_HV(1, 3));
 309         SR(VID_FIR_COEF_HV(1, 4));
 310         SR(VID_FIR_COEF_HV(1, 5));
 311         SR(VID_FIR_COEF_HV(1, 6));
 312         SR(VID_FIR_COEF_HV(1, 7));
 313
 314         SR(VID_CONV_COEF(1, 0));
 315         SR(VID_CONV_COEF(1, 1));
 316         SR(VID_CONV_COEF(1, 2));
 317         SR(VID_CONV_COEF(1, 3));
 318         SR(VID_CONV_COEF(1, 4));
 319
 320         SR(VID_FIR_COEF_V(1, 0));
 321         SR(VID_FIR_COEF_V(1, 1));
 322         SR(VID_FIR_COEF_V(1, 2));
 323         SR(VID_FIR_COEF_V(1, 3));
 324         SR(VID_FIR_COEF_V(1, 4));
 325         SR(VID_FIR_COEF_V(1, 5));
 326         SR(VID_FIR_COEF_V(1, 6));
 327         SR(VID_FIR_COEF_V(1, 7));
 328
 329         SR(VID_PRELOAD(1));
 330 }
 331
 332 void dispc_restore_context(void)
 333 {
 334         RR(SYSCONFIG);
 335         RR(IRQENABLE);
 336         /*RR(CONTROL);*/
 337         RR(CONFIG);
 338         RR(DEFAULT_COLOR0);
 339         RR(DEFAULT_COLOR1);
 340         RR(TRANS_COLOR0);
 341         RR(TRANS_COLOR1);
 342         RR(LINE_NUMBER);
 343         RR(TIMING_H);
 344         RR(TIMING_V);
 345         RR(POL_FREQ);
 346         RR(DIVISOR);
 347         RR(GLOBAL_ALPHA);
 348         RR(SIZE_DIG);
 349         RR(SIZE_LCD);
 350
 351         RR(GFX_BA0);
 352         RR(GFX_BA1);
 353         RR(GFX_POSITION);
 354         RR(GFX_SIZE);
 355         RR(GFX_ATTRIBUTES);
 356         RR(GFX_FIFO_THRESHOLD);
 357         RR(GFX_ROW_INC);
 358         RR(GFX_PIXEL_INC);
 359         RR(GFX_WINDOW_SKIP);
 360         RR(GFX_TABLE_BA);
 361
 362         RR(DATA_CYCLE1);
 363         RR(DATA_CYCLE2);
 364         RR(DATA_CYCLE3);
 365
 366         RR(CPR_COEF_R);
 367         RR(CPR_COEF_G);
 368         RR(CPR_COEF_B);
 369
 370         RR(GFX_PRELOAD);
 371
 372         /* VID1 */
 373         RR(VID_BA0(0));
 374         RR(VID_BA1(0));
 375         RR(VID_POSITION(0));
 376         RR(VID_SIZE(0));
 377         RR(VID_ATTRIBUTES(0));
 378         RR(VID_FIFO_THRESHOLD(0));
 379         RR(VID_ROW_INC(0));
 380         RR(VID_PIXEL_INC(0));
 381         RR(VID_FIR(0));
 382         RR(VID_PICTURE_SIZE(0));
 383         RR(VID_ACCU0(0));
 384         RR(VID_ACCU1(0));
 385
 386         RR(VID_FIR_COEF_H(0, 0));
 387         RR(VID_FIR_COEF_H(0, 1));
 388         RR(VID_FIR_COEF_H(0, 2));
 389         RR(VID_FIR_COEF_H(0, 3));
 390         RR(VID_FIR_COEF_H(0, 4));
 391         RR(VID_FIR_COEF_H(0, 5));
 392         RR(VID_FIR_COEF_H(0, 6));
 393         RR(VID_FIR_COEF_H(0, 7));
 394
 395         RR(VID_FIR_COEF_HV(0, 0));
 396         RR(VID_FIR_COEF_HV(0, 1));
 397         RR(VID_FIR_COEF_HV(0, 2));
 398         RR(VID_FIR_COEF_HV(0, 3));
 399         RR(VID_FIR_COEF_HV(0, 4));
 400         RR(VID_FIR_COEF_HV(0, 5));
 401         RR(VID_FIR_COEF_HV(0, 6));
 402         RR(VID_FIR_COEF_HV(0, 7));
 403
 404         RR(VID_CONV_COEF(0, 0));
 405         RR(VID_CONV_COEF(0, 1));
 406         RR(VID_CONV_COEF(0, 2));
 407         RR(VID_CONV_COEF(0, 3));
 408         RR(VID_CONV_COEF(0, 4));
 409
 410         RR(VID_FIR_COEF_V(0, 0));
 411         RR(VID_FIR_COEF_V(0, 1));
 412         RR(VID_FIR_COEF_V(0, 2));
 413         RR(VID_FIR_COEF_V(0, 3));
 414         RR(VID_FIR_COEF_V(0, 4));
 415         RR(VID_FIR_COEF_V(0, 5));
 416         RR(VID_FIR_COEF_V(0, 6));
 417         RR(VID_FIR_COEF_V(0, 7));
 418
 419         RR(VID_PRELOAD(0));
 420
 421         /* VID2 */
 422         RR(VID_BA0(1));
 423         RR(VID_BA1(1));
 424         RR(VID_POSITION(1));
 425         RR(VID_SIZE(1));
 426         RR(VID_ATTRIBUTES(1));
 427         RR(VID_FIFO_THRESHOLD(1));
 428         RR(VID_ROW_INC(1));
 429         RR(VID_PIXEL_INC(1));
 430         RR(VID_FIR(1));
 431         RR(VID_PICTURE_SIZE(1));
 432         RR(VID_ACCU0(1));
 433         RR(VID_ACCU1(1));
 434
 435         RR(VID_FIR_COEF_H(1, 0));
 436         RR(VID_FIR_COEF_H(1, 1));
 437         RR(VID_FIR_COEF_H(1, 2));
 438         RR(VID_FIR_COEF_H(1, 3));
 439         RR(VID_FIR_COEF_H(1, 4));
 440         RR(VID_FIR_COEF_H(1, 5));
 441         RR(VID_FIR_COEF_H(1, 6));
 442         RR(VID_FIR_COEF_H(1, 7));
 443
 444         RR(VID_FIR_COEF_HV(1, 0));
 445         RR(VID_FIR_COEF_HV(1, 1));
 446         RR(VID_FIR_COEF_HV(1, 2));
 447         RR(VID_FIR_COEF_HV(1, 3));
 448         RR(VID_FIR_COEF_HV(1, 4));
 449         RR(VID_FIR_COEF_HV(1, 5));
 450         RR(VID_FIR_COEF_HV(1, 6));
 451         RR(VID_FIR_COEF_HV(1, 7));
 452
 453         RR(VID_CONV_COEF(1, 0));
 454         RR(VID_CONV_COEF(1, 1));
 455         RR(VID_CONV_COEF(1, 2));
 456         RR(VID_CONV_COEF(1, 3));
 457         RR(VID_CONV_COEF(1, 4));
 458
 459         RR(VID_FIR_COEF_V(1, 0));
 460         RR(VID_FIR_COEF_V(1, 1));
 461         RR(VID_FIR_COEF_V(1, 2));
 462         RR(VID_FIR_COEF_V(1, 3));
 463         RR(VID_FIR_COEF_V(1, 4));
 464         RR(VID_FIR_COEF_V(1, 5));
 465         RR(VID_FIR_COEF_V(1, 6));
 466         RR(VID_FIR_COEF_V(1, 7));
 467
 468         RR(VID_PRELOAD(1));
 469
 470         /* enable last, because LCD & DIGIT enable are here */
 471         RR(CONTROL);
 472 }
 473
 474 #undef SR
 475 #undef RR
 476
 477 static inline void enable_clocks(bool enable)
 478 {
 479         if (enable)
 480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 481         else
 482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 483 }
 484
 485 void dispc_go(enum omap_channel channel)
 486 {
 487         int bit;
 488         unsigned long tmo;
 489
 490         enable_clocks(1);
 491
 492         if (channel == OMAP_DSS_CHANNEL_LCD)
 493                 bit = 0; /* LCDENABLE */
 494         else
 495                 bit = 1; /* DIGITALENABLE */
 496
 497         /* if the channel is not enabled, we don't need GO */
 498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 499                 goto end;
 500
 501         if (channel == OMAP_DSS_CHANNEL_LCD)
 502                 bit = 5; /* GOLCD */
 503         else
 504                 bit = 6; /* GODIGIT */
 505
 506         tmo = jiffies + msecs_to_jiffies(200);
 507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 508                 if (time_after(jiffies, tmo)) {
 509                         DSSERR("timeout waiting GO flag\n");
 510                         goto end;
 511                 }
 512                 cpu_relax();
 513         }
 514
 515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 516
 517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 518 end:
 519         enable_clocks(0);
 520 }
 521
 522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 523 {
 524         BUG_ON(plane == OMAP_DSS_GFX);
 525
 526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 527 }
 528
 529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 530 {
 531         BUG_ON(plane == OMAP_DSS_GFX);
 532
 533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 534 }
 535
 536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 537 {
 538         BUG_ON(plane == OMAP_DSS_GFX);
 539
 540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 541 }
 542
 543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 544                 int vscaleup, int five_taps)
 545 {
 546         /* Coefficients for horizontal up-sampling */
 547         static const u32 coef_hup[8] = {
 548                 0x00800000,
 549                 0x0D7CF800,
 550                 0x1E70F5FF,
 551                 0x335FF5FE,
 552                 0xF74949F7,
 553                 0xF55F33FB,
 554                 0xF5701EFE,
 555                 0xF87C0DFF,
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const u32 coef_hdown[8] = {
 560                 0x24382400,
 561                 0x28371FFE,
 562                 0x2C361BFB,
 563                 0x303516F9,
 564                 0x11343311,
 565                 0x1635300C,
 566                 0x1B362C08,
 567                 0x1F372804,
 568         };
 569
 570         /* Coefficients for horizontal and vertical up-sampling */
 571         static const u32 coef_hvup[2][8] = {
 572                 {
 573                 0x00800000,
 574                 0x037B02FF,
 575                 0x0C6F05FE,
 576                 0x205907FB,
 577                 0x00404000,
 578                 0x075920FE,
 579                 0x056F0CFF,
 580                 0x027B0300,
 581                 },
 582                 {
 583                 0x00800000,
 584                 0x0D7CF8FF,
 585                 0x1E70F5FE,
 586                 0x335FF5FB,
 587                 0xF7404000,
 588                 0xF55F33FE,
 589                 0xF5701EFF,
 590                 0xF87C0D00,
 591                 },
 592         };
 593
 594         /* Coefficients for horizontal and vertical down-sampling */
 595         static const u32 coef_hvdown[2][8] = {
 596                 {
 597                 0x24382400,
 598                 0x28391F04,
 599                 0x2D381B08,
 600                 0x3237170C,
 601                 0x123737F7,
 602                 0x173732F9,
 603                 0x1B382DFB,
 604                 0x1F3928FE,
 605                 },
 606                 {
 607                 0x24382400,
 608                 0x28371F04,
 609                 0x2C361B08,
 610                 0x3035160C,
 611                 0x113433F7,
 612                 0x163530F9,
 613                 0x1B362CFB,
 614                 0x1F3728FE,
 615                 },
 616         };
 617
 618         /* Coefficients for vertical up-sampling */
 619         static const u32 coef_vup[8] = {
 620                 0x00000000,
 621                 0x0000FF00,
 622                 0x0000FEFF,
 623                 0x0000FBFE,
 624                 0x000000F7,
 625                 0x0000FEFB,
 626                 0x0000FFFE,
 627                 0x000000FF,
 628         };
 629
 630
 631         /* Coefficients for vertical down-sampling */
 632         static const u32 coef_vdown[8] = {
 633                 0x00000000,
 634                 0x000004FE,
 635                 0x000008FB,
 636                 0x00000CF9,
 637                 0x0000F711,
 638                 0x0000F90C,
 639                 0x0000FB08,
 640                 0x0000FE04,
 641         };
 642
 643         const u32 *h_coef;
 644         const u32 *hv_coef;
 645         const u32 *hv_coef_mod;
 646         const u32 *v_coef;
 647         int i;
 648
 649         if (hscaleup)
 650                 h_coef = coef_hup;
 651         else
 652                 h_coef = coef_hdown;
 653
 654         if (vscaleup) {
 655                 hv_coef = coef_hvup[five_taps];
 656                 v_coef = coef_vup;
 657
 658                 if (hscaleup)
 659                         hv_coef_mod = NULL;
 660                 else
 661                         hv_coef_mod = coef_hvdown[five_taps];
 662         } else {
 663                 hv_coef = coef_hvdown[five_taps];
 664                 v_coef = coef_vdown;
 665
 666                 if (hscaleup)
 667                         hv_coef_mod = coef_hvup[five_taps];
 668                 else
 669                         hv_coef_mod = NULL;
 670         }
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = h_coef[i];
 676
 677                 hv = hv_coef[i];
 678
 679                 if (hv_coef_mod) {
 680                         hv &= 0xffffff00;
 681                         hv |= (hv_coef_mod[i] & 0xff);
 682                 }
 683
 684                 _dispc_write_firh_reg(plane, i, h);
 685                 _dispc_write_firhv_reg(plane, i, hv);
 686         }
 687
 688         if (!five_taps)
 689                 return;
 690
 691         for (i = 0; i < 8; i++) {
 692                 u32 v;
 693                 v = v_coef[i];
 694                 _dispc_write_firv_reg(plane, i, v);
 695         }
 696 }
 697
 698 static void _dispc_setup_color_conv_coef(void)
 699 {
 700         const struct color_conv_coef {
 701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 702                 int  full_range;
 703         }  ctbl_bt601_5 = {
 704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 705         };
 706
 707         const struct color_conv_coef *ct;
 708
 709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 710
 711         ct = &ctbl_bt601_5;
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 718
 719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 724
 725 #undef CVAL
 726
 727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 729 }
 730
 731
 732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 733 {
 734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 735                 DISPC_VID_BA0(0),
 736                 DISPC_VID_BA0(1) };
 737
 738         dispc_write_reg(ba0_reg[plane], paddr);
 739 }
 740
 741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 742 {
 743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 744                                       DISPC_VID_BA1(0),
 745                                       DISPC_VID_BA1(1) };
 746
 747         dispc_write_reg(ba1_reg[plane], paddr);
 748 }
 749
 750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 751 {
 752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 753                                       DISPC_VID_POSITION(0),
 754                                       DISPC_VID_POSITION(1) };
 755
 756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 757         dispc_write_reg(pos_reg[plane], val);
 758 }
 759
 760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 761 {
 762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 763                                       DISPC_VID_PICTURE_SIZE(0),
 764                                       DISPC_VID_PICTURE_SIZE(1) };
 765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 766         dispc_write_reg(siz_reg[plane], val);
 767 }
 768
 769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 770 {
 771         u32 val;
 772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 773                                       DISPC_VID_SIZE(1) };
 774
 775         BUG_ON(plane == OMAP_DSS_GFX);
 776
 777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 778         dispc_write_reg(vsi_reg[plane-1], val);
 779 }
 780
 781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 782 {
 783         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 784                                      DISPC_VID_PIXEL_INC(0),
 785                                      DISPC_VID_PIXEL_INC(1) };
 786
 787         dispc_write_reg(ri_reg[plane], inc);
 788 }
 789
 790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 791 {
 792         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 793                                      DISPC_VID_ROW_INC(0),
 794                                      DISPC_VID_ROW_INC(1) };
 795
 796         dispc_write_reg(ri_reg[plane], inc);
 797 }
 798
 799 static void _dispc_set_color_mode(enum omap_plane plane,
 800                 enum omap_color_mode color_mode)
 801 {
 802         u32 m = 0;
 803
 804         switch (color_mode) {
 805         case OMAP_DSS_COLOR_CLUT1:
 806                 m = 0x0; break;
 807         case OMAP_DSS_COLOR_CLUT2:
 808                 m = 0x1; break;
 809         case OMAP_DSS_COLOR_CLUT4:
 810                 m = 0x2; break;
 811         case OMAP_DSS_COLOR_CLUT8:
 812                 m = 0x3; break;
 813         case OMAP_DSS_COLOR_RGB12U:
 814                 m = 0x4; break;
 815         case OMAP_DSS_COLOR_ARGB16:
 816                 m = 0x5; break;
 817         case OMAP_DSS_COLOR_RGB16:
 818                 m = 0x6; break;
 819         case OMAP_DSS_COLOR_RGB24U:
 820                 m = 0x8; break;
 821         case OMAP_DSS_COLOR_RGB24P:
 822                 m = 0x9; break;
 823         case OMAP_DSS_COLOR_YUV2:
 824                 m = 0xa; break;
 825         case OMAP_DSS_COLOR_UYVY:
 826                 m = 0xb; break;
 827         case OMAP_DSS_COLOR_ARGB32:
 828                 m = 0xc; break;
 829         case OMAP_DSS_COLOR_RGBA32:
 830                 m = 0xd; break;
 831         case OMAP_DSS_COLOR_RGBX32:
 832                 m = 0xe; break;
 833         default:
 834                 BUG(); break;
 835         }
 836
 837         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 838 }
 839
 840 static void _dispc_set_channel_out(enum omap_plane plane,
 841                 enum omap_channel channel)
 842 {
 843         int shift;
 844         u32 val;
 845
 846         switch (plane) {
 847         case OMAP_DSS_GFX:
 848                 shift = 8;
 849                 break;
 850         case OMAP_DSS_VIDEO1:
 851         case OMAP_DSS_VIDEO2:
 852                 shift = 16;
 853                 break;
 854         default:
 855                 BUG();
 856                 return;
 857         }
 858
 859         val = dispc_read_reg(dispc_reg_att[plane]);
 860         val = FLD_MOD(val, channel, shift, shift);
 861         dispc_write_reg(dispc_reg_att[plane], val);
 862 }
 863
 864 void dispc_set_burst_size(enum omap_plane plane,
 865                 enum omap_burst_size burst_size)
 866 {
 867         int shift;
 868         u32 val;
 869
 870         enable_clocks(1);
 871
 872         switch (plane) {
 873         case OMAP_DSS_GFX:
 874                 shift = 6;
 875                 break;
 876         case OMAP_DSS_VIDEO1:
 877         case OMAP_DSS_VIDEO2:
 878                 shift = 14;
 879                 break;
 880         default:
 881                 BUG();
 882                 return;
 883         }
 884
 885         val = dispc_read_reg(dispc_reg_att[plane]);
 886         val = FLD_MOD(val, burst_size, shift+1, shift);
 887         dispc_write_reg(dispc_reg_att[plane], val);
 888
 889         enable_clocks(0);
 890 }
 891
 892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 893 {
 894         u32 val;
 895
 896         BUG_ON(plane == OMAP_DSS_GFX);
 897
 898         val = dispc_read_reg(dispc_reg_att[plane]);
 899         val = FLD_MOD(val, enable, 9, 9);
 900         dispc_write_reg(dispc_reg_att[plane], val);
 901 }
 902
 903 void dispc_set_lcd_size(u16 width, u16 height)
 904 {
 905         u32 val;
 906         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 907         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 908         enable_clocks(1);
 909         dispc_write_reg(DISPC_SIZE_LCD, val);
 910         enable_clocks(0);
 911 }
 912
 913 void dispc_set_digit_size(u16 width, u16 height)
 914 {
 915         u32 val;
 916         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 917         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 918         enable_clocks(1);
 919         dispc_write_reg(DISPC_SIZE_DIG, val);
 920         enable_clocks(0);
 921 }
 922
 923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 924 {
 925         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 926                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 927                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 928         u32 size;
 929
 930         enable_clocks(1);
 931
 932         if (cpu_is_omap24xx())
 933                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 934         else if (cpu_is_omap34xx())
 935                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 936         else
 937                 BUG();
 938
 939         if (cpu_is_omap34xx()) {
 940                 /* FIFOMERGE */
 941                 if (REG_GET(DISPC_CONFIG, 14, 14))
 942                         size *= 3;
 943         }
 944
 945         enable_clocks(0);
 946
 947         return size;
 948 }
 949
 950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 951 {
 952         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 953                                        DISPC_VID_FIFO_THRESHOLD(0),
 954                                        DISPC_VID_FIFO_THRESHOLD(1) };
 955         u32 size;
 956
 957         enable_clocks(1);
 958
 959         size = dispc_get_plane_fifo_size(plane);
 960
 961         BUG_ON(low > size || high > size);
 962
 963         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
 964                         plane, size,
 965                         REG_GET(ftrs_reg[plane], 11, 0),
 966                         REG_GET(ftrs_reg[plane], 27, 16),
 967                         low, high);
 968
 969         if (cpu_is_omap24xx())
 970                 dispc_write_reg(ftrs_reg[plane],
 971                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
 972         else
 973                 dispc_write_reg(ftrs_reg[plane],
 974                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
 975
 976         enable_clocks(0);
 977 }
 978
 979 void dispc_enable_fifomerge(bool enable)
 980 {
 981         enable_clocks(1);
 982
 983         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
 984         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
 985
 986         enable_clocks(0);
 987 }
 988
 989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
 990 {
 991         u32 val;
 992         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
 993                                       DISPC_VID_FIR(1) };
 994
 995         BUG_ON(plane == OMAP_DSS_GFX);
 996
 997         val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
 998         dispc_write_reg(fir_reg[plane-1], val);
 999 }
1000
1001 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1002 {
1003         u32 val;
1004         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1005                                       DISPC_VID_ACCU0(1) };
1006
1007         BUG_ON(plane == OMAP_DSS_GFX);
1008
1009         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1010         dispc_write_reg(ac0_reg[plane-1], val);
1011 }
1012
1013 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1014 {
1015         u32 val;
1016         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1017                                       DISPC_VID_ACCU1(1) };
1018
1019         BUG_ON(plane == OMAP_DSS_GFX);
1020
1021         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1022         dispc_write_reg(ac1_reg[plane-1], val);
1023 }
1024
1025
1026 static void _dispc_set_scaling(enum omap_plane plane,
1027                 u16 orig_width, u16 orig_height,
1028                 u16 out_width, u16 out_height,
1029                 bool ilace)
1030 {
1031         int fir_hinc;
1032         int fir_vinc;
1033         int hscaleup, vscaleup, five_taps;
1034         int fieldmode = 0;
1035         int accu0 = 0;
1036         int accu1 = 0;
1037         u32 l;
1038
1039         BUG_ON(plane == OMAP_DSS_GFX);
1040
1041         hscaleup = orig_width <= out_width;
1042         vscaleup = orig_height <= out_height;
1043         five_taps = orig_height > out_height * 2;
1044
1045         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1046
1047         if (!orig_width || orig_width == out_width)
1048                 fir_hinc = 0;
1049         else
1050                 fir_hinc = 1024 * orig_width / out_width;
1051
1052         if (!orig_height || orig_height == out_height)
1053                 fir_vinc = 0;
1054         else
1055                 fir_vinc = 1024 * orig_height / out_height;
1056
1057         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1058
1059         l = dispc_read_reg(dispc_reg_att[plane]);
1060         l &= ~((0x0f << 5) | (0x3 << 21));
1061
1062         l |= fir_hinc ? (1 << 5) : 0;
1063         l |= fir_vinc ? (1 << 6) : 0;
1064
1065         l |= hscaleup ? 0 : (1 << 7);
1066         l |= vscaleup ? 0 : (1 << 8);
1067
1068         l |= five_taps ? (1 << 21) : 0;
1069         l |= five_taps ? (1 << 22) : 0;
1070
1071         dispc_write_reg(dispc_reg_att[plane], l);
1072
1073         if (ilace) {
1074                 if (fieldmode) {
1075                         accu0 = fir_vinc / 2;
1076                         accu1 = 0;
1077                 } else {
1078                         accu0 = 0;
1079                         accu1 = fir_vinc / 2;
1080                         if (accu1 >= 1024/2) {
1081                                 accu0 = 1024/2;
1082                                 accu1 -= accu0;
1083                         }
1084                 }
1085         }
1086
1087         _dispc_set_vid_accu0(plane, 0, accu0);
1088         _dispc_set_vid_accu1(plane, 0, accu1);
1089 }
1090
1091 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1092                 bool mirroring, enum omap_color_mode color_mode)
1093 {
1094         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1095                         color_mode == OMAP_DSS_COLOR_UYVY) {
1096                 int vidrot = 0;
1097
1098                 if (mirroring) {
1099                         switch (rotation) {
1100                         case 0: vidrot = 2; break;
1101                         case 1: vidrot = 3; break;
1102                         case 2: vidrot = 0; break;
1103                         case 3: vidrot = 1; break;
1104                         }
1105                 } else {
1106                         switch (rotation) {
1107                         case 0: vidrot = 0; break;
1108                         case 1: vidrot = 1; break;
1109                         case 2: vidrot = 2; break;
1110                         case 3: vidrot = 1; break;
1111                         }
1112                 }
1113
1114                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1115
1116                 if (rotation == 1 || rotation == 3)
1117                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1118                 else
1119                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1120         } else {
1121                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1122                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1123         }
1124 }
1125
1126 static s32 pixinc(int pixels, u8 ps)
1127 {
1128         if (pixels == 1)
1129                 return 1;
1130         else if (pixels > 1)
1131                 return 1 + (pixels - 1) * ps;
1132         else if (pixels < 0)
1133                 return 1 - (-pixels + 1) * ps;
1134         else
1135                 BUG();
1136 }
1137
1138 static void calc_rotation_offset(u8 rotation, bool mirror,
1139                 u16 screen_width,
1140                 u16 width, u16 height,
1141                 enum omap_color_mode color_mode, bool fieldmode,
1142                 unsigned *offset0, unsigned *offset1,
1143                 s32 *row_inc, s32 *pix_inc)
1144 {
1145         u8 ps;
1146         u16 fbw, fbh;
1147
1148         switch (color_mode) {
1149         case OMAP_DSS_COLOR_RGB16:
1150         case OMAP_DSS_COLOR_ARGB16:
1151                 ps = 2;
1152                 break;
1153
1154         case OMAP_DSS_COLOR_RGB24P:
1155                 ps = 3;
1156                 break;
1157
1158         case OMAP_DSS_COLOR_RGB24U:
1159         case OMAP_DSS_COLOR_ARGB32:
1160         case OMAP_DSS_COLOR_RGBA32:
1161         case OMAP_DSS_COLOR_RGBX32:
1162                 ps = 4;
1163                 break;
1164
1165         case OMAP_DSS_COLOR_YUV2:
1166         case OMAP_DSS_COLOR_UYVY:
1167                 ps = 2;
1168                 break;
1169         default:
1170                 BUG();
1171                 return;
1172         }
1173
1174         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1175                         width, height);
1176
1177         /* width & height are overlay sizes, convert to fb sizes */
1178
1179         if (rotation == 0 || rotation == 2) {
1180                 fbw = width;
1181                 fbh = height;
1182         } else {
1183                 fbw = height;
1184                 fbh = width;
1185         }
1186
1187         switch (rotation + mirror * 4) {
1188         case 0:
1189                 *offset0 = 0;
1190                 if (fieldmode)
1191                         *offset1 = screen_width * ps;
1192                 else
1193                         *offset1 = 0;
1194                 *row_inc = pixinc(1 + (screen_width - fbw) +
1195                                 (fieldmode ? screen_width : 0),
1196                                 ps);
1197                 *pix_inc = pixinc(1, ps);
1198                 break;
1199         case 1:
1200                 *offset0 = screen_width * (fbh - 1) * ps;
1201                 if (fieldmode)
1202                         *offset1 = *offset0 + ps;
1203                 else
1204                         *offset1 = *offset0;
1205                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1206                                 (fieldmode ? 1 : 0), ps);
1207                 *pix_inc = pixinc(-screen_width, ps);
1208                 break;
1209         case 2:
1210                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1211                 if (fieldmode)
1212                         *offset1 = *offset0 - screen_width * ps;
1213                 else
1214                         *offset1 = *offset0;
1215                 *row_inc = pixinc(-1 -
1216                                 (screen_width - fbw) -
1217                                 (fieldmode ? screen_width : 0),
1218                                 ps);
1219                 *pix_inc = pixinc(-1, ps);
1220                 break;
1221         case 3:
1222                 *offset0 = (fbw - 1) * ps;
1223                 if (fieldmode)
1224                         *offset1 = *offset0 - ps;
1225                 else
1226                         *offset1 = *offset0;
1227                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1228                                 (fieldmode ? 1 : 0), ps);
1229                 *pix_inc = pixinc(screen_width, ps);
1230                 break;
1231
1232         /* mirroring */
1233         case 0 + 4:
1234                 *offset0 = (fbw - 1) * ps;
1235                 if (fieldmode)
1236                         *offset1 = *offset0 + screen_width * ps;
1237                 else
1238                         *offset1 = *offset0;
1239                 *row_inc = pixinc(screen_width * 2 - 1 +
1240                                 (fieldmode ? screen_width : 0),
1241                                 ps);
1242                 *pix_inc = pixinc(-1, ps);
1243                 break;
1244
1245         case 1 + 4:
1246                 *offset0 = 0;
1247                 if (fieldmode)
1248                         *offset1 = *offset0 + screen_width * ps;
1249                 else
1250                         *offset1 = *offset0;
1251                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1252                                 (fieldmode ? 1 : 0),
1253                                 ps);
1254                 *pix_inc = pixinc(screen_width, ps);
1255                 break;
1256
1257         case 2 + 4:
1258                 *offset0 = screen_width * (fbh - 1) * ps;
1259                 if (fieldmode)
1260                         *offset1 = *offset0 + screen_width * ps;
1261                 else
1262                         *offset1 = *offset0;
1263                 *row_inc = pixinc(1 - screen_width * 2 -
1264                                 (fieldmode ? screen_width : 0),
1265                                 ps);
1266                 *pix_inc = pixinc(1, ps);
1267                 break;
1268
1269         case 3 + 4:
1270                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1271                 if (fieldmode)
1272                         *offset1 = *offset0 + screen_width * ps;
1273                 else
1274                         *offset1 = *offset0;
1275                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1276                                 (fieldmode ? 1 : 0),
1277                                 ps);
1278                 *pix_inc = pixinc(-screen_width, ps);
1279                 break;
1280
1281         default:
1282                 BUG();
1283         }
1284 }
1285
1286 static int _dispc_setup_plane(enum omap_plane plane,
1287                 enum omap_channel channel_out,
1288                 u32 paddr, u16 screen_width,
1289                 u16 pos_x, u16 pos_y,
1290                 u16 width, u16 height,
1291                 u16 out_width, u16 out_height,
1292                 enum omap_color_mode color_mode,
1293                 bool ilace,
1294                 u8 rotation, int mirror)
1295 {
1296         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1297         bool five_taps = height > out_height * 2;
1298         bool fieldmode = 0;
1299         int cconv = 0;
1300         unsigned offset0, offset1;
1301         s32 row_inc;
1302         s32 pix_inc;
1303
1304         if (paddr == 0)
1305                 return -EINVAL;
1306
1307         if (plane == OMAP_DSS_GFX) {
1308                 if (width != out_width || height != out_height)
1309                         return -EINVAL;
1310
1311                 switch (color_mode) {
1312                 case OMAP_DSS_COLOR_ARGB16:
1313                 case OMAP_DSS_COLOR_RGB16:
1314                 case OMAP_DSS_COLOR_RGB24P:
1315                 case OMAP_DSS_COLOR_RGB24U:
1316                 case OMAP_DSS_COLOR_ARGB32:
1317                 case OMAP_DSS_COLOR_RGBA32:
1318                 case OMAP_DSS_COLOR_RGBX32:
1319                         break;
1320
1321                 default:
1322                         return -EINVAL;
1323                 }
1324         } else {
1325                 /* video plane */
1326                 if (width > (2048 >> five_taps))
1327                         return -EINVAL;
1328
1329                 if (out_width < width / maxdownscale ||
1330                    out_width > width * 8)
1331                         return -EINVAL;
1332
1333                 if (out_height < height / maxdownscale ||
1334                    out_height > height * 8)
1335                         return -EINVAL;
1336
1337                 switch (color_mode) {
1338                 case OMAP_DSS_COLOR_RGB16:
1339                 case OMAP_DSS_COLOR_RGB24P:
1340                 case OMAP_DSS_COLOR_RGB24U:
1341                 case OMAP_DSS_COLOR_RGBX32:
1342                         break;
1343
1344                 case OMAP_DSS_COLOR_ARGB16:
1345                 case OMAP_DSS_COLOR_ARGB32:
1346                 case OMAP_DSS_COLOR_RGBA32:
1347                         if (plane == OMAP_DSS_VIDEO1)
1348                                 return -EINVAL;
1349                         break;
1350
1351                 case OMAP_DSS_COLOR_YUV2:
1352                 case OMAP_DSS_COLOR_UYVY:
1353                         cconv = 1;
1354                         break;
1355
1356                 default:
1357                         return -EINVAL;
1358                 }
1359         }
1360
1361         if (ilace && height >= out_height)
1362                 fieldmode = 1;
1363
1364         calc_rotation_offset(rotation, mirror,
1365                         screen_width, width, height, color_mode,
1366                         fieldmode,
1367                         &offset0, &offset1, &row_inc, &pix_inc);
1368
1369         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1370                         offset0, offset1, row_inc, pix_inc);
1371
1372         if (ilace) {
1373                 if (fieldmode)
1374                         height /= 2;
1375                 pos_y /= 2;
1376                 out_height /= 2;
1377
1378                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1379                                 "out_height %d\n",
1380                                 height, pos_y, out_height);
1381         }
1382
1383         _dispc_set_channel_out(plane, channel_out);
1384         _dispc_set_color_mode(plane, color_mode);
1385
1386         _dispc_set_plane_ba0(plane, paddr + offset0);
1387         _dispc_set_plane_ba1(plane, paddr + offset1);
1388
1389         _dispc_set_row_inc(plane, row_inc);
1390         _dispc_set_pix_inc(plane, pix_inc);
1391
1392         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1393                         out_width, out_height);
1394
1395         _dispc_set_plane_pos(plane, pos_x, pos_y);
1396
1397         _dispc_set_pic_size(plane, width, height);
1398
1399         if (plane != OMAP_DSS_GFX) {
1400                 _dispc_set_scaling(plane, width, height,
1401                                    out_width, out_height,
1402                                    ilace);
1403                 _dispc_set_vid_size(plane, out_width, out_height);
1404                 _dispc_set_vid_color_conv(plane, cconv);
1405         }
1406
1407         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1408
1409         return 0;
1410 }
1411
1412 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1413 {
1414         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1415 }
1416
1417 static void dispc_disable_isr(void *data, u32 mask)
1418 {
1419         struct completion *compl = data;
1420         complete(compl);
1421 }
1422
1423 static void _enable_lcd_out(bool enable)
1424 {
1425         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1426 }
1427
1428 void dispc_enable_lcd_out(bool enable)
1429 {
1430         struct completion frame_done_completion;
1431         bool is_on;
1432         int r;
1433
1434         enable_clocks(1);
1435
1436         /* When we disable LCD output, we need to wait until frame is done.
1437          * Otherwise the DSS is still working, and turning off the clocks
1438          * prevents DSS from going to OFF mode */
1439         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1440
1441         if (!enable && is_on) {
1442                 init_completion(&frame_done_completion);
1443
1444                 r = omap_dispc_register_isr(dispc_disable_isr,
1445                                 &frame_done_completion,
1446                                 DISPC_IRQ_FRAMEDONE);
1447
1448                 if (r)
1449                         DSSERR("failed to register FRAMEDONE isr\n");
1450         }
1451
1452         _enable_lcd_out(enable);
1453
1454         if (!enable && is_on) {
1455                 if (!wait_for_completion_timeout(&frame_done_completion,
1456                                         msecs_to_jiffies(100)))
1457                         DSSERR("timeout waiting for FRAME DONE\n");
1458
1459                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1460                                 &frame_done_completion,
1461                                 DISPC_IRQ_FRAMEDONE);
1462
1463                 if (r)
1464                         DSSERR("failed to unregister FRAMEDONE isr\n");
1465         }
1466
1467         enable_clocks(0);
1468 }
1469
1470 static void _enable_digit_out(bool enable)
1471 {
1472         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1473 }
1474
1475 void dispc_enable_digit_out(bool enable)
1476 {
1477         struct completion frame_done_completion;
1478         int r;
1479
1480         enable_clocks(1);
1481
1482         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1483                 enable_clocks(0);
1484                 return;
1485         }
1486
1487         if (enable) {
1488                 /* When we enable digit output, we'll get an extra digit
1489                  * sync lost interrupt, that we need to ignore */
1490                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1491                 omap_dispc_set_irqs();
1492         }
1493
1494         /* When we disable digit output, we need to wait until fields are done.
1495          * Otherwise the DSS is still working, and turning off the clocks
1496          * prevents DSS from going to OFF mode. And when enabling, we need to
1497          * wait for the extra sync losts */
1498         init_completion(&frame_done_completion);
1499
1500         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1501                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1502         if (r)
1503                 DSSERR("failed to register EVSYNC isr\n");
1504
1505         _enable_digit_out(enable);
1506
1507         /* XXX I understand from TRM that we should only wait for the
1508          * current field to complete. But it seems we have to wait
1509          * for both fields */
1510         if (!wait_for_completion_timeout(&frame_done_completion,
1511                                 msecs_to_jiffies(100)))
1512                 DSSERR("timeout waiting for EVSYNC\n");
1513
1514         if (!wait_for_completion_timeout(&frame_done_completion,
1515                                 msecs_to_jiffies(100)))
1516                 DSSERR("timeout waiting for EVSYNC\n");
1517
1518         r = omap_dispc_unregister_isr(dispc_disable_isr,
1519                         &frame_done_completion,
1520                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1521         if (r)
1522                 DSSERR("failed to unregister EVSYNC isr\n");
1523
1524         if (enable) {
1525                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1526                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1527                 omap_dispc_set_irqs();
1528         }
1529
1530         enable_clocks(0);
1531 }
1532
1533 void dispc_lcd_enable_signal_polarity(bool act_high)
1534 {
1535         enable_clocks(1);
1536         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1537         enable_clocks(0);
1538 }
1539
1540 void dispc_lcd_enable_signal(bool enable)
1541 {
1542         enable_clocks(1);
1543         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1544         enable_clocks(0);
1545 }
1546
1547 void dispc_pck_free_enable(bool enable)
1548 {
1549         enable_clocks(1);
1550         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1551         enable_clocks(0);
1552 }
1553
1554 void dispc_enable_fifohandcheck(bool enable)
1555 {
1556         enable_clocks(1);
1557         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1558         enable_clocks(0);
1559 }
1560
1561
1562 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1563 {
1564         int mode;
1565
1566         switch (type) {
1567         case OMAP_DSS_LCD_DISPLAY_STN:
1568                 mode = 0;
1569                 break;
1570
1571         case OMAP_DSS_LCD_DISPLAY_TFT:
1572                 mode = 1;
1573                 break;
1574
1575         default:
1576                 BUG();
1577                 return;
1578         }
1579
1580         enable_clocks(1);
1581         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1582         enable_clocks(0);
1583 }
1584
1585 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1586 {
1587         enable_clocks(1);
1588         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1589         enable_clocks(0);
1590 }
1591
1592
1593 void dispc_set_default_color(enum omap_channel channel, u32 color)
1594 {
1595         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1596                                 DISPC_DEFAULT_COLOR1 };
1597
1598         enable_clocks(1);
1599         dispc_write_reg(def_reg[channel], color);
1600         enable_clocks(0);
1601 }
1602
1603 u32 dispc_get_default_color(enum omap_channel channel)
1604 {
1605         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1606                                 DISPC_DEFAULT_COLOR1 };
1607         u32 l;
1608
1609         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1610                channel != OMAP_DSS_CHANNEL_LCD);
1611
1612         enable_clocks(1);
1613         l = dispc_read_reg(def_reg[channel]);
1614         enable_clocks(0);
1615
1616         return l;
1617 }
1618
1619 void dispc_set_trans_key(enum omap_channel ch,
1620                 enum omap_dss_color_key_type type,
1621                 u32 trans_key)
1622 {
1623         const struct dispc_reg tr_reg[] = {
1624                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1625
1626         enable_clocks(1);
1627         if (ch == OMAP_DSS_CHANNEL_LCD)
1628                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1629         else /* OMAP_DSS_CHANNEL_DIGIT */
1630                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1631
1632         dispc_write_reg(tr_reg[ch], trans_key);
1633         enable_clocks(0);
1634 }
1635
1636 void dispc_get_trans_key(enum omap_channel ch,
1637                 enum omap_dss_color_key_type *type,
1638                 u32 *trans_key)
1639 {
1640         const struct dispc_reg tr_reg[] = {
1641                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1642
1643         enable_clocks(1);
1644         if (type) {
1645                 if (ch == OMAP_DSS_CHANNEL_LCD)
1646                         *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
1647                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1648                         *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
1649                 else
1650                         BUG();
1651         }
1652
1653         if (trans_key)
1654                 *trans_key = dispc_read_reg(tr_reg[ch]);
1655         enable_clocks(0);
1656 }
1657
1658 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1659 {
1660         enable_clocks(1);
1661         if (ch == OMAP_DSS_CHANNEL_LCD)
1662                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1663         else /* OMAP_DSS_CHANNEL_DIGIT */
1664                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1665         enable_clocks(0);
1666 }
1667
1668 bool dispc_trans_key_enabled(enum omap_channel ch)
1669 {
1670         bool enabled;
1671
1672         enable_clocks(1);
1673         if (ch == OMAP_DSS_CHANNEL_LCD)
1674                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1675         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1676                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1677         else BUG();
1678         enable_clocks(0);
1679
1680         return enabled;
1681 }
1682
1683
1684 void dispc_set_tft_data_lines(u8 data_lines)
1685 {
1686         int code;
1687
1688         switch (data_lines) {
1689         case 12:
1690                 code = 0;
1691                 break;
1692         case 16:
1693                 code = 1;
1694                 break;
1695         case 18:
1696                 code = 2;
1697                 break;
1698         case 24:
1699                 code = 3;
1700                 break;
1701         default:
1702                 BUG();
1703                 return;
1704         }
1705
1706         enable_clocks(1);
1707         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1708         enable_clocks(0);
1709 }
1710
1711 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1712 {
1713         u32 l;
1714         int stallmode;
1715         int gpout0 = 1;
1716         int gpout1;
1717
1718         switch (mode) {
1719         case OMAP_DSS_PARALLELMODE_BYPASS:
1720                 stallmode = 0;
1721                 gpout1 = 1;
1722                 break;
1723
1724         case OMAP_DSS_PARALLELMODE_RFBI:
1725                 stallmode = 1;
1726                 gpout1 = 0;
1727                 break;
1728
1729         case OMAP_DSS_PARALLELMODE_DSI:
1730                 stallmode = 1;
1731                 gpout1 = 1;
1732                 break;
1733
1734         default:
1735                 BUG();
1736                 return;
1737         }
1738
1739         enable_clocks(1);
1740
1741         l = dispc_read_reg(DISPC_CONTROL);
1742
1743         l = FLD_MOD(l, stallmode, 11, 11);
1744         l = FLD_MOD(l, gpout0, 15, 15);
1745         l = FLD_MOD(l, gpout1, 16, 16);
1746
1747         dispc_write_reg(DISPC_CONTROL, l);
1748
1749         enable_clocks(0);
1750 }
1751
1752 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1753                                    int vsw, int vfp, int vbp)
1754 {
1755         u32 timing_h, timing_v;
1756
1757         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1758                 BUG_ON(hsw < 1 || hsw > 64);
1759                 BUG_ON(hfp < 1 || hfp > 256);
1760                 BUG_ON(hbp < 1 || hbp > 256);
1761
1762                 BUG_ON(vsw < 1 || vsw > 64);
1763                 BUG_ON(vfp < 0 || vfp > 255);
1764                 BUG_ON(vbp < 0 || vbp > 255);
1765
1766                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1767                         FLD_VAL(hbp-1, 27, 20);
1768
1769                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1770                         FLD_VAL(vbp, 27, 20);
1771         } else {
1772                 BUG_ON(hsw < 1 || hsw > 256);
1773                 BUG_ON(hfp < 1 || hfp > 4096);
1774                 BUG_ON(hbp < 1 || hbp > 4096);
1775
1776                 BUG_ON(vsw < 1 || vsw > 256);
1777                 BUG_ON(vfp < 0 || vfp > 4095);
1778                 BUG_ON(vbp < 0 || vbp > 4095);
1779
1780                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1781                         FLD_VAL(hbp-1, 31, 20);
1782
1783                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1784                         FLD_VAL(vbp, 31, 20);
1785         }
1786
1787         enable_clocks(1);
1788         dispc_write_reg(DISPC_TIMING_H, timing_h);
1789         dispc_write_reg(DISPC_TIMING_V, timing_v);
1790         enable_clocks(0);
1791 }
1792
1793 /* change name to mode? */
1794 void dispc_set_lcd_timings(struct omap_video_timings *timings)
1795 {
1796         unsigned xtot, ytot;
1797         unsigned long ht, vt;
1798
1799         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
1800                         timings->vsw, timings->vfp, timings->vbp);
1801
1802         dispc_set_lcd_size(timings->x_res, timings->y_res);
1803
1804         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
1805         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
1806
1807         ht = (timings->pixel_clock * 1000) / xtot;
1808         vt = (timings->pixel_clock * 1000) / xtot / ytot;
1809
1810         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
1811         DSSDBG("pck %u\n", timings->pixel_clock);
1812         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
1813                         timings->hsw, timings->hfp, timings->hbp,
1814                         timings->vsw, timings->vfp, timings->vbp);
1815
1816         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
1817 }
1818
1819 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
1820 {
1821         BUG_ON(lck_div < 1);
1822         BUG_ON(pck_div < 2);
1823
1824         enable_clocks(1);
1825         dispc_write_reg(DISPC_DIVISOR,
1826                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
1827         enable_clocks(0);
1828 }
1829
1830 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
1831 {
1832         u32 l;
1833         l = dispc_read_reg(DISPC_DIVISOR);
1834         *lck_div = FLD_GET(l, 23, 16);
1835         *pck_div = FLD_GET(l, 7, 0);
1836 }
1837
1838 unsigned long dispc_fclk_rate(void)
1839 {
1840         unsigned long r = 0;
1841
1842         if (dss_get_dispc_clk_source() == 0)
1843                 r = dss_clk_get_rate(DSS_CLK_FCK1);
1844         else
1845 #ifdef CONFIG_OMAP2_DSS_DSI
1846                 r = dsi_get_dsi1_pll_rate();
1847 #else
1848         BUG();
1849 #endif
1850         return r;
1851 }
1852
1853 unsigned long dispc_lclk_rate(void)
1854 {
1855         int lcd;
1856         unsigned long r;
1857         u32 l;
1858
1859         l = dispc_read_reg(DISPC_DIVISOR);
1860
1861         lcd = FLD_GET(l, 23, 16);
1862
1863         r = dispc_fclk_rate();
1864
1865         return r / lcd;
1866 }
1867
1868 unsigned long dispc_pclk_rate(void)
1869 {
1870         int lcd, pcd;
1871         unsigned long r;
1872         u32 l;
1873
1874         l = dispc_read_reg(DISPC_DIVISOR);
1875
1876         lcd = FLD_GET(l, 23, 16);
1877         pcd = FLD_GET(l, 7, 0);
1878
1879         r = dispc_fclk_rate();
1880
1881         return r / lcd / pcd;
1882 }
1883
1884 void dispc_dump_clocks(struct seq_file *s)
1885 {
1886         int lcd, pcd;
1887
1888         enable_clocks(1);
1889
1890         dispc_get_lcd_divisor(&lcd, &pcd);
1891
1892         seq_printf(s, "- dispc -\n");
1893
1894         seq_printf(s, "dispc fclk source = %s\n",
1895                         dss_get_dispc_clk_source() == 0 ?
1896                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
1897
1898         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
1899                         dispc_fclk_rate(),
1900                         lcd, pcd,
1901                         dispc_pclk_rate());
1902
1903         enable_clocks(0);
1904 }
1905
1906 void dispc_dump_regs(struct seq_file *s)
1907 {
1908 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
1909
1910         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1911
1912         DUMPREG(DISPC_REVISION);
1913         DUMPREG(DISPC_SYSCONFIG);
1914         DUMPREG(DISPC_SYSSTATUS);
1915         DUMPREG(DISPC_IRQSTATUS);
1916         DUMPREG(DISPC_IRQENABLE);
1917         DUMPREG(DISPC_CONTROL);
1918         DUMPREG(DISPC_CONFIG);
1919         DUMPREG(DISPC_CAPABLE);
1920         DUMPREG(DISPC_DEFAULT_COLOR0);
1921         DUMPREG(DISPC_DEFAULT_COLOR1);
1922         DUMPREG(DISPC_TRANS_COLOR0);
1923         DUMPREG(DISPC_TRANS_COLOR1);
1924         DUMPREG(DISPC_LINE_STATUS);
1925         DUMPREG(DISPC_LINE_NUMBER);
1926         DUMPREG(DISPC_TIMING_H);
1927         DUMPREG(DISPC_TIMING_V);
1928         DUMPREG(DISPC_POL_FREQ);
1929         DUMPREG(DISPC_DIVISOR);
1930         DUMPREG(DISPC_GLOBAL_ALPHA);
1931         DUMPREG(DISPC_SIZE_DIG);
1932         DUMPREG(DISPC_SIZE_LCD);
1933
1934         DUMPREG(DISPC_GFX_BA0);
1935         DUMPREG(DISPC_GFX_BA1);
1936         DUMPREG(DISPC_GFX_POSITION);
1937         DUMPREG(DISPC_GFX_SIZE);
1938         DUMPREG(DISPC_GFX_ATTRIBUTES);
1939         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
1940         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
1941         DUMPREG(DISPC_GFX_ROW_INC);
1942         DUMPREG(DISPC_GFX_PIXEL_INC);
1943         DUMPREG(DISPC_GFX_WINDOW_SKIP);
1944         DUMPREG(DISPC_GFX_TABLE_BA);
1945
1946         DUMPREG(DISPC_DATA_CYCLE1);
1947         DUMPREG(DISPC_DATA_CYCLE2);
1948         DUMPREG(DISPC_DATA_CYCLE3);
1949
1950         DUMPREG(DISPC_CPR_COEF_R);
1951         DUMPREG(DISPC_CPR_COEF_G);
1952         DUMPREG(DISPC_CPR_COEF_B);
1953
1954         DUMPREG(DISPC_GFX_PRELOAD);
1955
1956         DUMPREG(DISPC_VID_BA0(0));
1957         DUMPREG(DISPC_VID_BA1(0));
1958         DUMPREG(DISPC_VID_POSITION(0));
1959         DUMPREG(DISPC_VID_SIZE(0));
1960         DUMPREG(DISPC_VID_ATTRIBUTES(0));
1961         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
1962         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
1963         DUMPREG(DISPC_VID_ROW_INC(0));
1964         DUMPREG(DISPC_VID_PIXEL_INC(0));
1965         DUMPREG(DISPC_VID_FIR(0));
1966         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
1967         DUMPREG(DISPC_VID_ACCU0(0));
1968         DUMPREG(DISPC_VID_ACCU1(0));
1969
1970         DUMPREG(DISPC_VID_BA0(1));
1971         DUMPREG(DISPC_VID_BA1(1));
1972         DUMPREG(DISPC_VID_POSITION(1));
1973         DUMPREG(DISPC_VID_SIZE(1));
1974         DUMPREG(DISPC_VID_ATTRIBUTES(1));
1975         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
1976         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
1977         DUMPREG(DISPC_VID_ROW_INC(1));
1978         DUMPREG(DISPC_VID_PIXEL_INC(1));
1979         DUMPREG(DISPC_VID_FIR(1));
1980         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
1981         DUMPREG(DISPC_VID_ACCU0(1));
1982         DUMPREG(DISPC_VID_ACCU1(1));
1983
1984         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
1985         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
1986         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
1987         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
1988         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
1989         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
1990         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
1991         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
1992         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
1993         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
1994         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
1995         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
1996         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
1997         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
1998         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
1999         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2000         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2001         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2002         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2003         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2004         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2005         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2006         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2007         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2008         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2009         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2010         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2011         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2012         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2013
2014         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2015         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2016         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2017         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2018         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2019         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2020         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2021         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2022         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2023         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2024         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2025         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2026         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2027         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2028         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2029         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2030         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2031         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2032         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2033         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2034         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2035         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2036         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2037         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2038         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2039         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2040         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2041         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2042         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2043
2044         DUMPREG(DISPC_VID_PRELOAD(0));
2045         DUMPREG(DISPC_VID_PRELOAD(1));
2046
2047         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2048 #undef DUMPREG
2049 }
2050
2051 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2052                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2053 {
2054         u32 l = 0;
2055
2056         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2057                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2058
2059         l |= FLD_VAL(onoff, 17, 17);
2060         l |= FLD_VAL(rf, 16, 16);
2061         l |= FLD_VAL(ieo, 15, 15);
2062         l |= FLD_VAL(ipc, 14, 14);
2063         l |= FLD_VAL(ihs, 13, 13);
2064         l |= FLD_VAL(ivs, 12, 12);
2065         l |= FLD_VAL(acbi, 11, 8);
2066         l |= FLD_VAL(acb, 7, 0);
2067
2068         enable_clocks(1);
2069         dispc_write_reg(DISPC_POL_FREQ, l);
2070         enable_clocks(0);
2071 }
2072
2073 void dispc_set_pol_freq(struct omap_panel *panel)
2074 {
2075         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2076                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2077                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2078                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2079                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2080                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2081                                  panel->acbi, panel->acb);
2082 }
2083
2084 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2085                 u16 *lck_div, u16 *pck_div)
2086 {
2087         u16 pcd_min = is_tft ? 2 : 3;
2088         unsigned long best_pck;
2089         u16 best_ld, cur_ld;
2090         u16 best_pd, cur_pd;
2091
2092         best_pck = 0;
2093         best_ld = 0;
2094         best_pd = 0;
2095
2096         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2097                 unsigned long lck = fck / cur_ld;
2098
2099                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2100                         unsigned long pck = lck / cur_pd;
2101                         long old_delta = abs(best_pck - req_pck);
2102                         long new_delta = abs(pck - req_pck);
2103
2104                         if (best_pck == 0 || new_delta < old_delta) {
2105                                 best_pck = pck;
2106                                 best_ld = cur_ld;
2107                                 best_pd = cur_pd;
2108
2109                                 if (pck == req_pck)
2110                                         goto found;
2111                         }
2112
2113                         if (pck < req_pck)
2114                                 break;
2115                 }
2116
2117                 if (lck / pcd_min < req_pck)
2118                         break;
2119         }
2120
2121 found:
2122         *lck_div = best_ld;
2123         *pck_div = best_pd;
2124 }
2125
2126 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2127                 struct dispc_clock_info *cinfo)
2128 {
2129         unsigned long prate;
2130         struct dispc_clock_info cur, best;
2131         int match = 0;
2132         int min_fck_per_pck;
2133         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2134
2135         if (cpu_is_omap34xx())
2136                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2137         else
2138                 prate = 0;
2139
2140         if (req_pck == dispc.cache_req_pck &&
2141                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2142                          dispc.cache_cinfo.fck == fck_rate)) {
2143                 DSSDBG("dispc clock info found from cache.\n");
2144                 *cinfo = dispc.cache_cinfo;
2145                 return 0;
2146         }
2147
2148         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2149
2150         if (min_fck_per_pck &&
2151                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2152                 DSSERR("Requested pixel clock not possible with the current "
2153                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2154                                 "the constraint off.\n");
2155                 min_fck_per_pck = 0;
2156         }
2157
2158 retry:
2159         memset(&cur, 0, sizeof(cur));
2160         memset(&best, 0, sizeof(best));
2161
2162         if (cpu_is_omap24xx()) {
2163                 /* XXX can we change the clock on omap2? */
2164                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2165                 cur.fck_div = 1;
2166
2167                 match = 1;
2168
2169                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2170                                 &cur.lck_div, &cur.pck_div);
2171
2172                 cur.lck = cur.fck / cur.lck_div;
2173                 cur.pck = cur.lck / cur.pck_div;
2174
2175                 best = cur;
2176
2177                 goto found;
2178         } else if (cpu_is_omap34xx()) {
2179                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2180                         cur.fck = prate / cur.fck_div * 2;
2181
2182                         if (cur.fck > DISPC_MAX_FCK)
2183                                 continue;
2184
2185                         if (min_fck_per_pck &&
2186                                         cur.fck < req_pck * min_fck_per_pck)
2187                                 continue;
2188
2189                         match = 1;
2190
2191                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2192                                         &cur.lck_div, &cur.pck_div);
2193
2194                         cur.lck = cur.fck / cur.lck_div;
2195                         cur.pck = cur.lck / cur.pck_div;
2196
2197                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2198                                 best = cur;
2199
2200                                 if (cur.pck == req_pck)
2201                                         goto found;
2202                         }
2203                 }
2204         } else {
2205                 BUG();
2206         }
2207
2208 found:
2209         if (!match) {
2210                 if (min_fck_per_pck) {
2211                         DSSERR("Could not find suitable clock settings.\n"
2212                                         "Turning FCK/PCK constraint off and"
2213                                         "trying again.\n");
2214                         min_fck_per_pck = 0;
2215                         goto retry;
2216                 }
2217
2218                 DSSERR("Could not find suitable clock settings.\n");
2219
2220                 return -EINVAL;
2221         }
2222
2223         if (cinfo)
2224                 *cinfo = best;
2225
2226         dispc.cache_req_pck = req_pck;
2227         dispc.cache_prate = prate;
2228         dispc.cache_cinfo = best;
2229
2230         return 0;
2231 }
2232
2233 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2234 {
2235         unsigned long prate;
2236         int r;
2237
2238         if (cpu_is_omap34xx()) {
2239                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2240                 DSSDBG("dpll4_m4 = %ld\n", prate);
2241         }
2242
2243         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2244         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2245         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2246
2247         if (cpu_is_omap34xx()) {
2248                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2249                 if (r)
2250                         return r;
2251         }
2252
2253         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2254
2255         return 0;
2256 }
2257
2258 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2259 {
2260         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2261
2262         if (cpu_is_omap34xx()) {
2263                 unsigned long prate;
2264                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2265                 cinfo->fck_div = prate / (cinfo->fck / 2);
2266         } else {
2267                 cinfo->fck_div = 0;
2268         }
2269
2270         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2271         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2272
2273         cinfo->lck = cinfo->fck / cinfo->lck_div;
2274         cinfo->pck = cinfo->lck / cinfo->pck_div;
2275
2276         return 0;
2277 }
2278
2279 static void omap_dispc_set_irqs(void)
2280 {
2281         unsigned long flags;
2282         u32 mask = dispc.irq_error_mask;
2283         int i;
2284         struct omap_dispc_isr_data *isr_data;
2285
2286         spin_lock_irqsave(&dispc.irq_lock, flags);
2287
2288         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2289                 isr_data = &dispc.registered_isr[i];
2290
2291                 if (isr_data->isr == NULL)
2292                         continue;
2293
2294                 mask |= isr_data->mask;
2295         }
2296
2297         enable_clocks(1);
2298         dispc_write_reg(DISPC_IRQENABLE, mask);
2299         enable_clocks(0);
2300
2301         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2302 }
2303
2304 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2305 {
2306         int i;
2307         int ret;
2308         unsigned long flags;
2309         struct omap_dispc_isr_data *isr_data;
2310
2311         if (isr == NULL)
2312                 return -EINVAL;
2313
2314         spin_lock_irqsave(&dispc.irq_lock, flags);
2315
2316         /* check for duplicate entry */
2317         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2318                 isr_data = &dispc.registered_isr[i];
2319                 if (isr_data->isr == isr && isr_data->arg == arg &&
2320                                 isr_data->mask == mask) {
2321                         ret = -EINVAL;
2322                         goto err;
2323                 }
2324         }
2325
2326         isr_data = NULL;
2327         ret = -EBUSY;
2328
2329         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2330                 isr_data = &dispc.registered_isr[i];
2331
2332                 if (isr_data->isr != NULL)
2333                         continue;
2334
2335                 isr_data->isr = isr;
2336                 isr_data->arg = arg;
2337                 isr_data->mask = mask;
2338                 ret = 0;
2339
2340                 break;
2341         }
2342 err:
2343         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2344
2345         if (ret == 0)
2346                 omap_dispc_set_irqs();
2347
2348         return ret;
2349 }
2350 EXPORT_SYMBOL(omap_dispc_register_isr);
2351
2352 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2353 {
2354         int i;
2355         unsigned long flags;
2356         int ret = -EINVAL;
2357         struct omap_dispc_isr_data *isr_data;
2358
2359         spin_lock_irqsave(&dispc.irq_lock, flags);
2360
2361         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2362                 isr_data = &dispc.registered_isr[i];
2363                 if (isr_data->isr != isr || isr_data->arg != arg ||
2364                                 isr_data->mask != mask)
2365                         continue;
2366
2367                 /* found the correct isr */
2368
2369                 isr_data->isr = NULL;
2370                 isr_data->arg = NULL;
2371                 isr_data->mask = 0;
2372
2373                 ret = 0;
2374                 break;
2375         }
2376
2377         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2378
2379         if (ret == 0)
2380                 omap_dispc_set_irqs();
2381
2382         return ret;
2383 }
2384 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2385
2386 #ifdef DEBUG
2387 static void print_irq_status(u32 status)
2388 {
2389         if ((status & dispc.irq_error_mask) == 0)
2390                 return;
2391
2392         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2393
2394 #define PIS(x) \
2395         if (status & DISPC_IRQ_##x) \
2396                 printk(#x " ");
2397         PIS(GFX_FIFO_UNDERFLOW);
2398         PIS(OCP_ERR);
2399         PIS(VID1_FIFO_UNDERFLOW);
2400         PIS(VID2_FIFO_UNDERFLOW);
2401         PIS(SYNC_LOST);
2402         PIS(SYNC_LOST_DIGIT);
2403 #undef PIS
2404
2405         printk("\n");
2406 }
2407 #endif
2408
2409 /* Called from dss.c. Note that we don't touch clocks here,
2410  * but we presume they are on because we got an IRQ. However,
2411  * an irq handler may turn the clocks off, so we may not have
2412  * clock later in the function. */
2413 void dispc_irq_handler(void)
2414 {
2415         int i;
2416         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2417         u32 handledirqs = 0;
2418         u32 unhandled_errors;
2419         struct omap_dispc_isr_data *isr_data;
2420
2421 #ifdef DEBUG
2422         if (dss_debug)
2423                 print_irq_status(irqstatus);
2424 #endif
2425         /* Ack the interrupt. Do it here before clocks are possibly turned
2426          * off */
2427         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2428
2429         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2430                 isr_data = &dispc.registered_isr[i];
2431
2432                 if (!isr_data->isr)
2433                         continue;
2434
2435                 if (isr_data->mask & irqstatus) {
2436                         isr_data->isr(isr_data->arg, irqstatus);
2437                         handledirqs |= isr_data->mask;
2438                 }
2439         }
2440
2441         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2442
2443         if (unhandled_errors) {
2444                 spin_lock(&dispc.error_lock);
2445                 dispc.error_irqs |= unhandled_errors;
2446                 spin_unlock(&dispc.error_lock);
2447
2448                 dispc.irq_error_mask &= ~unhandled_errors;
2449                 omap_dispc_set_irqs();
2450
2451                 schedule_work(&dispc.error_work);
2452         }
2453 }
2454
2455 static void dispc_error_worker(struct work_struct *work)
2456 {
2457         int i;
2458         u32 errors;
2459         unsigned long flags;
2460
2461         spin_lock_irqsave(&dispc.error_lock, flags);
2462         errors = dispc.error_irqs;
2463         dispc.error_irqs = 0;
2464         spin_unlock_irqrestore(&dispc.error_lock, flags);
2465
2466         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2467                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2468                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2469                         struct omap_overlay *ovl;
2470                         ovl = omap_dss_get_overlay(i);
2471
2472                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2473                                 continue;
2474
2475                         if (ovl->id == 0) {
2476                                 dispc_enable_plane(ovl->id, 0);
2477                                 dispc_go(ovl->manager->id);
2478                                 mdelay(50);
2479                                 break;
2480                         }
2481                 }
2482         }
2483
2484         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2485                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2486                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2487                         struct omap_overlay *ovl;
2488                         ovl = omap_dss_get_overlay(i);
2489
2490                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2491                                 continue;
2492
2493                         if (ovl->id == 1) {
2494                                 dispc_enable_plane(ovl->id, 0);
2495                                 dispc_go(ovl->manager->id);
2496                                 mdelay(50);
2497                                 break;
2498                         }
2499                 }
2500         }
2501
2502         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2503                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2504                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2505                         struct omap_overlay *ovl;
2506                         ovl = omap_dss_get_overlay(i);
2507
2508                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2509                                 continue;
2510
2511                         if (ovl->id == 2) {
2512                                 dispc_enable_plane(ovl->id, 0);
2513                                 dispc_go(ovl->manager->id);
2514                                 mdelay(50);
2515                                 break;
2516                         }
2517                 }
2518         }
2519
2520         if (errors & DISPC_IRQ_SYNC_LOST) {
2521                 struct omap_overlay_manager *manager = NULL;
2522                 bool enable = false;
2523
2524                 DSSERR("SYNC_LOST, disabling LCD\n");
2525
2526                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2527                         struct omap_overlay_manager *mgr;
2528                         mgr = omap_dss_get_overlay_manager(i);
2529
2530                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2531                                 manager = mgr;
2532                                 enable = mgr->display->state ==
2533                                                 OMAP_DSS_DISPLAY_ACTIVE;
2534                                 mgr->display->disable(mgr->display);
2535                                 break;
2536                         }
2537                 }
2538
2539                 if (manager) {
2540                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2541                                 struct omap_overlay *ovl;
2542                                 ovl = omap_dss_get_overlay(i);
2543
2544                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2545                                         continue;
2546
2547                                 if (ovl->id != 0 && ovl->manager == manager)
2548                                         dispc_enable_plane(ovl->id, 0);
2549                         }
2550
2551                         dispc_go(manager->id);
2552                         mdelay(50);
2553                         if (enable)
2554                                 manager->display->enable(manager->display);
2555                 }
2556         }
2557
2558         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2559                 struct omap_overlay_manager *manager = NULL;
2560                 bool enable = false;
2561
2562                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2563
2564                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2565                         struct omap_overlay_manager *mgr;
2566                         mgr = omap_dss_get_overlay_manager(i);
2567
2568                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2569                                 manager = mgr;
2570                                 enable = mgr->display->state ==
2571                                                 OMAP_DSS_DISPLAY_ACTIVE;
2572                                 mgr->display->disable(mgr->display);
2573                                 break;
2574                         }
2575                 }
2576
2577                 if (manager) {
2578                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2579                                 struct omap_overlay *ovl;
2580                                 ovl = omap_dss_get_overlay(i);
2581
2582                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2583                                         continue;
2584
2585                                 if (ovl->id != 0 && ovl->manager == manager)
2586                                         dispc_enable_plane(ovl->id, 0);
2587                         }
2588
2589                         dispc_go(manager->id);
2590                         mdelay(50);
2591                         if (enable)
2592                                 manager->display->enable(manager->display);
2593                 }
2594         }
2595
2596         if (errors & DISPC_IRQ_OCP_ERR) {
2597                 DSSERR("OCP_ERR\n");
2598                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2599                         struct omap_overlay_manager *mgr;
2600                         mgr = omap_dss_get_overlay_manager(i);
2601
2602                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2603                                 mgr->display->disable(mgr->display);
2604                 }
2605         }
2606
2607         dispc.irq_error_mask |= errors;
2608         omap_dispc_set_irqs();
2609 }
2610
2611 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2612 {
2613         void dispc_irq_wait_handler(void *data, u32 mask)
2614         {
2615                 complete((struct completion *)data);
2616         }
2617
2618         int r;
2619         DECLARE_COMPLETION_ONSTACK(completion);
2620
2621         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2622                         irqmask);
2623
2624         if (r)
2625                 return r;
2626
2627         timeout = wait_for_completion_timeout(&completion, timeout);
2628
2629         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2630
2631         if (timeout == 0)
2632                 return -ETIMEDOUT;
2633
2634         if (timeout == -ERESTARTSYS)
2635                 return -ERESTARTSYS;
2636
2637         return 0;
2638 }
2639
2640 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2641                 unsigned long timeout)
2642 {
2643         void dispc_irq_wait_handler(void *data, u32 mask)
2644         {
2645                 complete((struct completion *)data);
2646         }
2647
2648         int r;
2649         DECLARE_COMPLETION_ONSTACK(completion);
2650
2651         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2652                         irqmask);
2653
2654         if (r)
2655                 return r;
2656
2657         timeout = wait_for_completion_interruptible_timeout(&completion,
2658                         timeout);
2659
2660         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2661
2662         if (timeout == 0)
2663                 return -ETIMEDOUT;
2664
2665         if (timeout == -ERESTARTSYS)
2666                 return -ERESTARTSYS;
2667
2668         return 0;
2669 }
2670
2671 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2672 void dispc_fake_vsync_irq(void)
2673 {
2674         u32 irqstatus = DISPC_IRQ_VSYNC;
2675         int i;
2676
2677         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2678                 struct omap_dispc_isr_data *isr_data;
2679                 isr_data = &dispc.registered_isr[i];
2680
2681                 if (!isr_data->isr)
2682                         continue;
2683
2684                 if (isr_data->mask & irqstatus)
2685                         isr_data->isr(isr_data->arg, irqstatus);
2686         }
2687 }
2688 #endif
2689
2690 static void _omap_dispc_initialize_irq(void)
2691 {
2692         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2693
2694         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2695
2696         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2697          * so clear it */
2698         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2699
2700         omap_dispc_set_irqs();
2701 }
2702
2703 static void _omap_dispc_initial_config(void)
2704 {
2705         u32 l;
2706
2707         l = dispc_read_reg(DISPC_SYSCONFIG);
2708         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2709         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2710         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2711         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2712         dispc_write_reg(DISPC_SYSCONFIG, l);
2713
2714         /* FUNCGATED */
2715         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2716
2717         /* L3 firewall setting: enable access to OCM RAM */
2718         if (cpu_is_omap24xx())
2719                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2720
2721         _dispc_setup_color_conv_coef();
2722
2723         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2724 }
2725
2726 int dispc_init(void)
2727 {
2728         u32 rev;
2729
2730         spin_lock_init(&dispc.irq_lock);
2731         spin_lock_init(&dispc.error_lock);
2732
2733         INIT_WORK(&dispc.error_work, dispc_error_worker);
2734
2735         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2736         if (!dispc.base) {
2737                 DSSERR("can't ioremap DISPC\n");
2738                 return -ENOMEM;
2739         }
2740
2741         if (cpu_is_omap34xx()) {
2742                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2743                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2744                         DSSERR("Failed to get dpll4_m4_ck\n");
2745                         return -ENODEV;
2746                 }
2747         }
2748
2749         enable_clocks(1);
2750
2751         _omap_dispc_initial_config();
2752
2753         _omap_dispc_initialize_irq();
2754
2755         dispc_save_context();
2756
2757         rev = dispc_read_reg(DISPC_REVISION);
2758         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2759                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2760
2761         enable_clocks(0);
2762
2763         return 0;
2764 }
2765
2766 void dispc_exit(void)
2767 {
2768         if (cpu_is_omap34xx())
2769                 clk_put(dispc.dpll4_m4_ck);
2770         iounmap(dispc.base);
2771 }
2772
2773 int dispc_enable_plane(enum omap_plane plane, bool enable)
2774 {
2775         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2776
2777         enable_clocks(1);
2778         _dispc_enable_plane(plane, enable);
2779         enable_clocks(0);
2780
2781         return 0;
2782 }
2783
2784 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
2785                        u32 paddr, u16 screen_width,
2786                        u16 pos_x, u16 pos_y,
2787                        u16 width, u16 height,
2788                        u16 out_width, u16 out_height,
2789                        enum omap_color_mode color_mode,
2790                        bool ilace,
2791                        u8 rotation, bool mirror)
2792 {
2793         int r = 0;
2794
2795         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
2796                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
2797                plane, channel_out, paddr, screen_width, pos_x, pos_y,
2798                width, height,
2799                out_width, out_height,
2800                ilace, color_mode,
2801                rotation, mirror);
2802
2803         enable_clocks(1);
2804
2805         r = _dispc_setup_plane(plane, channel_out,
2806                            paddr, screen_width,
2807                            pos_x, pos_y,
2808                            width, height,
2809                            out_width, out_height,
2810                            color_mode, ilace,
2811                            rotation, mirror);
2812
2813         enable_clocks(0);
2814
2815         return r;
2816 }
2817
2818 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
2819                                  int x2, int y2, int w2, int h2)
2820 {
2821         if (x1 >= (x2+w2))
2822                 return 0;
2823
2824         if ((x1+w1) <= x2)
2825                 return 0;
2826
2827         if (y1 >= (y2+h2))
2828                 return 0;
2829
2830         if ((y1+h1) <= y2)
2831                 return 0;
2832
2833         return 1;
2834 }
2835
2836 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
2837 {
2838         if (pi->width != pi->out_width)
2839                 return 1;
2840
2841         if (pi->height != pi->out_height)
2842                 return 1;
2843
2844         return 0;
2845 }
2846
2847 /* returns the area that needs updating */
2848 void dispc_setup_partial_planes(struct omap_display *display,
2849                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
2850 {
2851         struct omap_overlay_manager *mgr;
2852         int i;
2853
2854         int x, y, w, h;
2855
2856         x = *xi;
2857         y = *yi;
2858         w = *wi;
2859         h = *hi;
2860
2861         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
2862                 *xi, *yi, *wi, *hi);
2863
2864
2865         mgr = display->manager;
2866
2867         if (!mgr) {
2868                 DSSDBG("no manager\n");
2869                 return;
2870         }
2871
2872         for (i = 0; i < mgr->num_overlays; i++) {
2873                 struct omap_overlay *ovl;
2874                 struct omap_overlay_info *pi;
2875                 ovl = mgr->overlays[i];
2876
2877                 if (ovl->manager != mgr)
2878                         continue;
2879
2880                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2881                         continue;
2882
2883                 pi = &ovl->info;
2884
2885                 if (!pi->enabled)
2886                         continue;
2887                 /*
2888                  * If the plane is intersecting and scaled, we
2889                  * enlarge the update region to accomodate the
2890                  * whole area
2891                  */
2892
2893                 if (dispc_is_intersecting(x, y, w, h,
2894                                           pi->pos_x, pi->pos_y,
2895                                           pi->out_width, pi->out_height)) {
2896                         if (dispc_is_overlay_scaled(pi)) {
2897
2898                                 int x1, y1, x2, y2;
2899
2900                                 if (x > pi->pos_x)
2901                                         x1 = pi->pos_x;
2902                                 else
2903                                         x1 = x;
2904
2905                                 if (y > pi->pos_y)
2906                                         y1 = pi->pos_y;
2907                                 else
2908                                         y1 = y;
2909
2910                                 if ((x + w) < (pi->pos_x + pi->out_width))
2911                                         x2 = pi->pos_x + pi->out_width;
2912                                 else
2913                                         x2 = x + w;
2914
2915                                 if ((y + h) < (pi->pos_y + pi->out_height))
2916                                         y2 = pi->pos_y + pi->out_height;
2917                                 else
2918                                         y2 = y + h;
2919
2920                                 x = x1;
2921                                 y = y1;
2922                                 w = x2 - x1;
2923                                 h = y2 - y1;
2924
2925                                 DSSDBG("Update area after enlarge due to "
2926                                         "scaling %d, %d %dx%d\n",
2927                                         x, y, w, h);
2928                         }
2929                 }
2930         }
2931
2932         for (i = 0; i < mgr->num_overlays; i++) {
2933                 struct omap_overlay *ovl = mgr->overlays[i];
2934                 struct omap_overlay_info *pi = &ovl->info;
2935
2936                 int px = pi->pos_x;
2937                 int py = pi->pos_y;
2938                 int pw = pi->width;
2939                 int ph = pi->height;
2940                 int pow = pi->out_width;
2941                 int poh = pi->out_height;
2942                 u32 pa = pi->paddr;
2943                 int psw = pi->screen_width;
2944                 int bpp;
2945
2946                 if (ovl->manager != mgr)
2947                         continue;
2948
2949                 /*
2950                  * If plane is not enabled or the update region
2951                  * does not intersect with the plane in question,
2952                  * we really disable the plane from hardware
2953                  */
2954
2955                 if (!pi->enabled ||
2956                     !dispc_is_intersecting(x, y, w, h,
2957                                            px, py, pow, poh)) {
2958                         dispc_enable_plane(ovl->id, 0);
2959                         continue;
2960                 }
2961
2962                 switch (pi->color_mode) {
2963                 case OMAP_DSS_COLOR_RGB16:
2964                 case OMAP_DSS_COLOR_ARGB16:
2965                 case OMAP_DSS_COLOR_YUV2:
2966                 case OMAP_DSS_COLOR_UYVY:
2967                         bpp = 16;
2968                         break;
2969
2970                 case OMAP_DSS_COLOR_RGB24P:
2971                         bpp = 24;
2972                         break;
2973
2974                 case OMAP_DSS_COLOR_RGB24U:
2975                 case OMAP_DSS_COLOR_ARGB32:
2976                 case OMAP_DSS_COLOR_RGBA32:
2977                 case OMAP_DSS_COLOR_RGBX32:
2978                         bpp = 32;
2979                         break;
2980
2981                 default:
2982                         BUG();
2983                         return;
2984                 }
2985
2986                 if (x > pi->pos_x) {
2987                         px = 0;
2988                         pw -= (x - pi->pos_x);
2989                         pa += (x - pi->pos_x) * bpp / 8;
2990                 } else {
2991                         px = pi->pos_x - x;
2992                 }
2993
2994                 if (y > pi->pos_y) {
2995                         py = 0;
2996                         ph -= (y - pi->pos_y);
2997                         pa += (y - pi->pos_y) * psw * bpp / 8;
2998                 } else {
2999                         py = pi->pos_y - y;
3000                 }
3001
3002                 if (w < (px+pw))
3003                         pw -= (px+pw) - (w);
3004
3005                 if (h < (py+ph))
3006                         ph -= (py+ph) - (h);
3007
3008                 /* Can't scale the GFX plane */
3009                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3010                                 dispc_is_overlay_scaled(pi) == 0) {
3011                         pow = pw;
3012                         poh = ph;
3013                 }
3014
3015                 DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3016                                 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3017
3018                 dispc_setup_plane(ovl->id, mgr->id,
3019                                 pa, psw,
3020                                 px, py,
3021                                 pw, ph,
3022                                 pow, poh,
3023                                 pi->color_mode, 0,
3024                                 pi->rotation, // XXX rotation probably wrong
3025                                 pi->mirror);
3026
3027                 dispc_enable_plane(ovl->id, 1);
3028         }
3029
3030         *xi = x;
3031         *yi = y;
3032         *wi = w;
3033         *hi = h;
3034
3035 }
3036