1c036c1d4f08fdf6ac42fcded3a6ae979be9f562
[pandora-kernel.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2  * linux/drivers/video/omap2/dss/dispc.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
29 #include <linux/io.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
34
35 #include <mach/sram.h>
36 #include <mach/board.h>
37 #include <mach/clock.h>
38
39 #include <mach/display.h>
40
41 #include "dss.h"
42
43 /* DISPC */
44 #define DISPC_BASE                      0x48050400
45
46 #define DISPC_SZ_REGS                   SZ_1K
47
48 struct dispc_reg { u16 idx; };
49
50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
51
52 /* DISPC common */
53 #define DISPC_REVISION                  DISPC_REG(0x0000)
54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
74
75 /* DISPC GFX plane */
76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
87
88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
91
92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
95
96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
97
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
100
101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
114
115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
119 /* coef index i = {0, 1, 2, 3, 4} */
120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
123
124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
125
126
127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
128                                          DISPC_IRQ_OCP_ERR | \
129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
131                                          DISPC_IRQ_SYNC_LOST | \
132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
133
134 #define DISPC_MAX_NR_ISRS               8
135
136 struct omap_dispc_isr_data {
137         omap_dispc_isr_t        isr;
138         void                    *arg;
139         u32                     mask;
140 };
141
142 #define REG_GET(idx, start, end) \
143         FLD_GET(dispc_read_reg(idx), start, end)
144
145 #define REG_FLD_MOD(idx, val, start, end)                               \
146         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
147
148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
149         DISPC_VID_ATTRIBUTES(0),
150         DISPC_VID_ATTRIBUTES(1) };
151
152 static struct {
153         void __iomem    *base;
154
155         struct clk      *dpll4_m4_ck;
156
157         spinlock_t      irq_lock;
158
159         unsigned long   cache_req_pck;
160         unsigned long   cache_prate;
161         struct dispc_clock_info cache_cinfo;
162
163         u32             irq_error_mask;
164         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
165
166         spinlock_t error_lock;
167         u32 error_irqs;
168         struct work_struct error_work;
169
170         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
171 } dispc;
172
173 static void omap_dispc_set_irqs(void);
174
175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
176 {
177         __raw_writel(val, dispc.base + idx.idx);
178 }
179
180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
181 {
182         return __raw_readl(dispc.base + idx.idx);
183 }
184
185 #define SR(reg) \
186         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
187 #define RR(reg) \
188         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
189
190 void dispc_save_context(void)
191 {
192         if (cpu_is_omap24xx())
193                 return;
194
195         SR(SYSCONFIG);
196         SR(IRQENABLE);
197         SR(CONTROL);
198         SR(CONFIG);
199         SR(DEFAULT_COLOR0);
200         SR(DEFAULT_COLOR1);
201         SR(TRANS_COLOR0);
202         SR(TRANS_COLOR1);
203         SR(LINE_NUMBER);
204         SR(TIMING_H);
205         SR(TIMING_V);
206         SR(POL_FREQ);
207         SR(DIVISOR);
208         SR(GLOBAL_ALPHA);
209         SR(SIZE_DIG);
210         SR(SIZE_LCD);
211
212         SR(GFX_BA0);
213         SR(GFX_BA1);
214         SR(GFX_POSITION);
215         SR(GFX_SIZE);
216         SR(GFX_ATTRIBUTES);
217         SR(GFX_FIFO_THRESHOLD);
218         SR(GFX_ROW_INC);
219         SR(GFX_PIXEL_INC);
220         SR(GFX_WINDOW_SKIP);
221         SR(GFX_TABLE_BA);
222
223         SR(DATA_CYCLE1);
224         SR(DATA_CYCLE2);
225         SR(DATA_CYCLE3);
226
227         SR(CPR_COEF_R);
228         SR(CPR_COEF_G);
229         SR(CPR_COEF_B);
230
231         SR(GFX_PRELOAD);
232
233         /* VID1 */
234         SR(VID_BA0(0));
235         SR(VID_BA1(0));
236         SR(VID_POSITION(0));
237         SR(VID_SIZE(0));
238         SR(VID_ATTRIBUTES(0));
239         SR(VID_FIFO_THRESHOLD(0));
240         SR(VID_ROW_INC(0));
241         SR(VID_PIXEL_INC(0));
242         SR(VID_FIR(0));
243         SR(VID_PICTURE_SIZE(0));
244         SR(VID_ACCU0(0));
245         SR(VID_ACCU1(0));
246
247         SR(VID_FIR_COEF_H(0, 0));
248         SR(VID_FIR_COEF_H(0, 1));
249         SR(VID_FIR_COEF_H(0, 2));
250         SR(VID_FIR_COEF_H(0, 3));
251         SR(VID_FIR_COEF_H(0, 4));
252         SR(VID_FIR_COEF_H(0, 5));
253         SR(VID_FIR_COEF_H(0, 6));
254         SR(VID_FIR_COEF_H(0, 7));
255
256         SR(VID_FIR_COEF_HV(0, 0));
257         SR(VID_FIR_COEF_HV(0, 1));
258         SR(VID_FIR_COEF_HV(0, 2));
259         SR(VID_FIR_COEF_HV(0, 3));
260         SR(VID_FIR_COEF_HV(0, 4));
261         SR(VID_FIR_COEF_HV(0, 5));
262         SR(VID_FIR_COEF_HV(0, 6));
263         SR(VID_FIR_COEF_HV(0, 7));
264
265         SR(VID_CONV_COEF(0, 0));
266         SR(VID_CONV_COEF(0, 1));
267         SR(VID_CONV_COEF(0, 2));
268         SR(VID_CONV_COEF(0, 3));
269         SR(VID_CONV_COEF(0, 4));
270
271         SR(VID_FIR_COEF_V(0, 0));
272         SR(VID_FIR_COEF_V(0, 1));
273         SR(VID_FIR_COEF_V(0, 2));
274         SR(VID_FIR_COEF_V(0, 3));
275         SR(VID_FIR_COEF_V(0, 4));
276         SR(VID_FIR_COEF_V(0, 5));
277         SR(VID_FIR_COEF_V(0, 6));
278         SR(VID_FIR_COEF_V(0, 7));
279
280         SR(VID_PRELOAD(0));
281
282         /* VID2 */
283         SR(VID_BA0(1));
284         SR(VID_BA1(1));
285         SR(VID_POSITION(1));
286         SR(VID_SIZE(1));
287         SR(VID_ATTRIBUTES(1));
288         SR(VID_FIFO_THRESHOLD(1));
289         SR(VID_ROW_INC(1));
290         SR(VID_PIXEL_INC(1));
291         SR(VID_FIR(1));
292         SR(VID_PICTURE_SIZE(1));
293         SR(VID_ACCU0(1));
294         SR(VID_ACCU1(1));
295
296         SR(VID_FIR_COEF_H(1, 0));
297         SR(VID_FIR_COEF_H(1, 1));
298         SR(VID_FIR_COEF_H(1, 2));
299         SR(VID_FIR_COEF_H(1, 3));
300         SR(VID_FIR_COEF_H(1, 4));
301         SR(VID_FIR_COEF_H(1, 5));
302         SR(VID_FIR_COEF_H(1, 6));
303         SR(VID_FIR_COEF_H(1, 7));
304
305         SR(VID_FIR_COEF_HV(1, 0));
306         SR(VID_FIR_COEF_HV(1, 1));
307         SR(VID_FIR_COEF_HV(1, 2));
308         SR(VID_FIR_COEF_HV(1, 3));
309         SR(VID_FIR_COEF_HV(1, 4));
310         SR(VID_FIR_COEF_HV(1, 5));
311         SR(VID_FIR_COEF_HV(1, 6));
312         SR(VID_FIR_COEF_HV(1, 7));
313
314         SR(VID_CONV_COEF(1, 0));
315         SR(VID_CONV_COEF(1, 1));
316         SR(VID_CONV_COEF(1, 2));
317         SR(VID_CONV_COEF(1, 3));
318         SR(VID_CONV_COEF(1, 4));
319
320         SR(VID_FIR_COEF_V(1, 0));
321         SR(VID_FIR_COEF_V(1, 1));
322         SR(VID_FIR_COEF_V(1, 2));
323         SR(VID_FIR_COEF_V(1, 3));
324         SR(VID_FIR_COEF_V(1, 4));
325         SR(VID_FIR_COEF_V(1, 5));
326         SR(VID_FIR_COEF_V(1, 6));
327         SR(VID_FIR_COEF_V(1, 7));
328
329         SR(VID_PRELOAD(1));
330 }
331
332 void dispc_restore_context(void)
333 {
334         RR(SYSCONFIG);
335         RR(IRQENABLE);
336         /*RR(CONTROL);*/
337         RR(CONFIG);
338         RR(DEFAULT_COLOR0);
339         RR(DEFAULT_COLOR1);
340         RR(TRANS_COLOR0);
341         RR(TRANS_COLOR1);
342         RR(LINE_NUMBER);
343         RR(TIMING_H);
344         RR(TIMING_V);
345         RR(POL_FREQ);
346         RR(DIVISOR);
347         RR(GLOBAL_ALPHA);
348         RR(SIZE_DIG);
349         RR(SIZE_LCD);
350
351         RR(GFX_BA0);
352         RR(GFX_BA1);
353         RR(GFX_POSITION);
354         RR(GFX_SIZE);
355         RR(GFX_ATTRIBUTES);
356         RR(GFX_FIFO_THRESHOLD);
357         RR(GFX_ROW_INC);
358         RR(GFX_PIXEL_INC);
359         RR(GFX_WINDOW_SKIP);
360         RR(GFX_TABLE_BA);
361
362         RR(DATA_CYCLE1);
363         RR(DATA_CYCLE2);
364         RR(DATA_CYCLE3);
365
366         RR(CPR_COEF_R);
367         RR(CPR_COEF_G);
368         RR(CPR_COEF_B);
369
370         RR(GFX_PRELOAD);
371
372         /* VID1 */
373         RR(VID_BA0(0));
374         RR(VID_BA1(0));
375         RR(VID_POSITION(0));
376         RR(VID_SIZE(0));
377         RR(VID_ATTRIBUTES(0));
378         RR(VID_FIFO_THRESHOLD(0));
379         RR(VID_ROW_INC(0));
380         RR(VID_PIXEL_INC(0));
381         RR(VID_FIR(0));
382         RR(VID_PICTURE_SIZE(0));
383         RR(VID_ACCU0(0));
384         RR(VID_ACCU1(0));
385
386         RR(VID_FIR_COEF_H(0, 0));
387         RR(VID_FIR_COEF_H(0, 1));
388         RR(VID_FIR_COEF_H(0, 2));
389         RR(VID_FIR_COEF_H(0, 3));
390         RR(VID_FIR_COEF_H(0, 4));
391         RR(VID_FIR_COEF_H(0, 5));
392         RR(VID_FIR_COEF_H(0, 6));
393         RR(VID_FIR_COEF_H(0, 7));
394
395         RR(VID_FIR_COEF_HV(0, 0));
396         RR(VID_FIR_COEF_HV(0, 1));
397         RR(VID_FIR_COEF_HV(0, 2));
398         RR(VID_FIR_COEF_HV(0, 3));
399         RR(VID_FIR_COEF_HV(0, 4));
400         RR(VID_FIR_COEF_HV(0, 5));
401         RR(VID_FIR_COEF_HV(0, 6));
402         RR(VID_FIR_COEF_HV(0, 7));
403
404         RR(VID_CONV_COEF(0, 0));
405         RR(VID_CONV_COEF(0, 1));
406         RR(VID_CONV_COEF(0, 2));
407         RR(VID_CONV_COEF(0, 3));
408         RR(VID_CONV_COEF(0, 4));
409
410         RR(VID_FIR_COEF_V(0, 0));
411         RR(VID_FIR_COEF_V(0, 1));
412         RR(VID_FIR_COEF_V(0, 2));
413         RR(VID_FIR_COEF_V(0, 3));
414         RR(VID_FIR_COEF_V(0, 4));
415         RR(VID_FIR_COEF_V(0, 5));
416         RR(VID_FIR_COEF_V(0, 6));
417         RR(VID_FIR_COEF_V(0, 7));
418
419         RR(VID_PRELOAD(0));
420
421         /* VID2 */
422         RR(VID_BA0(1));
423         RR(VID_BA1(1));
424         RR(VID_POSITION(1));
425         RR(VID_SIZE(1));
426         RR(VID_ATTRIBUTES(1));
427         RR(VID_FIFO_THRESHOLD(1));
428         RR(VID_ROW_INC(1));
429         RR(VID_PIXEL_INC(1));
430         RR(VID_FIR(1));
431         RR(VID_PICTURE_SIZE(1));
432         RR(VID_ACCU0(1));
433         RR(VID_ACCU1(1));
434
435         RR(VID_FIR_COEF_H(1, 0));
436         RR(VID_FIR_COEF_H(1, 1));
437         RR(VID_FIR_COEF_H(1, 2));
438         RR(VID_FIR_COEF_H(1, 3));
439         RR(VID_FIR_COEF_H(1, 4));
440         RR(VID_FIR_COEF_H(1, 5));
441         RR(VID_FIR_COEF_H(1, 6));
442         RR(VID_FIR_COEF_H(1, 7));
443
444         RR(VID_FIR_COEF_HV(1, 0));
445         RR(VID_FIR_COEF_HV(1, 1));
446         RR(VID_FIR_COEF_HV(1, 2));
447         RR(VID_FIR_COEF_HV(1, 3));
448         RR(VID_FIR_COEF_HV(1, 4));
449         RR(VID_FIR_COEF_HV(1, 5));
450         RR(VID_FIR_COEF_HV(1, 6));
451         RR(VID_FIR_COEF_HV(1, 7));
452
453         RR(VID_CONV_COEF(1, 0));
454         RR(VID_CONV_COEF(1, 1));
455         RR(VID_CONV_COEF(1, 2));
456         RR(VID_CONV_COEF(1, 3));
457         RR(VID_CONV_COEF(1, 4));
458
459         RR(VID_FIR_COEF_V(1, 0));
460         RR(VID_FIR_COEF_V(1, 1));
461         RR(VID_FIR_COEF_V(1, 2));
462         RR(VID_FIR_COEF_V(1, 3));
463         RR(VID_FIR_COEF_V(1, 4));
464         RR(VID_FIR_COEF_V(1, 5));
465         RR(VID_FIR_COEF_V(1, 6));
466         RR(VID_FIR_COEF_V(1, 7));
467
468         RR(VID_PRELOAD(1));
469
470         /* enable last, because LCD & DIGIT enable are here */
471         RR(CONTROL);
472 }
473
474 #undef SR
475 #undef RR
476
477 static inline void enable_clocks(bool enable)
478 {
479         if (enable)
480                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
481         else
482                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
483 }
484
485 void dispc_go(enum omap_channel channel)
486 {
487         int bit;
488         unsigned long tmo;
489
490         enable_clocks(1);
491
492         if (channel == OMAP_DSS_CHANNEL_LCD)
493                 bit = 0; /* LCDENABLE */
494         else
495                 bit = 1; /* DIGITALENABLE */
496
497         /* if the channel is not enabled, we don't need GO */
498         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
499                 goto end;
500
501         if (channel == OMAP_DSS_CHANNEL_LCD)
502                 bit = 5; /* GOLCD */
503         else
504                 bit = 6; /* GODIGIT */
505
506         tmo = jiffies + msecs_to_jiffies(200);
507         while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
508                 if (time_after(jiffies, tmo)) {
509                         DSSERR("timeout waiting GO flag\n");
510                         goto end;
511                 }
512                 cpu_relax();
513         }
514
515         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
516
517         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
518 end:
519         enable_clocks(0);
520 }
521
522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
523 {
524         BUG_ON(plane == OMAP_DSS_GFX);
525
526         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
527 }
528
529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
530 {
531         BUG_ON(plane == OMAP_DSS_GFX);
532
533         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
534 }
535
536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
537 {
538         BUG_ON(plane == OMAP_DSS_GFX);
539
540         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
541 }
542
543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
544                 int vscaleup, int five_taps)
545 {
546         /* Coefficients for horizontal up-sampling */
547         static const u32 coef_hup[8] = {
548                 0x00800000,
549                 0x0D7CF800,
550                 0x1E70F5FF,
551                 0x335FF5FE,
552                 0xF74949F7,
553                 0xF55F33FB,
554                 0xF5701EFE,
555                 0xF87C0DFF,
556         };
557
558         /* Coefficients for horizontal down-sampling */
559         static const u32 coef_hdown[8] = {
560                 0x24382400,
561                 0x28371FFE,
562                 0x2C361BFB,
563                 0x303516F9,
564                 0x11343311,
565                 0x1635300C,
566                 0x1B362C08,
567                 0x1F372804,
568         };
569
570         /* Coefficients for horizontal and vertical up-sampling */
571         static const u32 coef_hvup[2][8] = {
572                 {
573                 0x00800000,
574                 0x037B02FF,
575                 0x0C6F05FE,
576                 0x205907FB,
577                 0x00404000,
578                 0x075920FE,
579                 0x056F0CFF,
580                 0x027B0300,
581                 },
582                 {
583                 0x00800000,
584                 0x0D7CF8FF,
585                 0x1E70F5FE,
586                 0x335FF5FB,
587                 0xF7404000,
588                 0xF55F33FE,
589                 0xF5701EFF,
590                 0xF87C0D00,
591                 },
592         };
593
594         /* Coefficients for horizontal and vertical down-sampling */
595         static const u32 coef_hvdown[2][8] = {
596                 {
597                 0x24382400,
598                 0x28391F04,
599                 0x2D381B08,
600                 0x3237170C,
601                 0x123737F7,
602                 0x173732F9,
603                 0x1B382DFB,
604                 0x1F3928FE,
605                 },
606                 {
607                 0x24382400,
608                 0x28371F04,
609                 0x2C361B08,
610                 0x3035160C,
611                 0x113433F7,
612                 0x163530F9,
613                 0x1B362CFB,
614                 0x1F3728FE,
615                 },
616         };
617
618         /* Coefficients for vertical up-sampling */
619         static const u32 coef_vup[8] = {
620                 0x00000000,
621                 0x0000FF00,
622                 0x0000FEFF,
623                 0x0000FBFE,
624                 0x000000F7,
625                 0x0000FEFB,
626                 0x0000FFFE,
627                 0x000000FF,
628         };
629
630
631         /* Coefficients for vertical down-sampling */
632         static const u32 coef_vdown[8] = {
633                 0x00000000,
634                 0x000004FE,
635                 0x000008FB,
636                 0x00000CF9,
637                 0x0000F711,
638                 0x0000F90C,
639                 0x0000FB08,
640                 0x0000FE04,
641         };
642
643         const u32 *h_coef;
644         const u32 *hv_coef;
645         const u32 *hv_coef_mod;
646         const u32 *v_coef;
647         int i;
648
649         if (hscaleup)
650                 h_coef = coef_hup;
651         else
652                 h_coef = coef_hdown;
653
654         if (vscaleup) {
655                 hv_coef = coef_hvup[five_taps];
656                 v_coef = coef_vup;
657
658                 if (hscaleup)
659                         hv_coef_mod = NULL;
660                 else
661                         hv_coef_mod = coef_hvdown[five_taps];
662         } else {
663                 hv_coef = coef_hvdown[five_taps];
664                 v_coef = coef_vdown;
665
666                 if (hscaleup)
667                         hv_coef_mod = coef_hvup[five_taps];
668                 else
669                         hv_coef_mod = NULL;
670         }
671
672         for (i = 0; i < 8; i++) {
673                 u32 h, hv;
674
675                 h = h_coef[i];
676
677                 hv = hv_coef[i];
678
679                 if (hv_coef_mod) {
680                         hv &= 0xffffff00;
681                         hv |= (hv_coef_mod[i] & 0xff);
682                 }
683
684                 _dispc_write_firh_reg(plane, i, h);
685                 _dispc_write_firhv_reg(plane, i, hv);
686         }
687
688         if (!five_taps)
689                 return;
690
691         for (i = 0; i < 8; i++) {
692                 u32 v;
693                 v = v_coef[i];
694                 _dispc_write_firv_reg(plane, i, v);
695         }
696 }
697
698 static void _dispc_setup_color_conv_coef(void)
699 {
700         const struct color_conv_coef {
701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
702                 int  full_range;
703         }  ctbl_bt601_5 = {
704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
705         };
706
707         const struct color_conv_coef *ct;
708
709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
710
711         ct = &ctbl_bt601_5;
712
713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
718
719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
724
725 #undef CVAL
726
727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
729 }
730
731
732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
733 {
734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
735                 DISPC_VID_BA0(0),
736                 DISPC_VID_BA0(1) };
737
738         dispc_write_reg(ba0_reg[plane], paddr);
739 }
740
741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
742 {
743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
744                                       DISPC_VID_BA1(0),
745                                       DISPC_VID_BA1(1) };
746
747         dispc_write_reg(ba1_reg[plane], paddr);
748 }
749
750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
751 {
752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
753                                       DISPC_VID_POSITION(0),
754                                       DISPC_VID_POSITION(1) };
755
756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
757         dispc_write_reg(pos_reg[plane], val);
758 }
759
760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
761 {
762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
763                                       DISPC_VID_PICTURE_SIZE(0),
764                                       DISPC_VID_PICTURE_SIZE(1) };
765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
766         dispc_write_reg(siz_reg[plane], val);
767 }
768
769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
770 {
771         u32 val;
772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
773                                       DISPC_VID_SIZE(1) };
774
775         BUG_ON(plane == OMAP_DSS_GFX);
776
777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
778         dispc_write_reg(vsi_reg[plane-1], val);
779 }
780
781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
782 {
783         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
784                                      DISPC_VID_PIXEL_INC(0),
785                                      DISPC_VID_PIXEL_INC(1) };
786
787         dispc_write_reg(ri_reg[plane], inc);
788 }
789
790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
791 {
792         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
793                                      DISPC_VID_ROW_INC(0),
794                                      DISPC_VID_ROW_INC(1) };
795
796         dispc_write_reg(ri_reg[plane], inc);
797 }
798
799 static void _dispc_set_color_mode(enum omap_plane plane,
800                 enum omap_color_mode color_mode)
801 {
802         u32 m = 0;
803
804         switch (color_mode) {
805         case OMAP_DSS_COLOR_CLUT1:
806                 m = 0x0; break;
807         case OMAP_DSS_COLOR_CLUT2:
808                 m = 0x1; break;
809         case OMAP_DSS_COLOR_CLUT4:
810                 m = 0x2; break;
811         case OMAP_DSS_COLOR_CLUT8:
812                 m = 0x3; break;
813         case OMAP_DSS_COLOR_RGB12U:
814                 m = 0x4; break;
815         case OMAP_DSS_COLOR_ARGB16:
816                 m = 0x5; break;
817         case OMAP_DSS_COLOR_RGB16:
818                 m = 0x6; break;
819         case OMAP_DSS_COLOR_RGB24U:
820                 m = 0x8; break;
821         case OMAP_DSS_COLOR_RGB24P:
822                 m = 0x9; break;
823         case OMAP_DSS_COLOR_YUV2:
824                 m = 0xa; break;
825         case OMAP_DSS_COLOR_UYVY:
826                 m = 0xb; break;
827         case OMAP_DSS_COLOR_ARGB32:
828                 m = 0xc; break;
829         case OMAP_DSS_COLOR_RGBA32:
830                 m = 0xd; break;
831         case OMAP_DSS_COLOR_RGBX32:
832                 m = 0xe; break;
833         default:
834                 BUG(); break;
835         }
836
837         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
838 }
839
840 static void _dispc_set_channel_out(enum omap_plane plane,
841                 enum omap_channel channel)
842 {
843         int shift;
844         u32 val;
845
846         switch (plane) {
847         case OMAP_DSS_GFX:
848                 shift = 8;
849                 break;
850         case OMAP_DSS_VIDEO1:
851         case OMAP_DSS_VIDEO2:
852                 shift = 16;
853                 break;
854         default:
855                 BUG();
856                 return;
857         }
858
859         val = dispc_read_reg(dispc_reg_att[plane]);
860         val = FLD_MOD(val, channel, shift, shift);
861         dispc_write_reg(dispc_reg_att[plane], val);
862 }
863
864 void dispc_set_burst_size(enum omap_plane plane,
865                 enum omap_burst_size burst_size)
866 {
867         int shift;
868         u32 val;
869
870         enable_clocks(1);
871
872         switch (plane) {
873         case OMAP_DSS_GFX:
874                 shift = 6;
875                 break;
876         case OMAP_DSS_VIDEO1:
877         case OMAP_DSS_VIDEO2:
878                 shift = 14;
879                 break;
880         default:
881                 BUG();
882                 return;
883         }
884
885         val = dispc_read_reg(dispc_reg_att[plane]);
886         val = FLD_MOD(val, burst_size, shift+1, shift);
887         dispc_write_reg(dispc_reg_att[plane], val);
888
889         enable_clocks(0);
890 }
891
892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
893 {
894         u32 val;
895
896         BUG_ON(plane == OMAP_DSS_GFX);
897
898         val = dispc_read_reg(dispc_reg_att[plane]);
899         val = FLD_MOD(val, enable, 9, 9);
900         dispc_write_reg(dispc_reg_att[plane], val);
901 }
902
903 void dispc_set_lcd_size(u16 width, u16 height)
904 {
905         u32 val;
906         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
907         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
908         enable_clocks(1);
909         dispc_write_reg(DISPC_SIZE_LCD, val);
910         enable_clocks(0);
911 }
912
913 void dispc_set_digit_size(u16 width, u16 height)
914 {
915         u32 val;
916         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
917         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
918         enable_clocks(1);
919         dispc_write_reg(DISPC_SIZE_DIG, val);
920         enable_clocks(0);
921 }
922
923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
924 {
925         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
926                                       DISPC_VID_FIFO_SIZE_STATUS(0),
927                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
928         u32 size;
929
930         enable_clocks(1);
931
932         if (cpu_is_omap24xx())
933                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
934         else if (cpu_is_omap34xx())
935                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
936         else
937                 BUG();
938
939         if (cpu_is_omap34xx()) {
940                 /* FIFOMERGE */
941                 if (REG_GET(DISPC_CONFIG, 14, 14))
942                         size *= 3;
943         }
944
945         enable_clocks(0);
946
947         return size;
948 }
949
950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
951 {
952         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
953                                        DISPC_VID_FIFO_THRESHOLD(0),
954                                        DISPC_VID_FIFO_THRESHOLD(1) };
955         u32 size;
956
957         enable_clocks(1);
958
959         size = dispc_get_plane_fifo_size(plane);
960
961         BUG_ON(low > size || high > size);
962
963         DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
964                         plane, size,
965                         REG_GET(ftrs_reg[plane], 11, 0),
966                         REG_GET(ftrs_reg[plane], 27, 16),
967                         low, high);
968
969         if (cpu_is_omap24xx())
970                 dispc_write_reg(ftrs_reg[plane],
971                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
972         else
973                 dispc_write_reg(ftrs_reg[plane],
974                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
975
976         enable_clocks(0);
977 }
978
979 void dispc_enable_fifomerge(bool enable)
980 {
981         enable_clocks(1);
982
983         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
984         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
985
986         enable_clocks(0);
987 }
988
989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
990 {
991         u32 val;
992         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
993                                       DISPC_VID_FIR(1) };
994
995         BUG_ON(plane == OMAP_DSS_GFX);
996
997         if (cpu_is_omap24xx())
998                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
999         else
1000                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1001         dispc_write_reg(fir_reg[plane-1], val);
1002 }
1003
1004 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1005 {
1006         u32 val;
1007         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1008                                       DISPC_VID_ACCU0(1) };
1009
1010         BUG_ON(plane == OMAP_DSS_GFX);
1011
1012         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1013         dispc_write_reg(ac0_reg[plane-1], val);
1014 }
1015
1016 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1017 {
1018         u32 val;
1019         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1020                                       DISPC_VID_ACCU1(1) };
1021
1022         BUG_ON(plane == OMAP_DSS_GFX);
1023
1024         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1025         dispc_write_reg(ac1_reg[plane-1], val);
1026 }
1027
1028
1029 static void _dispc_set_scaling(enum omap_plane plane,
1030                 u16 orig_width, u16 orig_height,
1031                 u16 out_width, u16 out_height,
1032                 bool ilace, bool five_taps,
1033                 bool fieldmode)
1034 {
1035         int fir_hinc;
1036         int fir_vinc;
1037         int hscaleup, vscaleup;
1038         int accu0 = 0;
1039         int accu1 = 0;
1040         u32 l;
1041
1042         BUG_ON(plane == OMAP_DSS_GFX);
1043
1044         hscaleup = orig_width <= out_width;
1045         vscaleup = orig_height <= out_height;
1046
1047         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1048
1049         if (!orig_width || orig_width == out_width)
1050                 fir_hinc = 0;
1051         else
1052                 fir_hinc = 1024 * orig_width / out_width;
1053
1054         if (!orig_height || orig_height == out_height)
1055                 fir_vinc = 0;
1056         else
1057                 fir_vinc = 1024 * orig_height / out_height;
1058
1059         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1060
1061         l = dispc_read_reg(dispc_reg_att[plane]);
1062         l &= ~((0x0f << 5) | (0x3 << 21));
1063
1064         l |= fir_hinc ? (1 << 5) : 0;
1065         l |= fir_vinc ? (1 << 6) : 0;
1066
1067         l |= hscaleup ? 0 : (1 << 7);
1068         l |= vscaleup ? 0 : (1 << 8);
1069
1070         l |= five_taps ? (1 << 21) : 0;
1071         l |= five_taps ? (1 << 22) : 0;
1072
1073         dispc_write_reg(dispc_reg_att[plane], l);
1074
1075         if (ilace && !fieldmode) {
1076                 accu0 = 0;
1077                 accu1 = fir_vinc / 2;
1078                 if (accu1 >= 1024/2) {
1079                         accu0 = 1024/2;
1080                         accu1 -= accu0;
1081                 }
1082         }
1083
1084         _dispc_set_vid_accu0(plane, 0, accu0);
1085         _dispc_set_vid_accu1(plane, 0, accu1);
1086 }
1087
1088 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1089                 bool mirroring, enum omap_color_mode color_mode)
1090 {
1091         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1092                         color_mode == OMAP_DSS_COLOR_UYVY) {
1093                 int vidrot = 0;
1094
1095                 if (mirroring) {
1096                         switch (rotation) {
1097                         case 0: vidrot = 2; break;
1098                         case 1: vidrot = 3; break;
1099                         case 2: vidrot = 0; break;
1100                         case 3: vidrot = 1; break;
1101                         }
1102                 } else {
1103                         switch (rotation) {
1104                         case 0: vidrot = 0; break;
1105                         case 1: vidrot = 1; break;
1106                         case 2: vidrot = 2; break;
1107                         case 3: vidrot = 3; break;
1108                         }
1109                 }
1110
1111                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1112
1113                 if (rotation == 1 || rotation == 3)
1114                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1115                 else
1116                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1117         } else {
1118                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1119                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1120         }
1121 }
1122
1123 static s32 pixinc(int pixels, u8 ps)
1124 {
1125         if (pixels == 1)
1126                 return 1;
1127         else if (pixels > 1)
1128                 return 1 + (pixels - 1) * ps;
1129         else if (pixels < 0)
1130                 return 1 - (-pixels + 1) * ps;
1131         else
1132                 BUG();
1133 }
1134
1135 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1136                 u16 screen_width,
1137                 u16 width, u16 height,
1138                 enum omap_color_mode color_mode, bool fieldmode,
1139                 unsigned *offset0, unsigned *offset1,
1140                 s32 *row_inc, s32 *pix_inc)
1141 {
1142         u8 ps;
1143
1144         switch (color_mode) {
1145         case OMAP_DSS_COLOR_RGB16:
1146         case OMAP_DSS_COLOR_ARGB16:
1147                 ps = 2;
1148                 break;
1149
1150         case OMAP_DSS_COLOR_RGB24P:
1151                 ps = 3;
1152                 break;
1153
1154         case OMAP_DSS_COLOR_RGB24U:
1155         case OMAP_DSS_COLOR_ARGB32:
1156         case OMAP_DSS_COLOR_RGBA32:
1157         case OMAP_DSS_COLOR_RGBX32:
1158         case OMAP_DSS_COLOR_YUV2:
1159         case OMAP_DSS_COLOR_UYVY:
1160                 ps = 4;
1161                 break;
1162
1163         default:
1164                 BUG();
1165                 return;
1166         }
1167
1168         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1169                         width, height);
1170         switch (rotation + mirror * 4) {
1171         case 0:
1172         case 2:
1173                 /*
1174                  * If the pixel format is YUV or UYVY divide the width
1175                  * of the image by 2 for 0 and 180 degree rotation.
1176                  */
1177                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1178                         color_mode == OMAP_DSS_COLOR_UYVY)
1179                         width = width >> 1;
1180         case 1:
1181         case 3:
1182                 *offset0 = 0;
1183                 if (fieldmode)
1184                         *offset1 = screen_width * ps;
1185                 else
1186                         *offset1 = 0;
1187
1188                 *row_inc = pixinc(1 + (screen_width - width) +
1189                                 (fieldmode ? screen_width : 0),
1190                                 ps);
1191                 *pix_inc = pixinc(1, ps);
1192                 break;
1193
1194         case 4:
1195         case 6:
1196                 /* If the pixel format is YUV or UYVY divide the width
1197                  * of the image by 2  for 0 degree and 180 degree
1198                  */
1199                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1200                         color_mode == OMAP_DSS_COLOR_UYVY)
1201                         width = width >> 1;
1202         case 5:
1203         case 7:
1204                 *offset0 = 0;
1205                 if (fieldmode)
1206                         *offset1 = screen_width * ps;
1207                 else
1208                         *offset1 = 0;
1209                 *row_inc = pixinc(1 - (screen_width + width) -
1210                                 (fieldmode ? screen_width : 0),
1211                                 ps);
1212                 *pix_inc = pixinc(1, ps);
1213                 break;
1214
1215         default:
1216                 BUG();
1217         }
1218 }
1219
1220 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1221                 u16 screen_width,
1222                 u16 width, u16 height,
1223                 enum omap_color_mode color_mode, bool fieldmode,
1224                 unsigned *offset0, unsigned *offset1,
1225                 s32 *row_inc, s32 *pix_inc)
1226 {
1227         u8 ps;
1228         u16 fbw, fbh;
1229
1230         switch (color_mode) {
1231         case OMAP_DSS_COLOR_RGB16:
1232         case OMAP_DSS_COLOR_ARGB16:
1233                 ps = 2;
1234                 break;
1235
1236         case OMAP_DSS_COLOR_RGB24P:
1237                 ps = 3;
1238                 break;
1239
1240         case OMAP_DSS_COLOR_RGB24U:
1241         case OMAP_DSS_COLOR_ARGB32:
1242         case OMAP_DSS_COLOR_RGBA32:
1243         case OMAP_DSS_COLOR_RGBX32:
1244                 ps = 4;
1245                 break;
1246
1247         case OMAP_DSS_COLOR_YUV2:
1248         case OMAP_DSS_COLOR_UYVY:
1249                 ps = 2;
1250                 break;
1251         default:
1252                 BUG();
1253                 return;
1254         }
1255
1256         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1257                         width, height);
1258
1259         /* width & height are overlay sizes, convert to fb sizes */
1260
1261         if (rotation == 0 || rotation == 2) {
1262                 fbw = width;
1263                 fbh = height;
1264         } else {
1265                 fbw = height;
1266                 fbh = width;
1267         }
1268
1269         switch (rotation + mirror * 4) {
1270         case 0:
1271                 *offset0 = 0;
1272                 if (fieldmode)
1273                         *offset1 = screen_width * ps;
1274                 else
1275                         *offset1 = 0;
1276                 *row_inc = pixinc(1 + (screen_width - fbw) +
1277                                 (fieldmode ? screen_width : 0),
1278                                 ps);
1279                 *pix_inc = pixinc(1, ps);
1280                 break;
1281         case 1:
1282                 *offset0 = screen_width * (fbh - 1) * ps;
1283                 if (fieldmode)
1284                         *offset1 = *offset0 + ps;
1285                 else
1286                         *offset1 = *offset0;
1287                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1288                                 (fieldmode ? 1 : 0), ps);
1289                 *pix_inc = pixinc(-screen_width, ps);
1290                 break;
1291         case 2:
1292                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1293                 if (fieldmode)
1294                         *offset1 = *offset0 - screen_width * ps;
1295                 else
1296                         *offset1 = *offset0;
1297                 *row_inc = pixinc(-1 -
1298                                 (screen_width - fbw) -
1299                                 (fieldmode ? screen_width : 0),
1300                                 ps);
1301                 *pix_inc = pixinc(-1, ps);
1302                 break;
1303         case 3:
1304                 *offset0 = (fbw - 1) * ps;
1305                 if (fieldmode)
1306                         *offset1 = *offset0 - ps;
1307                 else
1308                         *offset1 = *offset0;
1309                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1310                                 (fieldmode ? 1 : 0), ps);
1311                 *pix_inc = pixinc(screen_width, ps);
1312                 break;
1313
1314         /* mirroring */
1315         case 0 + 4:
1316                 *offset0 = (fbw - 1) * ps;
1317                 if (fieldmode)
1318                         *offset1 = *offset0 + screen_width * ps;
1319                 else
1320                         *offset1 = *offset0;
1321                 *row_inc = pixinc(screen_width * 2 - 1 +
1322                                 (fieldmode ? screen_width : 0),
1323                                 ps);
1324                 *pix_inc = pixinc(-1, ps);
1325                 break;
1326
1327         case 1 + 4:
1328                 *offset0 = 0;
1329                 if (fieldmode)
1330                         *offset1 = *offset0 + screen_width * ps;
1331                 else
1332                         *offset1 = *offset0;
1333                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1334                                 (fieldmode ? 1 : 0),
1335                                 ps);
1336                 *pix_inc = pixinc(screen_width, ps);
1337                 break;
1338
1339         case 2 + 4:
1340                 *offset0 = screen_width * (fbh - 1) * ps;
1341                 if (fieldmode)
1342                         *offset1 = *offset0 + screen_width * ps;
1343                 else
1344                         *offset1 = *offset0;
1345                 *row_inc = pixinc(1 - screen_width * 2 -
1346                                 (fieldmode ? screen_width : 0),
1347                                 ps);
1348                 *pix_inc = pixinc(1, ps);
1349                 break;
1350
1351         case 3 + 4:
1352                 *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1353                 if (fieldmode)
1354                         *offset1 = *offset0 + screen_width * ps;
1355                 else
1356                         *offset1 = *offset0;
1357                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1358                                 (fieldmode ? 1 : 0),
1359                                 ps);
1360                 *pix_inc = pixinc(-screen_width, ps);
1361                 break;
1362
1363         default:
1364                 BUG();
1365         }
1366 }
1367
1368 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1369                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1370 {
1371         u32 fclk = 0;
1372         /* FIXME venc pclk? */
1373         u64 tmp, pclk = dispc_pclk_rate();
1374
1375         if (height > out_height) {
1376                 /* FIXME get real display PPL */
1377                 unsigned int ppl = 800;
1378
1379                 tmp = pclk * height * out_width;
1380                 do_div(tmp, 2 * out_height * ppl);
1381                 fclk = tmp;
1382
1383                 if (height > 2 * out_height) {
1384                         tmp = pclk * (height - 2 * out_height) * out_width;
1385                         do_div(tmp, 2 * out_height * (ppl - out_width));
1386                         fclk = max(fclk, (u32) tmp);
1387                 }
1388         }
1389
1390         if (width > out_width) {
1391                 tmp = pclk * width;
1392                 do_div(tmp, out_width);
1393                 fclk = max(fclk, (u32) tmp);
1394
1395                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1396                         fclk <<= 1;
1397         }
1398
1399         return fclk;
1400 }
1401
1402 static unsigned long calc_fclk(u16 width, u16 height,
1403                 u16 out_width, u16 out_height)
1404 {
1405         unsigned int hf, vf;
1406
1407         /*
1408          * FIXME how to determine the 'A' factor
1409          * for the no downscaling case ?
1410          */
1411
1412         if (width > 3 * out_width)
1413                 hf = 4;
1414         else if (width > 2 * out_width)
1415                 hf = 3;
1416         else if (width > out_width)
1417                 hf = 2;
1418         else
1419                 hf = 1;
1420
1421         if (height > out_height)
1422                 vf = 2;
1423         else
1424                 vf = 1;
1425
1426         /* FIXME venc pclk? */
1427         return dispc_pclk_rate() * vf * hf;
1428 }
1429
1430 static int _dispc_setup_plane(enum omap_plane plane,
1431                 enum omap_channel channel_out,
1432                 u32 paddr, u16 screen_width,
1433                 u16 pos_x, u16 pos_y,
1434                 u16 width, u16 height,
1435                 u16 out_width, u16 out_height,
1436                 enum omap_color_mode color_mode,
1437                 bool ilace,
1438                 enum omap_dss_rotation_type rotation_type,
1439                 u8 rotation, int mirror)
1440 {
1441         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1442         bool five_taps = 0;
1443         bool fieldmode = 0;
1444         int cconv = 0;
1445         unsigned offset0, offset1;
1446         s32 row_inc;
1447         s32 pix_inc;
1448         u16 frame_height = height;
1449
1450         if (paddr == 0)
1451                 return -EINVAL;
1452
1453         if (ilace && height == out_height)
1454                 fieldmode = 1;
1455
1456         if (ilace) {
1457                 if (fieldmode)
1458                         height /= 2;
1459                 pos_y /= 2;
1460                 out_height /= 2;
1461
1462                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1463                                 "out_height %d\n",
1464                                 height, pos_y, out_height);
1465         }
1466
1467         if (plane == OMAP_DSS_GFX) {
1468                 if (width != out_width || height != out_height)
1469                         return -EINVAL;
1470
1471                 switch (color_mode) {
1472                 case OMAP_DSS_COLOR_ARGB16:
1473                 case OMAP_DSS_COLOR_RGB16:
1474                 case OMAP_DSS_COLOR_RGB24P:
1475                 case OMAP_DSS_COLOR_RGB24U:
1476                 case OMAP_DSS_COLOR_ARGB32:
1477                 case OMAP_DSS_COLOR_RGBA32:
1478                 case OMAP_DSS_COLOR_RGBX32:
1479                         break;
1480
1481                 default:
1482                         return -EINVAL;
1483                 }
1484         } else {
1485                 /* video plane */
1486
1487                 unsigned long fclk = 0;
1488
1489                 if (out_width < width / maxdownscale ||
1490                    out_width > width * 8)
1491                         return -EINVAL;
1492
1493                 if (out_height < height / maxdownscale ||
1494                    out_height > height * 8)
1495                         return -EINVAL;
1496
1497                 switch (color_mode) {
1498                 case OMAP_DSS_COLOR_RGB16:
1499                 case OMAP_DSS_COLOR_RGB24P:
1500                 case OMAP_DSS_COLOR_RGB24U:
1501                 case OMAP_DSS_COLOR_RGBX32:
1502                         break;
1503
1504                 case OMAP_DSS_COLOR_ARGB16:
1505                 case OMAP_DSS_COLOR_ARGB32:
1506                 case OMAP_DSS_COLOR_RGBA32:
1507                         if (plane == OMAP_DSS_VIDEO1)
1508                                 return -EINVAL;
1509                         break;
1510
1511                 case OMAP_DSS_COLOR_YUV2:
1512                 case OMAP_DSS_COLOR_UYVY:
1513                         cconv = 1;
1514                         break;
1515
1516                 default:
1517                         return -EINVAL;
1518                 }
1519
1520                 /* Must use 5-tap filter? */
1521                 five_taps = height > out_height * 2;
1522
1523                 if (!five_taps) {
1524                         fclk = calc_fclk(width, height,
1525                                         out_width, out_height);
1526
1527                         /* Try 5-tap filter if 3-tap fclk is too high */
1528                         if (cpu_is_omap34xx() && height > out_height &&
1529                                         fclk > dispc_fclk_rate())
1530                                 five_taps = true;
1531                 }
1532
1533                 if (width > (2048 >> five_taps))
1534                         return -EINVAL;
1535
1536                 if (five_taps)
1537                         fclk = calc_fclk_five_taps(width, height,
1538                                         out_width, out_height, color_mode);
1539
1540                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1541                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1542
1543                 if (fclk > dispc_fclk_rate())
1544                         return -EINVAL;
1545         }
1546
1547         if (rotation_type == OMAP_DSS_ROT_DMA)
1548                 calc_dma_rotation_offset(rotation, mirror,
1549                                 screen_width, width, frame_height, color_mode,
1550                                 fieldmode,
1551                                 &offset0, &offset1, &row_inc, &pix_inc);
1552         else
1553                 calc_vrfb_rotation_offset(rotation, mirror,
1554                                 screen_width, width, frame_height, color_mode,
1555                                 fieldmode,
1556                                 &offset0, &offset1, &row_inc, &pix_inc);
1557
1558         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1559                         offset0, offset1, row_inc, pix_inc);
1560
1561         _dispc_set_channel_out(plane, channel_out);
1562         _dispc_set_color_mode(plane, color_mode);
1563
1564         _dispc_set_plane_ba0(plane, paddr + offset0);
1565         _dispc_set_plane_ba1(plane, paddr + offset1);
1566
1567         _dispc_set_row_inc(plane, row_inc);
1568         _dispc_set_pix_inc(plane, pix_inc);
1569
1570         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1571                         out_width, out_height);
1572
1573         _dispc_set_plane_pos(plane, pos_x, pos_y);
1574
1575         _dispc_set_pic_size(plane, width, height);
1576
1577         if (plane != OMAP_DSS_GFX) {
1578                 _dispc_set_scaling(plane, width, height,
1579                                    out_width, out_height,
1580                                    ilace, five_taps, fieldmode);
1581                 _dispc_set_vid_size(plane, out_width, out_height);
1582                 _dispc_set_vid_color_conv(plane, cconv);
1583         }
1584
1585         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1586
1587         return 0;
1588 }
1589
1590 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1591 {
1592         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1593 }
1594
1595 static void dispc_disable_isr(void *data, u32 mask)
1596 {
1597         struct completion *compl = data;
1598         complete(compl);
1599 }
1600
1601 static void _enable_lcd_out(bool enable)
1602 {
1603         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1604 }
1605
1606 void dispc_enable_lcd_out(bool enable)
1607 {
1608         struct completion frame_done_completion;
1609         bool is_on;
1610         int r;
1611
1612         enable_clocks(1);
1613
1614         /* When we disable LCD output, we need to wait until frame is done.
1615          * Otherwise the DSS is still working, and turning off the clocks
1616          * prevents DSS from going to OFF mode */
1617         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1618
1619         if (!enable && is_on) {
1620                 init_completion(&frame_done_completion);
1621
1622                 r = omap_dispc_register_isr(dispc_disable_isr,
1623                                 &frame_done_completion,
1624                                 DISPC_IRQ_FRAMEDONE);
1625
1626                 if (r)
1627                         DSSERR("failed to register FRAMEDONE isr\n");
1628         }
1629
1630         _enable_lcd_out(enable);
1631
1632         if (!enable && is_on) {
1633                 if (!wait_for_completion_timeout(&frame_done_completion,
1634                                         msecs_to_jiffies(100)))
1635                         DSSERR("timeout waiting for FRAME DONE\n");
1636
1637                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1638                                 &frame_done_completion,
1639                                 DISPC_IRQ_FRAMEDONE);
1640
1641                 if (r)
1642                         DSSERR("failed to unregister FRAMEDONE isr\n");
1643         }
1644
1645         enable_clocks(0);
1646 }
1647
1648 static void _enable_digit_out(bool enable)
1649 {
1650         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1651 }
1652
1653 void dispc_enable_digit_out(bool enable)
1654 {
1655         struct completion frame_done_completion;
1656         int r;
1657
1658         enable_clocks(1);
1659
1660         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1661                 enable_clocks(0);
1662                 return;
1663         }
1664
1665         if (enable) {
1666                 /* When we enable digit output, we'll get an extra digit
1667                  * sync lost interrupt, that we need to ignore */
1668                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1669                 omap_dispc_set_irqs();
1670         }
1671
1672         /* When we disable digit output, we need to wait until fields are done.
1673          * Otherwise the DSS is still working, and turning off the clocks
1674          * prevents DSS from going to OFF mode. And when enabling, we need to
1675          * wait for the extra sync losts */
1676         init_completion(&frame_done_completion);
1677
1678         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1679                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1680         if (r)
1681                 DSSERR("failed to register EVSYNC isr\n");
1682
1683         _enable_digit_out(enable);
1684
1685         /* XXX I understand from TRM that we should only wait for the
1686          * current field to complete. But it seems we have to wait
1687          * for both fields */
1688         if (!wait_for_completion_timeout(&frame_done_completion,
1689                                 msecs_to_jiffies(100)))
1690                 DSSERR("timeout waiting for EVSYNC\n");
1691
1692         if (!wait_for_completion_timeout(&frame_done_completion,
1693                                 msecs_to_jiffies(100)))
1694                 DSSERR("timeout waiting for EVSYNC\n");
1695
1696         r = omap_dispc_unregister_isr(dispc_disable_isr,
1697                         &frame_done_completion,
1698                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1699         if (r)
1700                 DSSERR("failed to unregister EVSYNC isr\n");
1701
1702         if (enable) {
1703                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1704                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1705                 omap_dispc_set_irqs();
1706         }
1707
1708         enable_clocks(0);
1709 }
1710
1711 void dispc_lcd_enable_signal_polarity(bool act_high)
1712 {
1713         enable_clocks(1);
1714         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1715         enable_clocks(0);
1716 }
1717
1718 void dispc_lcd_enable_signal(bool enable)
1719 {
1720         enable_clocks(1);
1721         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1722         enable_clocks(0);
1723 }
1724
1725 void dispc_pck_free_enable(bool enable)
1726 {
1727         enable_clocks(1);
1728         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1729         enable_clocks(0);
1730 }
1731
1732 void dispc_enable_fifohandcheck(bool enable)
1733 {
1734         enable_clocks(1);
1735         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1736         enable_clocks(0);
1737 }
1738
1739
1740 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1741 {
1742         int mode;
1743
1744         switch (type) {
1745         case OMAP_DSS_LCD_DISPLAY_STN:
1746                 mode = 0;
1747                 break;
1748
1749         case OMAP_DSS_LCD_DISPLAY_TFT:
1750                 mode = 1;
1751                 break;
1752
1753         default:
1754                 BUG();
1755                 return;
1756         }
1757
1758         enable_clocks(1);
1759         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1760         enable_clocks(0);
1761 }
1762
1763 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1764 {
1765         enable_clocks(1);
1766         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1767         enable_clocks(0);
1768 }
1769
1770
1771 void dispc_set_default_color(enum omap_channel channel, u32 color)
1772 {
1773         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1774                                 DISPC_DEFAULT_COLOR1 };
1775
1776         enable_clocks(1);
1777         dispc_write_reg(def_reg[channel], color);
1778         enable_clocks(0);
1779 }
1780
1781 u32 dispc_get_default_color(enum omap_channel channel)
1782 {
1783         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1784                                 DISPC_DEFAULT_COLOR1 };
1785         u32 l;
1786
1787         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1788                channel != OMAP_DSS_CHANNEL_LCD);
1789
1790         enable_clocks(1);
1791         l = dispc_read_reg(def_reg[channel]);
1792         enable_clocks(0);
1793
1794         return l;
1795 }
1796
1797 void dispc_set_trans_key(enum omap_channel ch,
1798                 enum omap_dss_color_key_type type,
1799                 u32 trans_key)
1800 {
1801         const struct dispc_reg tr_reg[] = {
1802                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1803
1804         enable_clocks(1);
1805         if (ch == OMAP_DSS_CHANNEL_LCD)
1806                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1807         else /* OMAP_DSS_CHANNEL_DIGIT */
1808                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1809
1810         dispc_write_reg(tr_reg[ch], trans_key);
1811         enable_clocks(0);
1812 }
1813
1814 void dispc_get_trans_key(enum omap_channel ch,
1815                 enum omap_dss_color_key_type *type,
1816                 u32 *trans_key)
1817 {
1818         const struct dispc_reg tr_reg[] = {
1819                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1820
1821         enable_clocks(1);
1822         if (type) {
1823                 if (ch == OMAP_DSS_CHANNEL_LCD)
1824                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1825                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1826                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1827                 else
1828                         BUG();
1829         }
1830
1831         if (trans_key)
1832                 *trans_key = dispc_read_reg(tr_reg[ch]);
1833         enable_clocks(0);
1834 }
1835
1836 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1837 {
1838         enable_clocks(1);
1839         if (ch == OMAP_DSS_CHANNEL_LCD)
1840                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1841         else /* OMAP_DSS_CHANNEL_DIGIT */
1842                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1843         enable_clocks(0);
1844 }
1845 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1846 {
1847         enable_clocks(1);
1848         if (ch == OMAP_DSS_CHANNEL_LCD)
1849                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1850         else /* OMAP_DSS_CHANNEL_DIGIT */
1851                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1852         enable_clocks(0);
1853 }
1854 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1855 {
1856         bool enabled;
1857
1858         enable_clocks(1);
1859         if (ch == OMAP_DSS_CHANNEL_LCD)
1860                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1861         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1862                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1863         else
1864                 BUG();
1865         enable_clocks(0);
1866
1867         return enabled;
1868
1869 }
1870
1871
1872 bool dispc_trans_key_enabled(enum omap_channel ch)
1873 {
1874         bool enabled;
1875
1876         enable_clocks(1);
1877         if (ch == OMAP_DSS_CHANNEL_LCD)
1878                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1879         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1880                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1881         else BUG();
1882         enable_clocks(0);
1883
1884         return enabled;
1885 }
1886
1887
1888 void dispc_set_tft_data_lines(u8 data_lines)
1889 {
1890         int code;
1891
1892         switch (data_lines) {
1893         case 12:
1894                 code = 0;
1895                 break;
1896         case 16:
1897                 code = 1;
1898                 break;
1899         case 18:
1900                 code = 2;
1901                 break;
1902         case 24:
1903                 code = 3;
1904                 break;
1905         default:
1906                 BUG();
1907                 return;
1908         }
1909
1910         enable_clocks(1);
1911         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1912         enable_clocks(0);
1913 }
1914
1915 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1916 {
1917         u32 l;
1918         int stallmode;
1919         int gpout0 = 1;
1920         int gpout1;
1921
1922         switch (mode) {
1923         case OMAP_DSS_PARALLELMODE_BYPASS:
1924                 stallmode = 0;
1925                 gpout1 = 1;
1926                 break;
1927
1928         case OMAP_DSS_PARALLELMODE_RFBI:
1929                 stallmode = 1;
1930                 gpout1 = 0;
1931                 break;
1932
1933         case OMAP_DSS_PARALLELMODE_DSI:
1934                 stallmode = 1;
1935                 gpout1 = 1;
1936                 break;
1937
1938         default:
1939                 BUG();
1940                 return;
1941         }
1942
1943         enable_clocks(1);
1944
1945         l = dispc_read_reg(DISPC_CONTROL);
1946
1947         l = FLD_MOD(l, stallmode, 11, 11);
1948         l = FLD_MOD(l, gpout0, 15, 15);
1949         l = FLD_MOD(l, gpout1, 16, 16);
1950
1951         dispc_write_reg(DISPC_CONTROL, l);
1952
1953         enable_clocks(0);
1954 }
1955
1956 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1957                                    int vsw, int vfp, int vbp)
1958 {
1959         u32 timing_h, timing_v;
1960
1961         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1962                 BUG_ON(hsw < 1 || hsw > 64);
1963                 BUG_ON(hfp < 1 || hfp > 256);
1964                 BUG_ON(hbp < 1 || hbp > 256);
1965
1966                 BUG_ON(vsw < 1 || vsw > 64);
1967                 BUG_ON(vfp < 0 || vfp > 255);
1968                 BUG_ON(vbp < 0 || vbp > 255);
1969
1970                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1971                         FLD_VAL(hbp-1, 27, 20);
1972
1973                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1974                         FLD_VAL(vbp, 27, 20);
1975         } else {
1976                 BUG_ON(hsw < 1 || hsw > 256);
1977                 BUG_ON(hfp < 1 || hfp > 4096);
1978                 BUG_ON(hbp < 1 || hbp > 4096);
1979
1980                 BUG_ON(vsw < 1 || vsw > 256);
1981                 BUG_ON(vfp < 0 || vfp > 4095);
1982                 BUG_ON(vbp < 0 || vbp > 4095);
1983
1984                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1985                         FLD_VAL(hbp-1, 31, 20);
1986
1987                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1988                         FLD_VAL(vbp, 31, 20);
1989         }
1990
1991         enable_clocks(1);
1992         dispc_write_reg(DISPC_TIMING_H, timing_h);
1993         dispc_write_reg(DISPC_TIMING_V, timing_v);
1994         enable_clocks(0);
1995 }
1996
1997 /* change name to mode? */
1998 void dispc_set_lcd_timings(struct omap_video_timings *timings)
1999 {
2000         unsigned xtot, ytot;
2001         unsigned long ht, vt;
2002
2003         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2004                         timings->vsw, timings->vfp, timings->vbp);
2005
2006         dispc_set_lcd_size(timings->x_res, timings->y_res);
2007
2008         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2009         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2010
2011         ht = (timings->pixel_clock * 1000) / xtot;
2012         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2013
2014         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2015         DSSDBG("pck %u\n", timings->pixel_clock);
2016         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2017                         timings->hsw, timings->hfp, timings->hbp,
2018                         timings->vsw, timings->vfp, timings->vbp);
2019
2020         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2021 }
2022
2023 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2024 {
2025         BUG_ON(lck_div < 1);
2026         BUG_ON(pck_div < 2);
2027
2028         enable_clocks(1);
2029         dispc_write_reg(DISPC_DIVISOR,
2030                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2031         enable_clocks(0);
2032 }
2033
2034 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2035 {
2036         u32 l;
2037         l = dispc_read_reg(DISPC_DIVISOR);
2038         *lck_div = FLD_GET(l, 23, 16);
2039         *pck_div = FLD_GET(l, 7, 0);
2040 }
2041
2042 unsigned long dispc_fclk_rate(void)
2043 {
2044         unsigned long r = 0;
2045
2046         if (dss_get_dispc_clk_source() == 0)
2047                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2048         else
2049 #ifdef CONFIG_OMAP2_DSS_DSI
2050                 r = dsi_get_dsi1_pll_rate();
2051 #else
2052         BUG();
2053 #endif
2054         return r;
2055 }
2056
2057 unsigned long dispc_lclk_rate(void)
2058 {
2059         int lcd;
2060         unsigned long r;
2061         u32 l;
2062
2063         l = dispc_read_reg(DISPC_DIVISOR);
2064
2065         lcd = FLD_GET(l, 23, 16);
2066
2067         r = dispc_fclk_rate();
2068
2069         return r / lcd;
2070 }
2071
2072 unsigned long dispc_pclk_rate(void)
2073 {
2074         int lcd, pcd;
2075         unsigned long r;
2076         u32 l;
2077
2078         l = dispc_read_reg(DISPC_DIVISOR);
2079
2080         lcd = FLD_GET(l, 23, 16);
2081         pcd = FLD_GET(l, 7, 0);
2082
2083         r = dispc_fclk_rate();
2084
2085         return r / lcd / pcd;
2086 }
2087
2088 void dispc_dump_clocks(struct seq_file *s)
2089 {
2090         int lcd, pcd;
2091
2092         enable_clocks(1);
2093
2094         dispc_get_lcd_divisor(&lcd, &pcd);
2095
2096         seq_printf(s, "- dispc -\n");
2097
2098         seq_printf(s, "dispc fclk source = %s\n",
2099                         dss_get_dispc_clk_source() == 0 ?
2100                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2101
2102         seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
2103                         dispc_fclk_rate(),
2104                         lcd, pcd,
2105                         dispc_pclk_rate());
2106
2107         enable_clocks(0);
2108 }
2109
2110 void dispc_dump_regs(struct seq_file *s)
2111 {
2112 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2113
2114         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2115
2116         DUMPREG(DISPC_REVISION);
2117         DUMPREG(DISPC_SYSCONFIG);
2118         DUMPREG(DISPC_SYSSTATUS);
2119         DUMPREG(DISPC_IRQSTATUS);
2120         DUMPREG(DISPC_IRQENABLE);
2121         DUMPREG(DISPC_CONTROL);
2122         DUMPREG(DISPC_CONFIG);
2123         DUMPREG(DISPC_CAPABLE);
2124         DUMPREG(DISPC_DEFAULT_COLOR0);
2125         DUMPREG(DISPC_DEFAULT_COLOR1);
2126         DUMPREG(DISPC_TRANS_COLOR0);
2127         DUMPREG(DISPC_TRANS_COLOR1);
2128         DUMPREG(DISPC_LINE_STATUS);
2129         DUMPREG(DISPC_LINE_NUMBER);
2130         DUMPREG(DISPC_TIMING_H);
2131         DUMPREG(DISPC_TIMING_V);
2132         DUMPREG(DISPC_POL_FREQ);
2133         DUMPREG(DISPC_DIVISOR);
2134         DUMPREG(DISPC_GLOBAL_ALPHA);
2135         DUMPREG(DISPC_SIZE_DIG);
2136         DUMPREG(DISPC_SIZE_LCD);
2137
2138         DUMPREG(DISPC_GFX_BA0);
2139         DUMPREG(DISPC_GFX_BA1);
2140         DUMPREG(DISPC_GFX_POSITION);
2141         DUMPREG(DISPC_GFX_SIZE);
2142         DUMPREG(DISPC_GFX_ATTRIBUTES);
2143         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2144         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2145         DUMPREG(DISPC_GFX_ROW_INC);
2146         DUMPREG(DISPC_GFX_PIXEL_INC);
2147         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2148         DUMPREG(DISPC_GFX_TABLE_BA);
2149
2150         DUMPREG(DISPC_DATA_CYCLE1);
2151         DUMPREG(DISPC_DATA_CYCLE2);
2152         DUMPREG(DISPC_DATA_CYCLE3);
2153
2154         DUMPREG(DISPC_CPR_COEF_R);
2155         DUMPREG(DISPC_CPR_COEF_G);
2156         DUMPREG(DISPC_CPR_COEF_B);
2157
2158         DUMPREG(DISPC_GFX_PRELOAD);
2159
2160         DUMPREG(DISPC_VID_BA0(0));
2161         DUMPREG(DISPC_VID_BA1(0));
2162         DUMPREG(DISPC_VID_POSITION(0));
2163         DUMPREG(DISPC_VID_SIZE(0));
2164         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2165         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2166         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2167         DUMPREG(DISPC_VID_ROW_INC(0));
2168         DUMPREG(DISPC_VID_PIXEL_INC(0));
2169         DUMPREG(DISPC_VID_FIR(0));
2170         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2171         DUMPREG(DISPC_VID_ACCU0(0));
2172         DUMPREG(DISPC_VID_ACCU1(0));
2173
2174         DUMPREG(DISPC_VID_BA0(1));
2175         DUMPREG(DISPC_VID_BA1(1));
2176         DUMPREG(DISPC_VID_POSITION(1));
2177         DUMPREG(DISPC_VID_SIZE(1));
2178         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2179         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2180         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2181         DUMPREG(DISPC_VID_ROW_INC(1));
2182         DUMPREG(DISPC_VID_PIXEL_INC(1));
2183         DUMPREG(DISPC_VID_FIR(1));
2184         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2185         DUMPREG(DISPC_VID_ACCU0(1));
2186         DUMPREG(DISPC_VID_ACCU1(1));
2187
2188         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2189         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2190         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2191         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2192         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2193         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2194         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2195         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2196         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2197         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2198         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2199         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2200         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2201         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2202         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2203         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2204         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2205         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2206         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2207         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2208         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2209         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2210         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2211         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2212         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2213         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2214         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2215         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2216         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2217
2218         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2219         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2220         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2221         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2222         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2223         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2224         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2225         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2226         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2227         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2228         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2229         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2230         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2231         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2232         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2233         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2234         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2235         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2236         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2237         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2238         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2239         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2240         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2241         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2242         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2243         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2244         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2245         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2246         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2247
2248         DUMPREG(DISPC_VID_PRELOAD(0));
2249         DUMPREG(DISPC_VID_PRELOAD(1));
2250
2251         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2252 #undef DUMPREG
2253 }
2254
2255 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2256                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2257 {
2258         u32 l = 0;
2259
2260         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2261                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2262
2263         l |= FLD_VAL(onoff, 17, 17);
2264         l |= FLD_VAL(rf, 16, 16);
2265         l |= FLD_VAL(ieo, 15, 15);
2266         l |= FLD_VAL(ipc, 14, 14);
2267         l |= FLD_VAL(ihs, 13, 13);
2268         l |= FLD_VAL(ivs, 12, 12);
2269         l |= FLD_VAL(acbi, 11, 8);
2270         l |= FLD_VAL(acb, 7, 0);
2271
2272         enable_clocks(1);
2273         dispc_write_reg(DISPC_POL_FREQ, l);
2274         enable_clocks(0);
2275 }
2276
2277 void dispc_set_pol_freq(struct omap_panel *panel)
2278 {
2279         _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2280                                  (panel->config & OMAP_DSS_LCD_RF) != 0,
2281                                  (panel->config & OMAP_DSS_LCD_IEO) != 0,
2282                                  (panel->config & OMAP_DSS_LCD_IPC) != 0,
2283                                  (panel->config & OMAP_DSS_LCD_IHS) != 0,
2284                                  (panel->config & OMAP_DSS_LCD_IVS) != 0,
2285                                  panel->acbi, panel->acb);
2286 }
2287
2288 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2289                 u16 *lck_div, u16 *pck_div)
2290 {
2291         u16 pcd_min = is_tft ? 2 : 3;
2292         unsigned long best_pck;
2293         u16 best_ld, cur_ld;
2294         u16 best_pd, cur_pd;
2295
2296         best_pck = 0;
2297         best_ld = 0;
2298         best_pd = 0;
2299
2300         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2301                 unsigned long lck = fck / cur_ld;
2302
2303                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2304                         unsigned long pck = lck / cur_pd;
2305                         long old_delta = abs(best_pck - req_pck);
2306                         long new_delta = abs(pck - req_pck);
2307
2308                         if (best_pck == 0 || new_delta < old_delta) {
2309                                 best_pck = pck;
2310                                 best_ld = cur_ld;
2311                                 best_pd = cur_pd;
2312
2313                                 if (pck == req_pck)
2314                                         goto found;
2315                         }
2316
2317                         if (pck < req_pck)
2318                                 break;
2319                 }
2320
2321                 if (lck / pcd_min < req_pck)
2322                         break;
2323         }
2324
2325 found:
2326         *lck_div = best_ld;
2327         *pck_div = best_pd;
2328 }
2329
2330 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2331                 struct dispc_clock_info *cinfo)
2332 {
2333         unsigned long prate;
2334         struct dispc_clock_info cur, best;
2335         int match = 0;
2336         int min_fck_per_pck;
2337         unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2338
2339         if (cpu_is_omap34xx())
2340                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2341         else
2342                 prate = 0;
2343
2344         if (req_pck == dispc.cache_req_pck &&
2345                         ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2346                          dispc.cache_cinfo.fck == fck_rate)) {
2347                 DSSDBG("dispc clock info found from cache.\n");
2348                 *cinfo = dispc.cache_cinfo;
2349                 return 0;
2350         }
2351
2352         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2353
2354         if (min_fck_per_pck &&
2355                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2356                 DSSERR("Requested pixel clock not possible with the current "
2357                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2358                                 "the constraint off.\n");
2359                 min_fck_per_pck = 0;
2360         }
2361
2362 retry:
2363         memset(&cur, 0, sizeof(cur));
2364         memset(&best, 0, sizeof(best));
2365
2366         if (cpu_is_omap24xx()) {
2367                 /* XXX can we change the clock on omap2? */
2368                 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2369                 cur.fck_div = 1;
2370
2371                 match = 1;
2372
2373                 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2374                                 &cur.lck_div, &cur.pck_div);
2375
2376                 cur.lck = cur.fck / cur.lck_div;
2377                 cur.pck = cur.lck / cur.pck_div;
2378
2379                 best = cur;
2380
2381                 goto found;
2382         } else if (cpu_is_omap34xx()) {
2383                 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2384                         cur.fck = prate / cur.fck_div * 2;
2385
2386                         if (cur.fck > DISPC_MAX_FCK)
2387                                 continue;
2388
2389                         if (min_fck_per_pck &&
2390                                         cur.fck < req_pck * min_fck_per_pck)
2391                                 continue;
2392
2393                         match = 1;
2394
2395                         find_lck_pck_divs(is_tft, req_pck, cur.fck,
2396                                         &cur.lck_div, &cur.pck_div);
2397
2398                         cur.lck = cur.fck / cur.lck_div;
2399                         cur.pck = cur.lck / cur.pck_div;
2400
2401                         if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2402                                 best = cur;
2403
2404                                 if (cur.pck == req_pck)
2405                                         goto found;
2406                         }
2407                 }
2408         } else {
2409                 BUG();
2410         }
2411
2412 found:
2413         if (!match) {
2414                 if (min_fck_per_pck) {
2415                         DSSERR("Could not find suitable clock settings.\n"
2416                                         "Turning FCK/PCK constraint off and"
2417                                         "trying again.\n");
2418                         min_fck_per_pck = 0;
2419                         goto retry;
2420                 }
2421
2422                 DSSERR("Could not find suitable clock settings.\n");
2423
2424                 return -EINVAL;
2425         }
2426
2427         if (cinfo)
2428                 *cinfo = best;
2429
2430         dispc.cache_req_pck = req_pck;
2431         dispc.cache_prate = prate;
2432         dispc.cache_cinfo = best;
2433
2434         return 0;
2435 }
2436
2437 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2438 {
2439         unsigned long prate;
2440         int r;
2441
2442         if (cpu_is_omap34xx()) {
2443                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2444                 DSSDBG("dpll4_m4 = %ld\n", prate);
2445         }
2446
2447         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2448         DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2449         DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2450
2451         if (cpu_is_omap34xx()) {
2452                 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2453                 if (r)
2454                         return r;
2455         }
2456
2457         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2458
2459         return 0;
2460 }
2461
2462 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2463 {
2464         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2465
2466         if (cpu_is_omap34xx()) {
2467                 unsigned long prate;
2468                 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2469                 cinfo->fck_div = prate / (cinfo->fck / 2);
2470         } else {
2471                 cinfo->fck_div = 0;
2472         }
2473
2474         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2475         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2476
2477         cinfo->lck = cinfo->fck / cinfo->lck_div;
2478         cinfo->pck = cinfo->lck / cinfo->pck_div;
2479
2480         return 0;
2481 }
2482
2483 static void omap_dispc_set_irqs(void)
2484 {
2485         unsigned long flags;
2486         u32 mask = dispc.irq_error_mask;
2487         int i;
2488         struct omap_dispc_isr_data *isr_data;
2489
2490         spin_lock_irqsave(&dispc.irq_lock, flags);
2491
2492         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2493                 isr_data = &dispc.registered_isr[i];
2494
2495                 if (isr_data->isr == NULL)
2496                         continue;
2497
2498                 mask |= isr_data->mask;
2499         }
2500
2501         enable_clocks(1);
2502         dispc_write_reg(DISPC_IRQENABLE, mask);
2503         enable_clocks(0);
2504
2505         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2506 }
2507
2508 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2509 {
2510         int i;
2511         int ret;
2512         unsigned long flags;
2513         struct omap_dispc_isr_data *isr_data;
2514
2515         if (isr == NULL)
2516                 return -EINVAL;
2517
2518         spin_lock_irqsave(&dispc.irq_lock, flags);
2519
2520         /* check for duplicate entry */
2521         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2522                 isr_data = &dispc.registered_isr[i];
2523                 if (isr_data->isr == isr && isr_data->arg == arg &&
2524                                 isr_data->mask == mask) {
2525                         ret = -EINVAL;
2526                         goto err;
2527                 }
2528         }
2529
2530         isr_data = NULL;
2531         ret = -EBUSY;
2532
2533         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2534                 isr_data = &dispc.registered_isr[i];
2535
2536                 if (isr_data->isr != NULL)
2537                         continue;
2538
2539                 isr_data->isr = isr;
2540                 isr_data->arg = arg;
2541                 isr_data->mask = mask;
2542                 ret = 0;
2543
2544                 break;
2545         }
2546 err:
2547         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2548
2549         if (ret == 0)
2550                 omap_dispc_set_irqs();
2551
2552         return ret;
2553 }
2554 EXPORT_SYMBOL(omap_dispc_register_isr);
2555
2556 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2557 {
2558         int i;
2559         unsigned long flags;
2560         int ret = -EINVAL;
2561         struct omap_dispc_isr_data *isr_data;
2562
2563         spin_lock_irqsave(&dispc.irq_lock, flags);
2564
2565         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2566                 isr_data = &dispc.registered_isr[i];
2567                 if (isr_data->isr != isr || isr_data->arg != arg ||
2568                                 isr_data->mask != mask)
2569                         continue;
2570
2571                 /* found the correct isr */
2572
2573                 isr_data->isr = NULL;
2574                 isr_data->arg = NULL;
2575                 isr_data->mask = 0;
2576
2577                 ret = 0;
2578                 break;
2579         }
2580
2581         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2582
2583         if (ret == 0)
2584                 omap_dispc_set_irqs();
2585
2586         return ret;
2587 }
2588 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2589
2590 #ifdef DEBUG
2591 static void print_irq_status(u32 status)
2592 {
2593         if ((status & dispc.irq_error_mask) == 0)
2594                 return;
2595
2596         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2597
2598 #define PIS(x) \
2599         if (status & DISPC_IRQ_##x) \
2600                 printk(#x " ");
2601         PIS(GFX_FIFO_UNDERFLOW);
2602         PIS(OCP_ERR);
2603         PIS(VID1_FIFO_UNDERFLOW);
2604         PIS(VID2_FIFO_UNDERFLOW);
2605         PIS(SYNC_LOST);
2606         PIS(SYNC_LOST_DIGIT);
2607 #undef PIS
2608
2609         printk("\n");
2610 }
2611 #endif
2612
2613 /* Called from dss.c. Note that we don't touch clocks here,
2614  * but we presume they are on because we got an IRQ. However,
2615  * an irq handler may turn the clocks off, so we may not have
2616  * clock later in the function. */
2617 void dispc_irq_handler(void)
2618 {
2619         int i;
2620         u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2621         u32 handledirqs = 0;
2622         u32 unhandled_errors;
2623         struct omap_dispc_isr_data *isr_data;
2624
2625 #ifdef DEBUG
2626         if (dss_debug)
2627                 print_irq_status(irqstatus);
2628 #endif
2629         /* Ack the interrupt. Do it here before clocks are possibly turned
2630          * off */
2631         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2632
2633         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2634                 isr_data = &dispc.registered_isr[i];
2635
2636                 if (!isr_data->isr)
2637                         continue;
2638
2639                 if (isr_data->mask & irqstatus) {
2640                         isr_data->isr(isr_data->arg, irqstatus);
2641                         handledirqs |= isr_data->mask;
2642                 }
2643         }
2644
2645         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2646
2647         if (unhandled_errors) {
2648                 spin_lock(&dispc.error_lock);
2649                 dispc.error_irqs |= unhandled_errors;
2650                 spin_unlock(&dispc.error_lock);
2651
2652                 dispc.irq_error_mask &= ~unhandled_errors;
2653                 omap_dispc_set_irqs();
2654
2655                 schedule_work(&dispc.error_work);
2656         }
2657 }
2658
2659 static void dispc_error_worker(struct work_struct *work)
2660 {
2661         int i;
2662         u32 errors;
2663         unsigned long flags;
2664
2665         spin_lock_irqsave(&dispc.error_lock, flags);
2666         errors = dispc.error_irqs;
2667         dispc.error_irqs = 0;
2668         spin_unlock_irqrestore(&dispc.error_lock, flags);
2669
2670         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2671                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2672                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2673                         struct omap_overlay *ovl;
2674                         ovl = omap_dss_get_overlay(i);
2675
2676                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2677                                 continue;
2678
2679                         if (ovl->id == 0) {
2680                                 dispc_enable_plane(ovl->id, 0);
2681                                 dispc_go(ovl->manager->id);
2682                                 mdelay(50);
2683                                 break;
2684                         }
2685                 }
2686         }
2687
2688         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2689                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2690                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2691                         struct omap_overlay *ovl;
2692                         ovl = omap_dss_get_overlay(i);
2693
2694                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2695                                 continue;
2696
2697                         if (ovl->id == 1) {
2698                                 dispc_enable_plane(ovl->id, 0);
2699                                 dispc_go(ovl->manager->id);
2700                                 mdelay(50);
2701                                 break;
2702                         }
2703                 }
2704         }
2705
2706         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2707                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2708                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2709                         struct omap_overlay *ovl;
2710                         ovl = omap_dss_get_overlay(i);
2711
2712                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2713                                 continue;
2714
2715                         if (ovl->id == 2) {
2716                                 dispc_enable_plane(ovl->id, 0);
2717                                 dispc_go(ovl->manager->id);
2718                                 mdelay(50);
2719                                 break;
2720                         }
2721                 }
2722         }
2723
2724         if (errors & DISPC_IRQ_SYNC_LOST) {
2725                 struct omap_overlay_manager *manager = NULL;
2726                 bool enable = false;
2727
2728                 DSSERR("SYNC_LOST, disabling LCD\n");
2729
2730                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2731                         struct omap_overlay_manager *mgr;
2732                         mgr = omap_dss_get_overlay_manager(i);
2733
2734                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2735                                 manager = mgr;
2736                                 enable = mgr->display->state ==
2737                                                 OMAP_DSS_DISPLAY_ACTIVE;
2738                                 mgr->display->disable(mgr->display);
2739                                 break;
2740                         }
2741                 }
2742
2743                 if (manager) {
2744                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2745                                 struct omap_overlay *ovl;
2746                                 ovl = omap_dss_get_overlay(i);
2747
2748                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2749                                         continue;
2750
2751                                 if (ovl->id != 0 && ovl->manager == manager)
2752                                         dispc_enable_plane(ovl->id, 0);
2753                         }
2754
2755                         dispc_go(manager->id);
2756                         mdelay(50);
2757                         if (enable)
2758                                 manager->display->enable(manager->display);
2759                 }
2760         }
2761
2762         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2763                 struct omap_overlay_manager *manager = NULL;
2764                 bool enable = false;
2765
2766                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2767
2768                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2769                         struct omap_overlay_manager *mgr;
2770                         mgr = omap_dss_get_overlay_manager(i);
2771
2772                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2773                                 manager = mgr;
2774                                 enable = mgr->display->state ==
2775                                                 OMAP_DSS_DISPLAY_ACTIVE;
2776                                 mgr->display->disable(mgr->display);
2777                                 break;
2778                         }
2779                 }
2780
2781                 if (manager) {
2782                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2783                                 struct omap_overlay *ovl;
2784                                 ovl = omap_dss_get_overlay(i);
2785
2786                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2787                                         continue;
2788
2789                                 if (ovl->id != 0 && ovl->manager == manager)
2790                                         dispc_enable_plane(ovl->id, 0);
2791                         }
2792
2793                         dispc_go(manager->id);
2794                         mdelay(50);
2795                         if (enable)
2796                                 manager->display->enable(manager->display);
2797                 }
2798         }
2799
2800         if (errors & DISPC_IRQ_OCP_ERR) {
2801                 DSSERR("OCP_ERR\n");
2802                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2803                         struct omap_overlay_manager *mgr;
2804                         mgr = omap_dss_get_overlay_manager(i);
2805
2806                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2807                                 mgr->display->disable(mgr->display);
2808                 }
2809         }
2810
2811         dispc.irq_error_mask |= errors;
2812         omap_dispc_set_irqs();
2813 }
2814
2815 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2816 {
2817         void dispc_irq_wait_handler(void *data, u32 mask)
2818         {
2819                 complete((struct completion *)data);
2820         }
2821
2822         int r;
2823         DECLARE_COMPLETION_ONSTACK(completion);
2824
2825         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2826                         irqmask);
2827
2828         if (r)
2829                 return r;
2830
2831         timeout = wait_for_completion_timeout(&completion, timeout);
2832
2833         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2834
2835         if (timeout == 0)
2836                 return -ETIMEDOUT;
2837
2838         if (timeout == -ERESTARTSYS)
2839                 return -ERESTARTSYS;
2840
2841         return 0;
2842 }
2843
2844 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2845                 unsigned long timeout)
2846 {
2847         void dispc_irq_wait_handler(void *data, u32 mask)
2848         {
2849                 complete((struct completion *)data);
2850         }
2851
2852         int r;
2853         DECLARE_COMPLETION_ONSTACK(completion);
2854
2855         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2856                         irqmask);
2857
2858         if (r)
2859                 return r;
2860
2861         timeout = wait_for_completion_interruptible_timeout(&completion,
2862                         timeout);
2863
2864         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2865
2866         if (timeout == 0)
2867                 return -ETIMEDOUT;
2868
2869         if (timeout == -ERESTARTSYS)
2870                 return -ERESTARTSYS;
2871
2872         return 0;
2873 }
2874
2875 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2876 void dispc_fake_vsync_irq(void)
2877 {
2878         u32 irqstatus = DISPC_IRQ_VSYNC;
2879         int i;
2880
2881         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2882                 struct omap_dispc_isr_data *isr_data;
2883                 isr_data = &dispc.registered_isr[i];
2884
2885                 if (!isr_data->isr)
2886                         continue;
2887
2888                 if (isr_data->mask & irqstatus)
2889                         isr_data->isr(isr_data->arg, irqstatus);
2890         }
2891 }
2892 #endif
2893
2894 static void _omap_dispc_initialize_irq(void)
2895 {
2896         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2897
2898         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2899
2900         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2901          * so clear it */
2902         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2903
2904         omap_dispc_set_irqs();
2905 }
2906
2907 void dispc_enable_sidle(void)
2908 {
2909         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
2910 }
2911
2912 void dispc_disable_sidle(void)
2913 {
2914         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
2915 }
2916
2917 static void _omap_dispc_initial_config(void)
2918 {
2919         u32 l;
2920
2921         l = dispc_read_reg(DISPC_SYSCONFIG);
2922         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
2923         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
2924         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
2925         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
2926         dispc_write_reg(DISPC_SYSCONFIG, l);
2927
2928         /* FUNCGATED */
2929         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2930
2931         /* L3 firewall setting: enable access to OCM RAM */
2932         if (cpu_is_omap24xx())
2933                 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2934
2935         _dispc_setup_color_conv_coef();
2936
2937         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2938 }
2939
2940 int dispc_init(void)
2941 {
2942         u32 rev;
2943
2944         spin_lock_init(&dispc.irq_lock);
2945         spin_lock_init(&dispc.error_lock);
2946
2947         INIT_WORK(&dispc.error_work, dispc_error_worker);
2948
2949         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2950         if (!dispc.base) {
2951                 DSSERR("can't ioremap DISPC\n");
2952                 return -ENOMEM;
2953         }
2954
2955         if (cpu_is_omap34xx()) {
2956                 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2957                 if (IS_ERR(dispc.dpll4_m4_ck)) {
2958                         DSSERR("Failed to get dpll4_m4_ck\n");
2959                         return -ENODEV;
2960                 }
2961         }
2962
2963         enable_clocks(1);
2964
2965         _omap_dispc_initial_config();
2966
2967         _omap_dispc_initialize_irq();
2968
2969         dispc_save_context();
2970
2971         rev = dispc_read_reg(DISPC_REVISION);
2972         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2973                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2974
2975         enable_clocks(0);
2976
2977         return 0;
2978 }
2979
2980 void dispc_exit(void)
2981 {
2982         if (cpu_is_omap34xx())
2983                 clk_put(dispc.dpll4_m4_ck);
2984         iounmap(dispc.base);
2985 }
2986
2987 int dispc_enable_plane(enum omap_plane plane, bool enable)
2988 {
2989         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2990
2991         enable_clocks(1);
2992         _dispc_enable_plane(plane, enable);
2993         enable_clocks(0);
2994
2995         return 0;
2996 }
2997
2998 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
2999                        u32 paddr, u16 screen_width,
3000                        u16 pos_x, u16 pos_y,
3001                        u16 width, u16 height,
3002                        u16 out_width, u16 out_height,
3003                        enum omap_color_mode color_mode,
3004                        bool ilace,
3005                        enum omap_dss_rotation_type rotation_type,
3006                        u8 rotation, bool mirror)
3007 {
3008         int r = 0;
3009
3010         DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
3011                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3012                plane, channel_out, paddr, screen_width, pos_x, pos_y,
3013                width, height,
3014                out_width, out_height,
3015                ilace, color_mode,
3016                rotation, mirror);
3017
3018         enable_clocks(1);
3019
3020         r = _dispc_setup_plane(plane, channel_out,
3021                            paddr, screen_width,
3022                            pos_x, pos_y,
3023                            width, height,
3024                            out_width, out_height,
3025                            color_mode, ilace,
3026                            rotation_type,
3027                            rotation, mirror);
3028
3029         enable_clocks(0);
3030
3031         return r;
3032 }
3033
3034 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
3035                                  int x2, int y2, int w2, int h2)
3036 {
3037         if (x1 >= (x2+w2))
3038                 return 0;
3039
3040         if ((x1+w1) <= x2)
3041                 return 0;
3042
3043         if (y1 >= (y2+h2))
3044                 return 0;
3045
3046         if ((y1+h1) <= y2)
3047                 return 0;
3048
3049         return 1;
3050 }
3051
3052 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
3053 {
3054         if (pi->width != pi->out_width)
3055                 return 1;
3056
3057         if (pi->height != pi->out_height)
3058                 return 1;
3059
3060         return 0;
3061 }
3062
3063 /* returns the area that needs updating */
3064 void dispc_setup_partial_planes(struct omap_display *display,
3065                                     u16 *xi, u16 *yi, u16 *wi, u16 *hi)
3066 {
3067         struct omap_overlay_manager *mgr;
3068         int i;
3069
3070         int x, y, w, h;
3071
3072         x = *xi;
3073         y = *yi;
3074         w = *wi;
3075         h = *hi;
3076
3077         DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
3078                 *xi, *yi, *wi, *hi);
3079
3080
3081         mgr = display->manager;
3082
3083         if (!mgr) {
3084                 DSSDBG("no manager\n");
3085                 return;
3086         }
3087
3088         for (i = 0; i < mgr->num_overlays; i++) {
3089                 struct omap_overlay *ovl;
3090                 struct omap_overlay_info *pi;
3091                 ovl = mgr->overlays[i];
3092
3093                 if (ovl->manager != mgr)
3094                         continue;
3095
3096                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
3097                         continue;
3098
3099                 pi = &ovl->info;
3100
3101                 if (!pi->enabled)
3102                         continue;
3103                 /*
3104                  * If the plane is intersecting and scaled, we
3105                  * enlarge the update region to accomodate the
3106                  * whole area
3107                  */
3108
3109                 if (dispc_is_intersecting(x, y, w, h,
3110                                           pi->pos_x, pi->pos_y,
3111                                           pi->out_width, pi->out_height)) {
3112                         if (dispc_is_overlay_scaled(pi)) {
3113
3114                                 int x1, y1, x2, y2;
3115
3116                                 if (x > pi->pos_x)
3117                                         x1 = pi->pos_x;
3118                                 else
3119                                         x1 = x;
3120
3121                                 if (y > pi->pos_y)
3122                                         y1 = pi->pos_y;
3123                                 else
3124                                         y1 = y;
3125
3126                                 if ((x + w) < (pi->pos_x + pi->out_width))
3127                                         x2 = pi->pos_x + pi->out_width;
3128                                 else
3129                                         x2 = x + w;
3130
3131                                 if ((y + h) < (pi->pos_y + pi->out_height))
3132                                         y2 = pi->pos_y + pi->out_height;
3133                                 else
3134                                         y2 = y + h;
3135
3136                                 x = x1;
3137                                 y = y1;
3138                                 w = x2 - x1;
3139                                 h = y2 - y1;
3140
3141                                 DSSDBG("Update area after enlarge due to "
3142                                         "scaling %d, %d %dx%d\n",
3143                                         x, y, w, h);
3144                         }
3145                 }
3146         }
3147
3148         for (i = 0; i < mgr->num_overlays; i++) {
3149                 struct omap_overlay *ovl = mgr->overlays[i];
3150                 struct omap_overlay_info *pi = &ovl->info;
3151
3152                 int px = pi->pos_x;
3153                 int py = pi->pos_y;
3154                 int pw = pi->width;
3155                 int ph = pi->height;
3156                 int pow = pi->out_width;
3157                 int poh = pi->out_height;
3158                 u32 pa = pi->paddr;
3159                 int psw = pi->screen_width;
3160                 int bpp;
3161
3162                 if (ovl->manager != mgr)
3163                         continue;
3164
3165                 /*
3166                  * If plane is not enabled or the update region
3167                  * does not intersect with the plane in question,
3168                  * we really disable the plane from hardware
3169                  */
3170
3171                 if (!pi->enabled ||
3172                     !dispc_is_intersecting(x, y, w, h,
3173                                            px, py, pow, poh)) {
3174                         dispc_enable_plane(ovl->id, 0);
3175                         continue;
3176                 }
3177
3178                 switch (pi->color_mode) {
3179                 case OMAP_DSS_COLOR_RGB16:
3180                 case OMAP_DSS_COLOR_ARGB16:
3181                 case OMAP_DSS_COLOR_YUV2:
3182                 case OMAP_DSS_COLOR_UYVY:
3183                         bpp = 16;
3184                         break;
3185
3186                 case OMAP_DSS_COLOR_RGB24P:
3187                         bpp = 24;
3188                         break;
3189
3190                 case OMAP_DSS_COLOR_RGB24U:
3191                 case OMAP_DSS_COLOR_ARGB32:
3192                 case OMAP_DSS_COLOR_RGBA32:
3193                 case OMAP_DSS_COLOR_RGBX32:
3194                         bpp = 32;
3195                         break;
3196
3197                 default:
3198                         BUG();
3199                         return;
3200                 }
3201
3202                 if (x > pi->pos_x) {
3203                         px = 0;
3204                         pw -= (x - pi->pos_x);
3205                         pa += (x - pi->pos_x) * bpp / 8;
3206                 } else {
3207                         px = pi->pos_x - x;
3208                 }
3209
3210                 if (y > pi->pos_y) {
3211                         py = 0;
3212                         ph -= (y - pi->pos_y);
3213                         pa += (y - pi->pos_y) * psw * bpp / 8;
3214                 } else {
3215                         py = pi->pos_y - y;
3216                 }
3217
3218                 if (w < (px+pw))
3219                         pw -= (px+pw) - (w);
3220
3221                 if (h < (py+ph))
3222                         ph -= (py+ph) - (h);
3223
3224                 /* Can't scale the GFX plane */
3225                 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3226                                 dispc_is_overlay_scaled(pi) == 0) {
3227                         pow = pw;
3228                         poh = ph;
3229                 }
3230
3231                 DSSDBG("calc  plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3232                                 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3233
3234                 dispc_setup_plane(ovl->id, mgr->id,
3235                                 pa, psw,
3236                                 px, py,
3237                                 pw, ph,
3238                                 pow, poh,
3239                                 pi->color_mode, 0,
3240                                 pi->rotation_type,
3241                                 pi->rotation,
3242                                 pi->mirror);
3243
3244                 dispc_enable_plane(ovl->id, 1);
3245         }
3246
3247         *xi = x;
3248         *yi = y;
3249         *wi = w;
3250         *hi = h;
3251
3252 }
3253