4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
41 #include "intelfbhw.h"
44 int min_m, max_m, min_m1, max_m1;
45 int min_m2, max_m2, min_n, max_n;
46 int min_p, max_p, min_p1, max_p1;
47 int min_vco, max_vco, p_transition_clk, ref_clk;
48 int p_inc_lo, p_inc_hi;
55 static struct pll_min_max plls[PLLS_MAX] = {
59 930000, 1400000, 165000, 48000,
65 1400000, 2800000, 200000, 96000,
70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
76 switch (pdev->device) {
77 case PCI_DEVICE_ID_INTEL_830M:
78 dinfo->name = "Intel(R) 830M";
79 dinfo->chipset = INTEL_830M;
81 dinfo->pll_index = PLLS_I8xx;
83 case PCI_DEVICE_ID_INTEL_845G:
84 dinfo->name = "Intel(R) 845G";
85 dinfo->chipset = INTEL_845G;
87 dinfo->pll_index = PLLS_I8xx;
89 case PCI_DEVICE_ID_INTEL_85XGM:
92 dinfo->pll_index = PLLS_I8xx;
93 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
94 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
95 INTEL_85X_VARIANT_MASK) {
96 case INTEL_VAR_855GME:
97 dinfo->name = "Intel(R) 855GME";
98 dinfo->chipset = INTEL_855GME;
100 case INTEL_VAR_855GM:
101 dinfo->name = "Intel(R) 855GM";
102 dinfo->chipset = INTEL_855GM;
104 case INTEL_VAR_852GME:
105 dinfo->name = "Intel(R) 852GME";
106 dinfo->chipset = INTEL_852GME;
108 case INTEL_VAR_852GM:
109 dinfo->name = "Intel(R) 852GM";
110 dinfo->chipset = INTEL_852GM;
113 dinfo->name = "Intel(R) 852GM/855GM";
114 dinfo->chipset = INTEL_85XGM;
118 case PCI_DEVICE_ID_INTEL_865G:
119 dinfo->name = "Intel(R) 865G";
120 dinfo->chipset = INTEL_865G;
122 dinfo->pll_index = PLLS_I8xx;
124 case PCI_DEVICE_ID_INTEL_915G:
125 dinfo->name = "Intel(R) 915G";
126 dinfo->chipset = INTEL_915G;
128 dinfo->pll_index = PLLS_I9xx;
130 case PCI_DEVICE_ID_INTEL_915GM:
131 dinfo->name = "Intel(R) 915GM";
132 dinfo->chipset = INTEL_915GM;
134 dinfo->pll_index = PLLS_I9xx;
136 case PCI_DEVICE_ID_INTEL_945G:
137 dinfo->name = "Intel(R) 945G";
138 dinfo->chipset = INTEL_945G;
140 dinfo->pll_index = PLLS_I9xx;
142 case PCI_DEVICE_ID_INTEL_945GM:
143 dinfo->name = "Intel(R) 945GM";
144 dinfo->chipset = INTEL_945GM;
146 dinfo->pll_index = PLLS_I9xx;
154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
157 struct pci_dev *bridge_dev;
161 if (!pdev || !aperture_size || !stolen_size)
164 /* Find the bridge device. It is always 0:0.0 */
165 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
166 ERR_MSG("cannot find bridge device\n");
170 /* Get the fb aperture size and "stolen" memory amount. */
172 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
173 switch (pdev->device) {
174 case PCI_DEVICE_ID_INTEL_915G:
175 case PCI_DEVICE_ID_INTEL_915GM:
176 case PCI_DEVICE_ID_INTEL_945G:
177 case PCI_DEVICE_ID_INTEL_945GM:
178 /* 915 and 945 chipsets support a 256MB aperture.
179 Aperture size is determined by inspected the
180 base address of the aperture. */
181 if (pci_resource_start(pdev, 2) & 0x08000000)
182 *aperture_size = MB(128);
184 *aperture_size = MB(256);
187 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
188 *aperture_size = MB(64);
190 *aperture_size = MB(128);
194 /* Stolen memory size is reduced by the GTT and the popup.
195 GTT is 1K per MB of aperture size, and popup is 4K. */
196 stolen_overhead = (*aperture_size / MB(1)) + 4;
197 switch(pdev->device) {
198 case PCI_DEVICE_ID_INTEL_830M:
199 case PCI_DEVICE_ID_INTEL_845G:
200 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
201 case INTEL_830_GMCH_GMS_STOLEN_512:
202 *stolen_size = KB(512) - KB(stolen_overhead);
204 case INTEL_830_GMCH_GMS_STOLEN_1024:
205 *stolen_size = MB(1) - KB(stolen_overhead);
207 case INTEL_830_GMCH_GMS_STOLEN_8192:
208 *stolen_size = MB(8) - KB(stolen_overhead);
210 case INTEL_830_GMCH_GMS_LOCAL:
211 ERR_MSG("only local memory found\n");
213 case INTEL_830_GMCH_GMS_DISABLED:
214 ERR_MSG("video memory is disabled\n");
217 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
218 tmp & INTEL_830_GMCH_GMS_MASK);
223 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
224 case INTEL_855_GMCH_GMS_STOLEN_1M:
225 *stolen_size = MB(1) - KB(stolen_overhead);
227 case INTEL_855_GMCH_GMS_STOLEN_4M:
228 *stolen_size = MB(4) - KB(stolen_overhead);
230 case INTEL_855_GMCH_GMS_STOLEN_8M:
231 *stolen_size = MB(8) - KB(stolen_overhead);
233 case INTEL_855_GMCH_GMS_STOLEN_16M:
234 *stolen_size = MB(16) - KB(stolen_overhead);
236 case INTEL_855_GMCH_GMS_STOLEN_32M:
237 *stolen_size = MB(32) - KB(stolen_overhead);
239 case INTEL_915G_GMCH_GMS_STOLEN_48M:
240 *stolen_size = MB(48) - KB(stolen_overhead);
242 case INTEL_915G_GMCH_GMS_STOLEN_64M:
243 *stolen_size = MB(64) - KB(stolen_overhead);
245 case INTEL_855_GMCH_GMS_DISABLED:
246 ERR_MSG("video memory is disabled\n");
249 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
250 tmp & INTEL_855_GMCH_GMS_MASK);
257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
261 if (INREG(LVDS) & PORT_ENABLE)
263 if (INREG(DVOA) & PORT_ENABLE)
265 if (INREG(DVOB) & PORT_ENABLE)
267 if (INREG(DVOC) & PORT_ENABLE)
274 intelfbhw_dvo_to_string(int dvo)
278 else if (dvo & DVOB_PORT)
280 else if (dvo & DVOC_PORT)
282 else if (dvo & LVDS_PORT)
290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
291 struct fb_var_screeninfo *var)
297 DBG_MSG("intelfbhw_validate_mode\n");
300 bytes_per_pixel = var->bits_per_pixel / 8;
301 if (bytes_per_pixel == 3)
304 /* Check if enough video memory. */
305 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
306 if (tmp > dinfo->fb.size) {
307 WRN_MSG("Not enough video ram for mode "
308 "(%d KByte vs %d KByte).\n",
309 BtoKB(tmp), BtoKB(dinfo->fb.size));
313 /* Check if x/y limits are OK. */
314 if (var->xres - 1 > HACTIVE_MASK) {
315 WRN_MSG("X resolution too large (%d vs %d).\n",
316 var->xres, HACTIVE_MASK + 1);
319 if (var->yres - 1 > VACTIVE_MASK) {
320 WRN_MSG("Y resolution too large (%d vs %d).\n",
321 var->yres, VACTIVE_MASK + 1);
325 /* Check for interlaced/doublescan modes. */
326 if (var->vmode & FB_VMODE_INTERLACED) {
327 WRN_MSG("Mode is interlaced.\n");
330 if (var->vmode & FB_VMODE_DOUBLE) {
331 WRN_MSG("Mode is double-scan.\n");
335 /* Check if clock is OK. */
336 tmp = 1000000000 / var->pixclock;
337 if (tmp < MIN_CLOCK) {
338 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
339 (tmp + 500) / 1000, MIN_CLOCK / 1000);
342 if (tmp > MAX_CLOCK) {
343 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
344 (tmp + 500) / 1000, MAX_CLOCK / 1000);
352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
354 struct intelfb_info *dinfo = GET_DINFO(info);
355 u32 offset, xoffset, yoffset;
358 DBG_MSG("intelfbhw_pan_display\n");
361 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
362 yoffset = var->yoffset;
364 if ((xoffset + var->xres > var->xres_virtual) ||
365 (yoffset + var->yres > var->yres_virtual))
368 offset = (yoffset * dinfo->pitch) +
369 (xoffset * var->bits_per_pixel) / 8;
371 offset += dinfo->fb.offset << 12;
373 OUTREG(DSPABASE, offset);
378 /* Blank the screen. */
380 intelfbhw_do_blank(int blank, struct fb_info *info)
382 struct intelfb_info *dinfo = GET_DINFO(info);
386 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
389 /* Turn plane A on or off */
390 tmp = INREG(DSPACNTR);
392 tmp &= ~DISPPLANE_PLANE_ENABLE;
394 tmp |= DISPPLANE_PLANE_ENABLE;
395 OUTREG(DSPACNTR, tmp);
397 tmp = INREG(DSPABASE);
398 OUTREG(DSPABASE, tmp);
400 /* Turn off/on the HW cursor */
402 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
404 if (dinfo->cursor_on) {
406 intelfbhw_cursor_hide(dinfo);
408 intelfbhw_cursor_show(dinfo);
410 dinfo->cursor_on = 1;
412 dinfo->cursor_blanked = blank;
415 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
417 case FB_BLANK_UNBLANK:
418 case FB_BLANK_NORMAL:
421 case FB_BLANK_VSYNC_SUSPEND:
424 case FB_BLANK_HSYNC_SUSPEND:
427 case FB_BLANK_POWERDOWN:
438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
439 unsigned red, unsigned green, unsigned blue,
443 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
444 regno, red, green, blue);
447 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
448 PALETTE_A : PALETTE_B;
450 OUTREG(palette_reg + (regno << 2),
451 (red << PALETTE_8_RED_SHIFT) |
452 (green << PALETTE_8_GREEN_SHIFT) |
453 (blue << PALETTE_8_BLUE_SHIFT));
458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
464 DBG_MSG("intelfbhw_read_hw_state\n");
470 /* Read in as much of the HW state as possible. */
471 hw->vga0_divisor = INREG(VGA0_DIVISOR);
472 hw->vga1_divisor = INREG(VGA1_DIVISOR);
473 hw->vga_pd = INREG(VGAPD);
474 hw->dpll_a = INREG(DPLL_A);
475 hw->dpll_b = INREG(DPLL_B);
476 hw->fpa0 = INREG(FPA0);
477 hw->fpa1 = INREG(FPA1);
478 hw->fpb0 = INREG(FPB0);
479 hw->fpb1 = INREG(FPB1);
485 /* This seems to be a problem with the 852GM/855GM */
486 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
487 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
488 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
495 hw->htotal_a = INREG(HTOTAL_A);
496 hw->hblank_a = INREG(HBLANK_A);
497 hw->hsync_a = INREG(HSYNC_A);
498 hw->vtotal_a = INREG(VTOTAL_A);
499 hw->vblank_a = INREG(VBLANK_A);
500 hw->vsync_a = INREG(VSYNC_A);
501 hw->src_size_a = INREG(SRC_SIZE_A);
502 hw->bclrpat_a = INREG(BCLRPAT_A);
503 hw->htotal_b = INREG(HTOTAL_B);
504 hw->hblank_b = INREG(HBLANK_B);
505 hw->hsync_b = INREG(HSYNC_B);
506 hw->vtotal_b = INREG(VTOTAL_B);
507 hw->vblank_b = INREG(VBLANK_B);
508 hw->vsync_b = INREG(VSYNC_B);
509 hw->src_size_b = INREG(SRC_SIZE_B);
510 hw->bclrpat_b = INREG(BCLRPAT_B);
515 hw->adpa = INREG(ADPA);
516 hw->dvoa = INREG(DVOA);
517 hw->dvob = INREG(DVOB);
518 hw->dvoc = INREG(DVOC);
519 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
520 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
521 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
522 hw->lvds = INREG(LVDS);
527 hw->pipe_a_conf = INREG(PIPEACONF);
528 hw->pipe_b_conf = INREG(PIPEBCONF);
529 hw->disp_arb = INREG(DISPARB);
534 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
535 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
536 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
537 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
542 for (i = 0; i < 4; i++) {
543 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
544 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
550 hw->cursor_size = INREG(CURSOR_SIZE);
555 hw->disp_a_ctrl = INREG(DSPACNTR);
556 hw->disp_b_ctrl = INREG(DSPBCNTR);
557 hw->disp_a_base = INREG(DSPABASE);
558 hw->disp_b_base = INREG(DSPBBASE);
559 hw->disp_a_stride = INREG(DSPASTRIDE);
560 hw->disp_b_stride = INREG(DSPBSTRIDE);
565 hw->vgacntrl = INREG(VGACNTRL);
570 hw->add_id = INREG(ADD_ID);
575 for (i = 0; i < 7; i++) {
576 hw->swf0x[i] = INREG(SWF00 + (i << 2));
577 hw->swf1x[i] = INREG(SWF10 + (i << 2));
579 hw->swf3x[i] = INREG(SWF30 + (i << 2));
582 for (i = 0; i < 8; i++)
583 hw->fence[i] = INREG(FENCE + (i << 2));
585 hw->instpm = INREG(INSTPM);
586 hw->mem_mode = INREG(MEM_MODE);
587 hw->fw_blc_0 = INREG(FW_BLC_0);
588 hw->fw_blc_1 = INREG(FW_BLC_1);
594 static int calc_vclock3(int index, int m, int n, int p)
596 if (p == 0 || n == 0)
598 return plls[index].ref_clk * m / n / p;
601 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
603 struct pll_min_max *pll = &plls[index];
606 m = (5 * (m1 + 2)) + (m2 + 2);
608 vco = pll->ref_clk * m / n;
610 if (index == PLLS_I8xx) {
611 p = ((p1 + 2) * (1 << (p2 + 1)));
613 p = ((p1) * (p2 ? 5 : 10));
619 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
622 int i, m1, m2, n, p1, p2;
623 int index = dinfo->pll_index;
624 DBG_MSG("intelfbhw_print_hw_state\n");
628 /* Read in as much of the HW state as possible. */
629 printk("hw state dump start\n");
630 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
631 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
632 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
633 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
634 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
635 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
636 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
639 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
641 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
643 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
645 printk(" VGA0: clock is %d\n",
646 calc_vclock(index, m1, m2, n, p1, p2, 0));
648 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
649 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
650 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
651 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
654 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
655 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
656 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
658 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
660 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
661 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
662 printk(" FPA0: 0x%08x\n", hw->fpa0);
663 printk(" FPA1: 0x%08x\n", hw->fpa1);
664 printk(" FPB0: 0x%08x\n", hw->fpb0);
665 printk(" FPB1: 0x%08x\n", hw->fpb1);
667 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
668 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
669 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
671 if (IS_I9XX(dinfo)) {
674 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
677 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
683 case 0x1: p1 = 1; break;
684 case 0x2: p1 = 2; break;
685 case 0x4: p1 = 3; break;
686 case 0x8: p1 = 4; break;
687 case 0x10: p1 = 5; break;
688 case 0x20: p1 = 6; break;
689 case 0x40: p1 = 7; break;
690 case 0x80: p1 = 8; break;
694 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
697 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
700 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
701 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
704 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
706 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
708 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
709 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
710 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
712 if (IS_I9XX(dinfo)) {
715 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
718 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
723 case 0x1: p1 = 1; break;
724 case 0x2: p1 = 2; break;
725 case 0x4: p1 = 3; break;
726 case 0x8: p1 = 4; break;
727 case 0x10: p1 = 5; break;
728 case 0x20: p1 = 6; break;
729 case 0x40: p1 = 7; break;
730 case 0x80: p1 = 8; break;
734 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
737 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
740 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
741 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
743 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
745 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
748 printk(" PALETTE_A:\n");
749 for (i = 0; i < PALETTE_8_ENTRIES)
750 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
751 printk(" PALETTE_B:\n");
752 for (i = 0; i < PALETTE_8_ENTRIES)
753 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
756 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
757 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
758 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
759 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
760 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
761 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
762 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
763 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
764 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
765 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
766 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
767 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
768 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
769 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
770 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
771 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
773 printk(" ADPA: 0x%08x\n", hw->adpa);
774 printk(" DVOA: 0x%08x\n", hw->dvoa);
775 printk(" DVOB: 0x%08x\n", hw->dvob);
776 printk(" DVOC: 0x%08x\n", hw->dvoc);
777 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
778 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
779 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
780 printk(" LVDS: 0x%08x\n", hw->lvds);
782 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
783 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
784 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
786 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
787 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
788 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
789 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
791 printk(" CURSOR_A_PALETTE: ");
792 for (i = 0; i < 4; i++) {
793 printk("0x%08x", hw->cursor_a_palette[i]);
798 printk(" CURSOR_B_PALETTE: ");
799 for (i = 0; i < 4; i++) {
800 printk("0x%08x", hw->cursor_b_palette[i]);
806 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
808 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
809 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
810 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
811 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
812 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
813 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
815 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
816 printk(" ADD_ID: 0x%08x\n", hw->add_id);
818 for (i = 0; i < 7; i++) {
819 printk(" SWF0%d 0x%08x\n", i,
822 for (i = 0; i < 7; i++) {
823 printk(" SWF1%d 0x%08x\n", i,
826 for (i = 0; i < 3; i++) {
827 printk(" SWF3%d 0x%08x\n", i,
830 for (i = 0; i < 8; i++)
831 printk(" FENCE%d 0x%08x\n", i,
834 printk(" INSTPM 0x%08x\n", hw->instpm);
835 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
836 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
837 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
839 printk("hw state dump end\n");
845 /* Split the M parameter into M1 and M2. */
847 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
851 struct pll_min_max *pll = &plls[index];
853 /* no point optimising too much - brute force m */
854 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
855 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
856 testm = (5 * (m1 + 2)) + (m2 + 2);
858 *retm1 = (unsigned int)m1;
859 *retm2 = (unsigned int)m2;
867 /* Split the P parameter into P1 and P2. */
869 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
872 struct pll_min_max *pll = &plls[index];
874 if (index == PLLS_I9xx) {
875 p2 = (p % 10) ? 1 : 0;
877 p1 = p / (p2 ? 5 : 10);
879 *retp1 = (unsigned int)p1;
880 *retp2 = (unsigned int)p2;
888 p1 = (p / (1 << (p2 + 1))) - 2;
889 if (p % 4 == 0 && p1 < pll->min_p1) {
891 p1 = (p / (1 << (p2 + 1))) - 2;
893 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
894 (p1 + 2) * (1 << (p2 + 1)) != p) {
897 *retp1 = (unsigned int)p1;
898 *retp2 = (unsigned int)p2;
904 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
905 u32 *retp2, u32 *retclock)
907 u32 m1, m2, n, p1, p2, n1, testm;
908 u32 f_vco, p, p_best = 0, m, f_out = 0;
909 u32 err_max, err_target, err_best = 10000000;
910 u32 n_best = 0, m_best = 0, f_best, f_err;
911 u32 p_min, p_max, p_inc, div_max;
912 struct pll_min_max *pll = &plls[index];
914 /* Accept 0.5% difference, but aim for 0.1% */
915 err_max = 5 * clock / 1000;
916 err_target = clock / 1000;
918 DBG_MSG("Clock is %d\n", clock);
920 div_max = pll->max_vco / clock;
922 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
924 p_max = ROUND_DOWN_TO(div_max, p_inc);
925 if (p_min < pll->min_p)
927 if (p_max > pll->max_p)
930 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
934 if (splitp(index, p, &p1, &p2)) {
935 WRN_MSG("cannot split p = %d\n", p);
943 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
948 for (testm = m - 1; testm <= m; testm++) {
949 f_out = calc_vclock3(index, m, n, p);
950 if (splitm(index, testm, &m1, &m2)) {
951 WRN_MSG("cannot split m = %d\n", m);
956 f_err = clock - f_out;
957 else/* slightly bias the error for bigger clocks */
958 f_err = f_out - clock + 1;
960 if (f_err < err_best) {
969 } while ((n <= pll->max_n) && (f_out >= clock));
971 } while ((p <= p_max));
974 WRN_MSG("cannot find parameters for clock %d\n", clock);
980 splitm(index, m, &m1, &m2);
981 splitp(index, p, &p1, &p2);
984 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
985 "f: %d (%d), VCO: %d\n",
986 m, m1, m2, n, n1, p, p1, p2,
987 calc_vclock3(index, m, n, p),
988 calc_vclock(index, m1, m2, n1, p1, p2, 0),
989 calc_vclock3(index, m, n, p) * p);
995 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1000 static __inline__ int
1001 check_overflow(u32 value, u32 limit, const char *description)
1003 if (value > limit) {
1004 WRN_MSG("%s value %d exceeds limit %d\n",
1005 description, value, limit);
1011 /* It is assumed that hw is filled in with the initial state information. */
1013 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
1014 struct fb_var_screeninfo *var)
1017 u32 *dpll, *fp0, *fp1;
1018 u32 m1, m2, n, p1, p2, clock_target, clock;
1019 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1020 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1021 u32 vsync_pol, hsync_pol;
1022 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1023 u32 stride_alignment;
1025 DBG_MSG("intelfbhw_mode_to_hw\n");
1028 hw->vgacntrl |= VGA_DISABLE;
1030 /* Check whether pipe A or pipe B is enabled. */
1031 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1033 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1036 /* Set which pipe's registers will be set. */
1037 if (pipe == PIPE_B) {
1047 ss = &hw->src_size_b;
1048 pipe_conf = &hw->pipe_b_conf;
1059 ss = &hw->src_size_a;
1060 pipe_conf = &hw->pipe_a_conf;
1063 /* Use ADPA register for sync control. */
1064 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1067 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1068 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1069 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1070 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1071 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1072 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1073 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1074 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1076 /* Connect correct pipe to the analog port DAC */
1077 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1078 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1080 /* Set DPMS state to D0 (on) */
1081 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1082 hw->adpa |= ADPA_DPMS_D0;
1084 hw->adpa |= ADPA_DAC_ENABLE;
1086 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1087 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1088 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1090 /* Desired clock in kHz */
1091 clock_target = 1000000000 / var->pixclock;
1093 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1094 &n, &p1, &p2, &clock)) {
1095 WRN_MSG("calc_pll_params failed\n");
1099 /* Check for overflow. */
1100 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1102 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1104 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1106 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1108 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1111 *dpll &= ~DPLL_P1_FORCE_DIV2;
1112 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1113 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1115 if (IS_I9XX(dinfo)) {
1116 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1117 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1119 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1122 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1123 (m1 << FP_M1_DIVISOR_SHIFT) |
1124 (m2 << FP_M2_DIVISOR_SHIFT);
1127 hw->dvob &= ~PORT_ENABLE;
1128 hw->dvoc &= ~PORT_ENABLE;
1130 /* Use display plane A. */
1131 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1132 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1133 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1134 switch (intelfb_var_to_depth(var)) {
1136 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1139 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1142 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1145 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1148 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1149 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1151 /* Set CRTC registers. */
1152 hactive = var->xres;
1153 hsync_start = hactive + var->right_margin;
1154 hsync_end = hsync_start + var->hsync_len;
1155 htotal = hsync_end + var->left_margin;
1156 hblank_start = hactive;
1157 hblank_end = htotal;
1159 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1160 hactive, hsync_start, hsync_end, htotal, hblank_start,
1163 vactive = var->yres;
1164 vsync_start = vactive + var->lower_margin;
1165 vsync_end = vsync_start + var->vsync_len;
1166 vtotal = vsync_end + var->upper_margin;
1167 vblank_start = vactive;
1168 vblank_end = vtotal;
1169 vblank_end = vsync_end + 1;
1171 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1172 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1175 /* Adjust for register values, and check for overflow. */
1177 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1180 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1183 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1186 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1189 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1192 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1196 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1199 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1202 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1205 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1208 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1211 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1214 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1215 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1216 (hblank_end << HSYNCEND_SHIFT);
1217 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1219 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1220 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1221 (vblank_end << VSYNCEND_SHIFT);
1222 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1223 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1224 (vactive << SRC_SIZE_VERT_SHIFT);
1226 hw->disp_a_stride = dinfo->pitch;
1227 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1229 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1230 var->xoffset * var->bits_per_pixel / 8;
1232 hw->disp_a_base += dinfo->fb.offset << 12;
1234 /* Check stride alignment. */
1235 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1237 if (hw->disp_a_stride % stride_alignment != 0) {
1238 WRN_MSG("display stride %d has bad alignment %d\n",
1239 hw->disp_a_stride, stride_alignment);
1243 /* Set the palette to 8-bit mode. */
1244 *pipe_conf &= ~PIPECONF_GAMMA;
1248 /* Program a (non-VGA) video mode. */
1250 intelfbhw_program_mode(struct intelfb_info *dinfo,
1251 const struct intelfb_hwstate *hw, int blank)
1255 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1256 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1257 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1258 u32 hsync_reg, htotal_reg, hblank_reg;
1259 u32 vsync_reg, vtotal_reg, vblank_reg;
1261 u32 count, tmp_val[3];
1263 /* Assume single pipe, display plane A, analog CRT. */
1266 DBG_MSG("intelfbhw_program_mode\n");
1270 tmp = INREG(VGACNTRL);
1272 OUTREG(VGACNTRL, tmp);
1274 /* Check whether pipe A or pipe B is enabled. */
1275 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1277 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1282 if (pipe == PIPE_B) {
1286 pipe_conf = &hw->pipe_b_conf;
1293 ss = &hw->src_size_b;
1297 pipe_conf_reg = PIPEBCONF;
1298 hsync_reg = HSYNC_B;
1299 htotal_reg = HTOTAL_B;
1300 hblank_reg = HBLANK_B;
1301 vsync_reg = VSYNC_B;
1302 vtotal_reg = VTOTAL_B;
1303 vblank_reg = VBLANK_B;
1304 src_size_reg = SRC_SIZE_B;
1309 pipe_conf = &hw->pipe_a_conf;
1316 ss = &hw->src_size_a;
1320 pipe_conf_reg = PIPEACONF;
1321 hsync_reg = HSYNC_A;
1322 htotal_reg = HTOTAL_A;
1323 hblank_reg = HBLANK_A;
1324 vsync_reg = VSYNC_A;
1325 vtotal_reg = VTOTAL_A;
1326 vblank_reg = VBLANK_A;
1327 src_size_reg = SRC_SIZE_A;
1331 tmp = INREG(pipe_conf_reg);
1332 tmp &= ~PIPECONF_ENABLE;
1333 OUTREG(pipe_conf_reg, tmp);
1337 tmp_val[count%3] = INREG(0x70000);
1338 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1342 if (count % 200 == 0) {
1343 tmp = INREG(pipe_conf_reg);
1344 tmp &= ~PIPECONF_ENABLE;
1345 OUTREG(pipe_conf_reg, tmp);
1347 } while(count < 2000);
1349 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1351 /* Disable planes A and B. */
1352 tmp = INREG(DSPACNTR);
1353 tmp &= ~DISPPLANE_PLANE_ENABLE;
1354 OUTREG(DSPACNTR, tmp);
1355 tmp = INREG(DSPBCNTR);
1356 tmp &= ~DISPPLANE_PLANE_ENABLE;
1357 OUTREG(DSPBCNTR, tmp);
1359 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1362 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1363 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1364 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1368 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1369 tmp |= ADPA_DPMS_D3;
1372 /* do some funky magic - xyzzy */
1373 OUTREG(0x61204, 0xabcd0000);
1376 tmp = INREG(dpll_reg);
1377 dpll_reg &= ~DPLL_VCO_ENABLE;
1378 OUTREG(dpll_reg, tmp);
1380 /* Set PLL parameters */
1381 OUTREG(fp0_reg, *fp0);
1382 OUTREG(fp1_reg, *fp1);
1385 OUTREG(dpll_reg, *dpll);
1388 OUTREG(DVOB, hw->dvob);
1389 OUTREG(DVOC, hw->dvoc);
1391 /* undo funky magic */
1392 OUTREG(0x61204, 0x00000000);
1395 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1396 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1398 /* Set pipe parameters */
1399 OUTREG(hsync_reg, *hs);
1400 OUTREG(hblank_reg, *hb);
1401 OUTREG(htotal_reg, *ht);
1402 OUTREG(vsync_reg, *vs);
1403 OUTREG(vblank_reg, *vb);
1404 OUTREG(vtotal_reg, *vt);
1405 OUTREG(src_size_reg, *ss);
1408 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1412 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1413 tmp |= ADPA_DPMS_D0;
1416 /* setup display plane */
1417 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1419 * i830M errata: the display plane must be enabled
1420 * to allow writes to the other bits in the plane
1423 tmp = INREG(DSPACNTR);
1424 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1425 tmp |= DISPPLANE_PLANE_ENABLE;
1426 OUTREG(DSPACNTR, tmp);
1428 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1433 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1434 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1435 OUTREG(DSPABASE, hw->disp_a_base);
1439 tmp = INREG(DSPACNTR);
1440 tmp |= DISPPLANE_PLANE_ENABLE;
1441 OUTREG(DSPACNTR, tmp);
1442 OUTREG(DSPABASE, hw->disp_a_base);
1448 /* forward declarations */
1449 static void refresh_ring(struct intelfb_info *dinfo);
1450 static void reset_state(struct intelfb_info *dinfo);
1451 static void do_flush(struct intelfb_info *dinfo);
1454 wait_ring(struct intelfb_info *dinfo, int n)
1458 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1461 DBG_MSG("wait_ring: %d\n", n);
1464 end = jiffies + (HZ * 3);
1465 while (dinfo->ring_space < n) {
1466 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1468 if (dinfo->ring_tail + RING_MIN_FREE <
1469 (u32 __iomem) dinfo->ring_head)
1470 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1471 - (dinfo->ring_tail + RING_MIN_FREE);
1473 dinfo->ring_space = (dinfo->ring.size +
1474 (u32 __iomem) dinfo->ring_head)
1475 - (dinfo->ring_tail + RING_MIN_FREE);
1476 if ((u32 __iomem) dinfo->ring_head != last_head) {
1477 end = jiffies + (HZ * 3);
1478 last_head = (u32 __iomem) dinfo->ring_head;
1481 if (time_before(end, jiffies)) {
1485 refresh_ring(dinfo);
1487 end = jiffies + (HZ * 3);
1490 WRN_MSG("ring buffer : space: %d wanted %d\n",
1491 dinfo->ring_space, n);
1492 WRN_MSG("lockup - turning off hardware "
1494 dinfo->ring_lockup = 1;
1504 do_flush(struct intelfb_info *dinfo) {
1506 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1512 intelfbhw_do_sync(struct intelfb_info *dinfo)
1515 DBG_MSG("intelfbhw_do_sync\n");
1522 * Send a flush, then wait until the ring is empty. This is what
1523 * the XFree86 driver does, and actually it doesn't seem a lot worse
1524 * than the recommended method (both have problems).
1527 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1528 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1532 refresh_ring(struct intelfb_info *dinfo)
1535 DBG_MSG("refresh_ring\n");
1538 dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1540 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1541 if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1542 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1543 - (dinfo->ring_tail + RING_MIN_FREE);
1545 dinfo->ring_space = (dinfo->ring.size +
1546 (u32 __iomem) dinfo->ring_head)
1547 - (dinfo->ring_tail + RING_MIN_FREE);
1551 reset_state(struct intelfb_info *dinfo)
1557 DBG_MSG("reset_state\n");
1560 for (i = 0; i < FENCE_NUM; i++)
1561 OUTREG(FENCE + (i << 2), 0);
1563 /* Flush the ring buffer if it's enabled. */
1564 tmp = INREG(PRI_RING_LENGTH);
1565 if (tmp & RING_ENABLE) {
1567 DBG_MSG("reset_state: ring was enabled\n");
1569 refresh_ring(dinfo);
1570 intelfbhw_do_sync(dinfo);
1574 OUTREG(PRI_RING_LENGTH, 0);
1575 OUTREG(PRI_RING_HEAD, 0);
1576 OUTREG(PRI_RING_TAIL, 0);
1577 OUTREG(PRI_RING_START, 0);
1580 /* Stop the 2D engine, and turn off the ring buffer. */
1582 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1585 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1586 dinfo->ring_active);
1592 dinfo->ring_active = 0;
1597 * Enable the ring buffer, and initialise the 2D engine.
1598 * It is assumed that the graphics engine has been stopped by previously
1599 * calling intelfb_2d_stop().
1602 intelfbhw_2d_start(struct intelfb_info *dinfo)
1605 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1606 dinfo->accel, dinfo->ring_active);
1612 /* Initialise the primary ring buffer. */
1613 OUTREG(PRI_RING_LENGTH, 0);
1614 OUTREG(PRI_RING_TAIL, 0);
1615 OUTREG(PRI_RING_HEAD, 0);
1617 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1618 OUTREG(PRI_RING_LENGTH,
1619 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1620 RING_NO_REPORT | RING_ENABLE);
1621 refresh_ring(dinfo);
1622 dinfo->ring_active = 1;
1625 /* 2D fillrect (solid fill or invert) */
1627 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1628 u32 color, u32 pitch, u32 bpp, u32 rop)
1630 u32 br00, br09, br13, br14, br16;
1633 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1634 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1637 br00 = COLOR_BLT_CMD;
1638 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1639 br13 = (rop << ROP_SHIFT) | pitch;
1640 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1645 br13 |= COLOR_DEPTH_8;
1648 br13 |= COLOR_DEPTH_16;
1651 br13 |= COLOR_DEPTH_32;
1652 br00 |= WRITE_ALPHA | WRITE_RGB;
1666 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1667 dinfo->ring_tail, dinfo->ring_space);
1672 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1673 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1675 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1678 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1679 curx, cury, dstx, dsty, w, h, pitch, bpp);
1682 br00 = XY_SRC_COPY_BLT_CMD;
1683 br09 = dinfo->fb_start;
1684 br11 = (pitch << PITCH_SHIFT);
1685 br12 = dinfo->fb_start;
1686 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1687 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1688 br23 = ((dstx + w) << WIDTH_SHIFT) |
1689 ((dsty + h) << HEIGHT_SHIFT);
1690 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1694 br13 |= COLOR_DEPTH_8;
1697 br13 |= COLOR_DEPTH_16;
1700 br13 |= COLOR_DEPTH_32;
1701 br00 |= WRITE_ALPHA | WRITE_RGB;
1718 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1719 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1721 int nbytes, ndwords, pad, tmp;
1722 u32 br00, br09, br13, br18, br19, br22, br23;
1723 int dat, ix, iy, iw;
1727 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1730 /* size in bytes of a padded scanline */
1731 nbytes = ROUND_UP_TO(w, 16) / 8;
1733 /* Total bytes of padded scanline data to write out. */
1734 nbytes = nbytes * h;
1737 * Check if the glyph data exceeds the immediate mode limit.
1738 * It would take a large font (1K pixels) to hit this limit.
1740 if (nbytes > MAX_MONO_IMM_SIZE)
1743 /* Src data is packaged a dword (32-bit) at a time. */
1744 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1747 * Ring has to be padded to a quad word. But because the command starts
1748 with 7 bytes, pad only if there is an even number of ndwords
1750 pad = !(ndwords % 2);
1752 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1753 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1754 br09 = dinfo->fb_start;
1755 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1758 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1759 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1763 br13 |= COLOR_DEPTH_8;
1766 br13 |= COLOR_DEPTH_16;
1769 br13 |= COLOR_DEPTH_32;
1770 br00 |= WRITE_ALPHA | WRITE_RGB;
1774 START_RING(8 + ndwords);
1783 iw = ROUND_UP_TO(w, 8) / 8;
1786 for (j = 0; j < 2; ++j) {
1787 for (i = 0; i < 2; ++i) {
1788 if (ix != iw || i == 0)
1789 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1791 if (ix == iw && iy != (h-1)) {
1805 /* HW cursor functions. */
1807 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1812 DBG_MSG("intelfbhw_cursor_init\n");
1815 if (dinfo->mobile || IS_I9XX(dinfo)) {
1816 if (!dinfo->cursor.physical)
1818 tmp = INREG(CURSOR_A_CONTROL);
1819 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1820 CURSOR_MEM_TYPE_LOCAL |
1821 (1 << CURSOR_PIPE_SELECT_SHIFT));
1822 tmp |= CURSOR_MODE_DISABLE;
1823 OUTREG(CURSOR_A_CONTROL, tmp);
1824 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1826 tmp = INREG(CURSOR_CONTROL);
1827 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1828 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1829 tmp = CURSOR_FORMAT_3C;
1830 OUTREG(CURSOR_CONTROL, tmp);
1831 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1832 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1833 (64 << CURSOR_SIZE_V_SHIFT);
1834 OUTREG(CURSOR_SIZE, tmp);
1839 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1844 DBG_MSG("intelfbhw_cursor_hide\n");
1847 dinfo->cursor_on = 0;
1848 if (dinfo->mobile || IS_I9XX(dinfo)) {
1849 if (!dinfo->cursor.physical)
1851 tmp = INREG(CURSOR_A_CONTROL);
1852 tmp &= ~CURSOR_MODE_MASK;
1853 tmp |= CURSOR_MODE_DISABLE;
1854 OUTREG(CURSOR_A_CONTROL, tmp);
1856 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1858 tmp = INREG(CURSOR_CONTROL);
1859 tmp &= ~CURSOR_ENABLE;
1860 OUTREG(CURSOR_CONTROL, tmp);
1865 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1870 DBG_MSG("intelfbhw_cursor_show\n");
1873 dinfo->cursor_on = 1;
1875 if (dinfo->cursor_blanked)
1878 if (dinfo->mobile || IS_I9XX(dinfo)) {
1879 if (!dinfo->cursor.physical)
1881 tmp = INREG(CURSOR_A_CONTROL);
1882 tmp &= ~CURSOR_MODE_MASK;
1883 tmp |= CURSOR_MODE_64_4C_AX;
1884 OUTREG(CURSOR_A_CONTROL, tmp);
1886 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1888 tmp = INREG(CURSOR_CONTROL);
1889 tmp |= CURSOR_ENABLE;
1890 OUTREG(CURSOR_CONTROL, tmp);
1895 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1900 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1904 * Sets the position. The coordinates are assumed to already
1905 * have any offset adjusted. Assume that the cursor is never
1906 * completely off-screen, and that x, y are always >= 0.
1909 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1910 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1911 OUTREG(CURSOR_A_POSITION, tmp);
1913 if (IS_I9XX(dinfo)) {
1914 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1919 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1922 DBG_MSG("intelfbhw_cursor_setcolor\n");
1925 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1926 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1927 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1928 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1932 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1935 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1936 int i, j, w = width / 8;
1937 int mod = width % 8, t_mask, d_mask;
1940 DBG_MSG("intelfbhw_cursor_load\n");
1943 if (!dinfo->cursor.virtual)
1946 t_mask = 0xff >> mod;
1947 d_mask = ~(0xff >> mod);
1948 for (i = height; i--; ) {
1949 for (j = 0; j < w; j++) {
1950 writeb(0x00, addr + j);
1951 writeb(*(data++), addr + j+8);
1954 writeb(t_mask, addr + j);
1955 writeb(*(data++) & d_mask, addr + j+8);
1962 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1963 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1967 DBG_MSG("intelfbhw_cursor_reset\n");
1970 if (!dinfo->cursor.virtual)
1973 for (i = 64; i--; ) {
1974 for (j = 0; j < 8; j++) {
1975 writeb(0xff, addr + j+0);
1976 writeb(0x00, addr + j+8);