drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m, min_m1, max_m1;
  45         int min_m2, max_m2, min_n, max_n;
  46         int min_p, max_p, min_p1, max_p1;
  47         int min_vco, max_vco, p_transition_clk, ref_clk;
  48         int p_inc_lo, p_inc_hi;
  49 };
  50
  51 #define PLLS_I8xx 0
  52 #define PLLS_I9xx 1
  53 #define PLLS_MAX 2
  54
  55 static struct pll_min_max plls[PLLS_MAX] = {
  56         { 108, 140, 18, 26,
  57           6, 16, 3, 16,
  58           4, 128, 0, 31,
  59           930000, 1400000, 165000, 48000,
  60           4, 2 }, //I8xx
  61
  62         { 75, 120, 10, 20,
  63           5, 9, 4, 7,
  64           5, 80, 1, 8,
  65           1400000, 2800000, 200000, 96000,
  66           10, 5 }  //I9xx
  67 };
  68
  69 int
  70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  71 {
  72         u32 tmp;
  73         if (!pdev || !dinfo)
  74                 return 1;
  75
  76         switch (pdev->device) {
  77         case PCI_DEVICE_ID_INTEL_830M:
  78                 dinfo->name = "Intel(R) 830M";
  79                 dinfo->chipset = INTEL_830M;
  80                 dinfo->mobile = 1;
  81                 dinfo->pll_index = PLLS_I8xx;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_845G:
  84                 dinfo->name = "Intel(R) 845G";
  85                 dinfo->chipset = INTEL_845G;
  86                 dinfo->mobile = 0;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 return 0;
  89         case PCI_DEVICE_ID_INTEL_85XGM:
  90                 tmp = 0;
  91                 dinfo->mobile = 1;
  92                 dinfo->pll_index = PLLS_I8xx;
  93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  95                         INTEL_85X_VARIANT_MASK) {
  96                 case INTEL_VAR_855GME:
  97                         dinfo->name = "Intel(R) 855GME";
  98                         dinfo->chipset = INTEL_855GME;
  99                         return 0;
 100                 case INTEL_VAR_855GM:
 101                         dinfo->name = "Intel(R) 855GM";
 102                         dinfo->chipset = INTEL_855GM;
 103                         return 0;
 104                 case INTEL_VAR_852GME:
 105                         dinfo->name = "Intel(R) 852GME";
 106                         dinfo->chipset = INTEL_852GME;
 107                         return 0;
 108                 case INTEL_VAR_852GM:
 109                         dinfo->name = "Intel(R) 852GM";
 110                         dinfo->chipset = INTEL_852GM;
 111                         return 0;
 112                 default:
 113                         dinfo->name = "Intel(R) 852GM/855GM";
 114                         dinfo->chipset = INTEL_85XGM;
 115                         return 0;
 116                 }
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_865G:
 119                 dinfo->name = "Intel(R) 865G";
 120                 dinfo->chipset = INTEL_865G;
 121                 dinfo->mobile = 0;
 122                 dinfo->pll_index = PLLS_I8xx;
 123                 return 0;
 124         case PCI_DEVICE_ID_INTEL_915G:
 125                 dinfo->name = "Intel(R) 915G";
 126                 dinfo->chipset = INTEL_915G;
 127                 dinfo->mobile = 0;
 128                 dinfo->pll_index = PLLS_I9xx;
 129                 return 0;
 130         case PCI_DEVICE_ID_INTEL_915GM:
 131                 dinfo->name = "Intel(R) 915GM";
 132                 dinfo->chipset = INTEL_915GM;
 133                 dinfo->mobile = 1;
 134                 dinfo->pll_index = PLLS_I9xx;
 135                 return 0;
 136         case PCI_DEVICE_ID_INTEL_945G:
 137                 dinfo->name = "Intel(R) 945G";
 138                 dinfo->chipset = INTEL_945G;
 139                 dinfo->mobile = 0;
 140                 dinfo->pll_index = PLLS_I9xx;
 141                 return 0;
 142         case PCI_DEVICE_ID_INTEL_945GM:
 143                 dinfo->name = "Intel(R) 945GM";
 144                 dinfo->chipset = INTEL_945GM;
 145                 dinfo->mobile = 1;
 146                 dinfo->pll_index = PLLS_I9xx;
 147                 return 0;
 148         default:
 149                 return 1;
 150         }
 151 }
 152
 153 int
 154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 155                      int *stolen_size)
 156 {
 157         struct pci_dev *bridge_dev;
 158         u16 tmp;
 159
 160         if (!pdev || !aperture_size || !stolen_size)
 161                 return 1;
 162
 163         /* Find the bridge device.  It is always 0:0.0 */
 164         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 165                 ERR_MSG("cannot find bridge device\n");
 166                 return 1;
 167         }
 168
 169         /* Get the fb aperture size and "stolen" memory amount. */
 170         tmp = 0;
 171         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 172         switch (pdev->device) {
 173         case PCI_DEVICE_ID_INTEL_830M:
 174         case PCI_DEVICE_ID_INTEL_845G:
 175                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 176                         *aperture_size = MB(64);
 177                 else
 178                         *aperture_size = MB(128);
 179                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 180                 case INTEL_830_GMCH_GMS_STOLEN_512:
 181                         *stolen_size = KB(512) - KB(132);
 182                         return 0;
 183                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 184                         *stolen_size = MB(1) - KB(132);
 185                         return 0;
 186                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 187                         *stolen_size = MB(8) - KB(132);
 188                         return 0;
 189                 case INTEL_830_GMCH_GMS_LOCAL:
 190                         ERR_MSG("only local memory found\n");
 191                         return 1;
 192                 case INTEL_830_GMCH_GMS_DISABLED:
 193                         ERR_MSG("video memory is disabled\n");
 194                         return 1;
 195                 default:
 196                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 197                                 tmp & INTEL_830_GMCH_GMS_MASK);
 198                         return 1;
 199                 }
 200                 break;
 201         default:
 202                 *aperture_size = MB(128);
 203                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 204                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 205                         *stolen_size = MB(1) - KB(132);
 206                         return 0;
 207                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 208                         *stolen_size = MB(4) - KB(132);
 209                         return 0;
 210                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 211                         *stolen_size = MB(8) - KB(132);
 212                         return 0;
 213                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 214                         *stolen_size = MB(16) - KB(132);
 215                         return 0;
 216                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 217                         *stolen_size = MB(32) - KB(132);
 218                         return 0;
 219                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 220                         *stolen_size = MB(48) - KB(132);
 221                         return 0;
 222                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 223                         *stolen_size = MB(64) - KB(132);
 224                         return 0;
 225                 case INTEL_855_GMCH_GMS_DISABLED:
 226                         ERR_MSG("video memory is disabled\n");
 227                         return 0;
 228                 default:
 229                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 230                                 tmp & INTEL_855_GMCH_GMS_MASK);
 231                         return 1;
 232                 }
 233         }
 234 }
 235
 236 int
 237 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 238 {
 239         int dvo = 0;
 240
 241         if (INREG(LVDS) & PORT_ENABLE)
 242                 dvo |= LVDS_PORT;
 243         if (INREG(DVOA) & PORT_ENABLE)
 244                 dvo |= DVOA_PORT;
 245         if (INREG(DVOB) & PORT_ENABLE)
 246                 dvo |= DVOB_PORT;
 247         if (INREG(DVOC) & PORT_ENABLE)
 248                 dvo |= DVOC_PORT;
 249
 250         return dvo;
 251 }
 252
 253 const char *
 254 intelfbhw_dvo_to_string(int dvo)
 255 {
 256         if (dvo & DVOA_PORT)
 257                 return "DVO port A";
 258         else if (dvo & DVOB_PORT)
 259                 return "DVO port B";
 260         else if (dvo & DVOC_PORT)
 261                 return "DVO port C";
 262         else if (dvo & LVDS_PORT)
 263                 return "LVDS port";
 264         else
 265                 return NULL;
 266 }
 267
 268
 269 int
 270 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 271                         struct fb_var_screeninfo *var)
 272 {
 273         int bytes_per_pixel;
 274         int tmp;
 275
 276 #if VERBOSE > 0
 277         DBG_MSG("intelfbhw_validate_mode\n");
 278 #endif
 279
 280         bytes_per_pixel = var->bits_per_pixel / 8;
 281         if (bytes_per_pixel == 3)
 282                 bytes_per_pixel = 4;
 283
 284         /* Check if enough video memory. */
 285         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 286         if (tmp > dinfo->fb.size) {
 287                 WRN_MSG("Not enough video ram for mode "
 288                         "(%d KByte vs %d KByte).\n",
 289                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 290                 return 1;
 291         }
 292
 293         /* Check if x/y limits are OK. */
 294         if (var->xres - 1 > HACTIVE_MASK) {
 295                 WRN_MSG("X resolution too large (%d vs %d).\n",
 296                         var->xres, HACTIVE_MASK + 1);
 297                 return 1;
 298         }
 299         if (var->yres - 1 > VACTIVE_MASK) {
 300                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 301                         var->yres, VACTIVE_MASK + 1);
 302                 return 1;
 303         }
 304
 305         /* Check for interlaced/doublescan modes. */
 306         if (var->vmode & FB_VMODE_INTERLACED) {
 307                 WRN_MSG("Mode is interlaced.\n");
 308                 return 1;
 309         }
 310         if (var->vmode & FB_VMODE_DOUBLE) {
 311                 WRN_MSG("Mode is double-scan.\n");
 312                 return 1;
 313         }
 314
 315         /* Check if clock is OK. */
 316         tmp = 1000000000 / var->pixclock;
 317         if (tmp < MIN_CLOCK) {
 318                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 319                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 320                 return 1;
 321         }
 322         if (tmp > MAX_CLOCK) {
 323                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 324                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 325                 return 1;
 326         }
 327
 328         return 0;
 329 }
 330
 331 int
 332 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 333 {
 334         struct intelfb_info *dinfo = GET_DINFO(info);
 335         u32 offset, xoffset, yoffset;
 336
 337 #if VERBOSE > 0
 338         DBG_MSG("intelfbhw_pan_display\n");
 339 #endif
 340
 341         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 342         yoffset = var->yoffset;
 343
 344         if ((xoffset + var->xres > var->xres_virtual) ||
 345             (yoffset + var->yres > var->yres_virtual))
 346                 return -EINVAL;
 347
 348         offset = (yoffset * dinfo->pitch) +
 349                  (xoffset * var->bits_per_pixel) / 8;
 350
 351         offset += dinfo->fb.offset << 12;
 352
 353         OUTREG(DSPABASE, offset);
 354
 355         return 0;
 356 }
 357
 358 /* Blank the screen. */
 359 void
 360 intelfbhw_do_blank(int blank, struct fb_info *info)
 361 {
 362         struct intelfb_info *dinfo = GET_DINFO(info);
 363         u32 tmp;
 364
 365 #if VERBOSE > 0
 366         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 367 #endif
 368
 369         /* Turn plane A on or off */
 370         tmp = INREG(DSPACNTR);
 371         if (blank)
 372                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 373         else
 374                 tmp |= DISPPLANE_PLANE_ENABLE;
 375         OUTREG(DSPACNTR, tmp);
 376         /* Flush */
 377         tmp = INREG(DSPABASE);
 378         OUTREG(DSPABASE, tmp);
 379
 380         /* Turn off/on the HW cursor */
 381 #if VERBOSE > 0
 382         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 383 #endif
 384         if (dinfo->cursor_on) {
 385                 if (blank) {
 386                         intelfbhw_cursor_hide(dinfo);
 387                 } else {
 388                         intelfbhw_cursor_show(dinfo);
 389                 }
 390                 dinfo->cursor_on = 1;
 391         }
 392         dinfo->cursor_blanked = blank;
 393
 394         /* Set DPMS level */
 395         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 396         switch (blank) {
 397         case FB_BLANK_UNBLANK:
 398         case FB_BLANK_NORMAL:
 399                 tmp |= ADPA_DPMS_D0;
 400                 break;
 401         case FB_BLANK_VSYNC_SUSPEND:
 402                 tmp |= ADPA_DPMS_D1;
 403                 break;
 404         case FB_BLANK_HSYNC_SUSPEND:
 405                 tmp |= ADPA_DPMS_D2;
 406                 break;
 407         case FB_BLANK_POWERDOWN:
 408                 tmp |= ADPA_DPMS_D3;
 409                 break;
 410         }
 411         OUTREG(ADPA, tmp);
 412
 413         return;
 414 }
 415
 416
 417 void
 418 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 419                     unsigned red, unsigned green, unsigned blue,
 420                     unsigned transp)
 421 {
 422 #if VERBOSE > 0
 423         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 424                 regno, red, green, blue);
 425 #endif
 426
 427         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 428                           PALETTE_A : PALETTE_B;
 429
 430         OUTREG(palette_reg + (regno << 2),
 431                (red << PALETTE_8_RED_SHIFT) |
 432                (green << PALETTE_8_GREEN_SHIFT) |
 433                (blue << PALETTE_8_BLUE_SHIFT));
 434 }
 435
 436
 437 int
 438 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 439                         int flag)
 440 {
 441         int i;
 442
 443 #if VERBOSE > 0
 444         DBG_MSG("intelfbhw_read_hw_state\n");
 445 #endif
 446
 447         if (!hw || !dinfo)
 448                 return -1;
 449
 450         /* Read in as much of the HW state as possible. */
 451         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 452         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 453         hw->vga_pd = INREG(VGAPD);
 454         hw->dpll_a = INREG(DPLL_A);
 455         hw->dpll_b = INREG(DPLL_B);
 456         hw->fpa0 = INREG(FPA0);
 457         hw->fpa1 = INREG(FPA1);
 458         hw->fpb0 = INREG(FPB0);
 459         hw->fpb1 = INREG(FPB1);
 460
 461         if (flag == 1)
 462                 return flag;
 463
 464 #if 0
 465         /* This seems to be a problem with the 852GM/855GM */
 466         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 467                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 468                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 469         }
 470 #endif
 471
 472         if (flag == 2)
 473                 return flag;
 474
 475         hw->htotal_a = INREG(HTOTAL_A);
 476         hw->hblank_a = INREG(HBLANK_A);
 477         hw->hsync_a = INREG(HSYNC_A);
 478         hw->vtotal_a = INREG(VTOTAL_A);
 479         hw->vblank_a = INREG(VBLANK_A);
 480         hw->vsync_a = INREG(VSYNC_A);
 481         hw->src_size_a = INREG(SRC_SIZE_A);
 482         hw->bclrpat_a = INREG(BCLRPAT_A);
 483         hw->htotal_b = INREG(HTOTAL_B);
 484         hw->hblank_b = INREG(HBLANK_B);
 485         hw->hsync_b = INREG(HSYNC_B);
 486         hw->vtotal_b = INREG(VTOTAL_B);
 487         hw->vblank_b = INREG(VBLANK_B);
 488         hw->vsync_b = INREG(VSYNC_B);
 489         hw->src_size_b = INREG(SRC_SIZE_B);
 490         hw->bclrpat_b = INREG(BCLRPAT_B);
 491
 492         if (flag == 3)
 493                 return flag;
 494
 495         hw->adpa = INREG(ADPA);
 496         hw->dvoa = INREG(DVOA);
 497         hw->dvob = INREG(DVOB);
 498         hw->dvoc = INREG(DVOC);
 499         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 500         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 501         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 502         hw->lvds = INREG(LVDS);
 503
 504         if (flag == 4)
 505                 return flag;
 506
 507         hw->pipe_a_conf = INREG(PIPEACONF);
 508         hw->pipe_b_conf = INREG(PIPEBCONF);
 509         hw->disp_arb = INREG(DISPARB);
 510
 511         if (flag == 5)
 512                 return flag;
 513
 514         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 515         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 516         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 517         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 518
 519         if (flag == 6)
 520                 return flag;
 521
 522         for (i = 0; i < 4; i++) {
 523                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 524                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 525         }
 526
 527         if (flag == 7)
 528                 return flag;
 529
 530         hw->cursor_size = INREG(CURSOR_SIZE);
 531
 532         if (flag == 8)
 533                 return flag;
 534
 535         hw->disp_a_ctrl = INREG(DSPACNTR);
 536         hw->disp_b_ctrl = INREG(DSPBCNTR);
 537         hw->disp_a_base = INREG(DSPABASE);
 538         hw->disp_b_base = INREG(DSPBBASE);
 539         hw->disp_a_stride = INREG(DSPASTRIDE);
 540         hw->disp_b_stride = INREG(DSPBSTRIDE);
 541
 542         if (flag == 9)
 543                 return flag;
 544
 545         hw->vgacntrl = INREG(VGACNTRL);
 546
 547         if (flag == 10)
 548                 return flag;
 549
 550         hw->add_id = INREG(ADD_ID);
 551
 552         if (flag == 11)
 553                 return flag;
 554
 555         for (i = 0; i < 7; i++) {
 556                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 557                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 558                 if (i < 3)
 559                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 560         }
 561
 562         for (i = 0; i < 8; i++)
 563                 hw->fence[i] = INREG(FENCE + (i << 2));
 564
 565         hw->instpm = INREG(INSTPM);
 566         hw->mem_mode = INREG(MEM_MODE);
 567         hw->fw_blc_0 = INREG(FW_BLC_0);
 568         hw->fw_blc_1 = INREG(FW_BLC_1);
 569
 570         return 0;
 571 }
 572
 573
 574 static int calc_vclock3(int index, int m, int n, int p)
 575 {
 576         if (p == 0 || n == 0)
 577                 return 0;
 578         return plls[index].ref_clk * m / n / p;
 579 }
 580
 581 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 582 {
 583         int p2_val;
 584         switch(index)
 585         {
 586         case PLLS_I9xx:
 587                 if (p1 == 0)
 588                         return 0;
 589                 if (lvds)
 590                         p2_val = p2 ? 7 : 14;
 591                 else
 592                         p2_val = p2 ? 5 : 10;
 593                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 594                          ((p1)) * (p2_val)));
 595         case PLLS_I8xx:
 596         default:
 597                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 598                          ((p1+2) * (1 << (p2 + 1)))));
 599         }
 600 }
 601
 602 void
 603 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 604 {
 605 #if REGDUMP
 606         int i, m1, m2, n, p1, p2;
 607         int index = dinfo->pll_index;
 608         DBG_MSG("intelfbhw_print_hw_state\n");
 609
 610         if (!hw || !dinfo)
 611                 return;
 612         /* Read in as much of the HW state as possible. */
 613         printk("hw state dump start\n");
 614         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 615         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 616         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 617         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 618         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 619         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 620         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 621                 p1 = 0;
 622         else
 623                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 624
 625         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 626
 627         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 628                m1, m2, n, p1, p2);
 629         printk("        VGA0: clock is %d\n",
 630                calc_vclock(index, m1, m2, n, p1, p2, 0));
 631
 632         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 633         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 634         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 635         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 636                 p1 = 0;
 637         else
 638                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 639         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 640         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 641                m1, m2, n, p1, p2);
 642         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 643
 644         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 645         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 646         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 647         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 648         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 649         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 650
 651         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 652         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 653         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 654
 655         if (IS_I9XX(dinfo)) {
 656                 int tmpp1;
 657
 658                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 659                         p1 = 0;
 660                 else
 661                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 662
 663                 tmpp1 = p1;
 664
 665                 switch (tmpp1)
 666                 {
 667                 case 0x1: p1 = 1; break;
 668                 case 0x2: p1 = 2; break;
 669                 case 0x4: p1 = 3; break;
 670                 case 0x8: p1 = 4; break;
 671                 case 0x10: p1 = 5; break;
 672                 case 0x20: p1 = 6; break;
 673                 case 0x40: p1 = 7; break;
 674                 case 0x80: p1 = 8; break;
 675                 default: break;
 676                 }
 677
 678                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 679
 680         } else {
 681                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 682                         p1 = 0;
 683                 else
 684                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 685                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 686         }
 687
 688         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 689                m1, m2, n, p1, p2);
 690         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 691
 692         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 693         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 694         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 695
 696         if (IS_I9XX(dinfo)) {
 697                 int tmpp1;
 698
 699                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 700                         p1 = 0;
 701                 else
 702                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 703
 704                 tmpp1 = p1;
 705
 706                 switch (tmpp1) {
 707                 case 0x1: p1 = 1; break;
 708                 case 0x2: p1 = 2; break;
 709                 case 0x4: p1 = 3; break;
 710                 case 0x8: p1 = 4; break;
 711                 case 0x10: p1 = 5; break;
 712                 case 0x20: p1 = 6; break;
 713                 case 0x40: p1 = 7; break;
 714                 case 0x80: p1 = 8; break;
 715                 default: break;
 716                 }
 717
 718                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 719
 720         } else {
 721                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 722                         p1 = 0;
 723                 else
 724                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 725                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 726         }
 727         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 728                m1, m2, n, p1, p2);
 729         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 730
 731 #if 0
 732         printk("        PALETTE_A:\n");
 733         for (i = 0; i < PALETTE_8_ENTRIES)
 734                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 735         printk("        PALETTE_B:\n");
 736         for (i = 0; i < PALETTE_8_ENTRIES)
 737                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 738 #endif
 739
 740         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 741         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 742         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 743         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 744         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 745         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 746         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 747         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 748         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 749         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 750         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 751         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 752         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 753         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 754         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 755         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 756
 757         printk("        ADPA:                   0x%08x\n", hw->adpa);
 758         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 759         printk("        DVOB:                   0x%08x\n", hw->dvob);
 760         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 761         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 762         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 763         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 764         printk("        LVDS:                   0x%08x\n", hw->lvds);
 765
 766         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 767         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 768         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 769
 770         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 771         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 772         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 773         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 774
 775         printk("        CURSOR_A_PALETTE:       ");
 776         for (i = 0; i < 4; i++) {
 777                 printk("0x%08x", hw->cursor_a_palette[i]);
 778                 if (i < 3)
 779                         printk(", ");
 780         }
 781         printk("\n");
 782         printk("        CURSOR_B_PALETTE:       ");
 783         for (i = 0; i < 4; i++) {
 784                 printk("0x%08x", hw->cursor_b_palette[i]);
 785                 if (i < 3)
 786                         printk(", ");
 787         }
 788         printk("\n");
 789
 790         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 791
 792         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 793         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 794         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 795         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 796         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 797         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 798
 799         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 800         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 801
 802         for (i = 0; i < 7; i++) {
 803                 printk("        SWF0%d                  0x%08x\n", i,
 804                         hw->swf0x[i]);
 805         }
 806         for (i = 0; i < 7; i++) {
 807                 printk("        SWF1%d                  0x%08x\n", i,
 808                         hw->swf1x[i]);
 809         }
 810         for (i = 0; i < 3; i++) {
 811                 printk("        SWF3%d                  0x%08x\n", i,
 812                        hw->swf3x[i]);
 813         }
 814         for (i = 0; i < 8; i++)
 815                 printk("        FENCE%d                 0x%08x\n", i,
 816                        hw->fence[i]);
 817
 818         printk("        INSTPM                  0x%08x\n", hw->instpm);
 819         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 820         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 821         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 822
 823         printk("hw state dump end\n");
 824 #endif
 825 }
 826
 827
 828
 829 /* Split the M parameter into M1 and M2. */
 830 static int
 831 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 832 {
 833         int m1, m2;
 834         int testm;
 835         /* no point optimising too much - brute force m */
 836         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 837                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 838                         testm = (5 * (m1 + 2)) + (m2 + 2);
 839                         if (testm == m) {
 840                                 *retm1 = (unsigned int)m1;
 841                                 *retm2 = (unsigned int)m2;
 842                                 return 0;
 843                         }
 844                 }
 845         }
 846         return 1;
 847 }
 848
 849 /* Split the P parameter into P1 and P2. */
 850 static int
 851 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 852 {
 853         int p1, p2;
 854
 855         if (index == PLLS_I9xx) {
 856                 p2 = (p % 10) ? 1 : 0;
 857
 858                 p1 = p / (p2 ? 5 : 10);
 859
 860                 *retp1 = (unsigned int)p1;
 861                 *retp2 = (unsigned int)p2;
 862                 return 0;
 863         }
 864
 865         if (index == PLLS_I8xx) {
 866                 if (p % 4 == 0)
 867                         p2 = 1;
 868                 else
 869                         p2 = 0;
 870                 p1 = (p / (1 << (p2 + 1))) - 2;
 871                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 872                         p2 = 0;
 873                         p1 = (p / (1 << (p2 + 1))) - 2;
 874                 }
 875                 if (p1 < plls[index].min_p1 ||
 876                     p1 > plls[index].max_p1 ||
 877                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 878                         return 1;
 879                 } else {
 880                         *retp1 = (unsigned int)p1;
 881                         *retp2 = (unsigned int)p2;
 882                         return 0;
 883                 }
 884         }
 885         return 1;
 886 }
 887
 888 static int
 889 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 890                 u32 *retp2, u32 *retclock)
 891 {
 892         u32 m1, m2, n, p1, p2, n1, testm;
 893         u32 f_vco, p, p_best = 0, m, f_out = 0;
 894         u32 err_max, err_target, err_best = 10000000;
 895         u32 n_best = 0, m_best = 0, f_best, f_err;
 896         u32 p_min, p_max, p_inc, div_max;
 897         struct pll_min_max *pll = &plls[index];
 898
 899         /* Accept 0.5% difference, but aim for 0.1% */
 900         err_max = 5 * clock / 1000;
 901         err_target = clock / 1000;
 902
 903         DBG_MSG("Clock is %d\n", clock);
 904
 905         div_max = pll->max_vco / clock;
 906
 907         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 908         p_min = p_inc;
 909         p_max = ROUND_DOWN_TO(div_max, p_inc);
 910         if (p_min < pll->min_p)
 911                 p_min = pll->min_p;
 912         if (p_max > pll->max_p)
 913                 p_max = pll->max_p;
 914
 915         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 916
 917         p = p_min;
 918         do {
 919                 if (splitp(index, p, &p1, &p2)) {
 920                         WRN_MSG("cannot split p = %d\n", p);
 921                         p += p_inc;
 922                         continue;
 923                 }
 924                 n = pll->min_n;
 925                 f_vco = clock * p;
 926
 927                 do {
 928                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 929                         if (m < pll->min_m)
 930                                 m = pll->min_m + 1;
 931                         if (m > pll->max_m)
 932                                 m = pll->max_m - 1;
 933                         for (testm = m - 1; testm <= m; testm++) {
 934                                 f_out = calc_vclock3(index, m, n, p);
 935                                 if (splitm(index, m, &m1, &m2)) {
 936                                         WRN_MSG("cannot split m = %d\n", m);
 937                                         n++;
 938                                         continue;
 939                                 }
 940                                 if (clock > f_out)
 941                                         f_err = clock - f_out;
 942                                 else/* slightly bias the error for bigger clocks */
 943                                         f_err = f_out - clock + 1;
 944
 945                                 if (f_err < err_best) {
 946                                         m_best = m;
 947                                         n_best = n;
 948                                         p_best = p;
 949                                         f_best = f_out;
 950                                         err_best = f_err;
 951                                 }
 952                         }
 953                         n++;
 954                 } while ((n <= pll->max_n) && (f_out >= clock));
 955                 p += p_inc;
 956         } while ((p <= p_max));
 957
 958         if (!m_best) {
 959                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 960                 return 1;
 961         }
 962         m = m_best;
 963         n = n_best;
 964         p = p_best;
 965         splitm(index, m, &m1, &m2);
 966         splitp(index, p, &p1, &p2);
 967         n1 = n - 2;
 968
 969         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 970                 "f: %d (%d), VCO: %d\n",
 971                 m, m1, m2, n, n1, p, p1, p2,
 972                 calc_vclock3(index, m, n, p),
 973                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 974                 calc_vclock3(index, m, n, p) * p);
 975         *retm1 = m1;
 976         *retm2 = m2;
 977         *retn = n1;
 978         *retp1 = p1;
 979         *retp2 = p2;
 980         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 981
 982         return 0;
 983 }
 984
 985 static __inline__ int
 986 check_overflow(u32 value, u32 limit, const char *description)
 987 {
 988         if (value > limit) {
 989                 WRN_MSG("%s value %d exceeds limit %d\n",
 990                         description, value, limit);
 991                 return 1;
 992         }
 993         return 0;
 994 }
 995
 996 /* It is assumed that hw is filled in with the initial state information. */
 997 int
 998 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 999                      struct fb_var_screeninfo *var)
1000 {
1001         int pipe = PIPE_A;
1002         u32 *dpll, *fp0, *fp1;
1003         u32 m1, m2, n, p1, p2, clock_target, clock;
1004         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1005         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1006         u32 vsync_pol, hsync_pol;
1007         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1008         u32 stride_alignment;
1009
1010         DBG_MSG("intelfbhw_mode_to_hw\n");
1011
1012         /* Disable VGA */
1013         hw->vgacntrl |= VGA_DISABLE;
1014
1015         /* Check whether pipe A or pipe B is enabled. */
1016         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1017                 pipe = PIPE_A;
1018         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1019                 pipe = PIPE_B;
1020
1021         /* Set which pipe's registers will be set. */
1022         if (pipe == PIPE_B) {
1023                 dpll = &hw->dpll_b;
1024                 fp0 = &hw->fpb0;
1025                 fp1 = &hw->fpb1;
1026                 hs = &hw->hsync_b;
1027                 hb = &hw->hblank_b;
1028                 ht = &hw->htotal_b;
1029                 vs = &hw->vsync_b;
1030                 vb = &hw->vblank_b;
1031                 vt = &hw->vtotal_b;
1032                 ss = &hw->src_size_b;
1033                 pipe_conf = &hw->pipe_b_conf;
1034         } else {
1035                 dpll = &hw->dpll_a;
1036                 fp0 = &hw->fpa0;
1037                 fp1 = &hw->fpa1;
1038                 hs = &hw->hsync_a;
1039                 hb = &hw->hblank_a;
1040                 ht = &hw->htotal_a;
1041                 vs = &hw->vsync_a;
1042                 vb = &hw->vblank_a;
1043                 vt = &hw->vtotal_a;
1044                 ss = &hw->src_size_a;
1045                 pipe_conf = &hw->pipe_a_conf;
1046         }
1047
1048         /* Use ADPA register for sync control. */
1049         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1050
1051         /* sync polarity */
1052         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1053                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1054         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1055                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1056         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1057                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1058         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1059                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1060
1061         /* Connect correct pipe to the analog port DAC */
1062         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1063         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1064
1065         /* Set DPMS state to D0 (on) */
1066         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1067         hw->adpa |= ADPA_DPMS_D0;
1068
1069         hw->adpa |= ADPA_DAC_ENABLE;
1070
1071         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1072         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1073         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1074
1075         /* Desired clock in kHz */
1076         clock_target = 1000000000 / var->pixclock;
1077
1078         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1079                             &n, &p1, &p2, &clock)) {
1080                 WRN_MSG("calc_pll_params failed\n");
1081                 return 1;
1082         }
1083
1084         /* Check for overflow. */
1085         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1086                 return 1;
1087         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1088                 return 1;
1089         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1090                 return 1;
1091         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1092                 return 1;
1093         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1094                 return 1;
1095
1096         *dpll &= ~DPLL_P1_FORCE_DIV2;
1097         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1098                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1099
1100         if (IS_I9XX(dinfo)) {
1101                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1102                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1103         } else {
1104                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1105         }
1106
1107         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1108                (m1 << FP_M1_DIVISOR_SHIFT) |
1109                (m2 << FP_M2_DIVISOR_SHIFT);
1110         *fp1 = *fp0;
1111
1112         hw->dvob &= ~PORT_ENABLE;
1113         hw->dvoc &= ~PORT_ENABLE;
1114
1115         /* Use display plane A. */
1116         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1117         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1118         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1119         switch (intelfb_var_to_depth(var)) {
1120         case 8:
1121                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1122                 break;
1123         case 15:
1124                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1125                 break;
1126         case 16:
1127                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1128                 break;
1129         case 24:
1130                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1131                 break;
1132         }
1133         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1134         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1135
1136         /* Set CRTC registers. */
1137         hactive = var->xres;
1138         hsync_start = hactive + var->right_margin;
1139         hsync_end = hsync_start + var->hsync_len;
1140         htotal = hsync_end + var->left_margin;
1141         hblank_start = hactive;
1142         hblank_end = htotal;
1143
1144         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1145                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1146                 hblank_end);
1147
1148         vactive = var->yres;
1149         vsync_start = vactive + var->lower_margin;
1150         vsync_end = vsync_start + var->vsync_len;
1151         vtotal = vsync_end + var->upper_margin;
1152         vblank_start = vactive;
1153         vblank_end = vtotal;
1154         vblank_end = vsync_end + 1;
1155
1156         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1157                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1158                 vblank_end);
1159
1160         /* Adjust for register values, and check for overflow. */
1161         hactive--;
1162         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1163                 return 1;
1164         hsync_start--;
1165         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1166                 return 1;
1167         hsync_end--;
1168         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1169                 return 1;
1170         htotal--;
1171         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1172                 return 1;
1173         hblank_start--;
1174         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1175                 return 1;
1176         hblank_end--;
1177         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1178                 return 1;
1179
1180         vactive--;
1181         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1182                 return 1;
1183         vsync_start--;
1184         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1185                 return 1;
1186         vsync_end--;
1187         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1188                 return 1;
1189         vtotal--;
1190         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1191                 return 1;
1192         vblank_start--;
1193         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1194                 return 1;
1195         vblank_end--;
1196         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1197                 return 1;
1198
1199         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1200         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1201               (hblank_end << HSYNCEND_SHIFT);
1202         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1203
1204         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1205         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1206               (vblank_end << VSYNCEND_SHIFT);
1207         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1208         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1209               (vactive << SRC_SIZE_VERT_SHIFT);
1210
1211         hw->disp_a_stride = dinfo->pitch;
1212         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1213
1214         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1215                           var->xoffset * var->bits_per_pixel / 8;
1216
1217         hw->disp_a_base += dinfo->fb.offset << 12;
1218
1219         /* Check stride alignment. */
1220         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1221                                             STRIDE_ALIGNMENT;
1222         if (hw->disp_a_stride % stride_alignment != 0) {
1223                 WRN_MSG("display stride %d has bad alignment %d\n",
1224                         hw->disp_a_stride, stride_alignment);
1225                 return 1;
1226         }
1227
1228         /* Set the palette to 8-bit mode. */
1229         *pipe_conf &= ~PIPECONF_GAMMA;
1230         return 0;
1231 }
1232
1233 /* Program a (non-VGA) video mode. */
1234 int
1235 intelfbhw_program_mode(struct intelfb_info *dinfo,
1236                      const struct intelfb_hwstate *hw, int blank)
1237 {
1238         int pipe = PIPE_A;
1239         u32 tmp;
1240         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1241         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1242         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1243         u32 hsync_reg, htotal_reg, hblank_reg;
1244         u32 vsync_reg, vtotal_reg, vblank_reg;
1245         u32 src_size_reg;
1246         u32 count, tmp_val[3];
1247
1248         /* Assume single pipe, display plane A, analog CRT. */
1249
1250 #if VERBOSE > 0
1251         DBG_MSG("intelfbhw_program_mode\n");
1252 #endif
1253
1254         /* Disable VGA */
1255         tmp = INREG(VGACNTRL);
1256         tmp |= VGA_DISABLE;
1257         OUTREG(VGACNTRL, tmp);
1258
1259         /* Check whether pipe A or pipe B is enabled. */
1260         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1261                 pipe = PIPE_A;
1262         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1263                 pipe = PIPE_B;
1264
1265         dinfo->pipe = pipe;
1266
1267         if (pipe == PIPE_B) {
1268                 dpll = &hw->dpll_b;
1269                 fp0 = &hw->fpb0;
1270                 fp1 = &hw->fpb1;
1271                 pipe_conf = &hw->pipe_b_conf;
1272                 hs = &hw->hsync_b;
1273                 hb = &hw->hblank_b;
1274                 ht = &hw->htotal_b;
1275                 vs = &hw->vsync_b;
1276                 vb = &hw->vblank_b;
1277                 vt = &hw->vtotal_b;
1278                 ss = &hw->src_size_b;
1279                 dpll_reg = DPLL_B;
1280                 fp0_reg = FPB0;
1281                 fp1_reg = FPB1;
1282                 pipe_conf_reg = PIPEBCONF;
1283                 hsync_reg = HSYNC_B;
1284                 htotal_reg = HTOTAL_B;
1285                 hblank_reg = HBLANK_B;
1286                 vsync_reg = VSYNC_B;
1287                 vtotal_reg = VTOTAL_B;
1288                 vblank_reg = VBLANK_B;
1289                 src_size_reg = SRC_SIZE_B;
1290         } else {
1291                 dpll = &hw->dpll_a;
1292                 fp0 = &hw->fpa0;
1293                 fp1 = &hw->fpa1;
1294                 pipe_conf = &hw->pipe_a_conf;
1295                 hs = &hw->hsync_a;
1296                 hb = &hw->hblank_a;
1297                 ht = &hw->htotal_a;
1298                 vs = &hw->vsync_a;
1299                 vb = &hw->vblank_a;
1300                 vt = &hw->vtotal_a;
1301                 ss = &hw->src_size_a;
1302                 dpll_reg = DPLL_A;
1303                 fp0_reg = FPA0;
1304                 fp1_reg = FPA1;
1305                 pipe_conf_reg = PIPEACONF;
1306                 hsync_reg = HSYNC_A;
1307                 htotal_reg = HTOTAL_A;
1308                 hblank_reg = HBLANK_A;
1309                 vsync_reg = VSYNC_A;
1310                 vtotal_reg = VTOTAL_A;
1311                 vblank_reg = VBLANK_A;
1312                 src_size_reg = SRC_SIZE_A;
1313         }
1314
1315         /* turn off pipe */
1316         tmp = INREG(pipe_conf_reg);
1317         tmp &= ~PIPECONF_ENABLE;
1318         OUTREG(pipe_conf_reg, tmp);
1319
1320         count = 0;
1321         do {
1322                 tmp_val[count%3] = INREG(0x70000);
1323                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1324                         break;
1325                 count++;
1326                 udelay(1);
1327                 if (count % 200 == 0) {
1328                         tmp = INREG(pipe_conf_reg);
1329                         tmp &= ~PIPECONF_ENABLE;
1330                         OUTREG(pipe_conf_reg, tmp);
1331                 }
1332         } while(count < 2000);
1333
1334         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1335
1336         /* Disable planes A and B. */
1337         tmp = INREG(DSPACNTR);
1338         tmp &= ~DISPPLANE_PLANE_ENABLE;
1339         OUTREG(DSPACNTR, tmp);
1340         tmp = INREG(DSPBCNTR);
1341         tmp &= ~DISPPLANE_PLANE_ENABLE;
1342         OUTREG(DSPBCNTR, tmp);
1343
1344         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1345         mdelay(20);
1346
1347         /* Disable Sync */
1348         tmp = INREG(ADPA);
1349         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1350         tmp |= ADPA_DPMS_D3;
1351         OUTREG(ADPA, tmp);
1352
1353         /* do some funky magic - xyzzy */
1354         OUTREG(0x61204, 0xabcd0000);
1355
1356         /* turn off PLL */
1357         tmp = INREG(dpll_reg);
1358         dpll_reg &= ~DPLL_VCO_ENABLE;
1359         OUTREG(dpll_reg, tmp);
1360
1361         /* Set PLL parameters */
1362         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1363         OUTREG(fp0_reg, *fp0);
1364         OUTREG(fp1_reg, *fp1);
1365
1366         /* Enable PLL */
1367         tmp = INREG(dpll_reg);
1368         tmp |= DPLL_VCO_ENABLE;
1369         OUTREG(dpll_reg, tmp);
1370
1371         /* Set DVOs B/C */
1372         OUTREG(DVOB, hw->dvob);
1373         OUTREG(DVOC, hw->dvoc);
1374
1375         /* undo funky magic */
1376         OUTREG(0x61204, 0x00000000);
1377
1378         /* Set ADPA */
1379         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1380         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1381
1382         /* Set pipe parameters */
1383         OUTREG(hsync_reg, *hs);
1384         OUTREG(hblank_reg, *hb);
1385         OUTREG(htotal_reg, *ht);
1386         OUTREG(vsync_reg, *vs);
1387         OUTREG(vblank_reg, *vb);
1388         OUTREG(vtotal_reg, *vt);
1389         OUTREG(src_size_reg, *ss);
1390
1391         /* Enable pipe */
1392         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1393
1394         /* Enable sync */
1395         tmp = INREG(ADPA);
1396         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1397         tmp |= ADPA_DPMS_D0;
1398         OUTREG(ADPA, tmp);
1399
1400         /* setup display plane */
1401         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1402                 /*
1403                  *      i830M errata: the display plane must be enabled
1404                  *      to allow writes to the other bits in the plane
1405                  *      control register.
1406                  */
1407                 tmp = INREG(DSPACNTR);
1408                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1409                         tmp |= DISPPLANE_PLANE_ENABLE;
1410                         OUTREG(DSPACNTR, tmp);
1411                         OUTREG(DSPACNTR,
1412                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1413                         mdelay(1);
1414                 }
1415         }
1416
1417         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1418         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1419         OUTREG(DSPABASE, hw->disp_a_base);
1420
1421         /* Enable plane */
1422         if (!blank) {
1423                 tmp = INREG(DSPACNTR);
1424                 tmp |= DISPPLANE_PLANE_ENABLE;
1425                 OUTREG(DSPACNTR, tmp);
1426                 OUTREG(DSPABASE, hw->disp_a_base);
1427         }
1428
1429         return 0;
1430 }
1431
1432 /* forward declarations */
1433 static void refresh_ring(struct intelfb_info *dinfo);
1434 static void reset_state(struct intelfb_info *dinfo);
1435 static void do_flush(struct intelfb_info *dinfo);
1436
1437 static int
1438 wait_ring(struct intelfb_info *dinfo, int n)
1439 {
1440         int i = 0;
1441         unsigned long end;
1442         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1443
1444 #if VERBOSE > 0
1445         DBG_MSG("wait_ring: %d\n", n);
1446 #endif
1447
1448         end = jiffies + (HZ * 3);
1449         while (dinfo->ring_space < n) {
1450                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1451                                                    RING_HEAD_MASK);
1452                 if (dinfo->ring_tail + RING_MIN_FREE <
1453                     (u32 __iomem) dinfo->ring_head)
1454                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1455                                 - (dinfo->ring_tail + RING_MIN_FREE);
1456                 else
1457                         dinfo->ring_space = (dinfo->ring.size +
1458                                              (u32 __iomem) dinfo->ring_head)
1459                                 - (dinfo->ring_tail + RING_MIN_FREE);
1460                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1461                         end = jiffies + (HZ * 3);
1462                         last_head = (u32 __iomem) dinfo->ring_head;
1463                 }
1464                 i++;
1465                 if (time_before(end, jiffies)) {
1466                         if (!i) {
1467                                 /* Try again */
1468                                 reset_state(dinfo);
1469                                 refresh_ring(dinfo);
1470                                 do_flush(dinfo);
1471                                 end = jiffies + (HZ * 3);
1472                                 i = 1;
1473                         } else {
1474                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1475                                         dinfo->ring_space, n);
1476                                 WRN_MSG("lockup - turning off hardware "
1477                                         "acceleration\n");
1478                                 dinfo->ring_lockup = 1;
1479                                 break;
1480                         }
1481                 }
1482                 udelay(1);
1483         }
1484         return i;
1485 }
1486
1487 static void
1488 do_flush(struct intelfb_info *dinfo) {
1489         START_RING(2);
1490         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1491         OUT_RING(MI_NOOP);
1492         ADVANCE_RING();
1493 }
1494
1495 void
1496 intelfbhw_do_sync(struct intelfb_info *dinfo)
1497 {
1498 #if VERBOSE > 0
1499         DBG_MSG("intelfbhw_do_sync\n");
1500 #endif
1501
1502         if (!dinfo->accel)
1503                 return;
1504
1505         /*
1506          * Send a flush, then wait until the ring is empty.  This is what
1507          * the XFree86 driver does, and actually it doesn't seem a lot worse
1508          * than the recommended method (both have problems).
1509          */
1510         do_flush(dinfo);
1511         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1512         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1513 }
1514
1515 static void
1516 refresh_ring(struct intelfb_info *dinfo)
1517 {
1518 #if VERBOSE > 0
1519         DBG_MSG("refresh_ring\n");
1520 #endif
1521
1522         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1523                                            RING_HEAD_MASK);
1524         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1525         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1526                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1527                         - (dinfo->ring_tail + RING_MIN_FREE);
1528         else
1529                 dinfo->ring_space = (dinfo->ring.size +
1530                                      (u32 __iomem) dinfo->ring_head)
1531                         - (dinfo->ring_tail + RING_MIN_FREE);
1532 }
1533
1534 static void
1535 reset_state(struct intelfb_info *dinfo)
1536 {
1537         int i;
1538         u32 tmp;
1539
1540 #if VERBOSE > 0
1541         DBG_MSG("reset_state\n");
1542 #endif
1543
1544         for (i = 0; i < FENCE_NUM; i++)
1545                 OUTREG(FENCE + (i << 2), 0);
1546
1547         /* Flush the ring buffer if it's enabled. */
1548         tmp = INREG(PRI_RING_LENGTH);
1549         if (tmp & RING_ENABLE) {
1550 #if VERBOSE > 0
1551                 DBG_MSG("reset_state: ring was enabled\n");
1552 #endif
1553                 refresh_ring(dinfo);
1554                 intelfbhw_do_sync(dinfo);
1555                 DO_RING_IDLE();
1556         }
1557
1558         OUTREG(PRI_RING_LENGTH, 0);
1559         OUTREG(PRI_RING_HEAD, 0);
1560         OUTREG(PRI_RING_TAIL, 0);
1561         OUTREG(PRI_RING_START, 0);
1562 }
1563
1564 /* Stop the 2D engine, and turn off the ring buffer. */
1565 void
1566 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1567 {
1568 #if VERBOSE > 0
1569         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1570                 dinfo->ring_active);
1571 #endif
1572
1573         if (!dinfo->accel)
1574                 return;
1575
1576         dinfo->ring_active = 0;
1577         reset_state(dinfo);
1578 }
1579
1580 /*
1581  * Enable the ring buffer, and initialise the 2D engine.
1582  * It is assumed that the graphics engine has been stopped by previously
1583  * calling intelfb_2d_stop().
1584  */
1585 void
1586 intelfbhw_2d_start(struct intelfb_info *dinfo)
1587 {
1588 #if VERBOSE > 0
1589         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1590                 dinfo->accel, dinfo->ring_active);
1591 #endif
1592
1593         if (!dinfo->accel)
1594                 return;
1595
1596         /* Initialise the primary ring buffer. */
1597         OUTREG(PRI_RING_LENGTH, 0);
1598         OUTREG(PRI_RING_TAIL, 0);
1599         OUTREG(PRI_RING_HEAD, 0);
1600
1601         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1602         OUTREG(PRI_RING_LENGTH,
1603                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1604                 RING_NO_REPORT | RING_ENABLE);
1605         refresh_ring(dinfo);
1606         dinfo->ring_active = 1;
1607 }
1608
1609 /* 2D fillrect (solid fill or invert) */
1610 void
1611 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1612                       u32 color, u32 pitch, u32 bpp, u32 rop)
1613 {
1614         u32 br00, br09, br13, br14, br16;
1615
1616 #if VERBOSE > 0
1617         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1618                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1619 #endif
1620
1621         br00 = COLOR_BLT_CMD;
1622         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1623         br13 = (rop << ROP_SHIFT) | pitch;
1624         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1625         br16 = color;
1626
1627         switch (bpp) {
1628         case 8:
1629                 br13 |= COLOR_DEPTH_8;
1630                 break;
1631         case 16:
1632                 br13 |= COLOR_DEPTH_16;
1633                 break;
1634         case 32:
1635                 br13 |= COLOR_DEPTH_32;
1636                 br00 |= WRITE_ALPHA | WRITE_RGB;
1637                 break;
1638         }
1639
1640         START_RING(6);
1641         OUT_RING(br00);
1642         OUT_RING(br13);
1643         OUT_RING(br14);
1644         OUT_RING(br09);
1645         OUT_RING(br16);
1646         OUT_RING(MI_NOOP);
1647         ADVANCE_RING();
1648
1649 #if VERBOSE > 0
1650         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1651                 dinfo->ring_tail, dinfo->ring_space);
1652 #endif
1653 }
1654
1655 void
1656 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1657                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1658 {
1659         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1660
1661 #if VERBOSE > 0
1662         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1663                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1664 #endif
1665
1666         br00 = XY_SRC_COPY_BLT_CMD;
1667         br09 = dinfo->fb_start;
1668         br11 = (pitch << PITCH_SHIFT);
1669         br12 = dinfo->fb_start;
1670         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1671         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1672         br23 = ((dstx + w) << WIDTH_SHIFT) |
1673                ((dsty + h) << HEIGHT_SHIFT);
1674         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1675
1676         switch (bpp) {
1677         case 8:
1678                 br13 |= COLOR_DEPTH_8;
1679                 break;
1680         case 16:
1681                 br13 |= COLOR_DEPTH_16;
1682                 break;
1683         case 32:
1684                 br13 |= COLOR_DEPTH_32;
1685                 br00 |= WRITE_ALPHA | WRITE_RGB;
1686                 break;
1687         }
1688
1689         START_RING(8);
1690         OUT_RING(br00);
1691         OUT_RING(br13);
1692         OUT_RING(br22);
1693         OUT_RING(br23);
1694         OUT_RING(br09);
1695         OUT_RING(br26);
1696         OUT_RING(br11);
1697         OUT_RING(br12);
1698         ADVANCE_RING();
1699 }
1700
1701 int
1702 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1703                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1704 {
1705         int nbytes, ndwords, pad, tmp;
1706         u32 br00, br09, br13, br18, br19, br22, br23;
1707         int dat, ix, iy, iw;
1708         int i, j;
1709
1710 #if VERBOSE > 0
1711         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1712 #endif
1713
1714         /* size in bytes of a padded scanline */
1715         nbytes = ROUND_UP_TO(w, 16) / 8;
1716
1717         /* Total bytes of padded scanline data to write out. */
1718         nbytes = nbytes * h;
1719
1720         /*
1721          * Check if the glyph data exceeds the immediate mode limit.
1722          * It would take a large font (1K pixels) to hit this limit.
1723          */
1724         if (nbytes > MAX_MONO_IMM_SIZE)
1725                 return 0;
1726
1727         /* Src data is packaged a dword (32-bit) at a time. */
1728         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1729
1730         /*
1731          * Ring has to be padded to a quad word. But because the command starts
1732            with 7 bytes, pad only if there is an even number of ndwords
1733          */
1734         pad = !(ndwords % 2);
1735
1736         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1737         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1738         br09 = dinfo->fb_start;
1739         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1740         br18 = bg;
1741         br19 = fg;
1742         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1743         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1744
1745         switch (bpp) {
1746         case 8:
1747                 br13 |= COLOR_DEPTH_8;
1748                 break;
1749         case 16:
1750                 br13 |= COLOR_DEPTH_16;
1751                 break;
1752         case 32:
1753                 br13 |= COLOR_DEPTH_32;
1754                 br00 |= WRITE_ALPHA | WRITE_RGB;
1755                 break;
1756         }
1757
1758         START_RING(8 + ndwords);
1759         OUT_RING(br00);
1760         OUT_RING(br13);
1761         OUT_RING(br22);
1762         OUT_RING(br23);
1763         OUT_RING(br09);
1764         OUT_RING(br18);
1765         OUT_RING(br19);
1766         ix = iy = 0;
1767         iw = ROUND_UP_TO(w, 8) / 8;
1768         while (ndwords--) {
1769                 dat = 0;
1770                 for (j = 0; j < 2; ++j) {
1771                         for (i = 0; i < 2; ++i) {
1772                                 if (ix != iw || i == 0)
1773                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1774                         }
1775                         if (ix == iw && iy != (h-1)) {
1776                                 ix = 0;
1777                                 ++iy;
1778                         }
1779                 }
1780                 OUT_RING(dat);
1781         }
1782         if (pad)
1783                 OUT_RING(MI_NOOP);
1784         ADVANCE_RING();
1785
1786         return 1;
1787 }
1788
1789 /* HW cursor functions. */
1790 void
1791 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1792 {
1793         u32 tmp;
1794
1795 #if VERBOSE > 0
1796         DBG_MSG("intelfbhw_cursor_init\n");
1797 #endif
1798
1799         if (dinfo->mobile || IS_I9XX(dinfo)) {
1800                 if (!dinfo->cursor.physical)
1801                         return;
1802                 tmp = INREG(CURSOR_A_CONTROL);
1803                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1804                          CURSOR_MEM_TYPE_LOCAL |
1805                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1806                 tmp |= CURSOR_MODE_DISABLE;
1807                 OUTREG(CURSOR_A_CONTROL, tmp);
1808                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1809         } else {
1810                 tmp = INREG(CURSOR_CONTROL);
1811                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1812                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1813                 tmp = CURSOR_FORMAT_3C;
1814                 OUTREG(CURSOR_CONTROL, tmp);
1815                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1816                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1817                       (64 << CURSOR_SIZE_V_SHIFT);
1818                 OUTREG(CURSOR_SIZE, tmp);
1819         }
1820 }
1821
1822 void
1823 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1824 {
1825         u32 tmp;
1826
1827 #if VERBOSE > 0
1828         DBG_MSG("intelfbhw_cursor_hide\n");
1829 #endif
1830
1831         dinfo->cursor_on = 0;
1832         if (dinfo->mobile || IS_I9XX(dinfo)) {
1833                 if (!dinfo->cursor.physical)
1834                         return;
1835                 tmp = INREG(CURSOR_A_CONTROL);
1836                 tmp &= ~CURSOR_MODE_MASK;
1837                 tmp |= CURSOR_MODE_DISABLE;
1838                 OUTREG(CURSOR_A_CONTROL, tmp);
1839                 /* Flush changes */
1840                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1841         } else {
1842                 tmp = INREG(CURSOR_CONTROL);
1843                 tmp &= ~CURSOR_ENABLE;
1844                 OUTREG(CURSOR_CONTROL, tmp);
1845         }
1846 }
1847
1848 void
1849 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1850 {
1851         u32 tmp;
1852
1853 #if VERBOSE > 0
1854         DBG_MSG("intelfbhw_cursor_show\n");
1855 #endif
1856
1857         dinfo->cursor_on = 1;
1858
1859         if (dinfo->cursor_blanked)
1860                 return;
1861
1862         if (dinfo->mobile || IS_I9XX(dinfo)) {
1863                 if (!dinfo->cursor.physical)
1864                         return;
1865                 tmp = INREG(CURSOR_A_CONTROL);
1866                 tmp &= ~CURSOR_MODE_MASK;
1867                 tmp |= CURSOR_MODE_64_4C_AX;
1868                 OUTREG(CURSOR_A_CONTROL, tmp);
1869                 /* Flush changes */
1870                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1871         } else {
1872                 tmp = INREG(CURSOR_CONTROL);
1873                 tmp |= CURSOR_ENABLE;
1874                 OUTREG(CURSOR_CONTROL, tmp);
1875         }
1876 }
1877
1878 void
1879 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1880 {
1881         u32 tmp;
1882
1883 #if VERBOSE > 0
1884         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1885 #endif
1886
1887         /*
1888          * Sets the position. The coordinates are assumed to already
1889          * have any offset adjusted. Assume that the cursor is never
1890          * completely off-screen, and that x, y are always >= 0.
1891          */
1892
1893         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1894               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1895         OUTREG(CURSOR_A_POSITION, tmp);
1896
1897         if (IS_I9XX(dinfo)) {
1898                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1899         }
1900 }
1901
1902 void
1903 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1904 {
1905 #if VERBOSE > 0
1906         DBG_MSG("intelfbhw_cursor_setcolor\n");
1907 #endif
1908
1909         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1910         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1911         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1912         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1913 }
1914
1915 void
1916 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1917                       u8 *data)
1918 {
1919         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1920         int i, j, w = width / 8;
1921         int mod = width % 8, t_mask, d_mask;
1922
1923 #if VERBOSE > 0
1924         DBG_MSG("intelfbhw_cursor_load\n");
1925 #endif
1926
1927         if (!dinfo->cursor.virtual)
1928                 return;
1929
1930         t_mask = 0xff >> mod;
1931         d_mask = ~(0xff >> mod);
1932         for (i = height; i--; ) {
1933                 for (j = 0; j < w; j++) {
1934                         writeb(0x00, addr + j);
1935                         writeb(*(data++), addr + j+8);
1936                 }
1937                 if (mod) {
1938                         writeb(t_mask, addr + j);
1939                         writeb(*(data++) & d_mask, addr + j+8);
1940                 }
1941                 addr += 16;
1942         }
1943 }
1944
1945 void
1946 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1947         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1948         int i, j;
1949
1950 #if VERBOSE > 0
1951         DBG_MSG("intelfbhw_cursor_reset\n");
1952 #endif
1953
1954         if (!dinfo->cursor.virtual)
1955                 return;
1956
1957         for (i = 64; i--; ) {
1958                 for (j = 0; j < 8; j++) {
1959                         writeb(0xff, addr + j+0);
1960                         writeb(0x00, addr + j+8);
1961                 }
1962                 addr += 16;
1963         }
1964 }