drivers/video/i810/i810_main.c

   1  /*-*- linux-c -*-
   2  *  linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
   3  *
   4  *      Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
   5  *      All Rights Reserved
   6  *
   7  *      Contributors:
   8  *         Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
   9  *                                        and enabling the power-on state of
  10  *                                        external VGA connectors for
  11  *                                        secondary displays
  12  *
  13  *         Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
  14  *                                        the VESA GTF
  15  *
  16  *         Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
  17  *                                        timings support
  18  *
  19  *      The code framework is a modification of vfb.c by Geert Uytterhoeven.
  20  *      DotClock and PLL calculations are partly based on i810_driver.c
  21  *              in xfree86 v4.0.3 by Precision Insight.
  22  *      Watermark calculation and tables are based on i810_wmark.c
  23  *              in xfre86 v4.0.3 by Precision Insight.  Slight modifications
  24  *              only to allow for integer operations instead of floating point.
  25  *
  26  *  This file is subject to the terms and conditions of the GNU General Public
  27  *  License. See the file COPYING in the main directory of this archive for
  28  *  more details.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/config.h>
  33 #include <linux/kernel.h>
  34 #include <linux/errno.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/tty.h>
  38 #include <linux/slab.h>
  39 #include <linux/fb.h>
  40 #include <linux/init.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci_ids.h>
  43 #include <linux/resource.h>
  44 #include <linux/unistd.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/div64.h>
  48
  49 #ifdef CONFIG_MTRR
  50 #include <asm/mtrr.h>
  51 #endif
  52
  53 #include <asm/page.h>
  54
  55 #include "i810_regs.h"
  56 #include "i810.h"
  57 #include "i810_main.h"
  58
  59 /* PCI */
  60 static const char *i810_pci_list[] __devinitdata = {
  61         "Intel(R) 810 Framebuffer Device"                                 ,
  62         "Intel(R) 810-DC100 Framebuffer Device"                           ,
  63         "Intel(R) 810E Framebuffer Device"                                ,
  64         "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device"  ,
  65         "Intel(R) 815 (Internal Graphics only) Framebuffer Device"        ,
  66         "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
  67 };
  68
  69 static struct pci_device_id i810fb_pci_tbl[] = {
  70         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
  71           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  72         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
  73           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1  },
  74         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
  75           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
  76         /* mvo: added i815 PCI-ID */
  77         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
  78           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
  79         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
  80           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
  81         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
  82           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
  83         { 0 },
  84 };
  85
  86 static struct pci_driver i810fb_driver = {
  87         .name     =     "i810fb",
  88         .id_table =     i810fb_pci_tbl,
  89         .probe    =     i810fb_init_pci,
  90         .remove   =     __exit_p(i810fb_remove_pci),
  91         .suspend  =     i810fb_suspend,
  92         .resume   =     i810fb_resume,
  93 };
  94
  95 static char *mode_option __devinitdata = NULL;
  96 static int vram       __devinitdata = 4;
  97 static int bpp        __devinitdata = 8;
  98 static int mtrr       __devinitdata = 0;
  99 static int accel      __devinitdata = 0;
 100 static int hsync1     __devinitdata = 0;
 101 static int hsync2     __devinitdata = 0;
 102 static int vsync1     __devinitdata = 0;
 103 static int vsync2     __devinitdata = 0;
 104 static int xres       __devinitdata = 640;
 105 static int yres       __devinitdata = 480;
 106 static int vyres      __devinitdata = 0;
 107 static int sync       __devinitdata = 0;
 108 static int ext_vga    __devinitdata = 0;
 109 static int dcolor     __devinitdata = 0;
 110
 111 /*------------------------------------------------------------*/
 112
 113 /**************************************************************
 114  *                Hardware Low Level Routines                 *
 115  **************************************************************/
 116
 117 /**
 118  * i810_screen_off - turns off/on display
 119  * @mmio: address of register space
 120  * @mode: on or off
 121  *
 122  * DESCRIPTION:
 123  * Blanks/unblanks the display
 124  */
 125 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
 126 {
 127         u32 count = WAIT_COUNT;
 128         u8 val;
 129
 130         i810_writeb(SR_INDEX, mmio, SR01);
 131         val = i810_readb(SR_DATA, mmio);
 132         val = (mode == OFF) ? val | SCR_OFF :
 133                 val & ~SCR_OFF;
 134
 135         while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
 136         i810_writeb(SR_INDEX, mmio, SR01);
 137         i810_writeb(SR_DATA, mmio, val);
 138 }
 139
 140 /**
 141  * i810_dram_off - turns off/on dram refresh
 142  * @mmio: address of register space
 143  * @mode: on or off
 144  *
 145  * DESCRIPTION:
 146  * Turns off DRAM refresh.  Must be off for only 2 vsyncs
 147  * before data becomes corrupt
 148  */
 149 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
 150 {
 151         u8 val;
 152
 153         val = i810_readb(DRAMCH, mmio);
 154         val &= DRAM_OFF;
 155         val = (mode == OFF) ? val : val | DRAM_ON;
 156         i810_writeb(DRAMCH, mmio, val);
 157 }
 158
 159 /**
 160  * i810_protect_regs - allows rw/ro mode of certain VGA registers
 161  * @mmio: address of register space
 162  * @mode: protect/unprotect
 163  *
 164  * DESCRIPTION:
 165  * The IBM VGA standard allows protection of certain VGA registers.
 166  * This will  protect or unprotect them.
 167  */
 168 static void i810_protect_regs(u8 __iomem *mmio, int mode)
 169 {
 170         u8 reg;
 171
 172         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 173         reg = i810_readb(CR_DATA_CGA, mmio);
 174         reg = (mode == OFF) ? reg & ~0x80 :
 175                 reg | 0x80;
 176
 177         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 178         i810_writeb(CR_DATA_CGA, mmio, reg);
 179 }
 180
 181 /**
 182  * i810_load_pll - loads values for the hardware PLL clock
 183  * @par: pointer to i810fb_par structure
 184  *
 185  * DESCRIPTION:
 186  * Loads the P, M, and N registers.
 187  */
 188 static void i810_load_pll(struct i810fb_par *par)
 189 {
 190         u32 tmp1, tmp2;
 191         u8 __iomem *mmio = par->mmio_start_virtual;
 192
 193         tmp1 = par->regs.M | par->regs.N << 16;
 194         tmp2 = i810_readl(DCLK_2D, mmio);
 195         tmp2 &= ~MN_MASK;
 196         i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
 197
 198         tmp1 = par->regs.P;
 199         tmp2 = i810_readl(DCLK_0DS, mmio);
 200         tmp2 &= ~(P_OR << 16);
 201         i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
 202
 203         i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
 204
 205 }
 206
 207 /**
 208  * i810_load_vga - load standard VGA registers
 209  * @par: pointer to i810fb_par structure
 210  *
 211  * DESCRIPTION:
 212  * Load values to VGA registers
 213  */
 214 static void i810_load_vga(struct i810fb_par *par)
 215 {
 216         u8 __iomem *mmio = par->mmio_start_virtual;
 217
 218         /* interlace */
 219         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 220         i810_writeb(CR_DATA_CGA, mmio, par->interlace);
 221
 222         i810_writeb(CR_INDEX_CGA, mmio, CR00);
 223         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
 224         i810_writeb(CR_INDEX_CGA, mmio, CR01);
 225         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
 226         i810_writeb(CR_INDEX_CGA, mmio, CR02);
 227         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
 228         i810_writeb(CR_INDEX_CGA, mmio, CR03);
 229         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
 230         i810_writeb(CR_INDEX_CGA, mmio, CR04);
 231         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
 232         i810_writeb(CR_INDEX_CGA, mmio, CR05);
 233         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
 234         i810_writeb(CR_INDEX_CGA, mmio, CR06);
 235         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
 236         i810_writeb(CR_INDEX_CGA, mmio, CR09);
 237         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
 238         i810_writeb(CR_INDEX_CGA, mmio, CR10);
 239         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
 240         i810_writeb(CR_INDEX_CGA, mmio, CR11);
 241         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
 242         i810_writeb(CR_INDEX_CGA, mmio, CR12);
 243         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
 244         i810_writeb(CR_INDEX_CGA, mmio, CR15);
 245         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
 246         i810_writeb(CR_INDEX_CGA, mmio, CR16);
 247         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
 248 }
 249
 250 /**
 251  * i810_load_vgax - load extended VGA registers
 252  * @par: pointer to i810fb_par structure
 253  *
 254  * DESCRIPTION:
 255  * Load values to extended VGA registers
 256  */
 257 static void i810_load_vgax(struct i810fb_par *par)
 258 {
 259         u8 __iomem *mmio = par->mmio_start_virtual;
 260
 261         i810_writeb(CR_INDEX_CGA, mmio, CR30);
 262         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
 263         i810_writeb(CR_INDEX_CGA, mmio, CR31);
 264         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
 265         i810_writeb(CR_INDEX_CGA, mmio, CR32);
 266         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
 267         i810_writeb(CR_INDEX_CGA, mmio, CR33);
 268         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
 269         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 270         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
 271         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 272         i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
 273 }
 274
 275 /**
 276  * i810_load_2d - load grahics registers
 277  * @par: pointer to i810fb_par structure
 278  *
 279  * DESCRIPTION:
 280  * Load values to graphics registers
 281  */
 282 static void i810_load_2d(struct i810fb_par *par)
 283 {
 284         u32 tmp;
 285         u8 tmp8;
 286         u8 __iomem *mmio = par->mmio_start_virtual;
 287
 288         i810_writel(FW_BLC, mmio, par->watermark);
 289         tmp = i810_readl(PIXCONF, mmio);
 290         tmp |= 1 | 1 << 20;
 291         i810_writel(PIXCONF, mmio, tmp);
 292
 293         i810_writel(OVRACT, mmio, par->ovract);
 294
 295         i810_writeb(GR_INDEX, mmio, GR10);
 296         tmp8 = i810_readb(GR_DATA, mmio);
 297         tmp8 |= 2;
 298         i810_writeb(GR_INDEX, mmio, GR10);
 299         i810_writeb(GR_DATA, mmio, tmp8);
 300 }
 301
 302 /**
 303  * i810_hires - enables high resolution mode
 304  * @mmio: address of register space
 305  */
 306 static void i810_hires(u8 __iomem *mmio)
 307 {
 308         u8 val;
 309
 310         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 311         val = i810_readb(CR_DATA_CGA, mmio);
 312         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 313         i810_writeb(CR_DATA_CGA, mmio, val | 1);
 314         /* Stop LCD displays from flickering */
 315         i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4);
 316 }
 317
 318 /**
 319  * i810_load_pitch - loads the characters per line of the display
 320  * @par: pointer to i810fb_par structure
 321  *
 322  * DESCRIPTION:
 323  * Loads the characters per line
 324  */
 325 static void i810_load_pitch(struct i810fb_par *par)
 326 {
 327         u32 tmp, pitch;
 328         u8 val;
 329         u8 __iomem *mmio = par->mmio_start_virtual;
 330
 331         pitch = par->pitch >> 3;
 332         i810_writeb(SR_INDEX, mmio, SR01);
 333         val = i810_readb(SR_DATA, mmio);
 334         val &= 0xE0;
 335         val |= 1 | 1 << 2;
 336         i810_writeb(SR_INDEX, mmio, SR01);
 337         i810_writeb(SR_DATA, mmio, val);
 338
 339         tmp = pitch & 0xFF;
 340         i810_writeb(CR_INDEX_CGA, mmio, CR13);
 341         i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
 342
 343         tmp = pitch >> 8;
 344         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 345         val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
 346         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 347         i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
 348 }
 349
 350 /**
 351  * i810_load_color - loads the color depth of the display
 352  * @par: pointer to i810fb_par structure
 353  *
 354  * DESCRIPTION:
 355  * Loads the color depth of the display and the graphics engine
 356  */
 357 static void i810_load_color(struct i810fb_par *par)
 358 {
 359         u8 __iomem *mmio = par->mmio_start_virtual;
 360         u32 reg1;
 361         u16 reg2;
 362
 363         reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
 364         reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
 365
 366         reg1 |= 0x8000 | par->pixconf;
 367         reg2 |= par->bltcntl;
 368         i810_writel(PIXCONF, mmio, reg1);
 369         i810_writew(BLTCNTL, mmio, reg2);
 370 }
 371
 372 /**
 373  * i810_load_regs - loads all registers for the mode
 374  * @par: pointer to i810fb_par structure
 375  *
 376  * DESCRIPTION:
 377  * Loads registers
 378  */
 379 static void i810_load_regs(struct i810fb_par *par)
 380 {
 381         u8 __iomem *mmio = par->mmio_start_virtual;
 382
 383         i810_screen_off(mmio, OFF);
 384         i810_protect_regs(mmio, OFF);
 385         i810_dram_off(mmio, OFF);
 386         i810_load_pll(par);
 387         i810_load_vga(par);
 388         i810_load_vgax(par);
 389         i810_dram_off(mmio, ON);
 390         i810_load_2d(par);
 391         i810_hires(mmio);
 392         i810_screen_off(mmio, ON);
 393         i810_protect_regs(mmio, ON);
 394         i810_load_color(par);
 395         i810_load_pitch(par);
 396 }
 397
 398 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
 399                           u8 __iomem *mmio)
 400 {
 401         i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
 402         i810_writeb(CLUT_DATA, mmio, red);
 403         i810_writeb(CLUT_DATA, mmio, green);
 404         i810_writeb(CLUT_DATA, mmio, blue);
 405 }
 406
 407 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
 408                           u8 __iomem *mmio)
 409 {
 410         i810_writeb(CLUT_INDEX_READ, mmio, regno);
 411         *red = i810_readb(CLUT_DATA, mmio);
 412         *green = i810_readb(CLUT_DATA, mmio);
 413         *blue = i810_readb(CLUT_DATA, mmio);
 414 }
 415
 416 /************************************************************
 417  *                   VGA State Restore                      *
 418  ************************************************************/
 419 static void i810_restore_pll(struct i810fb_par *par)
 420 {
 421         u32 tmp1, tmp2;
 422         u8 __iomem *mmio = par->mmio_start_virtual;
 423
 424         tmp1 = par->hw_state.dclk_2d;
 425         tmp2 = i810_readl(DCLK_2D, mmio);
 426         tmp1 &= ~MN_MASK;
 427         tmp2 &= MN_MASK;
 428         i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
 429
 430         tmp1 = par->hw_state.dclk_1d;
 431         tmp2 = i810_readl(DCLK_1D, mmio);
 432         tmp1 &= ~MN_MASK;
 433         tmp2 &= MN_MASK;
 434         i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
 435
 436         i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
 437 }
 438
 439 static void i810_restore_dac(struct i810fb_par *par)
 440 {
 441         u32 tmp1, tmp2;
 442         u8 __iomem *mmio = par->mmio_start_virtual;
 443
 444         tmp1 = par->hw_state.pixconf;
 445         tmp2 = i810_readl(PIXCONF, mmio);
 446         tmp1 &= DAC_BIT;
 447         tmp2 &= ~DAC_BIT;
 448         i810_writel(PIXCONF, mmio, tmp1 | tmp2);
 449 }
 450
 451 static void i810_restore_vgax(struct i810fb_par *par)
 452 {
 453         u8 i, j;
 454         u8 __iomem *mmio = par->mmio_start_virtual;
 455
 456         for (i = 0; i < 4; i++) {
 457                 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
 458                 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
 459         }
 460         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 461         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
 462         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 463         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
 464         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 465         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
 466
 467         /*restore interlace*/
 468         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 469         i = par->hw_state.cr70;
 470         i &= INTERLACE_BIT;
 471         j = i810_readb(CR_DATA_CGA, mmio);
 472         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 473         i810_writeb(CR_DATA_CGA, mmio, j | i);
 474
 475         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 476         i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
 477         i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
 478         i810_writeb(SR_INDEX, mmio, SR01);
 479         i = (par->hw_state.sr01) & ~0xE0 ;
 480         j = i810_readb(SR_DATA, mmio) & 0xE0;
 481         i810_writeb(SR_INDEX, mmio, SR01);
 482         i810_writeb(SR_DATA, mmio, i | j);
 483 }
 484
 485 static void i810_restore_vga(struct i810fb_par *par)
 486 {
 487         u8 i;
 488         u8 __iomem *mmio = par->mmio_start_virtual;
 489
 490         for (i = 0; i < 10; i++) {
 491                 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
 492                 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
 493         }
 494         for (i = 0; i < 8; i++) {
 495                 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
 496                 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
 497         }
 498 }
 499
 500 static void i810_restore_addr_map(struct i810fb_par *par)
 501 {
 502         u8 tmp;
 503         u8 __iomem *mmio = par->mmio_start_virtual;
 504
 505         i810_writeb(GR_INDEX, mmio, GR10);
 506         tmp = i810_readb(GR_DATA, mmio);
 507         tmp &= ADDR_MAP_MASK;
 508         tmp |= par->hw_state.gr10;
 509         i810_writeb(GR_INDEX, mmio, GR10);
 510         i810_writeb(GR_DATA, mmio, tmp);
 511 }
 512
 513 static void i810_restore_2d(struct i810fb_par *par)
 514 {
 515         u32 tmp_long;
 516         u16 tmp_word;
 517         u8 __iomem *mmio = par->mmio_start_virtual;
 518
 519         tmp_word = i810_readw(BLTCNTL, mmio);
 520         tmp_word &= ~(3 << 4);
 521         tmp_word |= par->hw_state.bltcntl;
 522         i810_writew(BLTCNTL, mmio, tmp_word);
 523
 524         i810_dram_off(mmio, OFF);
 525         i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
 526         i810_dram_off(mmio, ON);
 527
 528         tmp_word = i810_readw(HWSTAM, mmio);
 529         tmp_word &= 3 << 13;
 530         tmp_word |= par->hw_state.hwstam;
 531         i810_writew(HWSTAM, mmio, tmp_word);
 532
 533         tmp_long = i810_readl(FW_BLC, mmio);
 534         tmp_long &= FW_BLC_MASK;
 535         tmp_long |= par->hw_state.fw_blc;
 536         i810_writel(FW_BLC, mmio, tmp_long);
 537
 538         i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
 539         i810_writew(IER, mmio, par->hw_state.ier);
 540         i810_writew(IMR, mmio, par->hw_state.imr);
 541         i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
 542 }
 543
 544 static void i810_restore_vga_state(struct i810fb_par *par)
 545 {
 546         u8 __iomem *mmio = par->mmio_start_virtual;
 547
 548         i810_screen_off(mmio, OFF);
 549         i810_protect_regs(mmio, OFF);
 550         i810_dram_off(mmio, OFF);
 551         i810_restore_pll(par);
 552         i810_restore_dac(par);
 553         i810_restore_vga(par);
 554         i810_restore_vgax(par);
 555         i810_restore_addr_map(par);
 556         i810_dram_off(mmio, ON);
 557         i810_restore_2d(par);
 558         i810_screen_off(mmio, ON);
 559         i810_protect_regs(mmio, ON);
 560 }
 561
 562 /***********************************************************************
 563  *                         VGA State Save                              *
 564  ***********************************************************************/
 565
 566 static void i810_save_vgax(struct i810fb_par *par)
 567 {
 568         u8 i;
 569         u8 __iomem *mmio = par->mmio_start_virtual;
 570
 571         for (i = 0; i < 4; i++) {
 572                 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
 573                 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
 574         }
 575         i810_writeb(CR_INDEX_CGA, mmio, CR35);
 576         par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
 577         i810_writeb(CR_INDEX_CGA, mmio, CR39);
 578         par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
 579         i810_writeb(CR_INDEX_CGA, mmio, CR41);
 580         par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
 581         i810_writeb(CR_INDEX_CGA, mmio, CR70);
 582         par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
 583         par->hw_state.msr = i810_readb(MSR_READ, mmio);
 584         i810_writeb(CR_INDEX_CGA, mmio, CR80);
 585         par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
 586         i810_writeb(SR_INDEX, mmio, SR01);
 587         par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
 588 }
 589
 590 static void i810_save_vga(struct i810fb_par *par)
 591 {
 592         u8 i;
 593         u8 __iomem *mmio = par->mmio_start_virtual;
 594
 595         for (i = 0; i < 10; i++) {
 596                 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
 597                 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
 598         }
 599         for (i = 0; i < 8; i++) {
 600                 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
 601                 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
 602         }
 603 }
 604
 605 static void i810_save_2d(struct i810fb_par *par)
 606 {
 607         u8 __iomem *mmio = par->mmio_start_virtual;
 608
 609         par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
 610         par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
 611         par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
 612         par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
 613         par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
 614         par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
 615         par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
 616         par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
 617         par->hw_state.ier = i810_readw(IER, mmio);
 618         par->hw_state.imr = i810_readw(IMR, mmio);
 619         par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
 620 }
 621
 622 static void i810_save_vga_state(struct i810fb_par *par)
 623 {
 624         i810_save_vga(par);
 625         i810_save_vgax(par);
 626         i810_save_2d(par);
 627 }
 628
 629 /************************************************************
 630  *                    Helpers                               *
 631  ************************************************************/
 632 /**
 633  * get_line_length - calculates buffer pitch in bytes
 634  * @par: pointer to i810fb_par structure
 635  * @xres_virtual: virtual resolution of the frame
 636  * @bpp: bits per pixel
 637  *
 638  * DESCRIPTION:
 639  * Calculates buffer pitch in bytes.
 640  */
 641 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
 642 {
 643         u32 length;
 644
 645         length = xres_virtual*bpp;
 646         length = (length+31)&-32;
 647         length >>= 3;
 648         return length;
 649 }
 650
 651 /**
 652  * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
 653  * @freq: target pixelclock in picoseconds
 654  * @m: where to write M register
 655  * @n: where to write N register
 656  * @p: where to write P register
 657  *
 658  * DESCRIPTION:
 659  * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
 660  * Repeatedly computes the Freq until the actual Freq is equal to
 661  * the target Freq or until the loop count is zero.  In the latter
 662  * case, the actual frequency nearest the target will be used.
 663  */
 664 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
 665 {
 666         u32 m_reg, n_reg, p_divisor, n_target_max;
 667         u32 m_target, n_target, p_target, n_best, m_best, mod;
 668         u32 f_out, target_freq, diff = 0, mod_min, diff_min;
 669
 670         diff_min = mod_min = 0xFFFFFFFF;
 671         n_best = m_best = m_target = f_out = 0;
 672
 673         target_freq =  freq;
 674         n_target_max = 30;
 675
 676         /*
 677          * find P such that target freq is 16x reference freq (Hz).
 678          */
 679         p_divisor = 1;
 680         p_target = 0;
 681         while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
 682               p_divisor <= 32) {
 683                 p_divisor <<= 1;
 684                 p_target++;
 685         }
 686
 687         n_reg = m_reg = n_target = 3;
 688         while (diff_min && mod_min && (n_target < n_target_max)) {
 689                 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
 690                 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
 691                 m_target = m_reg;
 692                 n_target = n_reg;
 693                 if (f_out <= target_freq) {
 694                         n_reg++;
 695                         diff = target_freq - f_out;
 696                 } else {
 697                         m_reg++;
 698                         diff = f_out - target_freq;
 699                 }
 700
 701                 if (diff_min > diff) {
 702                         diff_min = diff;
 703                         n_best = n_target;
 704                         m_best = m_target;
 705                 }
 706
 707                 if (!diff && mod_min > mod) {
 708                         mod_min = mod;
 709                         n_best = n_target;
 710                         m_best = m_target;
 711                 }
 712         }
 713         if (m) *m = (m_best - 2) & 0x3FF;
 714         if (n) *n = (n_best - 2) & 0x3FF;
 715         if (p) *p = (p_target << 4);
 716 }
 717
 718 /*************************************************************
 719  *                Hardware Cursor Routines                   *
 720  *************************************************************/
 721
 722 /**
 723  * i810_enable_cursor - show or hide the hardware cursor
 724  * @mmio: address of register space
 725  * @mode: show (1) or hide (0)
 726  *
 727  * Description:
 728  * Shows or hides the hardware cursor
 729  */
 730 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
 731 {
 732         u32 temp;
 733
 734         temp = i810_readl(PIXCONF, mmio);
 735         temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
 736                 temp & ~CURSOR_ENABLE_MASK;
 737
 738         i810_writel(PIXCONF, mmio, temp);
 739 }
 740
 741 static void i810_reset_cursor_image(struct i810fb_par *par)
 742 {
 743         u8 __iomem *addr = par->cursor_heap.virtual;
 744         int i, j;
 745
 746         for (i = 64; i--; ) {
 747                 for (j = 0; j < 8; j++) {
 748                         i810_writeb(j, addr, 0xff);
 749                         i810_writeb(j+8, addr, 0x00);
 750                 }
 751                 addr +=16;
 752         }
 753 }
 754
 755 static void i810_load_cursor_image(int width, int height, u8 *data,
 756                                    struct i810fb_par *par)
 757 {
 758         u8 __iomem *addr = par->cursor_heap.virtual;
 759         int i, j, w = width/8;
 760         int mod = width % 8, t_mask, d_mask;
 761
 762         t_mask = 0xff >> mod;
 763         d_mask = ~(0xff >> mod);
 764         for (i = height; i--; ) {
 765                 for (j = 0; j < w; j++) {
 766                         i810_writeb(j+0, addr, 0x00);
 767                         i810_writeb(j+8, addr, *data++);
 768                 }
 769                 if (mod) {
 770                         i810_writeb(j+0, addr, t_mask);
 771                         i810_writeb(j+8, addr, *data++ & d_mask);
 772                 }
 773                 addr += 16;
 774         }
 775 }
 776
 777 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
 778 {
 779         struct i810fb_par *par = (struct i810fb_par *) info->par;
 780         u8 __iomem *mmio = par->mmio_start_virtual;
 781         u8 red, green, blue, trans, temp;
 782
 783         i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
 784
 785         temp = i810_readb(PIXCONF1, mmio);
 786         i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
 787
 788         i810_write_dac(4, red, green, blue, mmio);
 789
 790         i810_writeb(PIXCONF1, mmio, temp);
 791
 792         i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
 793         temp = i810_readb(PIXCONF1, mmio);
 794         i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
 795
 796         i810_write_dac(5, red, green, blue, mmio);
 797
 798         i810_writeb(PIXCONF1, mmio, temp);
 799 }
 800
 801 /**
 802  * i810_init_cursor - initializes the cursor
 803  * @par: pointer to i810fb_par structure
 804  *
 805  * DESCRIPTION:
 806  * Initializes the cursor registers
 807  */
 808 static void i810_init_cursor(struct i810fb_par *par)
 809 {
 810         u8 __iomem *mmio = par->mmio_start_virtual;
 811
 812         i810_enable_cursor(mmio, OFF);
 813         i810_writel(CURBASE, mmio, par->cursor_heap.physical);
 814         i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
 815 }
 816
 817 /*********************************************************************
 818  *                    Framebuffer hook helpers                       *
 819  *********************************************************************/
 820 /**
 821  * i810_round_off -  Round off values to capability of hardware
 822  * @var: pointer to fb_var_screeninfo structure
 823  *
 824  * DESCRIPTION:
 825  * @var contains user-defined information for the mode to be set.
 826  * This will try modify those values to ones nearest the
 827  * capability of the hardware
 828  */
 829 static void i810_round_off(struct fb_var_screeninfo *var)
 830 {
 831         u32 xres, yres, vxres, vyres;
 832
 833         /*
 834          *  Presently supports only these configurations
 835          */
 836
 837         xres = var->xres;
 838         yres = var->yres;
 839         vxres = var->xres_virtual;
 840         vyres = var->yres_virtual;
 841
 842         var->bits_per_pixel += 7;
 843         var->bits_per_pixel &= ~7;
 844
 845         if (var->bits_per_pixel < 8)
 846                 var->bits_per_pixel = 8;
 847         if (var->bits_per_pixel > 32)
 848                 var->bits_per_pixel = 32;
 849
 850         round_off_xres(&xres);
 851         if (xres < 40)
 852                 xres = 40;
 853         if (xres > 2048)
 854                 xres = 2048;
 855         xres = (xres + 7) & ~7;
 856
 857         if (vxres < xres)
 858                 vxres = xres;
 859
 860         round_off_yres(&xres, &yres);
 861         if (yres < 1)
 862                 yres = 1;
 863         if (yres >= 2048)
 864                 yres = 2048;
 865
 866         if (vyres < yres)
 867                 vyres = yres;
 868
 869         if (var->bits_per_pixel == 32)
 870                 var->accel_flags = 0;
 871
 872         /* round of horizontal timings to nearest 8 pixels */
 873         var->left_margin = (var->left_margin + 4) & ~7;
 874         var->right_margin = (var->right_margin + 4) & ~7;
 875         var->hsync_len = (var->hsync_len + 4) & ~7;
 876
 877         if (var->vmode & FB_VMODE_INTERLACED) {
 878                 if (!((yres + var->upper_margin + var->vsync_len +
 879                        var->lower_margin) & 1))
 880                         var->upper_margin++;
 881         }
 882
 883         var->xres = xres;
 884         var->yres = yres;
 885         var->xres_virtual = vxres;
 886         var->yres_virtual = vyres;
 887 }
 888
 889 /**
 890  * set_color_bitfields - sets rgba fields
 891  * @var: pointer to fb_var_screeninfo
 892  *
 893  * DESCRIPTION:
 894  * The length, offset and ordering  for each color field
 895  * (red, green, blue)  will be set as specified
 896  * by the hardware
 897  */
 898 static void set_color_bitfields(struct fb_var_screeninfo *var)
 899 {
 900         switch (var->bits_per_pixel) {
 901         case 8:
 902                 var->red.offset = 0;
 903                 var->red.length = 8;
 904                 var->green.offset = 0;
 905                 var->green.length = 8;
 906                 var->blue.offset = 0;
 907                 var->blue.length = 8;
 908                 var->transp.offset = 0;
 909                 var->transp.length = 0;
 910                 break;
 911         case 16:
 912                 var->green.length = (var->green.length == 5) ? 5 : 6;
 913                 var->red.length = 5;
 914                 var->blue.length = 5;
 915                 var->transp.length = 6 - var->green.length;
 916                 var->blue.offset = 0;
 917                 var->green.offset = 5;
 918                 var->red.offset = 5 + var->green.length;
 919                 var->transp.offset =  (5 + var->red.offset) & 15;
 920                 break;
 921         case 24:        /* RGB 888   */
 922         case 32:        /* RGBA 8888 */
 923                 var->red.offset = 16;
 924                 var->red.length = 8;
 925                 var->green.offset = 8;
 926                 var->green.length = 8;
 927                 var->blue.offset = 0;
 928                 var->blue.length = 8;
 929                 var->transp.length = var->bits_per_pixel - 24;
 930                 var->transp.offset = (var->transp.length) ? 24 : 0;
 931                 break;
 932         }
 933         var->red.msb_right = 0;
 934         var->green.msb_right = 0;
 935         var->blue.msb_right = 0;
 936         var->transp.msb_right = 0;
 937 }
 938
 939 /**
 940  * i810_check_params - check if contents in var are valid
 941  * @var: pointer to fb_var_screeninfo
 942  * @info: pointer to fb_info
 943  *
 944  * DESCRIPTION:
 945  * This will check if the framebuffer size is sufficient
 946  * for the current mode and if the user's monitor has the
 947  * required specifications to display the current mode.
 948  */
 949 static int i810_check_params(struct fb_var_screeninfo *var,
 950                              struct fb_info *info)
 951 {
 952         struct i810fb_par *par = (struct i810fb_par *) info->par;
 953         int line_length, vidmem, mode_valid = 0;
 954         u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
 955         /*
 956          *  Memory limit
 957          */
 958         line_length = get_line_length(par, vxres, var->bits_per_pixel);
 959         vidmem = line_length*vyres;
 960
 961         if (vidmem > par->fb.size) {
 962                 vyres = par->fb.size/line_length;
 963                 if (vyres < var->yres) {
 964                         vyres = yres;
 965                         vxres = par->fb.size/vyres;
 966                         vxres /= var->bits_per_pixel >> 3;
 967                         line_length = get_line_length(par, vxres,
 968                                                       var->bits_per_pixel);
 969                         vidmem = line_length * yres;
 970                         if (vxres < var->xres) {
 971                                 printk("i810fb: required video memory, "
 972                                        "%d bytes, for %dx%d-%d (virtual) "
 973                                        "is out of range\n",
 974                                        vidmem, vxres, vyres,
 975                                        var->bits_per_pixel);
 976                                 return -ENOMEM;
 977                         }
 978                 }
 979         }
 980
 981         var->xres_virtual = vxres;
 982         var->yres_virtual = vyres;
 983
 984         /*
 985          * Monitor limit
 986          */
 987         switch (var->bits_per_pixel) {
 988         case 8:
 989                 info->monspecs.dclkmax = 234000000;
 990                 break;
 991         case 16:
 992                 info->monspecs.dclkmax = 229000000;
 993                 break;
 994         case 24:
 995         case 32:
 996                 info->monspecs.dclkmax = 204000000;
 997                 break;
 998         }
 999
1000         info->monspecs.dclkmin = 15000000;
1001
1002         if (!fb_validate_mode(var, info))
1003                 mode_valid = 1;
1004
1005 #ifdef CONFIG_FB_I810_I2C
1006         if (!mode_valid && info->monspecs.gtf &&
1007             !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1008                 mode_valid = 1;
1009
1010         if (!mode_valid && info->monspecs.modedb_len) {
1011                 struct fb_videomode *mode;
1012
1013                 mode = fb_find_best_mode(var, &info->modelist);
1014                 if (mode) {
1015                         fb_videomode_to_var(var, mode);
1016                         mode_valid = 1;
1017                 }
1018         }
1019 #endif
1020         if (!mode_valid && info->monspecs.modedb_len == 0) {
1021                 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1022                         int default_sync = (info->monspecs.hfmin-HFMIN)
1023                                 |(info->monspecs.hfmax-HFMAX)
1024                                 |(info->monspecs.vfmin-VFMIN)
1025                                 |(info->monspecs.vfmax-VFMAX);
1026                         printk("i810fb: invalid video mode%s\n",
1027                                default_sync ? "" : ". Specifying "
1028                                "vsyncN/hsyncN parameters may help");
1029                 }
1030         }
1031
1032         return 0;
1033 }
1034
1035 /**
1036  * encode_fix - fill up fb_fix_screeninfo structure
1037  * @fix: pointer to fb_fix_screeninfo
1038  * @info: pointer to fb_info
1039  *
1040  * DESCRIPTION:
1041  * This will set up parameters that are unmodifiable by the user.
1042  */
1043 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1044 {
1045         struct i810fb_par *par = (struct i810fb_par *) info->par;
1046
1047         memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1048
1049         strcpy(fix->id, "I810");
1050         fix->smem_start = par->fb.physical;
1051         fix->smem_len = par->fb.size;
1052         fix->type = FB_TYPE_PACKED_PIXELS;
1053         fix->type_aux = 0;
1054         fix->xpanstep = 8;
1055         fix->ypanstep = 1;
1056
1057         switch (info->var.bits_per_pixel) {
1058         case 8:
1059                 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1060                 break;
1061         case 16:
1062         case 24:
1063         case 32:
1064                 if (info->var.nonstd)
1065                         fix->visual = FB_VISUAL_DIRECTCOLOR;
1066                 else
1067                         fix->visual = FB_VISUAL_TRUECOLOR;
1068                 break;
1069         default:
1070                 return -EINVAL;
1071         }
1072         fix->ywrapstep = 0;
1073         fix->line_length = par->pitch;
1074         fix->mmio_start = par->mmio_start_phys;
1075         fix->mmio_len = MMIO_SIZE;
1076         fix->accel = FB_ACCEL_I810;
1077
1078         return 0;
1079 }
1080
1081 /**
1082  * decode_var - modify par according to contents of var
1083  * @var: pointer to fb_var_screeninfo
1084  * @par: pointer to i810fb_par
1085  *
1086  * DESCRIPTION:
1087  * Based on the contents of @var, @par will be dynamically filled up.
1088  * @par contains all information necessary to modify the hardware.
1089 */
1090 static void decode_var(const struct fb_var_screeninfo *var,
1091                        struct i810fb_par *par)
1092 {
1093         u32 xres, yres, vxres, vyres;
1094
1095         xres = var->xres;
1096         yres = var->yres;
1097         vxres = var->xres_virtual;
1098         vyres = var->yres_virtual;
1099
1100         switch (var->bits_per_pixel) {
1101         case 8:
1102                 par->pixconf = PIXCONF8;
1103                 par->bltcntl = 0;
1104                 par->depth = 1;
1105                 par->blit_bpp = BPP8;
1106                 break;
1107         case 16:
1108                 if (var->green.length == 5)
1109                         par->pixconf = PIXCONF15;
1110                 else
1111                         par->pixconf = PIXCONF16;
1112                 par->bltcntl = 16;
1113                 par->depth = 2;
1114                 par->blit_bpp = BPP16;
1115                 break;
1116         case 24:
1117                 par->pixconf = PIXCONF24;
1118                 par->bltcntl = 32;
1119                 par->depth = 3;
1120                 par->blit_bpp = BPP24;
1121                 break;
1122         case 32:
1123                 par->pixconf = PIXCONF32;
1124                 par->bltcntl = 0;
1125                 par->depth = 4;
1126                 par->blit_bpp = 3 << 24;
1127                 break;
1128         }
1129         if (var->nonstd && var->bits_per_pixel != 8)
1130                 par->pixconf |= 1 << 27;
1131
1132         i810_calc_dclk(var->pixclock, &par->regs.M,
1133                        &par->regs.N, &par->regs.P);
1134         i810fb_encode_registers(var, par, xres, yres);
1135
1136         par->watermark = i810_get_watermark(var, par);
1137         par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1138 }
1139
1140 /**
1141  * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1142  * @regno: DAC index
1143  * @red: red
1144  * @green: green
1145  * @blue: blue
1146  * @transp: transparency (alpha)
1147  * @info: pointer to fb_info
1148  *
1149  * DESCRIPTION:
1150  * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1151  * and writes them to @red, @green and @blue respectively
1152  */
1153 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1154                             u8 *transp, struct fb_info *info)
1155 {
1156         struct i810fb_par *par = (struct i810fb_par *) info->par;
1157         u8 __iomem *mmio = par->mmio_start_virtual;
1158         u8 temp;
1159
1160         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1161                 if ((info->var.green.length == 5 && regno > 31) ||
1162                     (info->var.green.length == 6 && regno > 63))
1163                         return 1;
1164         }
1165
1166         temp = i810_readb(PIXCONF1, mmio);
1167         i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1168
1169         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1170             info->var.green.length == 5)
1171                 i810_read_dac(regno * 8, red, green, blue, mmio);
1172
1173         else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1174                  info->var.green.length == 6) {
1175                 u8 tmp;
1176
1177                 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1178                 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1179         }
1180         else
1181                 i810_read_dac(regno, red, green, blue, mmio);
1182
1183         *transp = 0;
1184         i810_writeb(PIXCONF1, mmio, temp);
1185
1186         return 0;
1187 }
1188
1189 /******************************************************************
1190  *           Framebuffer device-specific hooks                    *
1191  ******************************************************************/
1192
1193 static int i810fb_open(struct fb_info *info, int user)
1194 {
1195         struct i810fb_par *par = (struct i810fb_par *) info->par;
1196         u32 count = atomic_read(&par->use_count);
1197
1198         if (count == 0) {
1199                 memset(&par->state, 0, sizeof(struct vgastate));
1200                 par->state.flags = VGA_SAVE_CMAP;
1201                 par->state.vgabase = par->mmio_start_virtual;
1202                 save_vga(&par->state);
1203
1204                 i810_save_vga_state(par);
1205         }
1206
1207         atomic_inc(&par->use_count);
1208
1209         return 0;
1210 }
1211
1212 static int i810fb_release(struct fb_info *info, int user)
1213 {
1214         struct i810fb_par *par = (struct i810fb_par *) info->par;
1215         u32 count;
1216
1217         count = atomic_read(&par->use_count);
1218         if (count == 0)
1219                 return -EINVAL;
1220
1221         if (count == 1) {
1222                 i810_restore_vga_state(par);
1223                 restore_vga(&par->state);
1224         }
1225
1226         atomic_dec(&par->use_count);
1227
1228         return 0;
1229 }
1230
1231
1232 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1233                             unsigned blue, unsigned transp,
1234                             struct fb_info *info)
1235 {
1236         struct i810fb_par *par = (struct i810fb_par *) info->par;
1237         u8 __iomem *mmio = par->mmio_start_virtual;
1238         u8 temp;
1239         int i;
1240
1241         if (regno > 255) return 1;
1242
1243         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1244                 if ((info->var.green.length == 5 && regno > 31) ||
1245                     (info->var.green.length == 6 && regno > 63))
1246                         return 1;
1247         }
1248
1249         if (info->var.grayscale)
1250                 red = green = blue = (19595 * red + 38470 * green +
1251                                       7471 * blue) >> 16;
1252
1253         temp = i810_readb(PIXCONF1, mmio);
1254         i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1255
1256         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1257             info->var.green.length == 5) {
1258                 for (i = 0; i < 8; i++)
1259                         i810_write_dac((u8) (regno * 8) + i, (u8) red,
1260                                        (u8) green, (u8) blue, mmio);
1261         } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1262                  info->var.green.length == 6) {
1263                 u8 r, g, b;
1264
1265                 if (regno < 32) {
1266                         for (i = 0; i < 8; i++)
1267                                 i810_write_dac((u8) (regno * 8) + i,
1268                                                (u8) red, (u8) green,
1269                                                (u8) blue, mmio);
1270                 }
1271                 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1272                 for (i = 0; i < 4; i++)
1273                         i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1274                                        b, mmio);
1275         } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1276                 i810_write_dac((u8) regno, (u8) red, (u8) green,
1277                                (u8) blue, mmio);
1278         }
1279
1280         i810_writeb(PIXCONF1, mmio, temp);
1281
1282         if (regno < 16) {
1283                 switch (info->var.bits_per_pixel) {
1284                 case 16:
1285                         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1286                                 if (info->var.green.length == 5)
1287                                         ((u32 *)info->pseudo_palette)[regno] =
1288                                                 (regno << 10) | (regno << 5) |
1289                                                 regno;
1290                                 else
1291                                         ((u32 *)info->pseudo_palette)[regno] =
1292                                                 (regno << 11) | (regno << 5) |
1293                                                 regno;
1294                         } else {
1295                                 if (info->var.green.length == 5) {
1296                                         /* RGB 555 */
1297                                         ((u32 *)info->pseudo_palette)[regno] =
1298                                                 ((red & 0xf800) >> 1) |
1299                                                 ((green & 0xf800) >> 6) |
1300                                                 ((blue & 0xf800) >> 11);
1301                                 } else {
1302                                         /* RGB 565 */
1303                                         ((u32 *)info->pseudo_palette)[regno] =
1304                                                 (red & 0xf800) |
1305                                                 ((green & 0xf800) >> 5) |
1306                                                 ((blue & 0xf800) >> 11);
1307                                 }
1308                         }
1309                         break;
1310                 case 24:        /* RGB 888 */
1311                 case 32:        /* RGBA 8888 */
1312                         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1313                                 ((u32 *)info->pseudo_palette)[regno] =
1314                                         (regno << 16) | (regno << 8) |
1315                                         regno;
1316                         else
1317                                 ((u32 *)info->pseudo_palette)[regno] =
1318                                         ((red & 0xff00) << 8) |
1319                                         (green & 0xff00) |
1320                                         ((blue & 0xff00) >> 8);
1321                         break;
1322                 }
1323         }
1324         return 0;
1325 }
1326
1327 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1328                               struct fb_info *info)
1329 {
1330         struct i810fb_par *par = (struct i810fb_par *) info->par;
1331         u32 total;
1332
1333         total = var->xoffset * par->depth +
1334                 var->yoffset * info->fix.line_length;
1335         i810fb_load_front(total, info);
1336
1337         return 0;
1338 }
1339
1340 static int i810fb_blank (int blank_mode, struct fb_info *info)
1341 {
1342         struct i810fb_par *par = (struct i810fb_par *) info->par;
1343         u8 __iomem *mmio = par->mmio_start_virtual;
1344         int mode = 0, pwr, scr_off = 0;
1345
1346         pwr = i810_readl(PWR_CLKC, mmio);
1347
1348         switch (blank_mode) {
1349         case FB_BLANK_UNBLANK:
1350                 mode = POWERON;
1351                 pwr |= 1;
1352                 scr_off = ON;
1353                 break;
1354         case FB_BLANK_NORMAL:
1355                 mode = POWERON;
1356                 pwr |= 1;
1357                 scr_off = OFF;
1358                 break;
1359         case FB_BLANK_VSYNC_SUSPEND:
1360                 mode = STANDBY;
1361                 pwr |= 1;
1362                 scr_off = OFF;
1363                 break;
1364         case FB_BLANK_HSYNC_SUSPEND:
1365                 mode = SUSPEND;
1366                 pwr |= 1;
1367                 scr_off = OFF;
1368                 break;
1369         case FB_BLANK_POWERDOWN:
1370                 mode = POWERDOWN;
1371                 pwr &= ~1;
1372                 scr_off = OFF;
1373                 break;
1374         default:
1375                 return -EINVAL;
1376         }
1377
1378         i810_screen_off(mmio, scr_off);
1379         i810_writel(HVSYNC, mmio, mode);
1380         i810_writel(PWR_CLKC, mmio, pwr);
1381
1382         return 0;
1383 }
1384
1385 static int i810fb_set_par(struct fb_info *info)
1386 {
1387         struct i810fb_par *par = (struct i810fb_par *) info->par;
1388
1389         decode_var(&info->var, par);
1390         i810_load_regs(par);
1391         i810_init_cursor(par);
1392         encode_fix(&info->fix, info);
1393
1394         if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1395                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1396                 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1397                 FBINFO_HWACCEL_IMAGEBLIT;
1398                 info->pixmap.scan_align = 2;
1399         } else {
1400                 info->pixmap.scan_align = 1;
1401                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1402         }
1403         return 0;
1404 }
1405
1406 static int i810fb_check_var(struct fb_var_screeninfo *var,
1407                             struct fb_info *info)
1408 {
1409         int err;
1410
1411         if (IS_DVT) {
1412                 var->vmode &= ~FB_VMODE_MASK;
1413                 var->vmode |= FB_VMODE_NONINTERLACED;
1414         }
1415         if (var->vmode & FB_VMODE_DOUBLE) {
1416                 var->vmode &= ~FB_VMODE_MASK;
1417                 var->vmode |= FB_VMODE_NONINTERLACED;
1418         }
1419
1420         i810_round_off(var);
1421         if ((err = i810_check_params(var, info)))
1422                 return err;
1423
1424         i810fb_fill_var_timings(var);
1425         set_color_bitfields(var);
1426         return 0;
1427 }
1428
1429 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1430 {
1431         struct i810fb_par *par = (struct i810fb_par *)info->par;
1432         u8 __iomem *mmio = par->mmio_start_virtual;
1433
1434         if (!par->dev_flags & LOCKUP)
1435                 return -ENXIO;
1436
1437         if (cursor->image.width > 64 || cursor->image.height > 64)
1438                 return -ENXIO;
1439
1440         if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1441                 i810_init_cursor(par);
1442                 cursor->set |= FB_CUR_SETALL;
1443         }
1444
1445         i810_enable_cursor(mmio, OFF);
1446
1447         if (cursor->set & FB_CUR_SETPOS) {
1448                 u32 tmp;
1449
1450                 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1451                 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1452                 i810_writel(CURPOS, mmio, tmp);
1453         }
1454
1455         if (cursor->set & FB_CUR_SETSIZE)
1456                 i810_reset_cursor_image(par);
1457
1458         if (cursor->set & FB_CUR_SETCMAP)
1459                 i810_load_cursor_colors(cursor->image.fg_color,
1460                                         cursor->image.bg_color,
1461                                         info);
1462
1463         if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1464                 int size = ((cursor->image.width + 7) >> 3) *
1465                         cursor->image.height;
1466                 int i;
1467                 u8 *data = kmalloc(64 * 8, GFP_KERNEL);
1468
1469                 if (data == NULL)
1470                         return -ENOMEM;
1471
1472                 switch (cursor->rop) {
1473                 case ROP_XOR:
1474                         for (i = 0; i < size; i++)
1475                                 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1476                         break;
1477                 case ROP_COPY:
1478                 default:
1479                         for (i = 0; i < size; i++)
1480                                 data[i] = cursor->image.data[i] & cursor->mask[i];
1481                         break;
1482                 }
1483
1484                 i810_load_cursor_image(cursor->image.width,
1485                                        cursor->image.height, data,
1486                                        par);
1487                 kfree(data);
1488         }
1489
1490         if (cursor->enable)
1491                 i810_enable_cursor(mmio, ON);
1492
1493         return 0;
1494 }
1495
1496 static struct fb_ops i810fb_ops __devinitdata = {
1497         .owner =             THIS_MODULE,
1498         .fb_open =           i810fb_open,
1499         .fb_release =        i810fb_release,
1500         .fb_check_var =      i810fb_check_var,
1501         .fb_set_par =        i810fb_set_par,
1502         .fb_setcolreg =      i810fb_setcolreg,
1503         .fb_blank =          i810fb_blank,
1504         .fb_pan_display =    i810fb_pan_display,
1505         .fb_fillrect =       i810fb_fillrect,
1506         .fb_copyarea =       i810fb_copyarea,
1507         .fb_imageblit =      i810fb_imageblit,
1508         .fb_cursor =         i810fb_cursor,
1509         .fb_sync =           i810fb_sync,
1510 };
1511
1512 /***********************************************************************
1513  *                         Power Management                            *
1514  ***********************************************************************/
1515 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state)
1516 {
1517         struct fb_info *info = pci_get_drvdata(dev);
1518         struct i810fb_par *par = (struct i810fb_par *) info->par;
1519         int blank = 0, prev_state = par->cur_state;
1520
1521         if (state.event == prev_state)
1522                 return 0;
1523
1524         par->cur_state = state.event;
1525
1526         switch (state.event) {
1527         case 1:
1528                 blank = VESA_VSYNC_SUSPEND;
1529                 break;
1530         case 2:
1531                 blank = VESA_HSYNC_SUSPEND;
1532                 break;
1533         case 3:
1534                 blank = VESA_POWERDOWN;
1535                 break;
1536         default:
1537                 return -EINVAL;
1538         }
1539         info->fbops->fb_blank(blank, info);
1540
1541         if (!prev_state) {
1542                 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1543                 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1544                 pci_disable_device(dev);
1545         }
1546         pci_save_state(dev);
1547         pci_set_power_state(dev, pci_choose_state(dev, state));
1548
1549         return 0;
1550 }
1551
1552 static int i810fb_resume(struct pci_dev *dev)
1553 {
1554         struct fb_info *info = pci_get_drvdata(dev);
1555         struct i810fb_par *par = (struct i810fb_par *) info->par;
1556
1557         if (par->cur_state == 0)
1558                 return 0;
1559
1560         pci_restore_state(dev);
1561         pci_set_power_state(dev, PCI_D0);
1562         pci_enable_device(dev);
1563         agp_bind_memory(par->i810_gtt.i810_fb_memory,
1564                         par->fb.offset);
1565         agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1566                         par->cursor_heap.offset);
1567
1568         info->fbops->fb_blank(VESA_NO_BLANKING, info);
1569
1570         par->cur_state = 0;
1571
1572         return 0;
1573 }
1574 /***********************************************************************
1575  *                  AGP resource allocation                            *
1576  ***********************************************************************/
1577
1578 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1579 {
1580         par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1581         par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1582         par->iring.physical = par->aperture.physical +
1583                 (par->iring.offset << 12);
1584         par->iring.virtual = par->aperture.virtual +
1585                 (par->iring.offset << 12);
1586         par->cursor_heap.virtual = par->aperture.virtual+
1587                 (par->cursor_heap.offset << 12);
1588 }
1589
1590 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1591 {
1592         if (vram + 1 > par->aperture.size >> 20)
1593                 vram = (par->aperture.size >> 20) - 1;
1594         if (v_offset_default > (par->aperture.size >> 20))
1595                 v_offset_default = (par->aperture.size >> 20);
1596         if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1597                 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1598
1599         par->fb.size = vram << 20;
1600         par->fb.offset = v_offset_default << 20;
1601         par->fb.offset >>= 12;
1602
1603         par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1604         par->iring.size = RINGBUFFER_SIZE;
1605
1606         par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1607         par->cursor_heap.size = 4096;
1608 }
1609
1610 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1611 {
1612         struct i810fb_par *par = (struct i810fb_par *) info->par;
1613         int size;
1614         struct agp_bridge_data *bridge;
1615
1616         i810_fix_offsets(par);
1617         size = par->fb.size + par->iring.size;
1618
1619         if (!(bridge = agp_backend_acquire(par->dev))) {
1620                 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1621                 return -ENODEV;
1622         }
1623         if (!(par->i810_gtt.i810_fb_memory =
1624               agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1625                 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1626                        "memory\n");
1627                 agp_backend_release(bridge);
1628                 return -ENOMEM;
1629         }
1630         if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1631                             par->fb.offset)) {
1632                 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1633                 agp_backend_release(bridge);
1634                 return -EBUSY;
1635         }
1636
1637         if (!(par->i810_gtt.i810_cursor_memory =
1638               agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1639                                   AGP_PHYSICAL_MEMORY))) {
1640                 printk("i810fb_alloc_cursormem:  can't allocate"
1641                        "cursor memory\n");
1642                 agp_backend_release(bridge);
1643                 return -ENOMEM;
1644         }
1645         if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1646                             par->cursor_heap.offset)) {
1647                 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1648                 agp_backend_release(bridge);
1649                 return -EBUSY;
1650         }
1651
1652         par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1653
1654         i810_fix_pointers(par);
1655
1656         agp_backend_release(bridge);
1657
1658         return 0;
1659 }
1660
1661 /***************************************************************
1662  *                    Initialization                           *
1663  ***************************************************************/
1664
1665 /**
1666  * i810_init_monspecs
1667  * @info: pointer to device specific info structure
1668  *
1669  * DESCRIPTION:
1670  * Sets the the user monitor's horizontal and vertical
1671  * frequency limits
1672  */
1673 static void __devinit i810_init_monspecs(struct fb_info *info)
1674 {
1675         if (!hsync1)
1676                 hsync1 = HFMIN;
1677         if (!hsync2)
1678                 hsync2 = HFMAX;
1679         if (!info->monspecs.hfmax)
1680                 info->monspecs.hfmax = hsync2;
1681         if (!info->monspecs.hfmin)
1682                 info->monspecs.hfmin = hsync1;
1683         if (hsync2 < hsync1)
1684                 info->monspecs.hfmin = hsync2;
1685
1686         if (!vsync1)
1687                 vsync1 = VFMIN;
1688         if (!vsync2)
1689                 vsync2 = VFMAX;
1690         if (IS_DVT && vsync1 < 60)
1691                 vsync1 = 60;
1692         if (!info->monspecs.vfmax)
1693                 info->monspecs.vfmax = vsync2;
1694         if (!info->monspecs.vfmin)
1695                 info->monspecs.vfmin = vsync1;
1696         if (vsync2 < vsync1)
1697                 info->monspecs.vfmin = vsync2;
1698 }
1699
1700 /**
1701  * i810_init_defaults - initializes default values to use
1702  * @par: pointer to i810fb_par structure
1703  * @info: pointer to current fb_info structure
1704  */
1705 static void __devinit i810_init_defaults(struct i810fb_par *par,
1706                                       struct fb_info *info)
1707 {
1708         if (voffset)
1709                 v_offset_default = voffset;
1710         else if (par->aperture.size > 32 * 1024 * 1024)
1711                 v_offset_default = 16;
1712         else
1713                 v_offset_default = 8;
1714
1715         if (!vram)
1716                 vram = 1;
1717
1718         if (accel)
1719                 par->dev_flags |= HAS_ACCELERATION;
1720
1721         if (sync)
1722                 par->dev_flags |= ALWAYS_SYNC;
1723
1724         if (bpp < 8)
1725                 bpp = 8;
1726
1727         if (!vyres)
1728                 vyres = (vram << 20)/(xres*bpp >> 3);
1729
1730         par->i810fb_ops = i810fb_ops;
1731         info->var.xres = xres;
1732         info->var.yres = yres;
1733         info->var.yres_virtual = vyres;
1734         info->var.bits_per_pixel = bpp;
1735
1736         if (dcolor)
1737                 info->var.nonstd = 1;
1738
1739         if (par->dev_flags & HAS_ACCELERATION)
1740                 info->var.accel_flags = 1;
1741
1742         i810_init_monspecs(info);
1743 }
1744
1745 /**
1746  * i810_init_device - initialize device
1747  * @par: pointer to i810fb_par structure
1748  */
1749 static void __devinit i810_init_device(struct i810fb_par *par)
1750 {
1751         u8 reg;
1752         u8 __iomem *mmio = par->mmio_start_virtual;
1753
1754         if (mtrr) set_mtrr(par);
1755
1756         i810_init_cursor(par);
1757
1758         /* mvo: enable external vga-connector (for laptops) */
1759         if (ext_vga) {
1760                 i810_writel(HVSYNC, mmio, 0);
1761                 i810_writel(PWR_CLKC, mmio, 3);
1762         }
1763
1764         pci_read_config_byte(par->dev, 0x50, &reg);
1765         reg &= FREQ_MASK;
1766         par->mem_freq = (reg) ? 133 : 100;
1767
1768 }
1769
1770 static int __devinit
1771 i810_allocate_pci_resource(struct i810fb_par *par,
1772                            const struct pci_device_id *entry)
1773 {
1774         int err;
1775
1776         if ((err = pci_enable_device(par->dev))) {
1777                 printk("i810fb_init: cannot enable device\n");
1778                 return err;
1779         }
1780         par->res_flags |= PCI_DEVICE_ENABLED;
1781
1782         if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1783                 par->aperture.physical = pci_resource_start(par->dev, 0);
1784                 par->aperture.size = pci_resource_len(par->dev, 0);
1785                 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1786         } else {
1787                 par->aperture.physical = pci_resource_start(par->dev, 1);
1788                 par->aperture.size = pci_resource_len(par->dev, 1);
1789                 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1790         }
1791         if (!par->aperture.size) {
1792                 printk("i810fb_init: device is disabled\n");
1793                 return -ENOMEM;
1794         }
1795
1796         if (!request_mem_region(par->aperture.physical,
1797                                 par->aperture.size,
1798                                 i810_pci_list[entry->driver_data])) {
1799                 printk("i810fb_init: cannot request framebuffer region\n");
1800                 return -ENODEV;
1801         }
1802         par->res_flags |= FRAMEBUFFER_REQ;
1803
1804         par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1805                                         par->aperture.size);
1806         if (!par->aperture.virtual) {
1807                 printk("i810fb_init: cannot remap framebuffer region\n");
1808                 return -ENODEV;
1809         }
1810
1811         if (!request_mem_region(par->mmio_start_phys,
1812                                 MMIO_SIZE,
1813                                 i810_pci_list[entry->driver_data])) {
1814                 printk("i810fb_init: cannot request mmio region\n");
1815                 return -ENODEV;
1816         }
1817         par->res_flags |= MMIO_REQ;
1818
1819         par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1820                                                   MMIO_SIZE);
1821         if (!par->mmio_start_virtual) {
1822                 printk("i810fb_init: cannot remap mmio region\n");
1823                 return -ENODEV;
1824         }
1825
1826         return 0;
1827 }
1828
1829 static void __devinit i810fb_find_init_mode(struct fb_info *info)
1830 {
1831         struct fb_videomode mode;
1832         struct fb_var_screeninfo var;
1833         struct fb_monspecs *specs = NULL;
1834         int found = 0;
1835 #ifdef CONFIG_FB_I810_I2C
1836         int i;
1837         int err;
1838         struct i810fb_par *par = info->par;
1839 #endif
1840
1841         INIT_LIST_HEAD(&info->modelist);
1842         memset(&mode, 0, sizeof(struct fb_videomode));
1843         var = info->var;
1844 #ifdef CONFIG_FB_I810_I2C
1845         i810_create_i2c_busses(par);
1846
1847         for (i = 0; i < 3; i++) {
1848                 err = i810_probe_i2c_connector(info, &par->edid, i+1);
1849                 if (!err)
1850                         break;
1851         }
1852
1853         if (!err)
1854                 printk("i810fb_init_pci: DDC probe successful\n");
1855
1856         fb_edid_to_monspecs(par->edid, &info->monspecs);
1857
1858         if (info->monspecs.modedb == NULL)
1859                 printk("i810fb_init_pci: Unable to get Mode Database\n");
1860
1861         specs = &info->monspecs;
1862         fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
1863                                  &info->modelist);
1864         if (specs->modedb != NULL) {
1865                 if (specs->misc & FB_MISC_1ST_DETAIL) {
1866                         for (i = 0; i < specs->modedb_len; i++) {
1867                                 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1868                                         mode = specs->modedb[i];
1869                                         found = 1;
1870                                         break;
1871                                 }
1872                         }
1873                 }
1874
1875                 if (!found) {
1876                         mode = specs->modedb[0];
1877                         found = 1;
1878                 }
1879
1880                 fb_videomode_to_var(&var, &mode);
1881         }
1882 #endif
1883         if (mode_option)
1884                 fb_find_mode(&var, info, mode_option, specs->modedb,
1885                              specs->modedb_len, (found) ? &mode : NULL,
1886                              info->var.bits_per_pixel);
1887
1888         info->var = var;
1889         fb_destroy_modedb(specs->modedb);
1890         specs->modedb = NULL;
1891 }
1892
1893 #ifndef MODULE
1894 static int __devinit i810fb_setup(char *options)
1895 {
1896         char *this_opt, *suffix = NULL;
1897
1898         if (!options || !*options)
1899                 return 0;
1900
1901         while ((this_opt = strsep(&options, ",")) != NULL) {
1902                 if (!strncmp(this_opt, "mtrr", 4))
1903                         mtrr = 1;
1904                 else if (!strncmp(this_opt, "accel", 5))
1905                         accel = 1;
1906                 else if (!strncmp(this_opt, "ext_vga", 7))
1907                         ext_vga = 1;
1908                 else if (!strncmp(this_opt, "sync", 4))
1909                         sync = 1;
1910                 else if (!strncmp(this_opt, "vram:", 5))
1911                         vram = (simple_strtoul(this_opt+5, NULL, 0));
1912                 else if (!strncmp(this_opt, "voffset:", 8))
1913                         voffset = (simple_strtoul(this_opt+8, NULL, 0));
1914                 else if (!strncmp(this_opt, "xres:", 5))
1915                         xres = simple_strtoul(this_opt+5, NULL, 0);
1916                 else if (!strncmp(this_opt, "yres:", 5))
1917                         yres = simple_strtoul(this_opt+5, NULL, 0);
1918                 else if (!strncmp(this_opt, "vyres:", 6))
1919                         vyres = simple_strtoul(this_opt+6, NULL, 0);
1920                 else if (!strncmp(this_opt, "bpp:", 4))
1921                         bpp = simple_strtoul(this_opt+4, NULL, 0);
1922                 else if (!strncmp(this_opt, "hsync1:", 7)) {
1923                         hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1924                         if (strncmp(suffix, "H", 1))
1925                                 hsync1 *= 1000;
1926                 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1927                         hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1928                         if (strncmp(suffix, "H", 1))
1929                                 hsync2 *= 1000;
1930                 } else if (!strncmp(this_opt, "vsync1:", 7))
1931                         vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1932                 else if (!strncmp(this_opt, "vsync2:", 7))
1933                         vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1934                 else if (!strncmp(this_opt, "dcolor", 6))
1935                         dcolor = 1;
1936                 else
1937                         mode_option = this_opt;
1938         }
1939         return 0;
1940 }
1941 #endif
1942
1943 static int __devinit i810fb_init_pci (struct pci_dev *dev,
1944                                    const struct pci_device_id *entry)
1945 {
1946         struct fb_info    *info;
1947         struct i810fb_par *par = NULL;
1948         struct fb_videomode mode;
1949         int i, err = -1, vfreq, hfreq, pixclock;
1950
1951         i = 0;
1952
1953         info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
1954         if (!info)
1955                 return -ENOMEM;
1956
1957         par = info->par;
1958         par->dev = dev;
1959
1960         if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) {
1961                 i810fb_release_resource(info, par);
1962                 return -ENOMEM;
1963         }
1964         memset(info->pixmap.addr, 0, 8*1024);
1965         info->pixmap.size = 8*1024;
1966         info->pixmap.buf_align = 8;
1967         info->pixmap.access_align = 32;
1968         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1969
1970         if ((err = i810_allocate_pci_resource(par, entry))) {
1971                 i810fb_release_resource(info, par);
1972                 return err;
1973         }
1974
1975         i810_init_defaults(par, info);
1976
1977         if ((err = i810_alloc_agp_mem(info))) {
1978                 i810fb_release_resource(info, par);
1979                 return err;
1980         }
1981
1982         i810_init_device(par);
1983
1984         info->screen_base = par->fb.virtual;
1985         info->fbops = &par->i810fb_ops;
1986         info->pseudo_palette = par->pseudo_palette;
1987         fb_alloc_cmap(&info->cmap, 256, 0);
1988         i810fb_find_init_mode(info);
1989
1990         if ((err = info->fbops->fb_check_var(&info->var, info))) {
1991                 i810fb_release_resource(info, par);
1992                 return err;
1993         }
1994
1995         fb_var_to_videomode(&mode, &info->var);
1996         fb_add_videomode(&mode, &info->modelist);
1997         encode_fix(&info->fix, info);
1998
1999         i810fb_init_ringbuffer(info);
2000         err = register_framebuffer(info);
2001
2002         if (err < 0) {
2003                 i810fb_release_resource(info, par);
2004                 printk("i810fb_init: cannot register framebuffer device\n");
2005                 return err;
2006         }
2007
2008         pci_set_drvdata(dev, info);
2009         pixclock = 1000000000/(info->var.pixclock);
2010         pixclock *= 1000;
2011         hfreq = pixclock/(info->var.xres + info->var.left_margin +
2012                           info->var.hsync_len + info->var.right_margin);
2013         vfreq = hfreq/(info->var.yres + info->var.upper_margin +
2014                        info->var.vsync_len + info->var.lower_margin);
2015
2016         printk("I810FB: fb%d         : %s v%d.%d.%d%s\n"
2017                "I810FB: Video RAM   : %dK\n"
2018                "I810FB: Monitor     : H: %d-%d KHz V: %d-%d Hz\n"
2019                "I810FB: Mode        : %dx%d-%dbpp@%dHz\n",
2020                info->node,
2021                i810_pci_list[entry->driver_data],
2022                VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
2023                (int) par->fb.size>>10, info->monspecs.hfmin/1000,
2024                info->monspecs.hfmax/1000, info->monspecs.vfmin,
2025                info->monspecs.vfmax, info->var.xres,
2026                info->var.yres, info->var.bits_per_pixel, vfreq);
2027         return 0;
2028 }
2029
2030 /***************************************************************
2031  *                     De-initialization                        *
2032  ***************************************************************/
2033
2034 static void i810fb_release_resource(struct fb_info *info,
2035                                     struct i810fb_par *par)
2036 {
2037         struct gtt_data *gtt = &par->i810_gtt;
2038         unset_mtrr(par);
2039
2040         i810_delete_i2c_busses(par);
2041
2042         if (par->i810_gtt.i810_cursor_memory)
2043                 agp_free_memory(gtt->i810_cursor_memory);
2044         if (par->i810_gtt.i810_fb_memory)
2045                 agp_free_memory(gtt->i810_fb_memory);
2046
2047         if (par->mmio_start_virtual)
2048                 iounmap(par->mmio_start_virtual);
2049         if (par->aperture.virtual)
2050                 iounmap(par->aperture.virtual);
2051         if (par->edid)
2052                 kfree(par->edid);
2053         if (par->res_flags & FRAMEBUFFER_REQ)
2054                 release_mem_region(par->aperture.physical,
2055                                    par->aperture.size);
2056         if (par->res_flags & MMIO_REQ)
2057                 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
2058
2059         if (par->res_flags & PCI_DEVICE_ENABLED)
2060                 pci_disable_device(par->dev);
2061
2062         framebuffer_release(info);
2063
2064 }
2065
2066 static void __exit i810fb_remove_pci(struct pci_dev *dev)
2067 {
2068         struct fb_info *info = pci_get_drvdata(dev);
2069         struct i810fb_par *par = (struct i810fb_par *) info->par;
2070
2071         unregister_framebuffer(info);
2072         i810fb_release_resource(info, par);
2073         pci_set_drvdata(dev, NULL);
2074         printk("cleanup_module:  unloaded i810 framebuffer device\n");
2075 }
2076
2077 #ifndef MODULE
2078 static int __devinit i810fb_init(void)
2079 {
2080         char *option = NULL;
2081
2082         if (fb_get_options("i810fb", &option))
2083                 return -ENODEV;
2084         i810fb_setup(option);
2085
2086         return pci_register_driver(&i810fb_driver);
2087 }
2088 #endif
2089
2090 /*********************************************************************
2091  *                          Modularization                           *
2092  *********************************************************************/
2093
2094 #ifdef MODULE
2095
2096 static int __devinit i810fb_init(void)
2097 {
2098         hsync1 *= 1000;
2099         hsync2 *= 1000;
2100
2101         return pci_register_driver(&i810fb_driver);
2102 }
2103
2104 module_param(vram, int, 0);
2105 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2106                  " (default=4)");
2107 module_param(voffset, int, 0);
2108 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2109                  "memory (0 to maximum aperture size), in MiB (default = 48)");
2110 module_param(bpp, int, 0);
2111 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2112                  " (default = 8)");
2113 module_param(xres, int, 0);
2114 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2115 module_param(yres, int, 0);
2116 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2117 module_param(vyres,int, 0);
2118 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2119                  " (default = 480)");
2120 module_param(hsync1, int, 0);
2121 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2122                  " (default = 29)");
2123 module_param(hsync2, int, 0);
2124 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2125                  " (default = 30)");
2126 module_param(vsync1, int, 0);
2127 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2128                  " (default = 50)");
2129 module_param(vsync2, int, 0);
2130 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2131                  " (default = 60)");
2132 module_param(accel, bool, 0);
2133 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2134 module_param(mtrr, bool, 0);
2135 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2136 module_param(ext_vga, bool, 0);
2137 MODULE_PARM_DESC(ext_vga, "Enable external VGA connector (default = 0)");
2138 module_param(sync, bool, 0);
2139 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2140                  " (default = 0)");
2141 module_param(dcolor, bool, 0);
2142 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2143                  " (default = 0 = TrueColor)");
2144 module_param(mode_option, charp, 0);
2145 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2146
2147 MODULE_AUTHOR("Tony A. Daplas");
2148 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2149                    " compatible cards");
2150 MODULE_LICENSE("GPL");
2151
2152 static void __exit i810fb_exit(void)
2153 {
2154         pci_unregister_driver(&i810fb_driver);
2155 }
2156 module_exit(i810fb_exit);
2157
2158 #endif /* MODULE */
2159
2160 module_init(i810fb_init);