drivers/usb/otg/twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/io.h>
  34 #include <linux/delay.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/i2c/twl.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/err.h>
  40 #include <linux/notifier.h>
  41 #include <linux/slab.h>
  42
  43 /* Register defines */
  44
  45 #define MCPC_CTRL                       0x30
  46 #define MCPC_CTRL_RTSOL                 (1 << 7)
  47 #define MCPC_CTRL_EXTSWR                (1 << 6)
  48 #define MCPC_CTRL_EXTSWC                (1 << 5)
  49 #define MCPC_CTRL_VOICESW               (1 << 4)
  50 #define MCPC_CTRL_OUT64K                (1 << 3)
  51 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
  52 #define MCPC_CTRL_HS_UART               (1 << 0)
  53
  54 #define MCPC_IO_CTRL                    0x33
  55 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
  56 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
  57 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
  58 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
  59 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
  60 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
  61
  62 #define MCPC_CTRL2                      0x36
  63 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
  64
  65 #define OTHER_FUNC_CTRL                 0x80
  66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
  67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
  68
  69 #define OTHER_IFC_CTRL                  0x83
  70 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
  71 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
  72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
  73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
  74 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
  75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
  76
  77 #define OTHER_INT_EN_RISE               0x86
  78 #define OTHER_INT_EN_FALL               0x89
  79 #define OTHER_INT_STS                   0x8C
  80 #define OTHER_INT_LATCH                 0x8D
  81 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
  82 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
  83 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
  84 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
  85 #define OTHER_INT_MANU                  (1 << 1)
  86 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
  87
  88 #define ID_STATUS                       0x96
  89 #define ID_RES_FLOAT                    (1 << 4)
  90 #define ID_RES_440K                     (1 << 3)
  91 #define ID_RES_200K                     (1 << 2)
  92 #define ID_RES_102K                     (1 << 1)
  93 #define ID_RES_GND                      (1 << 0)
  94
  95 #define POWER_CTRL                      0xAC
  96 #define POWER_CTRL_OTG_ENAB             (1 << 5)
  97
  98 #define OTHER_IFC_CTRL2                 0xAF
  99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 105
 106 #define REG_CTRL_EN                     0xB2
 107 #define REG_CTRL_ERROR                  0xB5
 108 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 109
 110 #define OTHER_FUNC_CTRL2                0xB8
 111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 112
 113 /* following registers do not have separate _clr and _set registers */
 114 #define VBUS_DEBOUNCE                   0xC0
 115 #define ID_DEBOUNCE                     0xC1
 116 #define VBAT_TIMER                      0xD3
 117 #define PHY_PWR_CTRL                    0xFD
 118 #define PHY_PWR_PHYPWD                  (1 << 0)
 119 #define PHY_CLK_CTRL                    0xFE
 120 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 121 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 122 #define REQ_PHY_DPLL_CLK                (1 << 0)
 123 #define PHY_CLK_CTRL_STS                0xFF
 124 #define PHY_DPLL_CLK                    (1 << 0)
 125
 126 /* In module TWL4030_MODULE_PM_MASTER */
 127 #define STS_HW_CONDITIONS               0x0F
 128
 129 /* In module TWL4030_MODULE_PM_RECEIVER */
 130 #define VUSB_DEDICATED1                 0x7D
 131 #define VUSB_DEDICATED2                 0x7E
 132 #define VUSB1V5_DEV_GRP                 0x71
 133 #define VUSB1V5_TYPE                    0x72
 134 #define VUSB1V5_REMAP                   0x73
 135 #define VUSB1V8_DEV_GRP                 0x74
 136 #define VUSB1V8_TYPE                    0x75
 137 #define VUSB1V8_REMAP                   0x76
 138 #define VUSB3V1_DEV_GRP                 0x77
 139 #define VUSB3V1_TYPE                    0x78
 140 #define VUSB3V1_REMAP                   0x79
 141
 142 /* In module TWL4030_MODULE_INTBR */
 143 #define PMBR1                           0x0D
 144 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 145
 146 struct twl4030_usb {
 147         struct otg_transceiver  otg;
 148         struct device           *dev;
 149
 150         /* TWL4030 internal USB regulator supplies */
 151         struct regulator        *usb1v5;
 152         struct regulator        *usb1v8;
 153         struct regulator        *usb3v1;
 154
 155         /* for vbus reporting with irqs disabled */
 156         spinlock_t              lock;
 157
 158         /* pin configuration */
 159         enum twl4030_usb_mode   usb_mode;
 160
 161         int                     irq;
 162         u8                      linkstat;
 163         bool                    vbus_supplied;
 164         u8                      asleep;
 165         bool                    irq_enabled;
 166 };
 167
 168 /* internal define on top of container_of */
 169 #define xceiv_to_twl(x)         container_of((x), struct twl4030_usb, otg)
 170
 171 /*-------------------------------------------------------------------------*/
 172
 173 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 174                 u8 module, u8 data, u8 address)
 175 {
 176         u8 check;
 177
 178         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 179             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 180                                                 (check == data))
 181                 return 0;
 182         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 183                         1, module, address, check, data);
 184
 185         /* Failed once: Try again */
 186         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 187             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 188                                                 (check == data))
 189                 return 0;
 190         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 191                         2, module, address, check, data);
 192
 193         /* Failed again: Return error */
 194         return -EBUSY;
 195 }
 196
 197 #define twl4030_usb_write_verify(twl, address, data)    \
 198         twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
 199
 200 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 201                 u8 address, u8 data)
 202 {
 203         int ret = 0;
 204
 205         ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address);
 206         if (ret < 0)
 207                 dev_dbg(twl->dev,
 208                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 209         return ret;
 210 }
 211
 212 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 213 {
 214         u8 data;
 215         int ret = 0;
 216
 217         ret = twl_i2c_read_u8(module, &data, address);
 218         if (ret >= 0)
 219                 ret = data;
 220         else
 221                 dev_dbg(twl->dev,
 222                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 223                                         module, address, ret);
 224
 225         return ret;
 226 }
 227
 228 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 229 {
 230         return twl4030_readb(twl, TWL4030_MODULE_USB, address);
 231 }
 232
 233 /*-------------------------------------------------------------------------*/
 234
 235 static inline int
 236 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 237 {
 238         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
 239 }
 240
 241 static inline int
 242 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 243 {
 244         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
 245 }
 246
 247 /*-------------------------------------------------------------------------*/
 248
 249 static enum usb_xceiv_events twl4030_usb_linkstat(struct twl4030_usb *twl)
 250 {
 251         int     status;
 252         int     linkstat = USB_EVENT_NONE;
 253
 254         twl->vbus_supplied = false;
 255
 256         /*
 257          * For ID/VBUS sensing, see manual section 15.4.8 ...
 258          * except when using only battery backup power, two
 259          * comparators produce VBUS_PRES and ID_PRES signals,
 260          * which don't match docs elsewhere.  But ... BIT(7)
 261          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 262          * seem to match up.  If either is true the USB_PRES
 263          * signal is active, the OTG module is activated, and
 264          * its interrupt may be raised (may wake the system).
 265          */
 266         status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
 267                         STS_HW_CONDITIONS);
 268         if (status < 0)
 269                 dev_err(twl->dev, "USB link status err %d\n", status);
 270         else if (status & (BIT(7) | BIT(2))) {
 271                 if (status & (BIT(7)))
 272                         twl->vbus_supplied = true;
 273
 274                 if (status & BIT(2))
 275                         linkstat = USB_EVENT_ID;
 276                 else
 277                         linkstat = USB_EVENT_VBUS;
 278         } else
 279                 linkstat = USB_EVENT_NONE;
 280
 281         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 282                         status, status, linkstat);
 283
 284         if (twl->otg.last_event == linkstat)
 285                 return linkstat;
 286
 287         twl->otg.last_event = linkstat;
 288
 289         /* REVISIT this assumes host and peripheral controllers
 290          * are registered, and that both are active...
 291          */
 292
 293         spin_lock_irq(&twl->lock);
 294         twl->linkstat = linkstat;
 295         if (linkstat == USB_EVENT_ID) {
 296                 twl->otg.default_a = true;
 297                 twl->otg.state = OTG_STATE_A_IDLE;
 298         } else {
 299                 twl->otg.default_a = false;
 300                 twl->otg.state = OTG_STATE_B_IDLE;
 301         }
 302         spin_unlock_irq(&twl->lock);
 303
 304         return linkstat;
 305 }
 306
 307 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 308 {
 309         twl->usb_mode = mode;
 310
 311         switch (mode) {
 312         case T2_USB_MODE_ULPI:
 313                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
 314                                         ULPI_IFC_CTRL_CARKITMODE);
 315                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 316                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
 317                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
 318                                         ULPI_FUNC_CTRL_OPMODE_MASK);
 319                 break;
 320         case -1:
 321                 /* FIXME: power on defaults */
 322                 break;
 323         default:
 324                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 325                                 mode);
 326                 break;
 327         };
 328 }
 329
 330 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 331 {
 332         unsigned long timeout;
 333         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 334
 335         if (val >= 0) {
 336                 if (on) {
 337                         /* enable DPLL to access PHY registers over I2C */
 338                         val |= REQ_PHY_DPLL_CLK;
 339                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 340                                                 (u8)val) < 0);
 341
 342                         timeout = jiffies + HZ;
 343                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 344                                                         PHY_DPLL_CLK)
 345                                 && time_before(jiffies, timeout))
 346                                         udelay(10);
 347                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 348                                                         PHY_DPLL_CLK))
 349                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 350                                                 "PHY DPLL clock\n");
 351                 } else {
 352                         /* let ULPI control the DPLL clock */
 353                         val &= ~REQ_PHY_DPLL_CLK;
 354                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 355                                                 (u8)val) < 0);
 356                 }
 357         }
 358 }
 359
 360 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
 361 {
 362         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 363
 364         if (on)
 365                 pwr &= ~PHY_PWR_PHYPWD;
 366         else
 367                 pwr |= PHY_PWR_PHYPWD;
 368
 369         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 370 }
 371
 372 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
 373 {
 374         if (on) {
 375                 regulator_enable(twl->usb3v1);
 376                 regulator_enable(twl->usb1v8);
 377                 /*
 378                  * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 379                  * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 380                  * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 381                  * SLEEP. We work around this by clearing the bit after usv3v1
 382                  * is re-activated. This ensures that VUSB3V1 is really active.
 383                  */
 384                 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
 385                                                         VUSB_DEDICATED2);
 386                 regulator_enable(twl->usb1v5);
 387                 __twl4030_phy_power(twl, 1);
 388                 twl4030_usb_write(twl, PHY_CLK_CTRL,
 389                                   twl4030_usb_read(twl, PHY_CLK_CTRL) |
 390                                         (PHY_CLK_CTRL_CLOCKGATING_EN |
 391                                                 PHY_CLK_CTRL_CLK32K_EN));
 392         } else {
 393                 __twl4030_phy_power(twl, 0);
 394                 regulator_disable(twl->usb1v5);
 395                 regulator_disable(twl->usb1v8);
 396                 regulator_disable(twl->usb3v1);
 397         }
 398 }
 399
 400 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
 401 {
 402         if (twl->asleep)
 403                 return;
 404
 405         twl4030_phy_power(twl, 0);
 406         twl->asleep = 1;
 407         dev_dbg(twl->dev, "%s\n", __func__);
 408 }
 409
 410 static void __twl4030_phy_resume(struct twl4030_usb *twl)
 411 {
 412         twl4030_phy_power(twl, 1);
 413         twl4030_i2c_access(twl, 1);
 414         twl4030_usb_set_mode(twl, twl->usb_mode);
 415         if (twl->usb_mode == T2_USB_MODE_ULPI)
 416                 twl4030_i2c_access(twl, 0);
 417 }
 418
 419 static void twl4030_phy_resume(struct twl4030_usb *twl)
 420 {
 421         if (!twl->asleep)
 422                 return;
 423         __twl4030_phy_resume(twl);
 424         twl->asleep = 0;
 425         dev_dbg(twl->dev, "%s\n", __func__);
 426 }
 427
 428 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 429 {
 430         /* Enable writing to power configuration registers */
 431         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
 432                         TWL4030_PM_MASTER_KEY_CFG1,
 433                         TWL4030_PM_MASTER_PROTECT_KEY);
 434
 435         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
 436                         TWL4030_PM_MASTER_KEY_CFG2,
 437                         TWL4030_PM_MASTER_PROTECT_KEY);
 438
 439         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
 440         /*twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
 441
 442         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 443         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 444
 445         /* Initialize 3.1V regulator */
 446         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 447
 448         twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
 449         if (IS_ERR(twl->usb3v1))
 450                 return -ENODEV;
 451
 452         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 453
 454         /* Initialize 1.5V regulator */
 455         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 456
 457         twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
 458         if (IS_ERR(twl->usb1v5))
 459                 goto fail1;
 460
 461         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 462
 463         /* Initialize 1.8V regulator */
 464         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 465
 466         twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
 467         if (IS_ERR(twl->usb1v8))
 468                 goto fail2;
 469
 470         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 471
 472         /* disable access to power configuration registers */
 473         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
 474                         TWL4030_PM_MASTER_PROTECT_KEY);
 475
 476         return 0;
 477
 478 fail2:
 479         regulator_put(twl->usb1v5);
 480         twl->usb1v5 = NULL;
 481 fail1:
 482         regulator_put(twl->usb3v1);
 483         twl->usb3v1 = NULL;
 484         return -ENODEV;
 485 }
 486
 487 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 488                 struct device_attribute *attr, char *buf)
 489 {
 490         struct twl4030_usb *twl = dev_get_drvdata(dev);
 491         unsigned long flags;
 492         int ret = -EINVAL;
 493
 494         spin_lock_irqsave(&twl->lock, flags);
 495         ret = sprintf(buf, "%s\n",
 496                         twl->vbus_supplied ? "on" : "off");
 497         spin_unlock_irqrestore(&twl->lock, flags);
 498
 499         return ret;
 500 }
 501 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 502
 503 static ssize_t twl4030_usb_id_show(struct device *dev,
 504                 struct device_attribute *attr, char *buf)
 505 {
 506         int ret;
 507         int n = 0;
 508         struct twl4030_usb *twl = dev_get_drvdata(dev);
 509         twl4030_i2c_access(twl, 1);
 510         ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
 511         if ((ret < 0) || (!(ret & ULPI_OTG_ID_PULLUP))) {
 512                 /*
 513                  * enable ID pullup so that the id pin state can be measured,
 514                  * seems to be disabled sometimes for some reasons
 515                  */
 516                 dev_dbg(dev, "ULPI_OTG_ID_PULLUP not set (%x)\n", ret);
 517                 twl4030_usb_set_bits(twl, ULPI_OTG_CTRL, ULPI_OTG_ID_PULLUP);
 518                 mdelay(100);
 519         }
 520         ret = twl4030_usb_read(twl, ID_STATUS);
 521         twl4030_i2c_access(twl, 0);
 522         if (ret < 0)
 523                 return ret;
 524         if (ret & ID_RES_FLOAT)
 525                 n = scnprintf(buf, PAGE_SIZE, "%s\n", "floating");
 526         else if (ret & ID_RES_440K)
 527                 n = scnprintf(buf, PAGE_SIZE, "%s\n", "440k");
 528         else if (ret & ID_RES_200K)
 529                 n = scnprintf(buf, PAGE_SIZE, "%s\n", "200k");
 530         else if (ret & ID_RES_102K)
 531                 n = scnprintf(buf, PAGE_SIZE, "%s\n", "102k");
 532         else if (ret & ID_RES_GND)
 533                 n = scnprintf(buf, PAGE_SIZE, "%s\n", "GND");
 534         else
 535                 n = scnprintf(buf, PAGE_SIZE, "unknown: id=0x%x\n", ret);
 536         return n;
 537 }
 538 static DEVICE_ATTR(id, 0444, twl4030_usb_id_show, NULL);
 539
 540 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 541 {
 542         struct twl4030_usb *twl = _twl;
 543         int status_old = twl->otg.last_event;
 544         int status;
 545
 546         status = twl4030_usb_linkstat(twl);
 547         if (status >= 0) {
 548                 /* FIXME add a set_power() method so that B-devices can
 549                  * configure the charger appropriately.  It's not always
 550                  * correct to consume VBUS power, and how much current to
 551                  * consume is a function of the USB configuration chosen
 552                  * by the host.
 553                  *
 554                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 555                  * its disconnect() sibling, when changing to/from the
 556                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 557                  * starts to handle softconnect right.
 558                  */
 559                 if (status != status_old)
 560                         atomic_notifier_call_chain(&twl->otg.notifier, status,
 561                                 twl->otg.gadget);
 562         }
 563         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 static void twl4030_usb_phy_init(struct twl4030_usb *twl)
 569 {
 570         int status;
 571
 572         /*
 573          * Start in sleep state, we'll get otg.set_suspend(false) call
 574          * and power up when musb runtime_pm enable kicks in.
 575          */
 576         __twl4030_phy_power(twl, 0);
 577         twl->asleep = 1;
 578
 579         status = twl4030_usb_linkstat(twl);
 580         if (status >= 0 && status != USB_EVENT_NONE)
 581                 atomic_notifier_call_chain(&twl->otg.notifier, status,
 582                         twl->otg.gadget);
 583
 584         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 585 }
 586
 587 static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
 588 {
 589         struct twl4030_usb *twl = xceiv_to_twl(x);
 590
 591         if (suspend)
 592                 twl4030_phy_suspend(twl, 1);
 593         else
 594                 twl4030_phy_resume(twl);
 595
 596         return 0;
 597 }
 598
 599 static int twl4030_set_peripheral(struct otg_transceiver *x,
 600                 struct usb_gadget *gadget)
 601 {
 602         struct twl4030_usb *twl;
 603
 604         if (!x)
 605                 return -ENODEV;
 606
 607         twl = xceiv_to_twl(x);
 608         twl->otg.gadget = gadget;
 609         if (!gadget)
 610                 twl->otg.state = OTG_STATE_UNDEFINED;
 611
 612         return 0;
 613 }
 614
 615 static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
 616 {
 617         struct twl4030_usb *twl;
 618
 619         if (!x)
 620                 return -ENODEV;
 621
 622         twl = xceiv_to_twl(x);
 623         twl->otg.host = host;
 624         if (!host)
 625                 twl->otg.state = OTG_STATE_UNDEFINED;
 626
 627         return 0;
 628 }
 629
 630 static int __devinit twl4030_usb_probe(struct platform_device *pdev)
 631 {
 632         struct twl4030_usb_data *pdata = pdev->dev.platform_data;
 633         struct twl4030_usb      *twl;
 634         int                     status, err;
 635
 636         if (!pdata) {
 637                 dev_dbg(&pdev->dev, "platform_data not available\n");
 638                 return -EINVAL;
 639         }
 640
 641         twl = kzalloc(sizeof *twl, GFP_KERNEL);
 642         if (!twl)
 643                 return -ENOMEM;
 644
 645         twl->dev                = &pdev->dev;
 646         twl->irq                = platform_get_irq(pdev, 0);
 647         twl->otg.dev            = twl->dev;
 648         twl->otg.label          = "twl4030";
 649         twl->otg.set_host       = twl4030_set_host;
 650         twl->otg.set_peripheral = twl4030_set_peripheral;
 651         twl->otg.set_suspend    = twl4030_set_suspend;
 652         twl->usb_mode           = pdata->usb_mode;
 653         twl->vbus_supplied      = false;
 654         twl->asleep = 1;
 655
 656         /* init spinlock for workqueue */
 657         spin_lock_init(&twl->lock);
 658
 659         err = twl4030_usb_ldo_init(twl);
 660         if (err) {
 661                 dev_err(&pdev->dev, "ldo init failed\n");
 662                 kfree(twl);
 663                 return err;
 664         }
 665         otg_set_transceiver(&twl->otg);
 666
 667         platform_set_drvdata(pdev, twl);
 668         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 669                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 670         if (device_create_file(&pdev->dev, &dev_attr_id))
 671                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 672
 673         ATOMIC_INIT_NOTIFIER_HEAD(&twl->otg.notifier);
 674
 675         /* Our job is to use irqs and status from the power module
 676          * to keep the transceiver disabled when nothing's connected.
 677          *
 678          * FIXME we actually shouldn't start enabling it until the
 679          * USB controller drivers have said they're ready, by calling
 680          * set_host() and/or set_peripheral() ... OTG_capable boards
 681          * need both handles, otherwise just one suffices.
 682          */
 683         twl->irq_enabled = true;
 684         status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
 685                         IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 686                         "twl4030_usb", twl);
 687         if (status < 0) {
 688                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 689                         twl->irq, status);
 690                 kfree(twl);
 691                 return status;
 692         }
 693
 694         twl4030_usb_phy_init(twl);
 695
 696         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 697         return 0;
 698 }
 699
 700 static int __exit twl4030_usb_remove(struct platform_device *pdev)
 701 {
 702         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 703         int val;
 704
 705         free_irq(twl->irq, twl);
 706         device_remove_file(twl->dev, &dev_attr_id);
 707         device_remove_file(twl->dev, &dev_attr_vbus);
 708
 709         /* set transceiver mode to power on defaults */
 710         twl4030_usb_set_mode(twl, -1);
 711
 712         /* autogate 60MHz ULPI clock,
 713          * clear dpll clock request for i2c access,
 714          * disable 32KHz
 715          */
 716         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 717         if (val >= 0) {
 718                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 719                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 720                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 721         }
 722
 723         /* disable complete OTG block */
 724         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 725
 726         if (!twl->asleep)
 727                 twl4030_phy_power(twl, 0);
 728         regulator_put(twl->usb1v5);
 729         regulator_put(twl->usb1v8);
 730         regulator_put(twl->usb3v1);
 731
 732         kfree(twl);
 733
 734         return 0;
 735 }
 736
 737 static struct platform_driver twl4030_usb_driver = {
 738         .probe          = twl4030_usb_probe,
 739         .remove         = __exit_p(twl4030_usb_remove),
 740         .driver         = {
 741                 .name   = "twl4030_usb",
 742                 .owner  = THIS_MODULE,
 743         },
 744 };
 745
 746 static int __init twl4030_usb_init(void)
 747 {
 748         return platform_driver_register(&twl4030_usb_driver);
 749 }
 750 subsys_initcall(twl4030_usb_init);
 751
 752 static void __exit twl4030_usb_exit(void)
 753 {
 754         platform_driver_unregister(&twl4030_usb_driver);
 755 }
 756 module_exit(twl4030_usb_exit);
 757
 758 MODULE_ALIAS("platform:twl4030_usb");
 759 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 760 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 761 MODULE_LICENSE("GPL");