2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
168 static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
171 void __iomem *addr = otg->io_priv;
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
199 #define musb_ulpi_read NULL
200 #define musb_ulpi_write NULL
203 static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
208 /*-------------------------------------------------------------------------*/
210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
213 * Load an endpoint's FIFO
215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
246 musb_writeb(fifo, 0, src[index]);
249 writesb(fifo, src, len);
253 #if !defined(CONFIG_USB_MUSB_AM35X)
255 * Unload an endpoint's FIFO
257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
272 readsl(fifo, dst, len >> 2);
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
281 readsw(fifo, dst, len >> 1);
286 dst[index] = musb_readb(fifo, 0);
289 readsb(fifo, dst, len);
294 #endif /* normal PIO */
297 /*-------------------------------------------------------------------------*/
299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
300 static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
316 /* implicit CRC16 then EOP to end */
319 void musb_load_testpacket(struct musb *musb)
321 void __iomem *regs = musb->endpoints[0].regs;
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
329 /*-------------------------------------------------------------------------*/
332 * Handles OTG hnp timeouts, such as b_ase0_brst
334 void musb_otg_timer_func(unsigned long data)
336 struct musb *musb = (struct musb *)data;
339 spin_lock_irqsave(&musb->lock, flags);
340 switch (musb->xceiv->state) {
341 case OTG_STATE_B_WAIT_ACON:
342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
343 musb_g_disconnect(musb);
344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
347 case OTG_STATE_A_SUSPEND:
348 case OTG_STATE_A_WAIT_BCON:
349 dev_dbg(musb->controller, "HNP: %s timeout\n",
350 otg_state_string(musb->xceiv->state));
351 musb_platform_set_vbus(musb, 0);
352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
356 otg_state_string(musb->xceiv->state));
358 musb->ignore_disconnect = 0;
359 spin_unlock_irqrestore(&musb->lock, flags);
363 * Stops the HNP transition. Caller must take care of locking.
365 void musb_hnp_stop(struct musb *musb)
367 struct usb_hcd *hcd = musb_to_hcd(musb);
368 void __iomem *mbase = musb->mregs;
371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
373 switch (musb->xceiv->state) {
374 case OTG_STATE_A_PERIPHERAL:
375 musb_g_disconnect(musb);
376 dev_dbg(musb->controller, "HNP: back to %s\n",
377 otg_state_string(musb->xceiv->state));
379 case OTG_STATE_B_HOST:
380 dev_dbg(musb->controller, "HNP: Disabling HR\n");
381 hcd->self.is_b_host = 0;
382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
384 reg = musb_readb(mbase, MUSB_POWER);
385 reg |= MUSB_POWER_SUSPENDM;
386 musb_writeb(mbase, MUSB_POWER, reg);
387 /* REVISIT: Start SESSION_REQUEST here? */
390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
391 otg_state_string(musb->xceiv->state));
395 * When returning to A state after HNP, avoid hub_port_rebounce(),
396 * which cause occasional OPT A "Did not receive reset after connect"
399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
403 * Interrupt Service Routine to record USB "global" interrupts.
404 * Since these do not happen often and signify things of
405 * paramount importance, it seems OK to check them individually;
406 * the order of the tests is specified in the manual
408 * @param musb instance pointer
409 * @param int_usb register contents
414 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
417 irqreturn_t handled = IRQ_NONE;
419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
422 /* in host mode, the peripheral may issue remote wakeup.
423 * in peripheral mode, the host may resume the link.
424 * spurious RESUME irqs happen too, paired with SUSPEND.
426 if (int_usb & MUSB_INTR_RESUME) {
427 handled = IRQ_HANDLED;
428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
430 if (devctl & MUSB_DEVCTL_HM) {
431 void __iomem *mbase = musb->mregs;
433 switch (musb->xceiv->state) {
434 case OTG_STATE_A_SUSPEND:
435 /* remote wakeup? later, GetPortStatus
436 * will stop RESUME signaling
439 if (power & MUSB_POWER_SUSPENDM) {
441 musb->int_usb &= ~MUSB_INTR_SUSPEND;
442 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
446 power &= ~MUSB_POWER_SUSPENDM;
447 musb_writeb(mbase, MUSB_POWER,
448 power | MUSB_POWER_RESUME);
450 musb->port1_status |=
451 (USB_PORT_STAT_C_SUSPEND << 16)
452 | MUSB_PORT_STAT_RESUME;
453 musb->rh_timer = jiffies
454 + msecs_to_jiffies(20);
456 musb->xceiv->state = OTG_STATE_A_HOST;
458 usb_hcd_resume_root_hub(musb_to_hcd(musb));
460 case OTG_STATE_B_WAIT_ACON:
461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
466 WARNING("bogus %s RESUME (%s)\n",
468 otg_state_string(musb->xceiv->state));
471 switch (musb->xceiv->state) {
472 case OTG_STATE_A_SUSPEND:
473 /* possibly DISCONNECT is upcoming */
474 musb->xceiv->state = OTG_STATE_A_HOST;
475 usb_hcd_resume_root_hub(musb_to_hcd(musb));
477 case OTG_STATE_B_WAIT_ACON:
478 case OTG_STATE_B_PERIPHERAL:
479 /* disconnect while suspended? we may
480 * not get a disconnect irq...
482 if ((devctl & MUSB_DEVCTL_VBUS)
483 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
485 musb->int_usb |= MUSB_INTR_DISCONNECT;
486 musb->int_usb &= ~MUSB_INTR_SUSPEND;
491 case OTG_STATE_B_IDLE:
492 musb->int_usb &= ~MUSB_INTR_SUSPEND;
495 WARNING("bogus %s RESUME (%s)\n",
497 otg_state_string(musb->xceiv->state));
502 /* see manual for the order of the tests */
503 if (int_usb & MUSB_INTR_SESSREQ) {
504 void __iomem *mbase = musb->mregs;
506 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
507 && (devctl & MUSB_DEVCTL_BDEVICE)) {
508 dev_dbg(musb->controller, "SessReq while on B state\n");
512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
513 otg_state_string(musb->xceiv->state));
515 /* IRQ arrives from ID pin sense or (later, if VBUS power
516 * is removed) SRP. responses are time critical:
517 * - turn on VBUS (with silicon-specific mechanism)
518 * - go through A_WAIT_VRISE
519 * - ... to A_WAIT_BCON.
520 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
522 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
523 musb->ep0_stage = MUSB_EP0_START;
524 musb->xceiv->state = OTG_STATE_A_IDLE;
526 musb_platform_set_vbus(musb, 1);
528 handled = IRQ_HANDLED;
531 if (int_usb & MUSB_INTR_VBUSERROR) {
534 /* During connection as an A-Device, we may see a short
535 * current spikes causing voltage drop, because of cable
536 * and peripheral capacitance combined with vbus draw.
537 * (So: less common with truly self-powered devices, where
538 * vbus doesn't act like a power supply.)
540 * Such spikes are short; usually less than ~500 usec, max
541 * of ~2 msec. That is, they're not sustained overcurrent
542 * errors, though they're reported using VBUSERROR irqs.
544 * Workarounds: (a) hardware: use self powered devices.
545 * (b) software: ignore non-repeated VBUS errors.
547 * REVISIT: do delays from lots of DEBUG_KERNEL checks
548 * make trouble here, keeping VBUS < 4.4V ?
550 switch (musb->xceiv->state) {
551 case OTG_STATE_A_HOST:
552 /* recovery is dicey once we've gotten past the
553 * initial stages of enumeration, but if VBUS
554 * stayed ok at the other end of the link, and
555 * another reset is due (at least for high speed,
556 * to redo the chirp etc), it might work OK...
558 case OTG_STATE_A_WAIT_BCON:
559 case OTG_STATE_A_WAIT_VRISE:
560 if (musb->vbuserr_retry) {
561 void __iomem *mbase = musb->mregs;
563 musb->vbuserr_retry--;
565 devctl |= MUSB_DEVCTL_SESSION;
566 musb_writeb(mbase, MUSB_DEVCTL, devctl);
568 musb->port1_status |=
569 USB_PORT_STAT_OVERCURRENT
570 | (USB_PORT_STAT_C_OVERCURRENT << 16);
577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
578 otg_state_string(musb->xceiv->state),
581 switch (devctl & MUSB_DEVCTL_VBUS) {
582 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
583 s = "<SessEnd"; break;
584 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
585 s = "<AValid"; break;
586 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
587 s = "<VBusValid"; break;
588 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
595 /* go through A_WAIT_VFALL then start a new session */
597 musb_platform_set_vbus(musb, 0);
598 handled = IRQ_HANDLED;
601 if (int_usb & MUSB_INTR_SUSPEND) {
602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
603 otg_state_string(musb->xceiv->state), devctl, power);
604 handled = IRQ_HANDLED;
606 switch (musb->xceiv->state) {
607 case OTG_STATE_A_PERIPHERAL:
608 /* We also come here if the cable is removed, since
609 * this silicon doesn't report ID-no-longer-grounded.
611 * We depend on T(a_wait_bcon) to shut us down, and
612 * hope users don't do anything dicey during this
613 * undesired detour through A_WAIT_BCON.
616 usb_hcd_resume_root_hub(musb_to_hcd(musb));
617 musb_root_disconnect(musb);
618 musb_platform_try_idle(musb, jiffies
619 + msecs_to_jiffies(musb->a_wait_bcon
620 ? : OTG_TIME_A_WAIT_BCON));
623 case OTG_STATE_B_IDLE:
624 if (!musb->is_active)
626 case OTG_STATE_B_PERIPHERAL:
627 musb_g_suspend(musb);
628 musb->is_active = is_otg_enabled(musb)
629 && musb->xceiv->gadget->b_hnp_enable;
630 if (musb->is_active) {
631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
633 mod_timer(&musb->otg_timer, jiffies
635 OTG_TIME_B_ASE0_BRST));
638 case OTG_STATE_A_WAIT_BCON:
639 if (musb->a_wait_bcon != 0)
640 musb_platform_try_idle(musb, jiffies
641 + msecs_to_jiffies(musb->a_wait_bcon));
643 case OTG_STATE_A_HOST:
644 musb->xceiv->state = OTG_STATE_A_SUSPEND;
645 musb->is_active = is_otg_enabled(musb)
646 && musb->xceiv->host->b_hnp_enable;
648 case OTG_STATE_B_HOST:
649 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
653 /* "should not happen" */
659 if (int_usb & MUSB_INTR_CONNECT) {
660 struct usb_hcd *hcd = musb_to_hcd(musb);
662 handled = IRQ_HANDLED;
664 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
666 musb->ep0_stage = MUSB_EP0_START;
668 /* flush endpoints when transitioning from Device Mode */
669 if (is_peripheral_active(musb)) {
670 /* REVISIT HNP; just force disconnect */
672 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
673 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
674 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
675 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
676 |USB_PORT_STAT_HIGH_SPEED
677 |USB_PORT_STAT_ENABLE
679 musb->port1_status |= USB_PORT_STAT_CONNECTION
680 |(USB_PORT_STAT_C_CONNECTION << 16);
682 /* high vs full speed is just a guess until after reset */
683 if (devctl & MUSB_DEVCTL_LSDEV)
684 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
686 /* indicate new connection to OTG machine */
687 switch (musb->xceiv->state) {
688 case OTG_STATE_B_PERIPHERAL:
689 if (int_usb & MUSB_INTR_SUSPEND) {
690 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
691 int_usb &= ~MUSB_INTR_SUSPEND;
694 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
696 case OTG_STATE_B_WAIT_ACON:
697 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
699 musb->xceiv->state = OTG_STATE_B_HOST;
700 hcd->self.is_b_host = 1;
701 musb->ignore_disconnect = 0;
702 del_timer(&musb->otg_timer);
705 if ((devctl & MUSB_DEVCTL_VBUS)
706 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
707 musb->xceiv->state = OTG_STATE_A_HOST;
708 hcd->self.is_b_host = 0;
713 /* poke the root hub */
716 usb_hcd_poll_rh_status(hcd);
718 usb_hcd_resume_root_hub(hcd);
720 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
721 otg_state_string(musb->xceiv->state), devctl);
724 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
725 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
726 otg_state_string(musb->xceiv->state),
727 MUSB_MODE(musb), devctl);
728 handled = IRQ_HANDLED;
730 switch (musb->xceiv->state) {
731 case OTG_STATE_A_HOST:
732 case OTG_STATE_A_SUSPEND:
733 usb_hcd_resume_root_hub(musb_to_hcd(musb));
734 musb_root_disconnect(musb);
735 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
736 musb_platform_try_idle(musb, jiffies
737 + msecs_to_jiffies(musb->a_wait_bcon));
739 case OTG_STATE_B_HOST:
740 /* REVISIT this behaves for "real disconnect"
741 * cases; make sure the other transitions from
742 * from B_HOST act right too. The B_HOST code
743 * in hnp_stop() is currently not used...
745 musb_root_disconnect(musb);
746 musb_to_hcd(musb)->self.is_b_host = 0;
747 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
749 musb_g_disconnect(musb);
751 case OTG_STATE_A_PERIPHERAL:
753 musb_root_disconnect(musb);
755 case OTG_STATE_B_WAIT_ACON:
757 case OTG_STATE_B_PERIPHERAL:
758 case OTG_STATE_B_IDLE:
759 musb_g_disconnect(musb);
762 WARNING("unhandled DISCONNECT transition (%s)\n",
763 otg_state_string(musb->xceiv->state));
768 /* mentor saves a bit: bus reset and babble share the same irq.
769 * only host sees babble; only peripheral sees bus reset.
771 if (int_usb & MUSB_INTR_RESET) {
772 handled = IRQ_HANDLED;
773 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
775 * Looks like non-HS BABBLE can be ignored, but
776 * HS BABBLE is an error condition. For HS the solution
777 * is to avoid babble in the first place and fix what
778 * caused BABBLE. When HS BABBLE happens we can only
781 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
782 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
784 ERR("Stopping host session -- babble\n");
785 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
787 } else if (is_peripheral_capable()) {
788 dev_dbg(musb->controller, "BUS RESET as %s\n",
789 otg_state_string(musb->xceiv->state));
790 switch (musb->xceiv->state) {
791 case OTG_STATE_A_SUSPEND:
792 /* We need to ignore disconnect on suspend
793 * otherwise tusb 2.0 won't reconnect after a
794 * power cycle, which breaks otg compliance.
796 musb->ignore_disconnect = 1;
799 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
800 /* never use invalid T(a_wait_bcon) */
801 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
802 otg_state_string(musb->xceiv->state),
804 mod_timer(&musb->otg_timer, jiffies
805 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
807 case OTG_STATE_A_PERIPHERAL:
808 musb->ignore_disconnect = 0;
809 del_timer(&musb->otg_timer);
812 case OTG_STATE_B_WAIT_ACON:
813 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
814 otg_state_string(musb->xceiv->state));
815 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
818 case OTG_STATE_B_IDLE:
819 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
821 case OTG_STATE_B_PERIPHERAL:
825 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
826 otg_state_string(musb->xceiv->state));
832 /* REVISIT ... this would be for multiplexing periodic endpoints, or
833 * supporting transfer phasing to prevent exceeding ISO bandwidth
834 * limits of a given frame or microframe.
836 * It's not needed for peripheral side, which dedicates endpoints;
837 * though it _might_ use SOF irqs for other purposes.
839 * And it's not currently needed for host side, which also dedicates
840 * endpoints, relies on TX/RX interval registers, and isn't claimed
841 * to support ISO transfers yet.
843 if (int_usb & MUSB_INTR_SOF) {
844 void __iomem *mbase = musb->mregs;
845 struct musb_hw_ep *ep;
849 dev_dbg(musb->controller, "START_OF_FRAME\n");
850 handled = IRQ_HANDLED;
852 /* start any periodic Tx transfers waiting for current frame */
853 frame = musb_readw(mbase, MUSB_FRAME);
854 ep = musb->endpoints;
855 for (epnum = 1; (epnum < musb->nr_endpoints)
856 && (musb->epmask >= (1 << epnum));
859 * FIXME handle framecounter wraps (12 bits)
860 * eliminate duplicated StartUrb logic
862 if (ep->dwWaitFrame >= frame) {
864 pr_debug("SOF --> periodic TX%s on %d\n",
865 ep->tx_channel ? " DMA" : "",
868 musb_h_tx_start(musb, epnum);
870 cppi_hostdma_start(musb, epnum);
872 } /* end of for loop */
876 schedule_work(&musb->irq_work);
881 /*-------------------------------------------------------------------------*/
884 * Program the HDRC to start (enable interrupts, dma, etc.).
886 void musb_start(struct musb *musb)
888 void __iomem *regs = musb->mregs;
889 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
891 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
893 /* Set INT enable registers, enable interrupts */
894 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
895 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
896 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
898 musb_writeb(regs, MUSB_TESTMODE, 0);
900 /* put into basic highspeed mode and start session */
901 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
903 /* ENSUSPEND wedges tusb */
904 /* | MUSB_POWER_ENSUSPEND */
908 devctl = musb_readb(regs, MUSB_DEVCTL);
909 devctl &= ~MUSB_DEVCTL_SESSION;
911 if (is_otg_enabled(musb)) {
912 /* session started after:
913 * (a) ID-grounded irq, host mode;
914 * (b) vbus present/connect IRQ, peripheral mode;
915 * (c) peripheral initiates, using SRP
917 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
920 devctl |= MUSB_DEVCTL_SESSION;
922 } else if (is_host_enabled(musb)) {
923 /* assume ID pin is hard-wired to ground */
924 devctl |= MUSB_DEVCTL_SESSION;
926 } else /* peripheral is enabled */ {
927 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
930 musb_platform_enable(musb);
931 musb_writeb(regs, MUSB_DEVCTL, devctl);
935 static void musb_generic_disable(struct musb *musb)
937 void __iomem *mbase = musb->mregs;
940 /* disable interrupts */
941 musb_writeb(mbase, MUSB_INTRUSBE, 0);
942 musb_writew(mbase, MUSB_INTRTXE, 0);
943 musb_writew(mbase, MUSB_INTRRXE, 0);
946 musb_writeb(mbase, MUSB_DEVCTL, 0);
948 /* flush pending interrupts */
949 temp = musb_readb(mbase, MUSB_INTRUSB);
950 temp = musb_readw(mbase, MUSB_INTRTX);
951 temp = musb_readw(mbase, MUSB_INTRRX);
956 * Make the HDRC stop (disable interrupts, etc.);
957 * reversible by musb_start
958 * called on gadget driver unregister
959 * with controller locked, irqs blocked
960 * acts as a NOP unless some role activated the hardware
962 void musb_stop(struct musb *musb)
964 /* stop IRQs, timers, ... */
965 musb_platform_disable(musb);
966 musb_generic_disable(musb);
967 dev_dbg(musb->controller, "HDRC disabled\n");
970 * - mark host and/or peripheral drivers unusable/inactive
971 * - disable DMA (and enable it in HdrcStart)
972 * - make sure we can musb_start() after musb_stop(); with
973 * OTG mode, gadget driver module rmmod/modprobe cycles that
976 musb_platform_try_idle(musb, 0);
979 static void musb_shutdown(struct platform_device *pdev)
981 struct musb *musb = dev_to_musb(&pdev->dev);
984 pm_runtime_get_sync(musb->controller);
986 musb_gadget_cleanup(musb);
988 spin_lock_irqsave(&musb->lock, flags);
989 musb_platform_disable(musb);
990 musb_generic_disable(musb);
991 spin_unlock_irqrestore(&musb->lock, flags);
993 if (!is_otg_enabled(musb) && is_host_enabled(musb))
994 usb_remove_hcd(musb_to_hcd(musb));
995 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
996 musb_platform_exit(musb);
998 pm_runtime_put(musb->controller);
999 /* FIXME power down */
1003 /*-------------------------------------------------------------------------*/
1006 * The silicon either has hard-wired endpoint configurations, or else
1007 * "dynamic fifo" sizing. The driver has support for both, though at this
1008 * writing only the dynamic sizing is very well tested. Since we switched
1009 * away from compile-time hardware parameters, we can no longer rely on
1010 * dead code elimination to leave only the relevant one in the object file.
1012 * We don't currently use dynamic fifo setup capability to do anything
1013 * more than selecting one of a bunch of predefined configurations.
1015 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1016 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1017 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1018 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1019 || defined(CONFIG_USB_MUSB_AM35X) \
1020 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1021 static ushort __initdata fifo_mode = 4;
1022 #elif defined(CONFIG_USB_MUSB_UX500) \
1023 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1024 static ushort __initdata fifo_mode = 5;
1026 static ushort __initdata fifo_mode = 2;
1029 /* "modprobe ... fifo_mode=1" etc */
1030 module_param(fifo_mode, ushort, 0);
1031 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1034 * tables defining fifo_mode values. define more if you like.
1035 * for host side, make sure both halves of ep1 are set up.
1038 /* mode 0 - fits in 2KB */
1039 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1040 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1041 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1042 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1043 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1044 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1047 /* mode 1 - fits in 4KB */
1048 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1049 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1050 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1051 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1052 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1053 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1056 /* mode 2 - fits in 4KB */
1057 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1058 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1059 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1060 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1061 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1062 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1066 /* mode 3 - fits in 4KB */
1067 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1068 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1069 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1070 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1073 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1076 /* mode 4 - fits in 16KB */
1077 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1078 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1079 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1080 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1095 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1096 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1097 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1098 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1099 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1100 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1101 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1102 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1103 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1104 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1107 /* mode 5 - fits in 8KB */
1108 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1109 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1118 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1119 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1120 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1121 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1122 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1123 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1124 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1125 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1126 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1127 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1128 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1129 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1130 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1131 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1132 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1133 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1134 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1135 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1139 * configure a fifo; for non-shared endpoints, this may be called
1140 * once for a tx fifo and once for an rx fifo.
1142 * returns negative errno or offset for next fifo.
1145 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1146 const struct musb_fifo_cfg *cfg, u16 offset)
1148 void __iomem *mbase = musb->mregs;
1150 u16 maxpacket = cfg->maxpacket;
1151 u16 c_off = offset >> 3;
1154 /* expect hw_ep has already been zero-initialized */
1156 size = ffs(max(maxpacket, (u16) 8)) - 1;
1157 maxpacket = 1 << size;
1160 if (cfg->mode == BUF_DOUBLE) {
1161 if ((offset + (maxpacket << 1)) >
1162 (1 << (musb->config->ram_bits + 2)))
1164 c_size |= MUSB_FIFOSZ_DPB;
1166 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1170 /* configure the FIFO */
1171 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1173 /* EP0 reserved endpoint for control, bidirectional;
1174 * EP1 reserved for bulk, two unidirection halves.
1176 if (hw_ep->epnum == 1)
1177 musb->bulk_ep = hw_ep;
1178 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1179 switch (cfg->style) {
1181 musb_write_txfifosz(mbase, c_size);
1182 musb_write_txfifoadd(mbase, c_off);
1183 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1184 hw_ep->max_packet_sz_tx = maxpacket;
1187 musb_write_rxfifosz(mbase, c_size);
1188 musb_write_rxfifoadd(mbase, c_off);
1189 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1190 hw_ep->max_packet_sz_rx = maxpacket;
1193 musb_write_txfifosz(mbase, c_size);
1194 musb_write_txfifoadd(mbase, c_off);
1195 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1196 hw_ep->max_packet_sz_rx = maxpacket;
1198 musb_write_rxfifosz(mbase, c_size);
1199 musb_write_rxfifoadd(mbase, c_off);
1200 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1201 hw_ep->max_packet_sz_tx = maxpacket;
1203 hw_ep->is_shared_fifo = true;
1207 /* NOTE rx and tx endpoint irqs aren't managed separately,
1208 * which happens to be ok
1210 musb->epmask |= (1 << hw_ep->epnum);
1212 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1215 static struct musb_fifo_cfg __initdata ep0_cfg = {
1216 .style = FIFO_RXTX, .maxpacket = 64,
1219 static int __init ep_config_from_table(struct musb *musb)
1221 const struct musb_fifo_cfg *cfg;
1224 struct musb_hw_ep *hw_ep = musb->endpoints;
1226 if (musb->config->fifo_cfg) {
1227 cfg = musb->config->fifo_cfg;
1228 n = musb->config->fifo_cfg_size;
1232 switch (fifo_mode) {
1238 n = ARRAY_SIZE(mode_0_cfg);
1242 n = ARRAY_SIZE(mode_1_cfg);
1246 n = ARRAY_SIZE(mode_2_cfg);
1250 n = ARRAY_SIZE(mode_3_cfg);
1254 n = ARRAY_SIZE(mode_4_cfg);
1258 n = ARRAY_SIZE(mode_5_cfg);
1262 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1263 musb_driver_name, fifo_mode);
1267 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1268 /* assert(offset > 0) */
1270 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1271 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1274 for (i = 0; i < n; i++) {
1275 u8 epn = cfg->hw_ep_num;
1277 if (epn >= musb->config->num_eps) {
1278 pr_debug("%s: invalid ep %d\n",
1279 musb_driver_name, epn);
1282 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1284 pr_debug("%s: mem overrun, ep %d\n",
1285 musb_driver_name, epn);
1289 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1292 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1294 n + 1, musb->config->num_eps * 2 - 1,
1295 offset, (1 << (musb->config->ram_bits + 2)));
1297 if (!musb->bulk_ep) {
1298 pr_debug("%s: missing bulk\n", musb_driver_name);
1307 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1308 * @param musb the controller
1310 static int __init ep_config_from_hw(struct musb *musb)
1313 struct musb_hw_ep *hw_ep;
1314 void *mbase = musb->mregs;
1317 dev_dbg(musb->controller, "<== static silicon ep config\n");
1319 /* FIXME pick up ep0 maxpacket size */
1321 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1322 musb_ep_select(mbase, epnum);
1323 hw_ep = musb->endpoints + epnum;
1325 ret = musb_read_fifosize(musb, hw_ep, epnum);
1329 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1331 /* pick an RX/TX endpoint for bulk */
1332 if (hw_ep->max_packet_sz_tx < 512
1333 || hw_ep->max_packet_sz_rx < 512)
1336 /* REVISIT: this algorithm is lazy, we should at least
1337 * try to pick a double buffered endpoint.
1341 musb->bulk_ep = hw_ep;
1344 if (!musb->bulk_ep) {
1345 pr_debug("%s: missing bulk\n", musb_driver_name);
1352 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1354 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1355 * configure endpoints, or take their config from silicon
1357 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1361 char aInfo[90], aRevision[32], aDate[12];
1362 void __iomem *mbase = musb->mregs;
1366 /* log core options (read using indexed model) */
1367 reg = musb_read_configdata(mbase);
1369 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1370 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1371 strcat(aInfo, ", dyn FIFOs");
1372 musb->dyn_fifo = true;
1374 if (reg & MUSB_CONFIGDATA_MPRXE) {
1375 strcat(aInfo, ", bulk combine");
1376 musb->bulk_combine = true;
1378 if (reg & MUSB_CONFIGDATA_MPTXE) {
1379 strcat(aInfo, ", bulk split");
1380 musb->bulk_split = true;
1382 if (reg & MUSB_CONFIGDATA_HBRXE) {
1383 strcat(aInfo, ", HB-ISO Rx");
1384 musb->hb_iso_rx = true;
1386 if (reg & MUSB_CONFIGDATA_HBTXE) {
1387 strcat(aInfo, ", HB-ISO Tx");
1388 musb->hb_iso_tx = true;
1390 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1391 strcat(aInfo, ", SoftConn");
1393 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1394 musb_driver_name, reg, aInfo);
1397 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1398 musb->is_multipoint = 1;
1401 musb->is_multipoint = 0;
1403 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1405 "%s: kernel must blacklist external hubs\n",
1410 /* log release info */
1411 musb->hwvers = musb_read_hwvers(mbase);
1412 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1413 MUSB_HWVERS_MINOR(musb->hwvers),
1414 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1415 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1416 musb_driver_name, type, aRevision, aDate);
1419 musb_configure_ep0(musb);
1421 /* discover endpoint configuration */
1422 musb->nr_endpoints = 1;
1426 status = ep_config_from_table(musb);
1428 status = ep_config_from_hw(musb);
1433 /* finish init, and print endpoint config */
1434 for (i = 0; i < musb->nr_endpoints; i++) {
1435 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1437 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1438 #ifdef CONFIG_USB_MUSB_TUSB6010
1439 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1440 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1441 hw_ep->fifo_sync_va =
1442 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1445 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1447 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1450 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1451 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1452 hw_ep->rx_reinit = 1;
1453 hw_ep->tx_reinit = 1;
1455 if (hw_ep->max_packet_sz_tx) {
1456 dev_dbg(musb->controller,
1457 "%s: hw_ep %d%s, %smax %d\n",
1458 musb_driver_name, i,
1459 hw_ep->is_shared_fifo ? "shared" : "tx",
1460 hw_ep->tx_double_buffered
1461 ? "doublebuffer, " : "",
1462 hw_ep->max_packet_sz_tx);
1464 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1465 dev_dbg(musb->controller,
1466 "%s: hw_ep %d%s, %smax %d\n",
1467 musb_driver_name, i,
1469 hw_ep->rx_double_buffered
1470 ? "doublebuffer, " : "",
1471 hw_ep->max_packet_sz_rx);
1473 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1474 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1480 /*-------------------------------------------------------------------------*/
1482 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1483 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1485 static irqreturn_t generic_interrupt(int irq, void *__hci)
1487 unsigned long flags;
1488 irqreturn_t retval = IRQ_NONE;
1489 struct musb *musb = __hci;
1491 spin_lock_irqsave(&musb->lock, flags);
1493 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1494 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1495 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1497 if (musb->int_usb || musb->int_tx || musb->int_rx)
1498 retval = musb_interrupt(musb);
1500 spin_unlock_irqrestore(&musb->lock, flags);
1506 #define generic_interrupt NULL
1510 * handle all the irqs defined by the HDRC core. for now we expect: other
1511 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1512 * will be assigned, and the irq will already have been acked.
1514 * called in irq context with spinlock held, irqs blocked
1516 irqreturn_t musb_interrupt(struct musb *musb)
1518 irqreturn_t retval = IRQ_NONE;
1523 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1524 power = musb_readb(musb->mregs, MUSB_POWER);
1526 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1527 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1528 musb->int_usb, musb->int_tx, musb->int_rx);
1530 /* the core can interrupt us for multiple reasons; docs have
1531 * a generic interrupt flowchart to follow
1534 retval |= musb_stage0_irq(musb, musb->int_usb,
1537 /* "stage 1" is handling endpoint irqs */
1539 /* handle endpoint 0 first */
1540 if (musb->int_tx & 1) {
1541 if (devctl & MUSB_DEVCTL_HM)
1542 retval |= musb_h_ep0_irq(musb);
1544 retval |= musb_g_ep0_irq(musb);
1547 /* RX on endpoints 1-15 */
1548 reg = musb->int_rx >> 1;
1552 /* musb_ep_select(musb->mregs, ep_num); */
1553 /* REVISIT just retval = ep->rx_irq(...) */
1554 retval = IRQ_HANDLED;
1555 if (devctl & MUSB_DEVCTL_HM) {
1556 if (is_host_capable())
1557 musb_host_rx(musb, ep_num);
1559 if (is_peripheral_capable())
1560 musb_g_rx(musb, ep_num);
1568 /* TX on endpoints 1-15 */
1569 reg = musb->int_tx >> 1;
1573 /* musb_ep_select(musb->mregs, ep_num); */
1574 /* REVISIT just retval |= ep->tx_irq(...) */
1575 retval = IRQ_HANDLED;
1576 if (devctl & MUSB_DEVCTL_HM) {
1577 if (is_host_capable())
1578 musb_host_tx(musb, ep_num);
1580 if (is_peripheral_capable())
1581 musb_g_tx(musb, ep_num);
1590 EXPORT_SYMBOL_GPL(musb_interrupt);
1592 #ifndef CONFIG_MUSB_PIO_ONLY
1593 static int __initdata use_dma = 1;
1595 /* "modprobe ... use_dma=0" etc */
1596 module_param(use_dma, bool, 0);
1597 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1599 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1601 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1603 /* called with controller lock already held */
1606 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1607 if (!is_cppi_enabled()) {
1609 if (devctl & MUSB_DEVCTL_HM)
1610 musb_h_ep0_irq(musb);
1612 musb_g_ep0_irq(musb);
1616 /* endpoints 1..15 */
1618 if (devctl & MUSB_DEVCTL_HM) {
1619 if (is_host_capable())
1620 musb_host_tx(musb, epnum);
1622 if (is_peripheral_capable())
1623 musb_g_tx(musb, epnum);
1627 if (devctl & MUSB_DEVCTL_HM) {
1628 if (is_host_capable())
1629 musb_host_rx(musb, epnum);
1631 if (is_peripheral_capable())
1632 musb_g_rx(musb, epnum);
1642 /*-------------------------------------------------------------------------*/
1647 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1649 struct musb *musb = dev_to_musb(dev);
1650 unsigned long flags;
1653 spin_lock_irqsave(&musb->lock, flags);
1654 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1655 spin_unlock_irqrestore(&musb->lock, flags);
1661 musb_mode_store(struct device *dev, struct device_attribute *attr,
1662 const char *buf, size_t n)
1664 struct musb *musb = dev_to_musb(dev);
1665 unsigned long flags;
1668 spin_lock_irqsave(&musb->lock, flags);
1669 if (sysfs_streq(buf, "host"))
1670 status = musb_platform_set_mode(musb, MUSB_HOST);
1671 else if (sysfs_streq(buf, "peripheral"))
1672 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1673 else if (sysfs_streq(buf, "otg"))
1674 status = musb_platform_set_mode(musb, MUSB_OTG);
1677 spin_unlock_irqrestore(&musb->lock, flags);
1679 return (status == 0) ? n : status;
1681 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1684 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1685 const char *buf, size_t n)
1687 struct musb *musb = dev_to_musb(dev);
1688 unsigned long flags;
1691 if (sscanf(buf, "%lu", &val) < 1) {
1692 dev_err(dev, "Invalid VBUS timeout ms value\n");
1696 spin_lock_irqsave(&musb->lock, flags);
1697 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1698 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1699 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1700 musb->is_active = 0;
1701 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1702 spin_unlock_irqrestore(&musb->lock, flags);
1708 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1710 struct musb *musb = dev_to_musb(dev);
1711 unsigned long flags;
1715 spin_lock_irqsave(&musb->lock, flags);
1716 val = musb->a_wait_bcon;
1717 /* FIXME get_vbus_status() is normally #defined as false...
1718 * and is effectively TUSB-specific.
1720 vbus = musb_platform_get_vbus_status(musb);
1721 spin_unlock_irqrestore(&musb->lock, flags);
1723 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1724 vbus ? "on" : "off", val);
1726 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1728 /* Gadget drivers can't know that a host is connected so they might want
1729 * to start SRP, but users can. This allows userspace to trigger SRP.
1732 musb_srp_store(struct device *dev, struct device_attribute *attr,
1733 const char *buf, size_t n)
1735 struct musb *musb = dev_to_musb(dev);
1738 if (sscanf(buf, "%hu", &srp) != 1
1740 dev_err(dev, "SRP: Value must be 1\n");
1745 musb_g_wakeup(musb);
1749 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1751 static struct attribute *musb_attributes[] = {
1752 &dev_attr_mode.attr,
1753 &dev_attr_vbus.attr,
1758 static const struct attribute_group musb_attr_group = {
1759 .attrs = musb_attributes,
1764 /* Only used to provide driver mode change events */
1765 static void musb_irq_work(struct work_struct *data)
1767 struct musb *musb = container_of(data, struct musb, irq_work);
1768 static int old_state;
1770 if (musb->xceiv->state != old_state) {
1771 old_state = musb->xceiv->state;
1772 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1776 /* --------------------------------------------------------------------------
1780 static struct musb *__init
1781 allocate_instance(struct device *dev,
1782 struct musb_hdrc_config *config, void __iomem *mbase)
1785 struct musb_hw_ep *ep;
1787 struct usb_hcd *hcd;
1789 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1792 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1794 musb = hcd_to_musb(hcd);
1795 INIT_LIST_HEAD(&musb->control);
1796 INIT_LIST_HEAD(&musb->in_bulk);
1797 INIT_LIST_HEAD(&musb->out_bulk);
1799 hcd->uses_new_polling = 1;
1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1804 dev_set_drvdata(dev, musb);
1805 musb->mregs = mbase;
1806 musb->ctrl_base = mbase;
1807 musb->nIrq = -ENODEV;
1808 musb->config = config;
1809 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1810 for (epnum = 0, ep = musb->endpoints;
1811 epnum < musb->config->num_eps;
1817 musb->controller = dev;
1822 static void musb_free(struct musb *musb)
1824 /* this has multiple entry modes. it handles fault cleanup after
1825 * probe(), where things may be partially set up, as well as rmmod
1826 * cleanup after everything's been de-activated.
1830 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1833 if (musb->nIrq >= 0) {
1835 disable_irq_wake(musb->nIrq);
1836 free_irq(musb->nIrq, musb);
1838 if (is_dma_capable() && musb->dma_controller) {
1839 struct dma_controller *c = musb->dma_controller;
1842 dma_controller_destroy(c);
1849 * Perform generic per-controller initialization.
1851 * @pDevice: the controller (already clocked, etc)
1853 * @mregs: virtual address of controller registers,
1854 * not yet corrected for platform-specific offsets
1857 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1861 struct musb_hdrc_platform_data *plat = dev->platform_data;
1863 /* The driver might handle more features than the board; OK.
1864 * Fail when the board needs a feature that's not enabled.
1867 dev_dbg(dev, "no platform_data?\n");
1873 musb = allocate_instance(dev, plat->config, ctrl);
1879 pm_runtime_use_autosuspend(musb->controller);
1880 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1881 pm_runtime_enable(musb->controller);
1883 spin_lock_init(&musb->lock);
1884 musb->board_mode = plat->mode;
1885 musb->board_set_power = plat->set_power;
1886 musb->min_power = plat->min_power;
1887 musb->ops = plat->platform_ops;
1889 /* The musb_platform_init() call:
1890 * - adjusts musb->mregs and musb->isr if needed,
1891 * - may initialize an integrated tranceiver
1892 * - initializes musb->xceiv, usually by otg_get_transceiver()
1893 * - stops powering VBUS
1895 * There are various transceiver configurations. Blackfin,
1896 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1897 * external/discrete ones in various flavors (twl4030 family,
1898 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1900 musb->isr = generic_interrupt;
1901 status = musb_platform_init(musb);
1910 if (!musb->xceiv->io_ops) {
1911 musb->xceiv->io_priv = musb->mregs;
1912 musb->xceiv->io_ops = &musb_ulpi_access;
1915 #ifndef CONFIG_MUSB_PIO_ONLY
1916 if (use_dma && dev->dma_mask) {
1917 struct dma_controller *c;
1919 c = dma_controller_create(musb, musb->mregs);
1920 musb->dma_controller = c;
1925 /* ideally this would be abstracted in platform setup */
1926 if (!is_dma_capable() || !musb->dma_controller)
1927 dev->dma_mask = NULL;
1929 /* be sure interrupts are disabled before connecting ISR */
1930 musb_platform_disable(musb);
1931 musb_generic_disable(musb);
1933 /* setup musb parts of the core (especially endpoints) */
1934 status = musb_core_init(plat->config->multipoint
1935 ? MUSB_CONTROLLER_MHDRC
1936 : MUSB_CONTROLLER_HDRC, musb);
1940 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1942 /* Init IRQ workqueue before request_irq */
1943 INIT_WORK(&musb->irq_work, musb_irq_work);
1945 /* attach to the IRQ */
1946 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1947 dev_err(dev, "request_irq %d failed!\n", nIrq);
1952 /* FIXME this handles wakeup irqs wrong */
1953 if (enable_irq_wake(nIrq) == 0) {
1955 device_init_wakeup(dev, 1);
1960 /* host side needs more setup */
1961 if (is_host_enabled(musb)) {
1962 struct usb_hcd *hcd = musb_to_hcd(musb);
1964 otg_set_host(musb->xceiv, &hcd->self);
1966 if (is_otg_enabled(musb))
1967 hcd->self.otg_port = 1;
1968 musb->xceiv->host = &hcd->self;
1969 hcd->power_budget = 2 * (plat->power ? : 250);
1971 /* program PHY to use external vBus if required */
1972 if (plat->extvbus) {
1973 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1974 busctl |= MUSB_ULPI_USE_EXTVBUS;
1975 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1979 /* For the host-only role, we can activate right away.
1980 * (We expect the ID pin to be forcibly grounded!!)
1981 * Otherwise, wait till the gadget driver hooks up.
1983 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1984 struct usb_hcd *hcd = musb_to_hcd(musb);
1986 MUSB_HST_MODE(musb);
1987 musb->xceiv->default_a = 1;
1988 musb->xceiv->state = OTG_STATE_A_IDLE;
1990 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1992 hcd->self.uses_pio_for_control = 1;
1993 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
1995 musb_readb(musb->mregs, MUSB_DEVCTL),
1996 (musb_readb(musb->mregs, MUSB_DEVCTL)
1997 & MUSB_DEVCTL_BDEVICE
2000 } else /* peripheral is enabled */ {
2001 MUSB_DEV_MODE(musb);
2002 musb->xceiv->default_a = 0;
2003 musb->xceiv->state = OTG_STATE_B_IDLE;
2005 status = musb_gadget_setup(musb);
2007 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2008 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2010 musb_readb(musb->mregs, MUSB_DEVCTL));
2016 pm_runtime_put(musb->controller);
2018 status = musb_init_debugfs(musb);
2023 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2028 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2030 switch (musb->board_mode) {
2031 case MUSB_HOST: s = "Host"; break;
2032 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2033 default: s = "OTG"; break;
2036 (is_dma_capable() && musb->dma_controller)
2043 musb_exit_debugfs(musb);
2046 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2047 usb_remove_hcd(musb_to_hcd(musb));
2049 musb_gadget_cleanup(musb);
2053 device_init_wakeup(dev, 0);
2054 musb_platform_exit(musb);
2057 dev_err(musb->controller,
2058 "musb_init_controller failed with status %d\n", status);
2068 /*-------------------------------------------------------------------------*/
2070 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2071 * bridge to a platform device; this driver then suffices.
2074 #ifndef CONFIG_MUSB_PIO_ONLY
2075 static u64 *orig_dma_mask;
2078 static int __init musb_probe(struct platform_device *pdev)
2080 struct device *dev = &pdev->dev;
2081 int irq = platform_get_irq_byname(pdev, "mc");
2083 struct resource *iomem;
2086 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2087 if (!iomem || irq <= 0)
2090 base = ioremap(iomem->start, resource_size(iomem));
2092 dev_err(dev, "ioremap failed\n");
2096 #ifndef CONFIG_MUSB_PIO_ONLY
2097 /* clobbered by use_dma=n */
2098 orig_dma_mask = dev->dma_mask;
2100 status = musb_init_controller(dev, irq, base);
2107 static int __exit musb_remove(struct platform_device *pdev)
2109 struct musb *musb = dev_to_musb(&pdev->dev);
2110 void __iomem *ctrl_base = musb->ctrl_base;
2112 /* this gets called on rmmod.
2113 * - Host mode: host may still be active
2114 * - Peripheral mode: peripheral is deactivated (or never-activated)
2115 * - OTG mode: both roles are deactivated (or never-activated)
2117 musb_exit_debugfs(musb);
2118 musb_shutdown(pdev);
2122 device_init_wakeup(&pdev->dev, 0);
2123 #ifndef CONFIG_MUSB_PIO_ONLY
2124 pdev->dev.dma_mask = orig_dma_mask;
2131 static void musb_save_context(struct musb *musb)
2134 void __iomem *musb_base = musb->mregs;
2137 if (is_host_enabled(musb)) {
2138 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2139 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2140 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2142 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2143 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2144 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2145 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2146 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2147 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2149 for (i = 0; i < musb->config->num_eps; ++i) {
2150 struct musb_hw_ep *hw_ep;
2152 hw_ep = &musb->endpoints[i];
2160 musb_writeb(musb_base, MUSB_INDEX, i);
2161 musb->context.index_regs[i].txmaxp =
2162 musb_readw(epio, MUSB_TXMAXP);
2163 musb->context.index_regs[i].txcsr =
2164 musb_readw(epio, MUSB_TXCSR);
2165 musb->context.index_regs[i].rxmaxp =
2166 musb_readw(epio, MUSB_RXMAXP);
2167 musb->context.index_regs[i].rxcsr =
2168 musb_readw(epio, MUSB_RXCSR);
2170 if (musb->dyn_fifo) {
2171 musb->context.index_regs[i].txfifoadd =
2172 musb_read_txfifoadd(musb_base);
2173 musb->context.index_regs[i].rxfifoadd =
2174 musb_read_rxfifoadd(musb_base);
2175 musb->context.index_regs[i].txfifosz =
2176 musb_read_txfifosz(musb_base);
2177 musb->context.index_regs[i].rxfifosz =
2178 musb_read_rxfifosz(musb_base);
2180 if (is_host_enabled(musb)) {
2181 musb->context.index_regs[i].txtype =
2182 musb_readb(epio, MUSB_TXTYPE);
2183 musb->context.index_regs[i].txinterval =
2184 musb_readb(epio, MUSB_TXINTERVAL);
2185 musb->context.index_regs[i].rxtype =
2186 musb_readb(epio, MUSB_RXTYPE);
2187 musb->context.index_regs[i].rxinterval =
2188 musb_readb(epio, MUSB_RXINTERVAL);
2190 musb->context.index_regs[i].txfunaddr =
2191 musb_read_txfunaddr(musb_base, i);
2192 musb->context.index_regs[i].txhubaddr =
2193 musb_read_txhubaddr(musb_base, i);
2194 musb->context.index_regs[i].txhubport =
2195 musb_read_txhubport(musb_base, i);
2197 musb->context.index_regs[i].rxfunaddr =
2198 musb_read_rxfunaddr(musb_base, i);
2199 musb->context.index_regs[i].rxhubaddr =
2200 musb_read_rxhubaddr(musb_base, i);
2201 musb->context.index_regs[i].rxhubport =
2202 musb_read_rxhubport(musb_base, i);
2207 static void musb_restore_context(struct musb *musb)
2210 void __iomem *musb_base = musb->mregs;
2211 void __iomem *ep_target_regs;
2214 if (is_host_enabled(musb)) {
2215 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2216 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2217 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2219 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2220 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2221 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2222 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2223 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2225 for (i = 0; i < musb->config->num_eps; ++i) {
2226 struct musb_hw_ep *hw_ep;
2228 hw_ep = &musb->endpoints[i];
2236 musb_writeb(musb_base, MUSB_INDEX, i);
2237 musb_writew(epio, MUSB_TXMAXP,
2238 musb->context.index_regs[i].txmaxp);
2239 musb_writew(epio, MUSB_TXCSR,
2240 musb->context.index_regs[i].txcsr);
2241 musb_writew(epio, MUSB_RXMAXP,
2242 musb->context.index_regs[i].rxmaxp);
2243 musb_writew(epio, MUSB_RXCSR,
2244 musb->context.index_regs[i].rxcsr);
2246 if (musb->dyn_fifo) {
2247 musb_write_txfifosz(musb_base,
2248 musb->context.index_regs[i].txfifosz);
2249 musb_write_rxfifosz(musb_base,
2250 musb->context.index_regs[i].rxfifosz);
2251 musb_write_txfifoadd(musb_base,
2252 musb->context.index_regs[i].txfifoadd);
2253 musb_write_rxfifoadd(musb_base,
2254 musb->context.index_regs[i].rxfifoadd);
2257 if (is_host_enabled(musb)) {
2258 musb_writeb(epio, MUSB_TXTYPE,
2259 musb->context.index_regs[i].txtype);
2260 musb_writeb(epio, MUSB_TXINTERVAL,
2261 musb->context.index_regs[i].txinterval);
2262 musb_writeb(epio, MUSB_RXTYPE,
2263 musb->context.index_regs[i].rxtype);
2264 musb_writeb(epio, MUSB_RXINTERVAL,
2266 musb->context.index_regs[i].rxinterval);
2267 musb_write_txfunaddr(musb_base, i,
2268 musb->context.index_regs[i].txfunaddr);
2269 musb_write_txhubaddr(musb_base, i,
2270 musb->context.index_regs[i].txhubaddr);
2271 musb_write_txhubport(musb_base, i,
2272 musb->context.index_regs[i].txhubport);
2275 musb_read_target_reg_base(i, musb_base);
2277 musb_write_rxfunaddr(ep_target_regs,
2278 musb->context.index_regs[i].rxfunaddr);
2279 musb_write_rxhubaddr(ep_target_regs,
2280 musb->context.index_regs[i].rxhubaddr);
2281 musb_write_rxhubport(ep_target_regs,
2282 musb->context.index_regs[i].rxhubport);
2285 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2288 static int musb_suspend(struct device *dev)
2290 struct musb *musb = dev_to_musb(dev);
2291 unsigned long flags;
2293 spin_lock_irqsave(&musb->lock, flags);
2295 if (is_peripheral_active(musb)) {
2296 /* FIXME force disconnect unless we know USB will wake
2297 * the system up quickly enough to respond ...
2299 } else if (is_host_active(musb)) {
2300 /* we know all the children are suspended; sometimes
2301 * they will even be wakeup-enabled.
2305 spin_unlock_irqrestore(&musb->lock, flags);
2309 static int musb_resume_noirq(struct device *dev)
2311 /* for static cmos like DaVinci, register values were preserved
2312 * unless for some reason the whole soc powered down or the USB
2313 * module got reset through the PSC (vs just being disabled).
2318 static int musb_runtime_suspend(struct device *dev)
2320 struct musb *musb = dev_to_musb(dev);
2322 musb_save_context(musb);
2327 static int musb_runtime_resume(struct device *dev)
2329 struct musb *musb = dev_to_musb(dev);
2330 static int first = 1;
2333 * When pm_runtime_get_sync called for the first time in driver
2334 * init, some of the structure is still not initialized which is
2335 * used in restore function. But clock needs to be
2336 * enabled before any register access, so
2337 * pm_runtime_get_sync has to be called.
2338 * Also context restore without save does not make
2342 musb_restore_context(musb);
2348 static const struct dev_pm_ops musb_dev_pm_ops = {
2349 .suspend = musb_suspend,
2350 .resume_noirq = musb_resume_noirq,
2351 .runtime_suspend = musb_runtime_suspend,
2352 .runtime_resume = musb_runtime_resume,
2355 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2357 #define MUSB_DEV_PM_OPS NULL
2360 static struct platform_driver musb_driver = {
2362 .name = (char *)musb_driver_name,
2363 .bus = &platform_bus_type,
2364 .owner = THIS_MODULE,
2365 .pm = MUSB_DEV_PM_OPS,
2367 .remove = __exit_p(musb_remove),
2368 .shutdown = musb_shutdown,
2371 /*-------------------------------------------------------------------------*/
2373 static int __init musb_init(void)
2378 pr_info("%s: version " MUSB_VERSION ", "
2381 "otg (peripheral+host)",
2383 return platform_driver_probe(&musb_driver, musb_probe);
2386 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2387 * and before usb gadget and host-side drivers start to register
2389 fs_initcall(musb_init);
2391 static void __exit musb_cleanup(void)
2393 platform_driver_unregister(&musb_driver);
2395 module_exit(musb_cleanup);