2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
142 pm_runtime_get_sync(otg->io_dev);
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173 pm_runtime_put(otg->io_dev);
178 static int musb_ulpi_write(struct otg_transceiver *otg,
179 u32 offset, u32 data)
181 void __iomem *addr = otg->io_priv;
187 pm_runtime_get_sync(otg->io_dev);
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
212 pm_runtime_put(otg->io_dev);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct otg_io_access_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
226 /*-------------------------------------------------------------------------*/
228 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
231 * Load an endpoint's FIFO
233 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235 struct musb *musb = hw_ep->musb;
236 void __iomem *fifo = hw_ep->fifo;
240 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
241 'T', hw_ep->epnum, fifo, len, src);
243 /* we can't assume unaligned reads work */
244 if (likely((0x01 & (unsigned long) src) == 0)) {
247 /* best case is 32bit-aligned source address */
248 if ((0x02 & (unsigned long) src) == 0) {
250 writesl(fifo, src + index, len >> 2);
251 index += len & ~0x03;
254 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 writesw(fifo, src + index, len >> 1);
260 index += len & ~0x01;
264 musb_writeb(fifo, 0, src[index]);
267 writesb(fifo, src, len);
271 #if !defined(CONFIG_USB_MUSB_AM35X)
273 * Unload an endpoint's FIFO
275 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
277 struct musb *musb = hw_ep->musb;
278 void __iomem *fifo = hw_ep->fifo;
280 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
281 'R', hw_ep->epnum, fifo, len, dst);
283 /* we can't assume unaligned writes work */
284 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 /* best case is 32bit-aligned destination address */
288 if ((0x02 & (unsigned long) dst) == 0) {
290 readsl(fifo, dst, len >> 2);
294 *(u16 *)&dst[index] = musb_readw(fifo, 0);
299 readsw(fifo, dst, len >> 1);
304 dst[index] = musb_readb(fifo, 0);
307 readsb(fifo, dst, len);
312 #endif /* normal PIO */
315 /*-------------------------------------------------------------------------*/
317 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
318 static const u8 musb_test_packet[53] = {
319 /* implicit SYNC then DATA0 to start */
322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
327 /* JJJJJJJKKKKKKK x8 */
328 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
331 /* JKKKKKKK x10, JK */
332 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334 /* implicit CRC16 then EOP to end */
337 void musb_load_testpacket(struct musb *musb)
339 void __iomem *regs = musb->endpoints[0].regs;
341 musb_ep_select(musb->mregs, 0);
342 musb_write_fifo(musb->control_ep,
343 sizeof(musb_test_packet), musb_test_packet);
344 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
347 /*-------------------------------------------------------------------------*/
350 * Handles OTG hnp timeouts, such as b_ase0_brst
352 void musb_otg_timer_func(unsigned long data)
354 struct musb *musb = (struct musb *)data;
357 spin_lock_irqsave(&musb->lock, flags);
358 switch (musb->xceiv->state) {
359 case OTG_STATE_B_WAIT_ACON:
360 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
361 musb_g_disconnect(musb);
362 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
365 case OTG_STATE_A_SUSPEND:
366 case OTG_STATE_A_WAIT_BCON:
367 dev_dbg(musb->controller, "HNP: %s timeout\n",
368 otg_state_string(musb->xceiv->state));
369 musb_platform_set_vbus(musb, 0);
370 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
373 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
374 otg_state_string(musb->xceiv->state));
376 musb->ignore_disconnect = 0;
377 spin_unlock_irqrestore(&musb->lock, flags);
381 * Stops the HNP transition. Caller must take care of locking.
383 void musb_hnp_stop(struct musb *musb)
385 struct usb_hcd *hcd = musb_to_hcd(musb);
386 void __iomem *mbase = musb->mregs;
389 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
391 switch (musb->xceiv->state) {
392 case OTG_STATE_A_PERIPHERAL:
393 musb_g_disconnect(musb);
394 dev_dbg(musb->controller, "HNP: back to %s\n",
395 otg_state_string(musb->xceiv->state));
397 case OTG_STATE_B_HOST:
398 dev_dbg(musb->controller, "HNP: Disabling HR\n");
399 hcd->self.is_b_host = 0;
400 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
402 reg = musb_readb(mbase, MUSB_POWER);
403 reg |= MUSB_POWER_SUSPENDM;
404 musb_writeb(mbase, MUSB_POWER, reg);
405 /* REVISIT: Start SESSION_REQUEST here? */
408 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
409 otg_state_string(musb->xceiv->state));
413 * When returning to A state after HNP, avoid hub_port_rebounce(),
414 * which cause occasional OPT A "Did not receive reset after connect"
417 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
421 * Interrupt Service Routine to record USB "global" interrupts.
422 * Since these do not happen often and signify things of
423 * paramount importance, it seems OK to check them individually;
424 * the order of the tests is specified in the manual
426 * @param musb instance pointer
427 * @param int_usb register contents
432 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
435 irqreturn_t handled = IRQ_NONE;
437 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
440 /* in host mode, the peripheral may issue remote wakeup.
441 * in peripheral mode, the host may resume the link.
442 * spurious RESUME irqs happen too, paired with SUSPEND.
444 if (int_usb & MUSB_INTR_RESUME) {
445 handled = IRQ_HANDLED;
446 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
448 if (devctl & MUSB_DEVCTL_HM) {
449 void __iomem *mbase = musb->mregs;
451 switch (musb->xceiv->state) {
452 case OTG_STATE_A_SUSPEND:
453 /* remote wakeup? later, GetPortStatus
454 * will stop RESUME signaling
457 if (power & MUSB_POWER_SUSPENDM) {
459 int_usb &= ~MUSB_INTR_SUSPEND;
460 dev_err(musb->controller, "Spurious SUSPENDM\n");
464 power &= ~MUSB_POWER_SUSPENDM;
465 musb_writeb(mbase, MUSB_POWER,
466 power | MUSB_POWER_RESUME);
468 musb->port1_status |=
469 (USB_PORT_STAT_C_SUSPEND << 16)
470 | MUSB_PORT_STAT_RESUME;
471 musb->rh_timer = jiffies
472 + msecs_to_jiffies(20);
474 musb->xceiv->state = OTG_STATE_A_HOST;
476 usb_hcd_resume_root_hub(musb_to_hcd(musb));
478 case OTG_STATE_B_WAIT_ACON:
479 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
484 WARNING("bogus %s RESUME (%s)\n",
486 otg_state_string(musb->xceiv->state));
489 switch (musb->xceiv->state) {
490 case OTG_STATE_A_SUSPEND:
491 /* possibly DISCONNECT is upcoming */
492 musb->xceiv->state = OTG_STATE_A_HOST;
493 usb_hcd_resume_root_hub(musb_to_hcd(musb));
495 case OTG_STATE_B_WAIT_ACON:
496 case OTG_STATE_B_PERIPHERAL:
497 /* disconnect while suspended? we may
498 * not get a disconnect irq...
500 if ((devctl & MUSB_DEVCTL_VBUS)
501 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
503 if (!(int_usb & MUSB_INTR_DISCONNECT))
504 dev_err(musb->controller,
505 "disconnect while suspended?\n");
506 int_usb |= MUSB_INTR_DISCONNECT;
507 int_usb &= ~MUSB_INTR_SUSPEND;
512 case OTG_STATE_B_IDLE:
513 if (int_usb & MUSB_INTR_SUSPEND)
514 dev_err(musb->controller,
515 "bogus suspend+resume?\n");
516 int_usb &= ~MUSB_INTR_SUSPEND;
519 WARNING("bogus %s RESUME (%s)\n",
521 otg_state_string(musb->xceiv->state));
526 /* see manual for the order of the tests */
527 if (int_usb & MUSB_INTR_SESSREQ) {
528 void __iomem *mbase = musb->mregs;
530 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
531 && (devctl & MUSB_DEVCTL_BDEVICE)) {
532 dev_dbg(musb->controller, "SessReq while on B state\n");
536 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
537 otg_state_string(musb->xceiv->state));
539 /* IRQ arrives from ID pin sense or (later, if VBUS power
540 * is removed) SRP. responses are time critical:
541 * - turn on VBUS (with silicon-specific mechanism)
542 * - go through A_WAIT_VRISE
543 * - ... to A_WAIT_BCON.
544 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
546 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
547 musb->ep0_stage = MUSB_EP0_START;
548 musb->xceiv->state = OTG_STATE_A_IDLE;
550 musb_platform_set_vbus(musb, 1);
552 handled = IRQ_HANDLED;
555 if (int_usb & MUSB_INTR_VBUSERROR) {
558 /* During connection as an A-Device, we may see a short
559 * current spikes causing voltage drop, because of cable
560 * and peripheral capacitance combined with vbus draw.
561 * (So: less common with truly self-powered devices, where
562 * vbus doesn't act like a power supply.)
564 * Such spikes are short; usually less than ~500 usec, max
565 * of ~2 msec. That is, they're not sustained overcurrent
566 * errors, though they're reported using VBUSERROR irqs.
568 * Workarounds: (a) hardware: use self powered devices.
569 * (b) software: ignore non-repeated VBUS errors.
571 * REVISIT: do delays from lots of DEBUG_KERNEL checks
572 * make trouble here, keeping VBUS < 4.4V ?
574 switch (musb->xceiv->state) {
575 case OTG_STATE_A_HOST:
576 /* recovery is dicey once we've gotten past the
577 * initial stages of enumeration, but if VBUS
578 * stayed ok at the other end of the link, and
579 * another reset is due (at least for high speed,
580 * to redo the chirp etc), it might work OK...
582 case OTG_STATE_A_WAIT_BCON:
583 case OTG_STATE_A_WAIT_VRISE:
584 if (musb->vbuserr_retry) {
585 void __iomem *mbase = musb->mregs;
587 musb->vbuserr_retry--;
589 devctl |= MUSB_DEVCTL_SESSION;
590 musb_writeb(mbase, MUSB_DEVCTL, devctl);
592 musb->port1_status |=
593 USB_PORT_STAT_OVERCURRENT
594 | (USB_PORT_STAT_C_OVERCURRENT << 16);
601 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
602 "VBUS_ERROR in %s (%02x, %02x, %s), retry #%d, port1 %08x\n",
603 otg_state_string(musb->xceiv->state),
606 switch (devctl & MUSB_DEVCTL_VBUS) {
607 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
608 s = "<SessEnd"; break;
609 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
610 s = "<AValid"; break;
611 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
612 s = "<VBusValid"; break;
613 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
617 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
620 /* go through A_WAIT_VFALL then start a new session */
622 musb_platform_set_vbus(musb, 0);
623 handled = IRQ_HANDLED;
626 if (int_usb & MUSB_INTR_SUSPEND) {
627 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
628 otg_state_string(musb->xceiv->state), devctl, power);
629 handled = IRQ_HANDLED;
631 switch (musb->xceiv->state) {
632 case OTG_STATE_A_PERIPHERAL:
633 /* We also come here if the cable is removed, since
634 * this silicon doesn't report ID-no-longer-grounded.
636 * We depend on T(a_wait_bcon) to shut us down, and
637 * hope users don't do anything dicey during this
638 * undesired detour through A_WAIT_BCON.
641 usb_hcd_resume_root_hub(musb_to_hcd(musb));
642 musb_root_disconnect(musb);
643 musb_platform_try_idle(musb, jiffies
644 + msecs_to_jiffies(musb->a_wait_bcon
645 ? : OTG_TIME_A_WAIT_BCON));
648 case OTG_STATE_B_IDLE:
649 if (!musb->is_active)
651 case OTG_STATE_B_PERIPHERAL:
652 musb_g_suspend(musb);
653 musb->is_active = is_otg_enabled(musb)
654 && musb->xceiv->gadget->b_hnp_enable;
655 if (musb->is_active) {
656 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
657 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
658 mod_timer(&musb->otg_timer, jiffies
660 OTG_TIME_B_ASE0_BRST));
663 case OTG_STATE_A_WAIT_BCON:
664 if (musb->a_wait_bcon != 0)
665 musb_platform_try_idle(musb, jiffies
666 + msecs_to_jiffies(musb->a_wait_bcon));
668 case OTG_STATE_A_HOST:
669 musb->xceiv->state = OTG_STATE_A_SUSPEND;
670 musb->is_active = is_otg_enabled(musb)
671 && musb->xceiv->host->b_hnp_enable;
673 case OTG_STATE_B_HOST:
674 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
675 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
678 /* "should not happen" */
683 switch (musb->xceiv->state) {
684 case OTG_STATE_B_IDLE:
685 case OTG_STATE_B_PERIPHERAL:
686 cancel_delayed_work(&musb->vbus_workaround_work);
687 schedule_delayed_work(&musb->vbus_workaround_work, HZ / 2);
693 if (int_usb & MUSB_INTR_CONNECT) {
694 struct usb_hcd *hcd = musb_to_hcd(musb);
696 handled = IRQ_HANDLED;
698 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
700 musb->ep0_stage = MUSB_EP0_START;
702 /* flush endpoints when transitioning from Device Mode */
703 if (is_peripheral_active(musb)) {
704 /* REVISIT HNP; just force disconnect */
706 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
707 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
708 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
709 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
710 |USB_PORT_STAT_HIGH_SPEED
711 |USB_PORT_STAT_ENABLE
713 musb->port1_status |= USB_PORT_STAT_CONNECTION
714 |(USB_PORT_STAT_C_CONNECTION << 16);
716 /* high vs full speed is just a guess until after reset */
717 if (devctl & MUSB_DEVCTL_LSDEV)
718 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
720 /* indicate new connection to OTG machine */
721 switch (musb->xceiv->state) {
722 case OTG_STATE_B_PERIPHERAL:
723 if (int_usb & MUSB_INTR_SUSPEND) {
724 dev_err(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
725 int_usb &= ~MUSB_INTR_SUSPEND;
728 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
730 case OTG_STATE_B_WAIT_ACON:
731 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
733 musb->xceiv->state = OTG_STATE_B_HOST;
734 hcd->self.is_b_host = 1;
735 musb->ignore_disconnect = 0;
736 del_timer(&musb->otg_timer);
739 if ((devctl & MUSB_DEVCTL_VBUS)
740 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
741 musb->xceiv->state = OTG_STATE_A_HOST;
742 hcd->self.is_b_host = 0;
747 /* poke the root hub */
750 usb_hcd_poll_rh_status(hcd);
752 usb_hcd_resume_root_hub(hcd);
754 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
755 otg_state_string(musb->xceiv->state), devctl);
758 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
759 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
760 otg_state_string(musb->xceiv->state),
761 MUSB_MODE(musb), devctl);
762 handled = IRQ_HANDLED;
764 switch (musb->xceiv->state) {
765 case OTG_STATE_A_HOST:
766 case OTG_STATE_A_SUSPEND:
767 usb_hcd_resume_root_hub(musb_to_hcd(musb));
768 musb_root_disconnect(musb);
769 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
770 musb_platform_try_idle(musb, jiffies
771 + msecs_to_jiffies(musb->a_wait_bcon));
773 case OTG_STATE_B_HOST:
774 /* REVISIT this behaves for "real disconnect"
775 * cases; make sure the other transitions from
776 * from B_HOST act right too. The B_HOST code
777 * in hnp_stop() is currently not used...
779 musb_root_disconnect(musb);
780 musb_to_hcd(musb)->self.is_b_host = 0;
781 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
783 musb_g_disconnect(musb);
785 case OTG_STATE_A_PERIPHERAL:
787 musb_root_disconnect(musb);
789 case OTG_STATE_B_WAIT_ACON:
791 case OTG_STATE_B_PERIPHERAL:
792 case OTG_STATE_B_IDLE:
793 musb_g_disconnect(musb);
796 WARNING("unhandled DISCONNECT transition (%s)\n",
797 otg_state_string(musb->xceiv->state));
802 /* mentor saves a bit: bus reset and babble share the same irq.
803 * only host sees babble; only peripheral sees bus reset.
805 if (int_usb & MUSB_INTR_RESET) {
806 handled = IRQ_HANDLED;
807 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
809 * Looks like non-HS BABBLE can be ignored, but
810 * HS BABBLE is an error condition. For HS the solution
811 * is to avoid babble in the first place and fix what
812 * caused BABBLE. When HS BABBLE happens we can only
815 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
816 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
818 ERR("Stopping host session -- babble\n");
819 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
821 } else if (is_peripheral_capable()) {
822 dev_dbg(musb->controller, "BUS RESET as %s\n",
823 otg_state_string(musb->xceiv->state));
824 switch (musb->xceiv->state) {
825 case OTG_STATE_A_SUSPEND:
826 /* We need to ignore disconnect on suspend
827 * otherwise tusb 2.0 won't reconnect after a
828 * power cycle, which breaks otg compliance.
830 musb->ignore_disconnect = 1;
833 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
834 /* never use invalid T(a_wait_bcon) */
835 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
836 otg_state_string(musb->xceiv->state),
838 mod_timer(&musb->otg_timer, jiffies
839 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
841 case OTG_STATE_A_PERIPHERAL:
842 musb->ignore_disconnect = 0;
843 del_timer(&musb->otg_timer);
846 case OTG_STATE_B_WAIT_ACON:
847 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
848 otg_state_string(musb->xceiv->state));
849 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
852 case OTG_STATE_B_IDLE:
853 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
855 case OTG_STATE_B_PERIPHERAL:
859 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
860 otg_state_string(musb->xceiv->state));
866 /* REVISIT ... this would be for multiplexing periodic endpoints, or
867 * supporting transfer phasing to prevent exceeding ISO bandwidth
868 * limits of a given frame or microframe.
870 * It's not needed for peripheral side, which dedicates endpoints;
871 * though it _might_ use SOF irqs for other purposes.
873 * And it's not currently needed for host side, which also dedicates
874 * endpoints, relies on TX/RX interval registers, and isn't claimed
875 * to support ISO transfers yet.
877 if (int_usb & MUSB_INTR_SOF) {
878 void __iomem *mbase = musb->mregs;
879 struct musb_hw_ep *ep;
883 dev_dbg(musb->controller, "START_OF_FRAME\n");
884 handled = IRQ_HANDLED;
886 /* start any periodic Tx transfers waiting for current frame */
887 frame = musb_readw(mbase, MUSB_FRAME);
888 ep = musb->endpoints;
889 for (epnum = 1; (epnum < musb->nr_endpoints)
890 && (musb->epmask >= (1 << epnum));
893 * FIXME handle framecounter wraps (12 bits)
894 * eliminate duplicated StartUrb logic
896 if (ep->dwWaitFrame >= frame) {
898 pr_debug("SOF --> periodic TX%s on %d\n",
899 ep->tx_channel ? " DMA" : "",
902 musb_h_tx_start(musb, epnum);
904 cppi_hostdma_start(musb, epnum);
906 } /* end of for loop */
910 schedule_work(&musb->irq_work);
915 /*-------------------------------------------------------------------------*/
918 * Program the HDRC to start (enable interrupts, dma, etc.).
920 void musb_start(struct musb *musb)
922 void __iomem *regs = musb->mregs;
923 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
925 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
927 /* Set INT enable registers, enable interrupts */
928 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
929 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
930 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
932 musb_writeb(regs, MUSB_TESTMODE, 0);
934 /* put into basic highspeed mode and start session */
935 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
937 /* ENSUSPEND wedges tusb */
938 /* | MUSB_POWER_ENSUSPEND */
942 devctl = musb_readb(regs, MUSB_DEVCTL);
943 devctl &= ~MUSB_DEVCTL_SESSION;
945 if (is_otg_enabled(musb)) {
946 /* session started after:
947 * (a) ID-grounded irq, host mode;
948 * (b) vbus present/connect IRQ, peripheral mode;
949 * (c) peripheral initiates, using SRP
951 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
954 // devctl |= MUSB_DEVCTL_SESSION;
956 } else if (is_host_enabled(musb)) {
957 /* assume ID pin is hard-wired to ground */
958 devctl |= MUSB_DEVCTL_SESSION;
960 } else /* peripheral is enabled */ {
961 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
964 musb_platform_enable(musb);
965 musb_writeb(regs, MUSB_DEVCTL, devctl);
969 static void musb_generic_disable(struct musb *musb)
971 void __iomem *mbase = musb->mregs;
974 /* disable interrupts */
975 musb_writeb(mbase, MUSB_INTRUSBE, 0);
976 musb_writew(mbase, MUSB_INTRTXE, 0);
977 musb_writew(mbase, MUSB_INTRRXE, 0);
980 musb_writeb(mbase, MUSB_DEVCTL, 0);
982 /* flush pending interrupts */
983 temp = musb_readb(mbase, MUSB_INTRUSB);
984 temp = musb_readw(mbase, MUSB_INTRTX);
985 temp = musb_readw(mbase, MUSB_INTRRX);
990 * Make the HDRC stop (disable interrupts, etc.);
991 * reversible by musb_start
992 * called on gadget driver unregister
993 * with controller locked, irqs blocked
994 * acts as a NOP unless some role activated the hardware
996 void musb_stop(struct musb *musb)
998 /* stop IRQs, timers, ... */
999 musb_platform_disable(musb);
1000 musb_generic_disable(musb);
1001 dev_dbg(musb->controller, "HDRC disabled\n");
1004 * - mark host and/or peripheral drivers unusable/inactive
1005 * - disable DMA (and enable it in HdrcStart)
1006 * - make sure we can musb_start() after musb_stop(); with
1007 * OTG mode, gadget driver module rmmod/modprobe cycles that
1010 musb_platform_try_idle(musb, 0);
1013 static void musb_shutdown(struct platform_device *pdev)
1015 struct musb *musb = dev_to_musb(&pdev->dev);
1016 unsigned long flags;
1018 pm_runtime_get_sync(musb->controller);
1020 musb_gadget_cleanup(musb);
1022 spin_lock_irqsave(&musb->lock, flags);
1023 musb_platform_disable(musb);
1024 musb_generic_disable(musb);
1025 spin_unlock_irqrestore(&musb->lock, flags);
1027 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1028 usb_remove_hcd(musb_to_hcd(musb));
1029 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1030 musb_platform_exit(musb);
1032 pm_runtime_put(musb->controller);
1034 cancel_delayed_work(&musb->vbus_workaround_work);
1036 /* FIXME power down */
1040 /*-------------------------------------------------------------------------*/
1043 * The silicon either has hard-wired endpoint configurations, or else
1044 * "dynamic fifo" sizing. The driver has support for both, though at this
1045 * writing only the dynamic sizing is very well tested. Since we switched
1046 * away from compile-time hardware parameters, we can no longer rely on
1047 * dead code elimination to leave only the relevant one in the object file.
1049 * We don't currently use dynamic fifo setup capability to do anything
1050 * more than selecting one of a bunch of predefined configurations.
1052 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1053 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1054 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1055 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1056 || defined(CONFIG_USB_MUSB_AM35X) \
1057 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1058 static ushort __initdata fifo_mode = 4;
1059 #elif defined(CONFIG_USB_MUSB_UX500) \
1060 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1061 static ushort __initdata fifo_mode = 5;
1063 static ushort __initdata fifo_mode = 2;
1066 /* "modprobe ... fifo_mode=1" etc */
1067 module_param(fifo_mode, ushort, 0);
1068 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1071 * tables defining fifo_mode values. define more if you like.
1072 * for host side, make sure both halves of ep1 are set up.
1075 /* mode 0 - fits in 2KB */
1076 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1077 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1080 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1081 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1084 /* mode 1 - fits in 4KB */
1085 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1086 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1087 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1088 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1089 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1090 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1093 /* mode 2 - fits in 4KB */
1094 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1095 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1096 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1097 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1098 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1099 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1100 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1103 /* mode 3 - fits in 4KB */
1104 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1105 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1106 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1107 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1110 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1113 /* mode 4 - fits in 16KB */
1114 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1115 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1118 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1119 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1120 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1121 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1134 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1135 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1136 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1137 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1138 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1139 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1140 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1141 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1144 /* mode 5 - fits in 8KB */
1145 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1146 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1147 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1148 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1149 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1150 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1151 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1152 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1153 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1154 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1155 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1156 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1157 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1158 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1159 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1160 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1161 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1162 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1163 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1164 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1165 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1166 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1167 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1168 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1169 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1170 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1171 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1172 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1176 * configure a fifo; for non-shared endpoints, this may be called
1177 * once for a tx fifo and once for an rx fifo.
1179 * returns negative errno or offset for next fifo.
1182 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1183 const struct musb_fifo_cfg *cfg, u16 offset)
1185 void __iomem *mbase = musb->mregs;
1187 u16 maxpacket = cfg->maxpacket;
1188 u16 c_off = offset >> 3;
1191 /* expect hw_ep has already been zero-initialized */
1193 size = ffs(max(maxpacket, (u16) 8)) - 1;
1194 maxpacket = 1 << size;
1197 if (cfg->mode == BUF_DOUBLE) {
1198 if ((offset + (maxpacket << 1)) >
1199 (1 << (musb->config->ram_bits + 2)))
1201 c_size |= MUSB_FIFOSZ_DPB;
1203 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1207 /* configure the FIFO */
1208 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1210 /* EP0 reserved endpoint for control, bidirectional;
1211 * EP1 reserved for bulk, two unidirection halves.
1213 if (hw_ep->epnum == 1)
1214 musb->bulk_ep = hw_ep;
1215 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1216 switch (cfg->style) {
1218 musb_write_txfifosz(mbase, c_size);
1219 musb_write_txfifoadd(mbase, c_off);
1220 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1221 hw_ep->max_packet_sz_tx = maxpacket;
1224 musb_write_rxfifosz(mbase, c_size);
1225 musb_write_rxfifoadd(mbase, c_off);
1226 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1227 hw_ep->max_packet_sz_rx = maxpacket;
1230 musb_write_txfifosz(mbase, c_size);
1231 musb_write_txfifoadd(mbase, c_off);
1232 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1233 hw_ep->max_packet_sz_rx = maxpacket;
1235 musb_write_rxfifosz(mbase, c_size);
1236 musb_write_rxfifoadd(mbase, c_off);
1237 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1238 hw_ep->max_packet_sz_tx = maxpacket;
1240 hw_ep->is_shared_fifo = true;
1244 /* NOTE rx and tx endpoint irqs aren't managed separately,
1245 * which happens to be ok
1247 musb->epmask |= (1 << hw_ep->epnum);
1249 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1252 static struct musb_fifo_cfg __initdata ep0_cfg = {
1253 .style = FIFO_RXTX, .maxpacket = 64,
1256 static int __init ep_config_from_table(struct musb *musb)
1258 const struct musb_fifo_cfg *cfg;
1261 struct musb_hw_ep *hw_ep = musb->endpoints;
1263 if (musb->config->fifo_cfg) {
1264 cfg = musb->config->fifo_cfg;
1265 n = musb->config->fifo_cfg_size;
1269 switch (fifo_mode) {
1275 n = ARRAY_SIZE(mode_0_cfg);
1279 n = ARRAY_SIZE(mode_1_cfg);
1283 n = ARRAY_SIZE(mode_2_cfg);
1287 n = ARRAY_SIZE(mode_3_cfg);
1291 n = ARRAY_SIZE(mode_4_cfg);
1295 n = ARRAY_SIZE(mode_5_cfg);
1299 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1300 musb_driver_name, fifo_mode);
1304 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1305 /* assert(offset > 0) */
1307 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1308 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1311 for (i = 0; i < n; i++) {
1312 u8 epn = cfg->hw_ep_num;
1314 if (epn >= musb->config->num_eps) {
1315 pr_debug("%s: invalid ep %d\n",
1316 musb_driver_name, epn);
1319 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1321 pr_debug("%s: mem overrun, ep %d\n",
1322 musb_driver_name, epn);
1326 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1329 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1331 n + 1, musb->config->num_eps * 2 - 1,
1332 offset, (1 << (musb->config->ram_bits + 2)));
1334 if (!musb->bulk_ep) {
1335 pr_debug("%s: missing bulk\n", musb_driver_name);
1344 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1345 * @param musb the controller
1347 static int __init ep_config_from_hw(struct musb *musb)
1350 struct musb_hw_ep *hw_ep;
1351 void *mbase = musb->mregs;
1354 dev_dbg(musb->controller, "<== static silicon ep config\n");
1356 /* FIXME pick up ep0 maxpacket size */
1358 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1359 musb_ep_select(mbase, epnum);
1360 hw_ep = musb->endpoints + epnum;
1362 ret = musb_read_fifosize(musb, hw_ep, epnum);
1366 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1368 /* pick an RX/TX endpoint for bulk */
1369 if (hw_ep->max_packet_sz_tx < 512
1370 || hw_ep->max_packet_sz_rx < 512)
1373 /* REVISIT: this algorithm is lazy, we should at least
1374 * try to pick a double buffered endpoint.
1378 musb->bulk_ep = hw_ep;
1381 if (!musb->bulk_ep) {
1382 pr_debug("%s: missing bulk\n", musb_driver_name);
1389 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1391 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1392 * configure endpoints, or take their config from silicon
1394 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1398 char aInfo[90], aRevision[32], aDate[12];
1399 void __iomem *mbase = musb->mregs;
1403 /* log core options (read using indexed model) */
1404 reg = musb_read_configdata(mbase);
1406 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1407 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1408 strcat(aInfo, ", dyn FIFOs");
1409 musb->dyn_fifo = true;
1411 if (reg & MUSB_CONFIGDATA_MPRXE) {
1412 strcat(aInfo, ", bulk combine");
1413 musb->bulk_combine = true;
1415 if (reg & MUSB_CONFIGDATA_MPTXE) {
1416 strcat(aInfo, ", bulk split");
1417 musb->bulk_split = true;
1419 if (reg & MUSB_CONFIGDATA_HBRXE) {
1420 strcat(aInfo, ", HB-ISO Rx");
1421 musb->hb_iso_rx = true;
1423 if (reg & MUSB_CONFIGDATA_HBTXE) {
1424 strcat(aInfo, ", HB-ISO Tx");
1425 musb->hb_iso_tx = true;
1427 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1428 strcat(aInfo, ", SoftConn");
1430 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1431 musb_driver_name, reg, aInfo);
1434 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1435 musb->is_multipoint = 1;
1438 musb->is_multipoint = 0;
1440 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1442 "%s: kernel must blacklist external hubs\n",
1447 /* log release info */
1448 musb->hwvers = musb_read_hwvers(mbase);
1449 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1450 MUSB_HWVERS_MINOR(musb->hwvers),
1451 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1452 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1453 musb_driver_name, type, aRevision, aDate);
1456 musb_configure_ep0(musb);
1458 /* discover endpoint configuration */
1459 musb->nr_endpoints = 1;
1463 status = ep_config_from_table(musb);
1465 status = ep_config_from_hw(musb);
1470 /* finish init, and print endpoint config */
1471 for (i = 0; i < musb->nr_endpoints; i++) {
1472 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1474 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1475 #ifdef CONFIG_USB_MUSB_TUSB6010
1476 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1477 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1478 hw_ep->fifo_sync_va =
1479 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1482 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1484 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1487 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1488 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1489 hw_ep->rx_reinit = 1;
1490 hw_ep->tx_reinit = 1;
1492 if (hw_ep->max_packet_sz_tx) {
1493 dev_dbg(musb->controller,
1494 "%s: hw_ep %d%s, %smax %d\n",
1495 musb_driver_name, i,
1496 hw_ep->is_shared_fifo ? "shared" : "tx",
1497 hw_ep->tx_double_buffered
1498 ? "doublebuffer, " : "",
1499 hw_ep->max_packet_sz_tx);
1501 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1502 dev_dbg(musb->controller,
1503 "%s: hw_ep %d%s, %smax %d\n",
1504 musb_driver_name, i,
1506 hw_ep->rx_double_buffered
1507 ? "doublebuffer, " : "",
1508 hw_ep->max_packet_sz_rx);
1510 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1511 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1517 /*-------------------------------------------------------------------------*/
1519 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1520 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1522 static irqreturn_t generic_interrupt(int irq, void *__hci)
1524 unsigned long flags;
1525 irqreturn_t retval = IRQ_NONE;
1526 struct musb *musb = __hci;
1529 spin_lock_irqsave(&musb->lock, flags);
1531 for (i = 0; i < 8; i++) {
1532 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1533 /* SOF is not enabled, but status is still often set */
1534 musb->int_usb &= ~MUSB_INTR_SOF;
1535 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1536 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1538 if (musb->int_usb || musb->int_tx || musb->int_rx)
1539 retval = musb_interrupt(musb);
1544 spin_unlock_irqrestore(&musb->lock, flags);
1550 #define generic_interrupt NULL
1554 * handle all the irqs defined by the HDRC core. for now we expect: other
1555 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1556 * will be assigned, and the irq will already have been acked.
1558 * called in irq context with spinlock held, irqs blocked
1560 irqreturn_t musb_interrupt(struct musb *musb)
1562 irqreturn_t retval = IRQ_NONE;
1567 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1568 power = musb_readb(musb->mregs, MUSB_POWER);
1570 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1571 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1572 musb->int_usb, musb->int_tx, musb->int_rx);
1574 /* the core can interrupt us for multiple reasons; docs have
1575 * a generic interrupt flowchart to follow
1578 retval |= musb_stage0_irq(musb, musb->int_usb,
1581 /* "stage 1" is handling endpoint irqs */
1583 /* handle endpoint 0 first */
1584 if (musb->int_tx & 1) {
1585 if (devctl & MUSB_DEVCTL_HM)
1586 retval |= musb_h_ep0_irq(musb);
1588 retval |= musb_g_ep0_irq(musb);
1591 /* RX on endpoints 1-15 */
1592 reg = musb->int_rx >> 1;
1596 /* musb_ep_select(musb->mregs, ep_num); */
1597 /* REVISIT just retval = ep->rx_irq(...) */
1598 retval = IRQ_HANDLED;
1599 if (devctl & MUSB_DEVCTL_HM) {
1600 if (is_host_capable())
1601 musb_host_rx(musb, ep_num);
1603 if (is_peripheral_capable())
1604 musb_g_rx(musb, ep_num);
1612 /* TX on endpoints 1-15 */
1613 reg = musb->int_tx >> 1;
1617 /* musb_ep_select(musb->mregs, ep_num); */
1618 /* REVISIT just retval |= ep->tx_irq(...) */
1619 retval = IRQ_HANDLED;
1620 if (devctl & MUSB_DEVCTL_HM) {
1621 if (is_host_capable())
1622 musb_host_tx(musb, ep_num);
1624 if (is_peripheral_capable())
1625 musb_g_tx(musb, ep_num);
1634 EXPORT_SYMBOL_GPL(musb_interrupt);
1636 #ifndef CONFIG_MUSB_PIO_ONLY
1637 static int __initdata use_dma = 1;
1639 /* "modprobe ... use_dma=0" etc */
1640 module_param(use_dma, bool, 0);
1641 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1643 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1645 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1647 /* called with controller lock already held */
1650 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1651 if (!is_cppi_enabled()) {
1653 if (devctl & MUSB_DEVCTL_HM)
1654 musb_h_ep0_irq(musb);
1656 musb_g_ep0_irq(musb);
1660 /* endpoints 1..15 */
1662 if (devctl & MUSB_DEVCTL_HM) {
1663 if (is_host_capable())
1664 musb_host_tx(musb, epnum);
1666 if (is_peripheral_capable())
1667 musb_g_tx(musb, epnum);
1671 if (devctl & MUSB_DEVCTL_HM) {
1672 if (is_host_capable())
1673 musb_host_rx(musb, epnum);
1675 if (is_peripheral_capable())
1676 musb_g_rx(musb, epnum);
1686 /*-------------------------------------------------------------------------*/
1691 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1697 spin_lock_irqsave(&musb->lock, flags);
1698 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1699 spin_unlock_irqrestore(&musb->lock, flags);
1705 musb_mode_store(struct device *dev, struct device_attribute *attr,
1706 const char *buf, size_t n)
1708 struct musb *musb = dev_to_musb(dev);
1709 unsigned long flags;
1712 spin_lock_irqsave(&musb->lock, flags);
1713 if (sysfs_streq(buf, "host"))
1714 status = musb_platform_set_mode(musb, MUSB_HOST);
1715 else if (sysfs_streq(buf, "peripheral"))
1716 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1717 else if (sysfs_streq(buf, "otg"))
1718 status = musb_platform_set_mode(musb, MUSB_OTG);
1721 spin_unlock_irqrestore(&musb->lock, flags);
1723 return (status == 0) ? n : status;
1725 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1728 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1729 const char *buf, size_t n)
1731 struct musb *musb = dev_to_musb(dev);
1732 unsigned long flags;
1735 if (sscanf(buf, "%lu", &val) < 1) {
1736 dev_err(dev, "Invalid VBUS timeout ms value\n");
1740 spin_lock_irqsave(&musb->lock, flags);
1741 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1742 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1743 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1744 musb->is_active = 0;
1745 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1746 spin_unlock_irqrestore(&musb->lock, flags);
1752 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1754 struct musb *musb = dev_to_musb(dev);
1755 unsigned long flags;
1759 spin_lock_irqsave(&musb->lock, flags);
1760 val = musb->a_wait_bcon;
1761 /* FIXME get_vbus_status() is normally #defined as false...
1762 * and is effectively TUSB-specific.
1764 vbus = musb_platform_get_vbus_status(musb);
1765 spin_unlock_irqrestore(&musb->lock, flags);
1767 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1768 vbus ? "on" : "off", val);
1770 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1772 /* Gadget drivers can't know that a host is connected so they might want
1773 * to start SRP, but users can. This allows userspace to trigger SRP.
1776 musb_srp_store(struct device *dev, struct device_attribute *attr,
1777 const char *buf, size_t n)
1779 struct musb *musb = dev_to_musb(dev);
1782 if (sscanf(buf, "%hu", &srp) != 1
1784 dev_err(dev, "SRP: Value must be 1\n");
1789 musb_g_wakeup(musb);
1793 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1795 static struct attribute *musb_attributes[] = {
1796 &dev_attr_mode.attr,
1797 &dev_attr_vbus.attr,
1802 static const struct attribute_group musb_attr_group = {
1803 .attrs = musb_attributes,
1808 /* Only used to provide driver mode change events */
1809 static void musb_irq_work(struct work_struct *data)
1811 struct musb *musb = container_of(data, struct musb, irq_work);
1812 static int old_state;
1814 if (musb->xceiv->state != old_state) {
1815 old_state = musb->xceiv->state;
1816 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1820 #include <linux/usb/ulpi.h>
1822 static void musb_vbus_workaround_work(struct work_struct *work)
1824 struct musb *musb = container_of(work, struct musb, vbus_workaround_work.work);
1828 if (musb_ulpi_access.write == NULL)
1831 pm_runtime_get_sync(musb->controller);
1833 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1836 * I don't really know why but VBUS sometimes gets stuck and
1837 * causes session to never end. It would look like some pullup
1838 * is enabled when it shouldn't be on certain PHY states.
1839 * Turning on pulldowns magically drains VBUS to zero and allows
1840 * session to end, so let's do that here.
1842 * XXX: probably better check VBUS on TWL?
1843 * beagle sometimes has session bit set but no VBUS on twl?
1845 if ((musb->xceiv->state == OTG_STATE_B_PERIPHERAL ||
1846 musb->xceiv->state == OTG_STATE_B_IDLE) &&
1847 (devctl & MUSB_DEVCTL_VBUS) != (3 << MUSB_DEVCTL_VBUS_SHIFT) &&
1848 (devctl & MUSB_DEVCTL_VBUS) != (0 << MUSB_DEVCTL_VBUS_SHIFT)) {
1849 dev_dbg(musb->controller, "VBUS workaround..\n");
1850 ret = musb_ulpi_access.write(musb->xceiv, ULPI_SET(ULPI_OTG_CTRL),
1851 ULPI_OTG_CTRL_DM_PULLDOWN | ULPI_OTG_CTRL_DP_PULLDOWN);
1853 // dev_err(musb->controller, "VBUS workaround error\n");
1856 pm_runtime_put(musb->controller);
1859 /* --------------------------------------------------------------------------
1863 static struct musb *__init
1864 allocate_instance(struct device *dev,
1865 struct musb_hdrc_config *config, void __iomem *mbase)
1868 struct musb_hw_ep *ep;
1870 struct usb_hcd *hcd;
1872 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1875 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1877 musb = hcd_to_musb(hcd);
1878 INIT_LIST_HEAD(&musb->control);
1879 INIT_LIST_HEAD(&musb->in_bulk);
1880 INIT_LIST_HEAD(&musb->out_bulk);
1882 hcd->uses_new_polling = 1;
1885 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1886 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1887 dev_set_drvdata(dev, musb);
1888 musb->mregs = mbase;
1889 musb->ctrl_base = mbase;
1890 musb->nIrq = -ENODEV;
1891 musb->config = config;
1892 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1893 for (epnum = 0, ep = musb->endpoints;
1894 epnum < musb->config->num_eps;
1900 musb->controller = dev;
1905 static void musb_free(struct musb *musb)
1907 /* this has multiple entry modes. it handles fault cleanup after
1908 * probe(), where things may be partially set up, as well as rmmod
1909 * cleanup after everything's been de-activated.
1913 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1916 if (musb->nIrq >= 0) {
1918 disable_irq_wake(musb->nIrq);
1919 free_irq(musb->nIrq, musb);
1921 if (is_dma_capable() && musb->dma_controller) {
1922 struct dma_controller *c = musb->dma_controller;
1925 dma_controller_destroy(c);
1928 usb_put_hcd(musb_to_hcd(musb));
1932 * Perform generic per-controller initialization.
1934 * @pDevice: the controller (already clocked, etc)
1936 * @mregs: virtual address of controller registers,
1937 * not yet corrected for platform-specific offsets
1940 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1944 struct musb_hdrc_platform_data *plat = dev->platform_data;
1946 /* The driver might handle more features than the board; OK.
1947 * Fail when the board needs a feature that's not enabled.
1950 dev_dbg(dev, "no platform_data?\n");
1956 musb = allocate_instance(dev, plat->config, ctrl);
1962 pm_runtime_use_autosuspend(musb->controller);
1963 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1964 pm_runtime_enable(musb->controller);
1966 spin_lock_init(&musb->lock);
1967 musb->board_mode = plat->mode;
1968 musb->board_set_power = plat->set_power;
1969 musb->min_power = plat->min_power;
1970 musb->ops = plat->platform_ops;
1972 /* The musb_platform_init() call:
1973 * - adjusts musb->mregs and musb->isr if needed,
1974 * - may initialize an integrated tranceiver
1975 * - initializes musb->xceiv, usually by otg_get_transceiver()
1976 * - stops powering VBUS
1978 * There are various transceiver configurations. Blackfin,
1979 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1980 * external/discrete ones in various flavors (twl4030 family,
1981 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1983 musb->isr = generic_interrupt;
1984 status = musb_platform_init(musb);
1993 if (!musb->xceiv->io_ops) {
1994 musb->xceiv->io_dev = musb->controller;
1995 musb->xceiv->io_priv = musb->mregs;
1996 musb->xceiv->io_ops = &musb_ulpi_access;
1999 #ifndef CONFIG_MUSB_PIO_ONLY
2000 if (use_dma && dev->dma_mask) {
2001 struct dma_controller *c;
2003 c = dma_controller_create(musb, musb->mregs);
2004 musb->dma_controller = c;
2009 /* ideally this would be abstracted in platform setup */
2010 if (!is_dma_capable() || !musb->dma_controller)
2011 dev->dma_mask = NULL;
2013 /* be sure interrupts are disabled before connecting ISR */
2014 musb_platform_disable(musb);
2015 musb_generic_disable(musb);
2017 /* setup musb parts of the core (especially endpoints) */
2018 status = musb_core_init(plat->config->multipoint
2019 ? MUSB_CONTROLLER_MHDRC
2020 : MUSB_CONTROLLER_HDRC, musb);
2024 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2026 /* Init IRQ workqueue before request_irq */
2027 INIT_WORK(&musb->irq_work, musb_irq_work);
2029 INIT_DELAYED_WORK(&musb->vbus_workaround_work, musb_vbus_workaround_work);
2031 /* attach to the IRQ */
2032 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2033 dev_err(dev, "request_irq %d failed!\n", nIrq);
2038 /* FIXME this handles wakeup irqs wrong */
2039 if (enable_irq_wake(nIrq) == 0) {
2041 device_init_wakeup(dev, 1);
2046 /* host side needs more setup */
2047 if (is_host_enabled(musb)) {
2048 struct usb_hcd *hcd = musb_to_hcd(musb);
2050 otg_set_host(musb->xceiv, &hcd->self);
2052 if (is_otg_enabled(musb))
2053 hcd->self.otg_port = 1;
2054 musb->xceiv->host = &hcd->self;
2055 hcd->power_budget = 2 * (plat->power ? : 250);
2057 /* program PHY to use external vBus if required */
2058 if (plat->extvbus) {
2059 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2060 busctl |= MUSB_ULPI_USE_EXTVBUS;
2061 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2065 /* For the host-only role, we can activate right away.
2066 * (We expect the ID pin to be forcibly grounded!!)
2067 * Otherwise, wait till the gadget driver hooks up.
2069 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2070 struct usb_hcd *hcd = musb_to_hcd(musb);
2072 MUSB_HST_MODE(musb);
2073 musb->xceiv->default_a = 1;
2074 musb->xceiv->state = OTG_STATE_A_IDLE;
2076 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2078 hcd->self.uses_pio_for_control = 1;
2079 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2081 musb_readb(musb->mregs, MUSB_DEVCTL),
2082 (musb_readb(musb->mregs, MUSB_DEVCTL)
2083 & MUSB_DEVCTL_BDEVICE
2086 } else /* peripheral is enabled */ {
2087 if (musb->xceiv->default_a) {
2088 MUSB_HST_MODE(musb);
2089 musb->xceiv->state = OTG_STATE_A_IDLE;
2091 MUSB_DEV_MODE(musb);
2092 musb->xceiv->state = OTG_STATE_B_IDLE;
2095 status = musb_gadget_setup(musb);
2097 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2098 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2100 musb_readb(musb->mregs, MUSB_DEVCTL));
2106 pm_runtime_put(musb->controller);
2108 status = musb_init_debugfs(musb);
2113 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2118 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2120 switch (musb->board_mode) {
2121 case MUSB_HOST: s = "Host"; break;
2122 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2123 default: s = "OTG"; break;
2126 (is_dma_capable() && musb->dma_controller)
2133 musb_exit_debugfs(musb);
2136 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2137 usb_remove_hcd(musb_to_hcd(musb));
2139 musb_gadget_cleanup(musb);
2143 device_init_wakeup(dev, 0);
2144 musb_platform_exit(musb);
2147 dev_err(musb->controller,
2148 "musb_init_controller failed with status %d\n", status);
2158 /*-------------------------------------------------------------------------*/
2160 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2161 * bridge to a platform device; this driver then suffices.
2164 #ifndef CONFIG_MUSB_PIO_ONLY
2165 static u64 *orig_dma_mask;
2168 static int __init musb_probe(struct platform_device *pdev)
2170 struct device *dev = &pdev->dev;
2171 int irq = platform_get_irq_byname(pdev, "mc");
2173 struct resource *iomem;
2176 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2177 if (!iomem || irq <= 0)
2180 base = ioremap(iomem->start, resource_size(iomem));
2182 dev_err(dev, "ioremap failed\n");
2186 #ifndef CONFIG_MUSB_PIO_ONLY
2187 /* clobbered by use_dma=n */
2188 orig_dma_mask = dev->dma_mask;
2190 status = musb_init_controller(dev, irq, base);
2197 static int __exit musb_remove(struct platform_device *pdev)
2199 struct musb *musb = dev_to_musb(&pdev->dev);
2200 void __iomem *ctrl_base = musb->ctrl_base;
2202 /* this gets called on rmmod.
2203 * - Host mode: host may still be active
2204 * - Peripheral mode: peripheral is deactivated (or never-activated)
2205 * - OTG mode: both roles are deactivated (or never-activated)
2207 musb_exit_debugfs(musb);
2208 musb_shutdown(pdev);
2212 device_init_wakeup(&pdev->dev, 0);
2213 #ifndef CONFIG_MUSB_PIO_ONLY
2214 pdev->dev.dma_mask = orig_dma_mask;
2221 static void musb_save_context(struct musb *musb)
2224 void __iomem *musb_base = musb->mregs;
2227 if (is_host_enabled(musb)) {
2228 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2229 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2230 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2232 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2233 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2234 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2235 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2236 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2237 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2239 for (i = 0; i < musb->config->num_eps; ++i) {
2240 struct musb_hw_ep *hw_ep;
2242 hw_ep = &musb->endpoints[i];
2250 musb_writeb(musb_base, MUSB_INDEX, i);
2251 musb->context.index_regs[i].txmaxp =
2252 musb_readw(epio, MUSB_TXMAXP);
2253 musb->context.index_regs[i].txcsr =
2254 musb_readw(epio, MUSB_TXCSR);
2255 musb->context.index_regs[i].rxmaxp =
2256 musb_readw(epio, MUSB_RXMAXP);
2257 musb->context.index_regs[i].rxcsr =
2258 musb_readw(epio, MUSB_RXCSR);
2260 if (musb->dyn_fifo) {
2261 musb->context.index_regs[i].txfifoadd =
2262 musb_read_txfifoadd(musb_base);
2263 musb->context.index_regs[i].rxfifoadd =
2264 musb_read_rxfifoadd(musb_base);
2265 musb->context.index_regs[i].txfifosz =
2266 musb_read_txfifosz(musb_base);
2267 musb->context.index_regs[i].rxfifosz =
2268 musb_read_rxfifosz(musb_base);
2270 if (is_host_enabled(musb)) {
2271 musb->context.index_regs[i].txtype =
2272 musb_readb(epio, MUSB_TXTYPE);
2273 musb->context.index_regs[i].txinterval =
2274 musb_readb(epio, MUSB_TXINTERVAL);
2275 musb->context.index_regs[i].rxtype =
2276 musb_readb(epio, MUSB_RXTYPE);
2277 musb->context.index_regs[i].rxinterval =
2278 musb_readb(epio, MUSB_RXINTERVAL);
2280 musb->context.index_regs[i].txfunaddr =
2281 musb_read_txfunaddr(musb_base, i);
2282 musb->context.index_regs[i].txhubaddr =
2283 musb_read_txhubaddr(musb_base, i);
2284 musb->context.index_regs[i].txhubport =
2285 musb_read_txhubport(musb_base, i);
2287 musb->context.index_regs[i].rxfunaddr =
2288 musb_read_rxfunaddr(musb_base, i);
2289 musb->context.index_regs[i].rxhubaddr =
2290 musb_read_rxhubaddr(musb_base, i);
2291 musb->context.index_regs[i].rxhubport =
2292 musb_read_rxhubport(musb_base, i);
2297 static void musb_restore_context(struct musb *musb)
2300 void __iomem *musb_base = musb->mregs;
2301 void __iomem *ep_target_regs;
2304 if (is_host_enabled(musb)) {
2305 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2306 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2307 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2309 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2310 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2311 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2312 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2313 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2315 for (i = 0; i < musb->config->num_eps; ++i) {
2316 struct musb_hw_ep *hw_ep;
2318 hw_ep = &musb->endpoints[i];
2326 musb_writeb(musb_base, MUSB_INDEX, i);
2327 musb_writew(epio, MUSB_TXMAXP,
2328 musb->context.index_regs[i].txmaxp);
2329 musb_writew(epio, MUSB_TXCSR,
2330 musb->context.index_regs[i].txcsr);
2331 musb_writew(epio, MUSB_RXMAXP,
2332 musb->context.index_regs[i].rxmaxp);
2333 musb_writew(epio, MUSB_RXCSR,
2334 musb->context.index_regs[i].rxcsr);
2336 if (musb->dyn_fifo) {
2337 musb_write_txfifosz(musb_base,
2338 musb->context.index_regs[i].txfifosz);
2339 musb_write_rxfifosz(musb_base,
2340 musb->context.index_regs[i].rxfifosz);
2341 musb_write_txfifoadd(musb_base,
2342 musb->context.index_regs[i].txfifoadd);
2343 musb_write_rxfifoadd(musb_base,
2344 musb->context.index_regs[i].rxfifoadd);
2347 if (is_host_enabled(musb)) {
2348 musb_writeb(epio, MUSB_TXTYPE,
2349 musb->context.index_regs[i].txtype);
2350 musb_writeb(epio, MUSB_TXINTERVAL,
2351 musb->context.index_regs[i].txinterval);
2352 musb_writeb(epio, MUSB_RXTYPE,
2353 musb->context.index_regs[i].rxtype);
2354 musb_writeb(epio, MUSB_RXINTERVAL,
2356 musb->context.index_regs[i].rxinterval);
2357 musb_write_txfunaddr(musb_base, i,
2358 musb->context.index_regs[i].txfunaddr);
2359 musb_write_txhubaddr(musb_base, i,
2360 musb->context.index_regs[i].txhubaddr);
2361 musb_write_txhubport(musb_base, i,
2362 musb->context.index_regs[i].txhubport);
2365 musb_read_target_reg_base(i, musb_base);
2367 musb_write_rxfunaddr(ep_target_regs,
2368 musb->context.index_regs[i].rxfunaddr);
2369 musb_write_rxhubaddr(ep_target_regs,
2370 musb->context.index_regs[i].rxhubaddr);
2371 musb_write_rxhubport(ep_target_regs,
2372 musb->context.index_regs[i].rxhubport);
2375 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2378 static int musb_suspend(struct device *dev)
2380 struct musb *musb = dev_to_musb(dev);
2381 unsigned long flags;
2384 spin_lock_irqsave(&musb->lock, flags);
2387 /* FIXME force disconnect unless we know USB will wake
2388 * the system up quickly enough to respond ...
2391 * FIXME: musb must be already runtime suspended at this point.
2392 * If it's not, framework will try to suspend it late when
2393 * i2c will be off, and twl4030 will want to access it for it's
2394 * stuff, causing data abort.
2396 int pm_usage_count =
2397 atomic_read(&musb->controller->power.usage_count);
2398 if (pm_usage_count > 1) {
2399 dev_err(dev, "can't suspend while still active, "
2400 "try removing gadget drivers (usage_count %d)\n",
2406 spin_unlock_irqrestore(&musb->lock, flags);
2410 static int musb_resume_noirq(struct device *dev)
2412 /* for static cmos like DaVinci, register values were preserved
2413 * unless for some reason the whole soc powered down or the USB
2414 * module got reset through the PSC (vs just being disabled).
2419 static int musb_runtime_suspend(struct device *dev)
2421 struct musb *musb = dev_to_musb(dev);
2423 musb_save_context(musb);
2428 static int musb_runtime_resume(struct device *dev)
2430 struct musb *musb = dev_to_musb(dev);
2431 static int first = 1;
2434 * When pm_runtime_get_sync called for the first time in driver
2435 * init, some of the structure is still not initialized which is
2436 * used in restore function. But clock needs to be
2437 * enabled before any register access, so
2438 * pm_runtime_get_sync has to be called.
2439 * Also context restore without save does not make
2443 musb_restore_context(musb);
2449 static const struct dev_pm_ops musb_dev_pm_ops = {
2450 .suspend = musb_suspend,
2451 .resume_noirq = musb_resume_noirq,
2452 .runtime_suspend = musb_runtime_suspend,
2453 .runtime_resume = musb_runtime_resume,
2456 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2458 #define MUSB_DEV_PM_OPS NULL
2461 static struct platform_driver musb_driver = {
2463 .name = (char *)musb_driver_name,
2464 .bus = &platform_bus_type,
2465 .owner = THIS_MODULE,
2466 .pm = MUSB_DEV_PM_OPS,
2468 .remove = __exit_p(musb_remove),
2469 .shutdown = musb_shutdown,
2472 /*-------------------------------------------------------------------------*/
2474 static int __init musb_init(void)
2479 pr_info("%s: version " MUSB_VERSION ", ?dma?, otg (peripheral+host)\n",
2481 return platform_driver_probe(&musb_driver, musb_probe);
2484 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2485 * and before usb gadget and host-side drivers start to register
2487 fs_initcall(musb_init);
2489 static void __exit musb_cleanup(void)
2491 platform_driver_unregister(&musb_driver);
2493 module_exit(musb_cleanup);