2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
142 pm_runtime_get_sync(otg->io_dev);
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173 pm_runtime_put(otg->io_dev);
178 static int musb_ulpi_write(struct otg_transceiver *otg,
179 u32 offset, u32 data)
181 void __iomem *addr = otg->io_priv;
187 pm_runtime_get_sync(otg->io_dev);
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
212 pm_runtime_put(otg->io_dev);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct otg_io_access_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
226 /*-------------------------------------------------------------------------*/
228 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
231 * Load an endpoint's FIFO
233 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235 struct musb *musb = hw_ep->musb;
236 void __iomem *fifo = hw_ep->fifo;
240 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
241 'T', hw_ep->epnum, fifo, len, src);
243 /* we can't assume unaligned reads work */
244 if (likely((0x01 & (unsigned long) src) == 0)) {
247 /* best case is 32bit-aligned source address */
248 if ((0x02 & (unsigned long) src) == 0) {
250 writesl(fifo, src + index, len >> 2);
251 index += len & ~0x03;
254 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 writesw(fifo, src + index, len >> 1);
260 index += len & ~0x01;
264 musb_writeb(fifo, 0, src[index]);
267 writesb(fifo, src, len);
271 #if !defined(CONFIG_USB_MUSB_AM35X)
273 * Unload an endpoint's FIFO
275 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
277 struct musb *musb = hw_ep->musb;
278 void __iomem *fifo = hw_ep->fifo;
280 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
281 'R', hw_ep->epnum, fifo, len, dst);
283 /* we can't assume unaligned writes work */
284 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 /* best case is 32bit-aligned destination address */
288 if ((0x02 & (unsigned long) dst) == 0) {
290 readsl(fifo, dst, len >> 2);
294 *(u16 *)&dst[index] = musb_readw(fifo, 0);
299 readsw(fifo, dst, len >> 1);
304 dst[index] = musb_readb(fifo, 0);
307 readsb(fifo, dst, len);
312 #endif /* normal PIO */
315 /*-------------------------------------------------------------------------*/
317 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
318 static const u8 musb_test_packet[53] = {
319 /* implicit SYNC then DATA0 to start */
322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
327 /* JJJJJJJKKKKKKK x8 */
328 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
331 /* JKKKKKKK x10, JK */
332 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334 /* implicit CRC16 then EOP to end */
337 void musb_load_testpacket(struct musb *musb)
339 void __iomem *regs = musb->endpoints[0].regs;
341 musb_ep_select(musb->mregs, 0);
342 musb_write_fifo(musb->control_ep,
343 sizeof(musb_test_packet), musb_test_packet);
344 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
347 /*-------------------------------------------------------------------------*/
350 * Handles OTG hnp timeouts, such as b_ase0_brst
352 void musb_otg_timer_func(unsigned long data)
354 struct musb *musb = (struct musb *)data;
357 spin_lock_irqsave(&musb->lock, flags);
358 switch (musb->xceiv->state) {
359 case OTG_STATE_B_WAIT_ACON:
360 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
361 musb_g_disconnect(musb);
362 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
365 case OTG_STATE_A_SUSPEND:
366 case OTG_STATE_A_WAIT_BCON:
367 dev_dbg(musb->controller, "HNP: %s timeout\n",
368 otg_state_string(musb->xceiv->state));
369 musb_platform_set_vbus(musb, 0);
370 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
373 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
374 otg_state_string(musb->xceiv->state));
376 musb->ignore_disconnect = 0;
377 spin_unlock_irqrestore(&musb->lock, flags);
381 * Stops the HNP transition. Caller must take care of locking.
383 void musb_hnp_stop(struct musb *musb)
385 struct usb_hcd *hcd = musb_to_hcd(musb);
386 void __iomem *mbase = musb->mregs;
389 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
391 switch (musb->xceiv->state) {
392 case OTG_STATE_A_PERIPHERAL:
393 musb_g_disconnect(musb);
394 dev_dbg(musb->controller, "HNP: back to %s\n",
395 otg_state_string(musb->xceiv->state));
397 case OTG_STATE_B_HOST:
398 dev_dbg(musb->controller, "HNP: Disabling HR\n");
399 hcd->self.is_b_host = 0;
400 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
402 reg = musb_readb(mbase, MUSB_POWER);
403 reg |= MUSB_POWER_SUSPENDM;
404 musb_writeb(mbase, MUSB_POWER, reg);
405 /* REVISIT: Start SESSION_REQUEST here? */
408 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
409 otg_state_string(musb->xceiv->state));
413 * When returning to A state after HNP, avoid hub_port_rebounce(),
414 * which cause occasional OPT A "Did not receive reset after connect"
417 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
421 * Interrupt Service Routine to record USB "global" interrupts.
422 * Since these do not happen often and signify things of
423 * paramount importance, it seems OK to check them individually;
424 * the order of the tests is specified in the manual
426 * @param musb instance pointer
427 * @param int_usb register contents
432 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
435 irqreturn_t handled = IRQ_NONE;
437 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
440 /* in host mode, the peripheral may issue remote wakeup.
441 * in peripheral mode, the host may resume the link.
442 * spurious RESUME irqs happen too, paired with SUSPEND.
444 if (int_usb & MUSB_INTR_RESUME) {
445 handled = IRQ_HANDLED;
446 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
448 if (devctl & MUSB_DEVCTL_HM) {
449 void __iomem *mbase = musb->mregs;
451 switch (musb->xceiv->state) {
452 case OTG_STATE_A_SUSPEND:
453 /* remote wakeup? later, GetPortStatus
454 * will stop RESUME signaling
457 if (power & MUSB_POWER_SUSPENDM) {
459 musb->int_usb &= ~MUSB_INTR_SUSPEND;
460 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
464 power &= ~MUSB_POWER_SUSPENDM;
465 musb_writeb(mbase, MUSB_POWER,
466 power | MUSB_POWER_RESUME);
468 musb->port1_status |=
469 (USB_PORT_STAT_C_SUSPEND << 16)
470 | MUSB_PORT_STAT_RESUME;
471 musb->rh_timer = jiffies
472 + msecs_to_jiffies(20);
474 musb->xceiv->state = OTG_STATE_A_HOST;
476 usb_hcd_resume_root_hub(musb_to_hcd(musb));
478 case OTG_STATE_B_WAIT_ACON:
479 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
484 WARNING("bogus %s RESUME (%s)\n",
486 otg_state_string(musb->xceiv->state));
489 switch (musb->xceiv->state) {
490 case OTG_STATE_A_SUSPEND:
491 /* possibly DISCONNECT is upcoming */
492 musb->xceiv->state = OTG_STATE_A_HOST;
493 usb_hcd_resume_root_hub(musb_to_hcd(musb));
495 case OTG_STATE_B_WAIT_ACON:
496 case OTG_STATE_B_PERIPHERAL:
497 /* disconnect while suspended? we may
498 * not get a disconnect irq...
500 if ((devctl & MUSB_DEVCTL_VBUS)
501 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
503 musb->int_usb |= MUSB_INTR_DISCONNECT;
504 musb->int_usb &= ~MUSB_INTR_SUSPEND;
509 case OTG_STATE_B_IDLE:
510 musb->int_usb &= ~MUSB_INTR_SUSPEND;
513 WARNING("bogus %s RESUME (%s)\n",
515 otg_state_string(musb->xceiv->state));
520 /* see manual for the order of the tests */
521 if (int_usb & MUSB_INTR_SESSREQ) {
522 void __iomem *mbase = musb->mregs;
524 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
525 && (devctl & MUSB_DEVCTL_BDEVICE)) {
526 dev_dbg(musb->controller, "SessReq while on B state\n");
530 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
531 otg_state_string(musb->xceiv->state));
533 /* IRQ arrives from ID pin sense or (later, if VBUS power
534 * is removed) SRP. responses are time critical:
535 * - turn on VBUS (with silicon-specific mechanism)
536 * - go through A_WAIT_VRISE
537 * - ... to A_WAIT_BCON.
538 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
540 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
541 musb->ep0_stage = MUSB_EP0_START;
542 musb->xceiv->state = OTG_STATE_A_IDLE;
544 musb_platform_set_vbus(musb, 1);
546 handled = IRQ_HANDLED;
549 if (int_usb & MUSB_INTR_VBUSERROR) {
552 /* During connection as an A-Device, we may see a short
553 * current spikes causing voltage drop, because of cable
554 * and peripheral capacitance combined with vbus draw.
555 * (So: less common with truly self-powered devices, where
556 * vbus doesn't act like a power supply.)
558 * Such spikes are short; usually less than ~500 usec, max
559 * of ~2 msec. That is, they're not sustained overcurrent
560 * errors, though they're reported using VBUSERROR irqs.
562 * Workarounds: (a) hardware: use self powered devices.
563 * (b) software: ignore non-repeated VBUS errors.
565 * REVISIT: do delays from lots of DEBUG_KERNEL checks
566 * make trouble here, keeping VBUS < 4.4V ?
568 switch (musb->xceiv->state) {
569 case OTG_STATE_A_HOST:
570 /* recovery is dicey once we've gotten past the
571 * initial stages of enumeration, but if VBUS
572 * stayed ok at the other end of the link, and
573 * another reset is due (at least for high speed,
574 * to redo the chirp etc), it might work OK...
576 case OTG_STATE_A_WAIT_BCON:
577 case OTG_STATE_A_WAIT_VRISE:
578 if (musb->vbuserr_retry) {
579 void __iomem *mbase = musb->mregs;
581 musb->vbuserr_retry--;
583 devctl |= MUSB_DEVCTL_SESSION;
584 musb_writeb(mbase, MUSB_DEVCTL, devctl);
586 musb->port1_status |=
587 USB_PORT_STAT_OVERCURRENT
588 | (USB_PORT_STAT_C_OVERCURRENT << 16);
595 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
596 otg_state_string(musb->xceiv->state),
599 switch (devctl & MUSB_DEVCTL_VBUS) {
600 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
601 s = "<SessEnd"; break;
602 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
603 s = "<AValid"; break;
604 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
605 s = "<VBusValid"; break;
606 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
610 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
613 /* go through A_WAIT_VFALL then start a new session */
615 musb_platform_set_vbus(musb, 0);
616 handled = IRQ_HANDLED;
619 if (int_usb & MUSB_INTR_SUSPEND) {
620 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
621 otg_state_string(musb->xceiv->state), devctl, power);
622 handled = IRQ_HANDLED;
624 switch (musb->xceiv->state) {
625 case OTG_STATE_A_PERIPHERAL:
626 /* We also come here if the cable is removed, since
627 * this silicon doesn't report ID-no-longer-grounded.
629 * We depend on T(a_wait_bcon) to shut us down, and
630 * hope users don't do anything dicey during this
631 * undesired detour through A_WAIT_BCON.
634 usb_hcd_resume_root_hub(musb_to_hcd(musb));
635 musb_root_disconnect(musb);
636 musb_platform_try_idle(musb, jiffies
637 + msecs_to_jiffies(musb->a_wait_bcon
638 ? : OTG_TIME_A_WAIT_BCON));
641 case OTG_STATE_B_IDLE:
642 if (!musb->is_active)
644 case OTG_STATE_B_PERIPHERAL:
645 musb_g_suspend(musb);
646 musb->is_active = is_otg_enabled(musb)
647 && musb->xceiv->gadget->b_hnp_enable;
648 if (musb->is_active) {
649 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
650 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
651 mod_timer(&musb->otg_timer, jiffies
653 OTG_TIME_B_ASE0_BRST));
656 case OTG_STATE_A_WAIT_BCON:
657 if (musb->a_wait_bcon != 0)
658 musb_platform_try_idle(musb, jiffies
659 + msecs_to_jiffies(musb->a_wait_bcon));
661 case OTG_STATE_A_HOST:
662 musb->xceiv->state = OTG_STATE_A_SUSPEND;
663 musb->is_active = is_otg_enabled(musb)
664 && musb->xceiv->host->b_hnp_enable;
666 case OTG_STATE_B_HOST:
667 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
668 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
671 /* "should not happen" */
676 switch (musb->xceiv->state) {
677 case OTG_STATE_B_IDLE:
678 case OTG_STATE_B_PERIPHERAL:
679 cancel_delayed_work(&musb->vbus_workaround_work);
680 schedule_delayed_work(&musb->vbus_workaround_work, HZ / 2);
686 if (int_usb & MUSB_INTR_CONNECT) {
687 struct usb_hcd *hcd = musb_to_hcd(musb);
689 handled = IRQ_HANDLED;
691 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
693 musb->ep0_stage = MUSB_EP0_START;
695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb)) {
697 /* REVISIT HNP; just force disconnect */
699 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
700 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
701 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
702 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
703 |USB_PORT_STAT_HIGH_SPEED
704 |USB_PORT_STAT_ENABLE
706 musb->port1_status |= USB_PORT_STAT_CONNECTION
707 |(USB_PORT_STAT_C_CONNECTION << 16);
709 /* high vs full speed is just a guess until after reset */
710 if (devctl & MUSB_DEVCTL_LSDEV)
711 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
713 /* indicate new connection to OTG machine */
714 switch (musb->xceiv->state) {
715 case OTG_STATE_B_PERIPHERAL:
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
718 int_usb &= ~MUSB_INTR_SUSPEND;
721 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
723 case OTG_STATE_B_WAIT_ACON:
724 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
726 musb->xceiv->state = OTG_STATE_B_HOST;
727 hcd->self.is_b_host = 1;
728 musb->ignore_disconnect = 0;
729 del_timer(&musb->otg_timer);
732 if ((devctl & MUSB_DEVCTL_VBUS)
733 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
734 musb->xceiv->state = OTG_STATE_A_HOST;
735 hcd->self.is_b_host = 0;
740 /* poke the root hub */
743 usb_hcd_poll_rh_status(hcd);
745 usb_hcd_resume_root_hub(hcd);
747 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
748 otg_state_string(musb->xceiv->state), devctl);
751 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
752 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
753 otg_state_string(musb->xceiv->state),
754 MUSB_MODE(musb), devctl);
755 handled = IRQ_HANDLED;
757 switch (musb->xceiv->state) {
758 case OTG_STATE_A_HOST:
759 case OTG_STATE_A_SUSPEND:
760 usb_hcd_resume_root_hub(musb_to_hcd(musb));
761 musb_root_disconnect(musb);
762 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
763 musb_platform_try_idle(musb, jiffies
764 + msecs_to_jiffies(musb->a_wait_bcon));
766 case OTG_STATE_B_HOST:
767 /* REVISIT this behaves for "real disconnect"
768 * cases; make sure the other transitions from
769 * from B_HOST act right too. The B_HOST code
770 * in hnp_stop() is currently not used...
772 musb_root_disconnect(musb);
773 musb_to_hcd(musb)->self.is_b_host = 0;
774 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
776 musb_g_disconnect(musb);
778 case OTG_STATE_A_PERIPHERAL:
780 musb_root_disconnect(musb);
782 case OTG_STATE_B_WAIT_ACON:
784 case OTG_STATE_B_PERIPHERAL:
785 case OTG_STATE_B_IDLE:
786 musb_g_disconnect(musb);
789 WARNING("unhandled DISCONNECT transition (%s)\n",
790 otg_state_string(musb->xceiv->state));
795 /* mentor saves a bit: bus reset and babble share the same irq.
796 * only host sees babble; only peripheral sees bus reset.
798 if (int_usb & MUSB_INTR_RESET) {
799 handled = IRQ_HANDLED;
800 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
802 * Looks like non-HS BABBLE can be ignored, but
803 * HS BABBLE is an error condition. For HS the solution
804 * is to avoid babble in the first place and fix what
805 * caused BABBLE. When HS BABBLE happens we can only
808 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
809 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
811 ERR("Stopping host session -- babble\n");
812 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
814 } else if (is_peripheral_capable()) {
815 dev_dbg(musb->controller, "BUS RESET as %s\n",
816 otg_state_string(musb->xceiv->state));
817 switch (musb->xceiv->state) {
818 case OTG_STATE_A_SUSPEND:
819 /* We need to ignore disconnect on suspend
820 * otherwise tusb 2.0 won't reconnect after a
821 * power cycle, which breaks otg compliance.
823 musb->ignore_disconnect = 1;
826 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
827 /* never use invalid T(a_wait_bcon) */
828 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
829 otg_state_string(musb->xceiv->state),
831 mod_timer(&musb->otg_timer, jiffies
832 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
834 case OTG_STATE_A_PERIPHERAL:
835 musb->ignore_disconnect = 0;
836 del_timer(&musb->otg_timer);
839 case OTG_STATE_B_WAIT_ACON:
840 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
841 otg_state_string(musb->xceiv->state));
842 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
845 case OTG_STATE_B_IDLE:
846 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
848 case OTG_STATE_B_PERIPHERAL:
852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
853 otg_state_string(musb->xceiv->state));
859 /* REVISIT ... this would be for multiplexing periodic endpoints, or
860 * supporting transfer phasing to prevent exceeding ISO bandwidth
861 * limits of a given frame or microframe.
863 * It's not needed for peripheral side, which dedicates endpoints;
864 * though it _might_ use SOF irqs for other purposes.
866 * And it's not currently needed for host side, which also dedicates
867 * endpoints, relies on TX/RX interval registers, and isn't claimed
868 * to support ISO transfers yet.
870 if (int_usb & MUSB_INTR_SOF) {
871 void __iomem *mbase = musb->mregs;
872 struct musb_hw_ep *ep;
876 dev_dbg(musb->controller, "START_OF_FRAME\n");
877 handled = IRQ_HANDLED;
879 /* start any periodic Tx transfers waiting for current frame */
880 frame = musb_readw(mbase, MUSB_FRAME);
881 ep = musb->endpoints;
882 for (epnum = 1; (epnum < musb->nr_endpoints)
883 && (musb->epmask >= (1 << epnum));
886 * FIXME handle framecounter wraps (12 bits)
887 * eliminate duplicated StartUrb logic
889 if (ep->dwWaitFrame >= frame) {
891 pr_debug("SOF --> periodic TX%s on %d\n",
892 ep->tx_channel ? " DMA" : "",
895 musb_h_tx_start(musb, epnum);
897 cppi_hostdma_start(musb, epnum);
899 } /* end of for loop */
903 schedule_work(&musb->irq_work);
908 /*-------------------------------------------------------------------------*/
911 * Program the HDRC to start (enable interrupts, dma, etc.).
913 void musb_start(struct musb *musb)
915 void __iomem *regs = musb->mregs;
916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
920 /* Set INT enable registers, enable interrupts */
921 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
922 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
923 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
925 musb_writeb(regs, MUSB_TESTMODE, 0);
927 /* put into basic highspeed mode and start session */
928 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
930 /* ENSUSPEND wedges tusb */
931 /* | MUSB_POWER_ENSUSPEND */
935 devctl = musb_readb(regs, MUSB_DEVCTL);
936 devctl &= ~MUSB_DEVCTL_SESSION;
938 if (is_otg_enabled(musb)) {
939 /* session started after:
940 * (a) ID-grounded irq, host mode;
941 * (b) vbus present/connect IRQ, peripheral mode;
942 * (c) peripheral initiates, using SRP
944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
947 devctl |= MUSB_DEVCTL_SESSION;
949 } else if (is_host_enabled(musb)) {
950 /* assume ID pin is hard-wired to ground */
951 devctl |= MUSB_DEVCTL_SESSION;
953 } else /* peripheral is enabled */ {
954 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
957 musb_platform_enable(musb);
958 musb_writeb(regs, MUSB_DEVCTL, devctl);
962 static void musb_generic_disable(struct musb *musb)
964 void __iomem *mbase = musb->mregs;
967 /* disable interrupts */
968 musb_writeb(mbase, MUSB_INTRUSBE, 0);
969 musb_writew(mbase, MUSB_INTRTXE, 0);
970 musb_writew(mbase, MUSB_INTRRXE, 0);
973 musb_writeb(mbase, MUSB_DEVCTL, 0);
975 /* flush pending interrupts */
976 temp = musb_readb(mbase, MUSB_INTRUSB);
977 temp = musb_readw(mbase, MUSB_INTRTX);
978 temp = musb_readw(mbase, MUSB_INTRRX);
983 * Make the HDRC stop (disable interrupts, etc.);
984 * reversible by musb_start
985 * called on gadget driver unregister
986 * with controller locked, irqs blocked
987 * acts as a NOP unless some role activated the hardware
989 void musb_stop(struct musb *musb)
991 /* stop IRQs, timers, ... */
992 musb_platform_disable(musb);
993 musb_generic_disable(musb);
994 dev_dbg(musb->controller, "HDRC disabled\n");
997 * - mark host and/or peripheral drivers unusable/inactive
998 * - disable DMA (and enable it in HdrcStart)
999 * - make sure we can musb_start() after musb_stop(); with
1000 * OTG mode, gadget driver module rmmod/modprobe cycles that
1003 musb_platform_try_idle(musb, 0);
1006 static void musb_shutdown(struct platform_device *pdev)
1008 struct musb *musb = dev_to_musb(&pdev->dev);
1009 unsigned long flags;
1011 pm_runtime_get_sync(musb->controller);
1013 musb_gadget_cleanup(musb);
1015 spin_lock_irqsave(&musb->lock, flags);
1016 musb_platform_disable(musb);
1017 musb_generic_disable(musb);
1018 spin_unlock_irqrestore(&musb->lock, flags);
1020 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1021 usb_remove_hcd(musb_to_hcd(musb));
1022 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1023 musb_platform_exit(musb);
1025 pm_runtime_put(musb->controller);
1027 cancel_delayed_work(&musb->vbus_workaround_work);
1029 /* FIXME power down */
1033 /*-------------------------------------------------------------------------*/
1036 * The silicon either has hard-wired endpoint configurations, or else
1037 * "dynamic fifo" sizing. The driver has support for both, though at this
1038 * writing only the dynamic sizing is very well tested. Since we switched
1039 * away from compile-time hardware parameters, we can no longer rely on
1040 * dead code elimination to leave only the relevant one in the object file.
1042 * We don't currently use dynamic fifo setup capability to do anything
1043 * more than selecting one of a bunch of predefined configurations.
1045 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1046 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1047 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1048 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1049 || defined(CONFIG_USB_MUSB_AM35X) \
1050 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1051 static ushort __initdata fifo_mode = 4;
1052 #elif defined(CONFIG_USB_MUSB_UX500) \
1053 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1054 static ushort __initdata fifo_mode = 5;
1056 static ushort __initdata fifo_mode = 2;
1059 /* "modprobe ... fifo_mode=1" etc */
1060 module_param(fifo_mode, ushort, 0);
1061 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1064 * tables defining fifo_mode values. define more if you like.
1065 * for host side, make sure both halves of ep1 are set up.
1068 /* mode 0 - fits in 2KB */
1069 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1073 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1074 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1077 /* mode 1 - fits in 4KB */
1078 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1079 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1080 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1081 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1082 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1083 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1086 /* mode 2 - fits in 4KB */
1087 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1088 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1093 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1096 /* mode 3 - fits in 4KB */
1097 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1098 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1099 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1100 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1103 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1106 /* mode 4 - fits in 16KB */
1107 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1108 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1109 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1110 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1111 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1112 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1113 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1114 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1117 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1118 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1119 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1120 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1121 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1122 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1123 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1124 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1125 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1126 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1127 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1128 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1129 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1130 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1131 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1132 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1133 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1134 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1137 /* mode 5 - fits in 8KB */
1138 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1139 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1142 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1143 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1144 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1145 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1146 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1147 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1148 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1149 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1150 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1151 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1152 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1153 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1154 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1155 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1156 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1157 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1158 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1159 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1160 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1161 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1162 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1163 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1164 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1165 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1169 * configure a fifo; for non-shared endpoints, this may be called
1170 * once for a tx fifo and once for an rx fifo.
1172 * returns negative errno or offset for next fifo.
1175 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1176 const struct musb_fifo_cfg *cfg, u16 offset)
1178 void __iomem *mbase = musb->mregs;
1180 u16 maxpacket = cfg->maxpacket;
1181 u16 c_off = offset >> 3;
1184 /* expect hw_ep has already been zero-initialized */
1186 size = ffs(max(maxpacket, (u16) 8)) - 1;
1187 maxpacket = 1 << size;
1190 if (cfg->mode == BUF_DOUBLE) {
1191 if ((offset + (maxpacket << 1)) >
1192 (1 << (musb->config->ram_bits + 2)))
1194 c_size |= MUSB_FIFOSZ_DPB;
1196 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1200 /* configure the FIFO */
1201 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1203 /* EP0 reserved endpoint for control, bidirectional;
1204 * EP1 reserved for bulk, two unidirection halves.
1206 if (hw_ep->epnum == 1)
1207 musb->bulk_ep = hw_ep;
1208 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1209 switch (cfg->style) {
1211 musb_write_txfifosz(mbase, c_size);
1212 musb_write_txfifoadd(mbase, c_off);
1213 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1214 hw_ep->max_packet_sz_tx = maxpacket;
1217 musb_write_rxfifosz(mbase, c_size);
1218 musb_write_rxfifoadd(mbase, c_off);
1219 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1220 hw_ep->max_packet_sz_rx = maxpacket;
1223 musb_write_txfifosz(mbase, c_size);
1224 musb_write_txfifoadd(mbase, c_off);
1225 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1226 hw_ep->max_packet_sz_rx = maxpacket;
1228 musb_write_rxfifosz(mbase, c_size);
1229 musb_write_rxfifoadd(mbase, c_off);
1230 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1231 hw_ep->max_packet_sz_tx = maxpacket;
1233 hw_ep->is_shared_fifo = true;
1237 /* NOTE rx and tx endpoint irqs aren't managed separately,
1238 * which happens to be ok
1240 musb->epmask |= (1 << hw_ep->epnum);
1242 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1245 static struct musb_fifo_cfg __initdata ep0_cfg = {
1246 .style = FIFO_RXTX, .maxpacket = 64,
1249 static int __init ep_config_from_table(struct musb *musb)
1251 const struct musb_fifo_cfg *cfg;
1254 struct musb_hw_ep *hw_ep = musb->endpoints;
1256 if (musb->config->fifo_cfg) {
1257 cfg = musb->config->fifo_cfg;
1258 n = musb->config->fifo_cfg_size;
1262 switch (fifo_mode) {
1268 n = ARRAY_SIZE(mode_0_cfg);
1272 n = ARRAY_SIZE(mode_1_cfg);
1276 n = ARRAY_SIZE(mode_2_cfg);
1280 n = ARRAY_SIZE(mode_3_cfg);
1284 n = ARRAY_SIZE(mode_4_cfg);
1288 n = ARRAY_SIZE(mode_5_cfg);
1292 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1293 musb_driver_name, fifo_mode);
1297 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1298 /* assert(offset > 0) */
1300 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1301 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1304 for (i = 0; i < n; i++) {
1305 u8 epn = cfg->hw_ep_num;
1307 if (epn >= musb->config->num_eps) {
1308 pr_debug("%s: invalid ep %d\n",
1309 musb_driver_name, epn);
1312 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1314 pr_debug("%s: mem overrun, ep %d\n",
1315 musb_driver_name, epn);
1319 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1322 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1324 n + 1, musb->config->num_eps * 2 - 1,
1325 offset, (1 << (musb->config->ram_bits + 2)));
1327 if (!musb->bulk_ep) {
1328 pr_debug("%s: missing bulk\n", musb_driver_name);
1337 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1338 * @param musb the controller
1340 static int __init ep_config_from_hw(struct musb *musb)
1343 struct musb_hw_ep *hw_ep;
1344 void *mbase = musb->mregs;
1347 dev_dbg(musb->controller, "<== static silicon ep config\n");
1349 /* FIXME pick up ep0 maxpacket size */
1351 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1352 musb_ep_select(mbase, epnum);
1353 hw_ep = musb->endpoints + epnum;
1355 ret = musb_read_fifosize(musb, hw_ep, epnum);
1359 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1361 /* pick an RX/TX endpoint for bulk */
1362 if (hw_ep->max_packet_sz_tx < 512
1363 || hw_ep->max_packet_sz_rx < 512)
1366 /* REVISIT: this algorithm is lazy, we should at least
1367 * try to pick a double buffered endpoint.
1371 musb->bulk_ep = hw_ep;
1374 if (!musb->bulk_ep) {
1375 pr_debug("%s: missing bulk\n", musb_driver_name);
1382 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1384 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1385 * configure endpoints, or take their config from silicon
1387 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1391 char aInfo[90], aRevision[32], aDate[12];
1392 void __iomem *mbase = musb->mregs;
1396 /* log core options (read using indexed model) */
1397 reg = musb_read_configdata(mbase);
1399 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1400 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1401 strcat(aInfo, ", dyn FIFOs");
1402 musb->dyn_fifo = true;
1404 if (reg & MUSB_CONFIGDATA_MPRXE) {
1405 strcat(aInfo, ", bulk combine");
1406 musb->bulk_combine = true;
1408 if (reg & MUSB_CONFIGDATA_MPTXE) {
1409 strcat(aInfo, ", bulk split");
1410 musb->bulk_split = true;
1412 if (reg & MUSB_CONFIGDATA_HBRXE) {
1413 strcat(aInfo, ", HB-ISO Rx");
1414 musb->hb_iso_rx = true;
1416 if (reg & MUSB_CONFIGDATA_HBTXE) {
1417 strcat(aInfo, ", HB-ISO Tx");
1418 musb->hb_iso_tx = true;
1420 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1421 strcat(aInfo, ", SoftConn");
1423 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1424 musb_driver_name, reg, aInfo);
1427 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1428 musb->is_multipoint = 1;
1431 musb->is_multipoint = 0;
1433 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1435 "%s: kernel must blacklist external hubs\n",
1440 /* log release info */
1441 musb->hwvers = musb_read_hwvers(mbase);
1442 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1443 MUSB_HWVERS_MINOR(musb->hwvers),
1444 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1445 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1446 musb_driver_name, type, aRevision, aDate);
1449 musb_configure_ep0(musb);
1451 /* discover endpoint configuration */
1452 musb->nr_endpoints = 1;
1456 status = ep_config_from_table(musb);
1458 status = ep_config_from_hw(musb);
1463 /* finish init, and print endpoint config */
1464 for (i = 0; i < musb->nr_endpoints; i++) {
1465 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1467 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1468 #ifdef CONFIG_USB_MUSB_TUSB6010
1469 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1470 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1471 hw_ep->fifo_sync_va =
1472 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1475 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1477 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1480 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1481 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1482 hw_ep->rx_reinit = 1;
1483 hw_ep->tx_reinit = 1;
1485 if (hw_ep->max_packet_sz_tx) {
1486 dev_dbg(musb->controller,
1487 "%s: hw_ep %d%s, %smax %d\n",
1488 musb_driver_name, i,
1489 hw_ep->is_shared_fifo ? "shared" : "tx",
1490 hw_ep->tx_double_buffered
1491 ? "doublebuffer, " : "",
1492 hw_ep->max_packet_sz_tx);
1494 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1495 dev_dbg(musb->controller,
1496 "%s: hw_ep %d%s, %smax %d\n",
1497 musb_driver_name, i,
1499 hw_ep->rx_double_buffered
1500 ? "doublebuffer, " : "",
1501 hw_ep->max_packet_sz_rx);
1503 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1504 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1510 /*-------------------------------------------------------------------------*/
1512 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1513 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1515 static irqreturn_t generic_interrupt(int irq, void *__hci)
1517 unsigned long flags;
1518 irqreturn_t retval = IRQ_NONE;
1519 struct musb *musb = __hci;
1521 spin_lock_irqsave(&musb->lock, flags);
1523 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1524 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1525 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1527 if (musb->int_usb || musb->int_tx || musb->int_rx)
1528 retval = musb_interrupt(musb);
1530 spin_unlock_irqrestore(&musb->lock, flags);
1536 #define generic_interrupt NULL
1540 * handle all the irqs defined by the HDRC core. for now we expect: other
1541 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1542 * will be assigned, and the irq will already have been acked.
1544 * called in irq context with spinlock held, irqs blocked
1546 irqreturn_t musb_interrupt(struct musb *musb)
1548 irqreturn_t retval = IRQ_NONE;
1553 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1554 power = musb_readb(musb->mregs, MUSB_POWER);
1556 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1557 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1558 musb->int_usb, musb->int_tx, musb->int_rx);
1560 /* the core can interrupt us for multiple reasons; docs have
1561 * a generic interrupt flowchart to follow
1564 retval |= musb_stage0_irq(musb, musb->int_usb,
1567 /* "stage 1" is handling endpoint irqs */
1569 /* handle endpoint 0 first */
1570 if (musb->int_tx & 1) {
1571 if (devctl & MUSB_DEVCTL_HM)
1572 retval |= musb_h_ep0_irq(musb);
1574 retval |= musb_g_ep0_irq(musb);
1577 /* RX on endpoints 1-15 */
1578 reg = musb->int_rx >> 1;
1582 /* musb_ep_select(musb->mregs, ep_num); */
1583 /* REVISIT just retval = ep->rx_irq(...) */
1584 retval = IRQ_HANDLED;
1585 if (devctl & MUSB_DEVCTL_HM) {
1586 if (is_host_capable())
1587 musb_host_rx(musb, ep_num);
1589 if (is_peripheral_capable())
1590 musb_g_rx(musb, ep_num);
1598 /* TX on endpoints 1-15 */
1599 reg = musb->int_tx >> 1;
1603 /* musb_ep_select(musb->mregs, ep_num); */
1604 /* REVISIT just retval |= ep->tx_irq(...) */
1605 retval = IRQ_HANDLED;
1606 if (devctl & MUSB_DEVCTL_HM) {
1607 if (is_host_capable())
1608 musb_host_tx(musb, ep_num);
1610 if (is_peripheral_capable())
1611 musb_g_tx(musb, ep_num);
1620 EXPORT_SYMBOL_GPL(musb_interrupt);
1622 #ifndef CONFIG_MUSB_PIO_ONLY
1623 static int __initdata use_dma = 1;
1625 /* "modprobe ... use_dma=0" etc */
1626 module_param(use_dma, bool, 0);
1627 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1629 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1631 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1633 /* called with controller lock already held */
1636 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1637 if (!is_cppi_enabled()) {
1639 if (devctl & MUSB_DEVCTL_HM)
1640 musb_h_ep0_irq(musb);
1642 musb_g_ep0_irq(musb);
1646 /* endpoints 1..15 */
1648 if (devctl & MUSB_DEVCTL_HM) {
1649 if (is_host_capable())
1650 musb_host_tx(musb, epnum);
1652 if (is_peripheral_capable())
1653 musb_g_tx(musb, epnum);
1657 if (devctl & MUSB_DEVCTL_HM) {
1658 if (is_host_capable())
1659 musb_host_rx(musb, epnum);
1661 if (is_peripheral_capable())
1662 musb_g_rx(musb, epnum);
1672 /*-------------------------------------------------------------------------*/
1677 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1679 struct musb *musb = dev_to_musb(dev);
1680 unsigned long flags;
1683 spin_lock_irqsave(&musb->lock, flags);
1684 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1685 spin_unlock_irqrestore(&musb->lock, flags);
1691 musb_mode_store(struct device *dev, struct device_attribute *attr,
1692 const char *buf, size_t n)
1694 struct musb *musb = dev_to_musb(dev);
1695 unsigned long flags;
1698 spin_lock_irqsave(&musb->lock, flags);
1699 if (sysfs_streq(buf, "host"))
1700 status = musb_platform_set_mode(musb, MUSB_HOST);
1701 else if (sysfs_streq(buf, "peripheral"))
1702 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1703 else if (sysfs_streq(buf, "otg"))
1704 status = musb_platform_set_mode(musb, MUSB_OTG);
1707 spin_unlock_irqrestore(&musb->lock, flags);
1709 return (status == 0) ? n : status;
1711 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1714 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1715 const char *buf, size_t n)
1717 struct musb *musb = dev_to_musb(dev);
1718 unsigned long flags;
1721 if (sscanf(buf, "%lu", &val) < 1) {
1722 dev_err(dev, "Invalid VBUS timeout ms value\n");
1726 spin_lock_irqsave(&musb->lock, flags);
1727 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1728 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1729 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1730 musb->is_active = 0;
1731 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1732 spin_unlock_irqrestore(&musb->lock, flags);
1738 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1740 struct musb *musb = dev_to_musb(dev);
1741 unsigned long flags;
1745 spin_lock_irqsave(&musb->lock, flags);
1746 val = musb->a_wait_bcon;
1747 /* FIXME get_vbus_status() is normally #defined as false...
1748 * and is effectively TUSB-specific.
1750 vbus = musb_platform_get_vbus_status(musb);
1751 spin_unlock_irqrestore(&musb->lock, flags);
1753 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1754 vbus ? "on" : "off", val);
1756 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1758 /* Gadget drivers can't know that a host is connected so they might want
1759 * to start SRP, but users can. This allows userspace to trigger SRP.
1762 musb_srp_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t n)
1765 struct musb *musb = dev_to_musb(dev);
1768 if (sscanf(buf, "%hu", &srp) != 1
1770 dev_err(dev, "SRP: Value must be 1\n");
1775 musb_g_wakeup(musb);
1779 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1781 static struct attribute *musb_attributes[] = {
1782 &dev_attr_mode.attr,
1783 &dev_attr_vbus.attr,
1788 static const struct attribute_group musb_attr_group = {
1789 .attrs = musb_attributes,
1794 /* Only used to provide driver mode change events */
1795 static void musb_irq_work(struct work_struct *data)
1797 struct musb *musb = container_of(data, struct musb, irq_work);
1798 static int old_state;
1800 if (musb->xceiv->state != old_state) {
1801 old_state = musb->xceiv->state;
1802 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1806 #include <linux/usb/ulpi.h>
1808 static void musb_vbus_workaround_work(struct work_struct *work)
1810 struct musb *musb = container_of(work, struct musb, vbus_workaround_work.work);
1814 if (musb_ulpi_access.write == NULL)
1817 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1820 * I don't really know why but VBUS sometimes gets stuck and
1821 * causes session to never end. It would look like some pullup
1822 * is enabled when it shouldn't be on certain PHY states.
1823 * Turning on pulldowns magically drains VBUS to zero and allows
1824 * session to end, so let's do that here.
1826 * XXX: probably better check VBUS on TWL?
1827 * beagle sometimes has session bit set but no VBUS on twl?
1829 if ((musb->xceiv->state == OTG_STATE_B_PERIPHERAL ||
1830 musb->xceiv->state == OTG_STATE_B_IDLE) &&
1831 (devctl & MUSB_DEVCTL_VBUS) != (3 << MUSB_DEVCTL_VBUS_SHIFT) &&
1832 (devctl & MUSB_DEVCTL_VBUS) != (0 << MUSB_DEVCTL_VBUS_SHIFT)) {
1833 dev_dbg(musb->controller, "VBUS workaround..\n");
1834 ret = musb_ulpi_access.write(musb->xceiv, ULPI_SET(ULPI_OTG_CTRL),
1835 ULPI_OTG_CTRL_DM_PULLDOWN | ULPI_OTG_CTRL_DP_PULLDOWN);
1837 // dev_err(musb->controller, "VBUS workaround error\n");
1841 /* --------------------------------------------------------------------------
1845 static struct musb *__init
1846 allocate_instance(struct device *dev,
1847 struct musb_hdrc_config *config, void __iomem *mbase)
1850 struct musb_hw_ep *ep;
1852 struct usb_hcd *hcd;
1854 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1857 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1859 musb = hcd_to_musb(hcd);
1860 INIT_LIST_HEAD(&musb->control);
1861 INIT_LIST_HEAD(&musb->in_bulk);
1862 INIT_LIST_HEAD(&musb->out_bulk);
1864 hcd->uses_new_polling = 1;
1867 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1868 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1869 dev_set_drvdata(dev, musb);
1870 musb->mregs = mbase;
1871 musb->ctrl_base = mbase;
1872 musb->nIrq = -ENODEV;
1873 musb->config = config;
1874 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1875 for (epnum = 0, ep = musb->endpoints;
1876 epnum < musb->config->num_eps;
1882 musb->controller = dev;
1887 static void musb_free(struct musb *musb)
1889 /* this has multiple entry modes. it handles fault cleanup after
1890 * probe(), where things may be partially set up, as well as rmmod
1891 * cleanup after everything's been de-activated.
1895 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1898 if (musb->nIrq >= 0) {
1900 disable_irq_wake(musb->nIrq);
1901 free_irq(musb->nIrq, musb);
1903 if (is_dma_capable() && musb->dma_controller) {
1904 struct dma_controller *c = musb->dma_controller;
1907 dma_controller_destroy(c);
1910 usb_put_hcd(musb_to_hcd(musb));
1914 * Perform generic per-controller initialization.
1916 * @pDevice: the controller (already clocked, etc)
1918 * @mregs: virtual address of controller registers,
1919 * not yet corrected for platform-specific offsets
1922 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1926 struct musb_hdrc_platform_data *plat = dev->platform_data;
1928 /* The driver might handle more features than the board; OK.
1929 * Fail when the board needs a feature that's not enabled.
1932 dev_dbg(dev, "no platform_data?\n");
1938 musb = allocate_instance(dev, plat->config, ctrl);
1944 pm_runtime_use_autosuspend(musb->controller);
1945 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1946 pm_runtime_enable(musb->controller);
1948 spin_lock_init(&musb->lock);
1949 musb->board_mode = plat->mode;
1950 musb->board_set_power = plat->set_power;
1951 musb->min_power = plat->min_power;
1952 musb->ops = plat->platform_ops;
1954 /* The musb_platform_init() call:
1955 * - adjusts musb->mregs and musb->isr if needed,
1956 * - may initialize an integrated tranceiver
1957 * - initializes musb->xceiv, usually by otg_get_transceiver()
1958 * - stops powering VBUS
1960 * There are various transceiver configurations. Blackfin,
1961 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1962 * external/discrete ones in various flavors (twl4030 family,
1963 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1965 musb->isr = generic_interrupt;
1966 status = musb_platform_init(musb);
1975 if (!musb->xceiv->io_ops) {
1976 musb->xceiv->io_dev = musb->controller;
1977 musb->xceiv->io_priv = musb->mregs;
1978 musb->xceiv->io_ops = &musb_ulpi_access;
1981 #ifndef CONFIG_MUSB_PIO_ONLY
1982 if (use_dma && dev->dma_mask) {
1983 struct dma_controller *c;
1985 c = dma_controller_create(musb, musb->mregs);
1986 musb->dma_controller = c;
1991 /* ideally this would be abstracted in platform setup */
1992 if (!is_dma_capable() || !musb->dma_controller)
1993 dev->dma_mask = NULL;
1995 /* be sure interrupts are disabled before connecting ISR */
1996 musb_platform_disable(musb);
1997 musb_generic_disable(musb);
1999 /* setup musb parts of the core (especially endpoints) */
2000 status = musb_core_init(plat->config->multipoint
2001 ? MUSB_CONTROLLER_MHDRC
2002 : MUSB_CONTROLLER_HDRC, musb);
2006 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2008 /* Init IRQ workqueue before request_irq */
2009 INIT_WORK(&musb->irq_work, musb_irq_work);
2011 INIT_DELAYED_WORK(&musb->vbus_workaround_work, musb_vbus_workaround_work);
2013 /* attach to the IRQ */
2014 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2015 dev_err(dev, "request_irq %d failed!\n", nIrq);
2020 /* FIXME this handles wakeup irqs wrong */
2021 if (enable_irq_wake(nIrq) == 0) {
2023 device_init_wakeup(dev, 1);
2028 /* host side needs more setup */
2029 if (is_host_enabled(musb)) {
2030 struct usb_hcd *hcd = musb_to_hcd(musb);
2032 otg_set_host(musb->xceiv, &hcd->self);
2034 if (is_otg_enabled(musb))
2035 hcd->self.otg_port = 1;
2036 musb->xceiv->host = &hcd->self;
2037 hcd->power_budget = 2 * (plat->power ? : 250);
2039 /* program PHY to use external vBus if required */
2040 if (plat->extvbus) {
2041 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2042 busctl |= MUSB_ULPI_USE_EXTVBUS;
2043 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2047 /* For the host-only role, we can activate right away.
2048 * (We expect the ID pin to be forcibly grounded!!)
2049 * Otherwise, wait till the gadget driver hooks up.
2051 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2052 struct usb_hcd *hcd = musb_to_hcd(musb);
2054 MUSB_HST_MODE(musb);
2055 musb->xceiv->default_a = 1;
2056 musb->xceiv->state = OTG_STATE_A_IDLE;
2058 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2060 hcd->self.uses_pio_for_control = 1;
2061 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2063 musb_readb(musb->mregs, MUSB_DEVCTL),
2064 (musb_readb(musb->mregs, MUSB_DEVCTL)
2065 & MUSB_DEVCTL_BDEVICE
2068 } else /* peripheral is enabled */ {
2069 if (musb->xceiv->default_a) {
2070 MUSB_HST_MODE(musb);
2071 musb->xceiv->state = OTG_STATE_A_IDLE;
2073 MUSB_DEV_MODE(musb);
2074 musb->xceiv->state = OTG_STATE_B_IDLE;
2077 status = musb_gadget_setup(musb);
2079 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2080 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2082 musb_readb(musb->mregs, MUSB_DEVCTL));
2088 pm_runtime_put(musb->controller);
2090 status = musb_init_debugfs(musb);
2095 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2100 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2102 switch (musb->board_mode) {
2103 case MUSB_HOST: s = "Host"; break;
2104 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2105 default: s = "OTG"; break;
2108 (is_dma_capable() && musb->dma_controller)
2115 musb_exit_debugfs(musb);
2118 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2119 usb_remove_hcd(musb_to_hcd(musb));
2121 musb_gadget_cleanup(musb);
2125 device_init_wakeup(dev, 0);
2126 musb_platform_exit(musb);
2129 dev_err(musb->controller,
2130 "musb_init_controller failed with status %d\n", status);
2140 /*-------------------------------------------------------------------------*/
2142 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2143 * bridge to a platform device; this driver then suffices.
2146 #ifndef CONFIG_MUSB_PIO_ONLY
2147 static u64 *orig_dma_mask;
2150 static int __init musb_probe(struct platform_device *pdev)
2152 struct device *dev = &pdev->dev;
2153 int irq = platform_get_irq_byname(pdev, "mc");
2155 struct resource *iomem;
2158 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2159 if (!iomem || irq <= 0)
2162 base = ioremap(iomem->start, resource_size(iomem));
2164 dev_err(dev, "ioremap failed\n");
2168 #ifndef CONFIG_MUSB_PIO_ONLY
2169 /* clobbered by use_dma=n */
2170 orig_dma_mask = dev->dma_mask;
2172 status = musb_init_controller(dev, irq, base);
2179 static int __exit musb_remove(struct platform_device *pdev)
2181 struct musb *musb = dev_to_musb(&pdev->dev);
2182 void __iomem *ctrl_base = musb->ctrl_base;
2184 /* this gets called on rmmod.
2185 * - Host mode: host may still be active
2186 * - Peripheral mode: peripheral is deactivated (or never-activated)
2187 * - OTG mode: both roles are deactivated (or never-activated)
2189 musb_exit_debugfs(musb);
2190 musb_shutdown(pdev);
2194 device_init_wakeup(&pdev->dev, 0);
2195 #ifndef CONFIG_MUSB_PIO_ONLY
2196 pdev->dev.dma_mask = orig_dma_mask;
2203 static void musb_save_context(struct musb *musb)
2206 void __iomem *musb_base = musb->mregs;
2209 if (is_host_enabled(musb)) {
2210 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2211 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2212 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2214 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2215 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2216 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2217 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2218 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2219 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2221 for (i = 0; i < musb->config->num_eps; ++i) {
2222 struct musb_hw_ep *hw_ep;
2224 hw_ep = &musb->endpoints[i];
2232 musb_writeb(musb_base, MUSB_INDEX, i);
2233 musb->context.index_regs[i].txmaxp =
2234 musb_readw(epio, MUSB_TXMAXP);
2235 musb->context.index_regs[i].txcsr =
2236 musb_readw(epio, MUSB_TXCSR);
2237 musb->context.index_regs[i].rxmaxp =
2238 musb_readw(epio, MUSB_RXMAXP);
2239 musb->context.index_regs[i].rxcsr =
2240 musb_readw(epio, MUSB_RXCSR);
2242 if (musb->dyn_fifo) {
2243 musb->context.index_regs[i].txfifoadd =
2244 musb_read_txfifoadd(musb_base);
2245 musb->context.index_regs[i].rxfifoadd =
2246 musb_read_rxfifoadd(musb_base);
2247 musb->context.index_regs[i].txfifosz =
2248 musb_read_txfifosz(musb_base);
2249 musb->context.index_regs[i].rxfifosz =
2250 musb_read_rxfifosz(musb_base);
2252 if (is_host_enabled(musb)) {
2253 musb->context.index_regs[i].txtype =
2254 musb_readb(epio, MUSB_TXTYPE);
2255 musb->context.index_regs[i].txinterval =
2256 musb_readb(epio, MUSB_TXINTERVAL);
2257 musb->context.index_regs[i].rxtype =
2258 musb_readb(epio, MUSB_RXTYPE);
2259 musb->context.index_regs[i].rxinterval =
2260 musb_readb(epio, MUSB_RXINTERVAL);
2262 musb->context.index_regs[i].txfunaddr =
2263 musb_read_txfunaddr(musb_base, i);
2264 musb->context.index_regs[i].txhubaddr =
2265 musb_read_txhubaddr(musb_base, i);
2266 musb->context.index_regs[i].txhubport =
2267 musb_read_txhubport(musb_base, i);
2269 musb->context.index_regs[i].rxfunaddr =
2270 musb_read_rxfunaddr(musb_base, i);
2271 musb->context.index_regs[i].rxhubaddr =
2272 musb_read_rxhubaddr(musb_base, i);
2273 musb->context.index_regs[i].rxhubport =
2274 musb_read_rxhubport(musb_base, i);
2279 static void musb_restore_context(struct musb *musb)
2282 void __iomem *musb_base = musb->mregs;
2283 void __iomem *ep_target_regs;
2286 if (is_host_enabled(musb)) {
2287 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2288 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2289 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2291 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2292 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2293 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2294 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2295 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2297 for (i = 0; i < musb->config->num_eps; ++i) {
2298 struct musb_hw_ep *hw_ep;
2300 hw_ep = &musb->endpoints[i];
2308 musb_writeb(musb_base, MUSB_INDEX, i);
2309 musb_writew(epio, MUSB_TXMAXP,
2310 musb->context.index_regs[i].txmaxp);
2311 musb_writew(epio, MUSB_TXCSR,
2312 musb->context.index_regs[i].txcsr);
2313 musb_writew(epio, MUSB_RXMAXP,
2314 musb->context.index_regs[i].rxmaxp);
2315 musb_writew(epio, MUSB_RXCSR,
2316 musb->context.index_regs[i].rxcsr);
2318 if (musb->dyn_fifo) {
2319 musb_write_txfifosz(musb_base,
2320 musb->context.index_regs[i].txfifosz);
2321 musb_write_rxfifosz(musb_base,
2322 musb->context.index_regs[i].rxfifosz);
2323 musb_write_txfifoadd(musb_base,
2324 musb->context.index_regs[i].txfifoadd);
2325 musb_write_rxfifoadd(musb_base,
2326 musb->context.index_regs[i].rxfifoadd);
2329 if (is_host_enabled(musb)) {
2330 musb_writeb(epio, MUSB_TXTYPE,
2331 musb->context.index_regs[i].txtype);
2332 musb_writeb(epio, MUSB_TXINTERVAL,
2333 musb->context.index_regs[i].txinterval);
2334 musb_writeb(epio, MUSB_RXTYPE,
2335 musb->context.index_regs[i].rxtype);
2336 musb_writeb(epio, MUSB_RXINTERVAL,
2338 musb->context.index_regs[i].rxinterval);
2339 musb_write_txfunaddr(musb_base, i,
2340 musb->context.index_regs[i].txfunaddr);
2341 musb_write_txhubaddr(musb_base, i,
2342 musb->context.index_regs[i].txhubaddr);
2343 musb_write_txhubport(musb_base, i,
2344 musb->context.index_regs[i].txhubport);
2347 musb_read_target_reg_base(i, musb_base);
2349 musb_write_rxfunaddr(ep_target_regs,
2350 musb->context.index_regs[i].rxfunaddr);
2351 musb_write_rxhubaddr(ep_target_regs,
2352 musb->context.index_regs[i].rxhubaddr);
2353 musb_write_rxhubport(ep_target_regs,
2354 musb->context.index_regs[i].rxhubport);
2357 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2360 static int musb_suspend(struct device *dev)
2362 struct musb *musb = dev_to_musb(dev);
2363 unsigned long flags;
2366 spin_lock_irqsave(&musb->lock, flags);
2368 if (is_peripheral_active(musb)) {
2369 /* FIXME force disconnect unless we know USB will wake
2370 * the system up quickly enough to respond ...
2373 * FIXME: musb must be already runtime suspended at this point.
2374 * If it's not, framework will try to suspend it late when
2375 * i2c will be off, and twl4030 will want to access it for it's
2376 * stuff, causing data abort.
2378 int pm_usage_count =
2379 atomic_read(&musb->controller->power.usage_count);
2380 if (pm_usage_count > 1) {
2381 dev_err(dev, "can't suspend while still active, "
2382 "try removing gadget drivers (usage_count %d)\n",
2386 } else if (is_host_active(musb)) {
2387 /* we know all the children are suspended; sometimes
2388 * they will even be wakeup-enabled.
2392 spin_unlock_irqrestore(&musb->lock, flags);
2396 static int musb_resume_noirq(struct device *dev)
2398 /* for static cmos like DaVinci, register values were preserved
2399 * unless for some reason the whole soc powered down or the USB
2400 * module got reset through the PSC (vs just being disabled).
2405 static int musb_runtime_suspend(struct device *dev)
2407 struct musb *musb = dev_to_musb(dev);
2409 musb_save_context(musb);
2414 static int musb_runtime_resume(struct device *dev)
2416 struct musb *musb = dev_to_musb(dev);
2417 static int first = 1;
2420 * When pm_runtime_get_sync called for the first time in driver
2421 * init, some of the structure is still not initialized which is
2422 * used in restore function. But clock needs to be
2423 * enabled before any register access, so
2424 * pm_runtime_get_sync has to be called.
2425 * Also context restore without save does not make
2429 musb_restore_context(musb);
2435 static const struct dev_pm_ops musb_dev_pm_ops = {
2436 .suspend = musb_suspend,
2437 .resume_noirq = musb_resume_noirq,
2438 .runtime_suspend = musb_runtime_suspend,
2439 .runtime_resume = musb_runtime_resume,
2442 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2444 #define MUSB_DEV_PM_OPS NULL
2447 static struct platform_driver musb_driver = {
2449 .name = (char *)musb_driver_name,
2450 .bus = &platform_bus_type,
2451 .owner = THIS_MODULE,
2452 .pm = MUSB_DEV_PM_OPS,
2454 .remove = __exit_p(musb_remove),
2455 .shutdown = musb_shutdown,
2458 /*-------------------------------------------------------------------------*/
2460 static int __init musb_init(void)
2465 pr_info("%s: version " MUSB_VERSION ", ?dma?, otg (peripheral+host)\n",
2467 return platform_driver_probe(&musb_driver, musb_probe);
2470 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2471 * and before usb gadget and host-side drivers start to register
2473 fs_initcall(musb_init);
2475 static void __exit musb_cleanup(void)
2477 platform_driver_unregister(&musb_driver);
2479 module_exit(musb_cleanup);